dpi.c 8.0 KB

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  1. /*
  2. * linux/drivers/video/omap2/dss/dpi.c
  3. *
  4. * Copyright (C) 2009 Nokia Corporation
  5. * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  6. *
  7. * Some code and ideas taken from drivers/video/omap/ driver
  8. * by Imre Deak.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License version 2 as published by
  12. * the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but WITHOUT
  15. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  17. * more details.
  18. *
  19. * You should have received a copy of the GNU General Public License along with
  20. * this program. If not, see <http://www.gnu.org/licenses/>.
  21. */
  22. #define DSS_SUBSYS_NAME "DPI"
  23. #include <linux/kernel.h>
  24. #include <linux/delay.h>
  25. #include <linux/err.h>
  26. #include <linux/errno.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/regulator/consumer.h>
  29. #include <video/omapdss.h>
  30. #include <plat/cpu.h>
  31. #include "dss.h"
  32. static struct {
  33. struct regulator *vdds_dsi_reg;
  34. struct platform_device *dsidev;
  35. } dpi;
  36. static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
  37. {
  38. int dsi_module;
  39. dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
  40. return dsi_get_dsidev_from_id(dsi_module);
  41. }
  42. static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
  43. {
  44. if (dssdev->clocks.dispc.dispc_fclk_src ==
  45. OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
  46. dssdev->clocks.dispc.dispc_fclk_src ==
  47. OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
  48. dssdev->clocks.dispc.channel.lcd_clk_src ==
  49. OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
  50. dssdev->clocks.dispc.channel.lcd_clk_src ==
  51. OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
  52. return true;
  53. else
  54. return false;
  55. }
  56. static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
  57. unsigned long pck_req, unsigned long *fck, int *lck_div,
  58. int *pck_div)
  59. {
  60. struct dsi_clock_info dsi_cinfo;
  61. struct dispc_clock_info dispc_cinfo;
  62. int r;
  63. r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
  64. &dsi_cinfo, &dispc_cinfo);
  65. if (r)
  66. return r;
  67. r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
  68. if (r)
  69. return r;
  70. dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
  71. r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
  72. if (r)
  73. return r;
  74. *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
  75. *lck_div = dispc_cinfo.lck_div;
  76. *pck_div = dispc_cinfo.pck_div;
  77. return 0;
  78. }
  79. static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
  80. unsigned long pck_req, unsigned long *fck, int *lck_div,
  81. int *pck_div)
  82. {
  83. struct dss_clock_info dss_cinfo;
  84. struct dispc_clock_info dispc_cinfo;
  85. int r;
  86. r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
  87. if (r)
  88. return r;
  89. r = dss_set_clock_div(&dss_cinfo);
  90. if (r)
  91. return r;
  92. r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
  93. if (r)
  94. return r;
  95. *fck = dss_cinfo.fck;
  96. *lck_div = dispc_cinfo.lck_div;
  97. *pck_div = dispc_cinfo.pck_div;
  98. return 0;
  99. }
  100. static int dpi_set_mode(struct omap_dss_device *dssdev)
  101. {
  102. struct omap_video_timings *t = &dssdev->panel.timings;
  103. int lck_div = 0, pck_div = 0;
  104. unsigned long fck = 0;
  105. unsigned long pck;
  106. bool is_tft;
  107. int r = 0;
  108. dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
  109. dssdev->panel.acbi, dssdev->panel.acb);
  110. is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
  111. if (dpi_use_dsi_pll(dssdev))
  112. r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
  113. &fck, &lck_div, &pck_div);
  114. else
  115. r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
  116. &fck, &lck_div, &pck_div);
  117. if (r)
  118. return r;
  119. pck = fck / lck_div / pck_div / 1000;
  120. if (pck != t->pixel_clock) {
  121. DSSWARN("Could not find exact pixel clock. "
  122. "Requested %d kHz, got %lu kHz\n",
  123. t->pixel_clock, pck);
  124. t->pixel_clock = pck;
  125. }
  126. dispc_set_lcd_timings(dssdev->manager->id, t);
  127. return 0;
  128. }
  129. static void dpi_basic_init(struct omap_dss_device *dssdev)
  130. {
  131. bool is_tft;
  132. is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
  133. dispc_set_parallel_interface_mode(dssdev->manager->id,
  134. OMAP_DSS_PARALLELMODE_BYPASS);
  135. dispc_set_lcd_display_type(dssdev->manager->id, is_tft ?
  136. OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
  137. dispc_set_tft_data_lines(dssdev->manager->id,
  138. dssdev->phy.dpi.data_lines);
  139. }
  140. int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
  141. {
  142. int r;
  143. if (dssdev->manager == NULL) {
  144. DSSERR("failed to enable display: no manager\n");
  145. return -ENODEV;
  146. }
  147. r = omap_dss_start_device(dssdev);
  148. if (r) {
  149. DSSERR("failed to start device\n");
  150. goto err_start_dev;
  151. }
  152. if (cpu_is_omap34xx()) {
  153. r = regulator_enable(dpi.vdds_dsi_reg);
  154. if (r)
  155. goto err_reg_enable;
  156. }
  157. r = dss_runtime_get();
  158. if (r)
  159. goto err_get_dss;
  160. r = dispc_runtime_get();
  161. if (r)
  162. goto err_get_dispc;
  163. dpi_basic_init(dssdev);
  164. if (dpi_use_dsi_pll(dssdev)) {
  165. r = dsi_runtime_get(dpi.dsidev);
  166. if (r)
  167. goto err_get_dsi;
  168. r = dsi_pll_init(dpi.dsidev, 0, 1);
  169. if (r)
  170. goto err_dsi_pll_init;
  171. }
  172. r = dpi_set_mode(dssdev);
  173. if (r)
  174. goto err_set_mode;
  175. mdelay(2);
  176. dssdev->manager->enable(dssdev->manager);
  177. return 0;
  178. err_set_mode:
  179. if (dpi_use_dsi_pll(dssdev))
  180. dsi_pll_uninit(dpi.dsidev, true);
  181. err_dsi_pll_init:
  182. if (dpi_use_dsi_pll(dssdev))
  183. dsi_runtime_put(dpi.dsidev);
  184. err_get_dsi:
  185. dispc_runtime_put();
  186. err_get_dispc:
  187. dss_runtime_put();
  188. err_get_dss:
  189. if (cpu_is_omap34xx())
  190. regulator_disable(dpi.vdds_dsi_reg);
  191. err_reg_enable:
  192. omap_dss_stop_device(dssdev);
  193. err_start_dev:
  194. return r;
  195. }
  196. EXPORT_SYMBOL(omapdss_dpi_display_enable);
  197. void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
  198. {
  199. dssdev->manager->disable(dssdev->manager);
  200. if (dpi_use_dsi_pll(dssdev)) {
  201. dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
  202. dsi_pll_uninit(dpi.dsidev, true);
  203. dsi_runtime_put(dpi.dsidev);
  204. }
  205. dispc_runtime_put();
  206. dss_runtime_put();
  207. if (cpu_is_omap34xx())
  208. regulator_disable(dpi.vdds_dsi_reg);
  209. omap_dss_stop_device(dssdev);
  210. }
  211. EXPORT_SYMBOL(omapdss_dpi_display_disable);
  212. void dpi_set_timings(struct omap_dss_device *dssdev,
  213. struct omap_video_timings *timings)
  214. {
  215. int r;
  216. DSSDBG("dpi_set_timings\n");
  217. dssdev->panel.timings = *timings;
  218. if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
  219. r = dss_runtime_get();
  220. if (r)
  221. return;
  222. r = dispc_runtime_get();
  223. if (r) {
  224. dss_runtime_put();
  225. return;
  226. }
  227. dpi_set_mode(dssdev);
  228. dispc_go(dssdev->manager->id);
  229. dispc_runtime_put();
  230. dss_runtime_put();
  231. }
  232. }
  233. EXPORT_SYMBOL(dpi_set_timings);
  234. int dpi_check_timings(struct omap_dss_device *dssdev,
  235. struct omap_video_timings *timings)
  236. {
  237. bool is_tft;
  238. int r;
  239. int lck_div, pck_div;
  240. unsigned long fck;
  241. unsigned long pck;
  242. struct dispc_clock_info dispc_cinfo;
  243. if (!dispc_lcd_timings_ok(timings))
  244. return -EINVAL;
  245. if (timings->pixel_clock == 0)
  246. return -EINVAL;
  247. is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
  248. if (dpi_use_dsi_pll(dssdev)) {
  249. struct dsi_clock_info dsi_cinfo;
  250. r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
  251. timings->pixel_clock * 1000,
  252. &dsi_cinfo, &dispc_cinfo);
  253. if (r)
  254. return r;
  255. fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
  256. } else {
  257. struct dss_clock_info dss_cinfo;
  258. r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
  259. &dss_cinfo, &dispc_cinfo);
  260. if (r)
  261. return r;
  262. fck = dss_cinfo.fck;
  263. }
  264. lck_div = dispc_cinfo.lck_div;
  265. pck_div = dispc_cinfo.pck_div;
  266. pck = fck / lck_div / pck_div / 1000;
  267. timings->pixel_clock = pck;
  268. return 0;
  269. }
  270. EXPORT_SYMBOL(dpi_check_timings);
  271. int dpi_init_display(struct omap_dss_device *dssdev)
  272. {
  273. DSSDBG("init_display\n");
  274. if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
  275. struct regulator *vdds_dsi;
  276. vdds_dsi = dss_get_vdds_dsi();
  277. if (IS_ERR(vdds_dsi)) {
  278. DSSERR("can't get VDDS_DSI regulator\n");
  279. return PTR_ERR(vdds_dsi);
  280. }
  281. dpi.vdds_dsi_reg = vdds_dsi;
  282. }
  283. if (dpi_use_dsi_pll(dssdev)) {
  284. enum omap_dss_clk_source dispc_fclk_src =
  285. dssdev->clocks.dispc.dispc_fclk_src;
  286. dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);
  287. }
  288. return 0;
  289. }
  290. int dpi_init(void)
  291. {
  292. return 0;
  293. }
  294. void dpi_exit(void)
  295. {
  296. }