at91sam9g45.dtsi 6.4 KB

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  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9G45 family SoC";
  14. compatible = "atmel,at91sam9g45";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. serial4 = &usart3;
  22. gpio0 = &pioA;
  23. gpio1 = &pioB;
  24. gpio2 = &pioC;
  25. gpio3 = &pioD;
  26. gpio4 = &pioE;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. i2c1 = &i2c1;
  31. };
  32. cpus {
  33. cpu@0 {
  34. compatible = "arm,arm926ejs";
  35. };
  36. };
  37. memory {
  38. reg = <0x70000000 0x10000000>;
  39. };
  40. ahb {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. apb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. aic: interrupt-controller@fffff000 {
  51. #interrupt-cells = <3>;
  52. compatible = "atmel,at91rm9200-aic";
  53. interrupt-controller;
  54. reg = <0xfffff000 0x200>;
  55. atmel,external-irqs = <31>;
  56. };
  57. ramc0: ramc@ffffe400 {
  58. compatible = "atmel,at91sam9g45-ddramc";
  59. reg = <0xffffe400 0x200
  60. 0xffffe600 0x200>;
  61. };
  62. pmc: pmc@fffffc00 {
  63. compatible = "atmel,at91rm9200-pmc";
  64. reg = <0xfffffc00 0x100>;
  65. };
  66. rstc@fffffd00 {
  67. compatible = "atmel,at91sam9g45-rstc";
  68. reg = <0xfffffd00 0x10>;
  69. };
  70. pit: timer@fffffd30 {
  71. compatible = "atmel,at91sam9260-pit";
  72. reg = <0xfffffd30 0xf>;
  73. interrupts = <1 4 7>;
  74. };
  75. shdwc@fffffd10 {
  76. compatible = "atmel,at91sam9rl-shdwc";
  77. reg = <0xfffffd10 0x10>;
  78. };
  79. tcb0: timer@fff7c000 {
  80. compatible = "atmel,at91rm9200-tcb";
  81. reg = <0xfff7c000 0x100>;
  82. interrupts = <18 4 0>;
  83. };
  84. tcb1: timer@fffd4000 {
  85. compatible = "atmel,at91rm9200-tcb";
  86. reg = <0xfffd4000 0x100>;
  87. interrupts = <18 4 0>;
  88. };
  89. dma: dma-controller@ffffec00 {
  90. compatible = "atmel,at91sam9g45-dma";
  91. reg = <0xffffec00 0x200>;
  92. interrupts = <21 4 0>;
  93. };
  94. pioA: gpio@fffff200 {
  95. compatible = "atmel,at91rm9200-gpio";
  96. reg = <0xfffff200 0x100>;
  97. interrupts = <2 4 1>;
  98. #gpio-cells = <2>;
  99. gpio-controller;
  100. interrupt-controller;
  101. };
  102. pioB: gpio@fffff400 {
  103. compatible = "atmel,at91rm9200-gpio";
  104. reg = <0xfffff400 0x100>;
  105. interrupts = <3 4 1>;
  106. #gpio-cells = <2>;
  107. gpio-controller;
  108. interrupt-controller;
  109. };
  110. pioC: gpio@fffff600 {
  111. compatible = "atmel,at91rm9200-gpio";
  112. reg = <0xfffff600 0x100>;
  113. interrupts = <4 4 1>;
  114. #gpio-cells = <2>;
  115. gpio-controller;
  116. interrupt-controller;
  117. };
  118. pioD: gpio@fffff800 {
  119. compatible = "atmel,at91rm9200-gpio";
  120. reg = <0xfffff800 0x100>;
  121. interrupts = <5 4 1>;
  122. #gpio-cells = <2>;
  123. gpio-controller;
  124. interrupt-controller;
  125. };
  126. pioE: gpio@fffffa00 {
  127. compatible = "atmel,at91rm9200-gpio";
  128. reg = <0xfffffa00 0x100>;
  129. interrupts = <5 4 1>;
  130. #gpio-cells = <2>;
  131. gpio-controller;
  132. interrupt-controller;
  133. };
  134. dbgu: serial@ffffee00 {
  135. compatible = "atmel,at91sam9260-usart";
  136. reg = <0xffffee00 0x200>;
  137. interrupts = <1 4 7>;
  138. status = "disabled";
  139. };
  140. usart0: serial@fff8c000 {
  141. compatible = "atmel,at91sam9260-usart";
  142. reg = <0xfff8c000 0x200>;
  143. interrupts = <7 4 5>;
  144. atmel,use-dma-rx;
  145. atmel,use-dma-tx;
  146. status = "disabled";
  147. };
  148. usart1: serial@fff90000 {
  149. compatible = "atmel,at91sam9260-usart";
  150. reg = <0xfff90000 0x200>;
  151. interrupts = <8 4 5>;
  152. atmel,use-dma-rx;
  153. atmel,use-dma-tx;
  154. status = "disabled";
  155. };
  156. usart2: serial@fff94000 {
  157. compatible = "atmel,at91sam9260-usart";
  158. reg = <0xfff94000 0x200>;
  159. interrupts = <9 4 5>;
  160. atmel,use-dma-rx;
  161. atmel,use-dma-tx;
  162. status = "disabled";
  163. };
  164. usart3: serial@fff98000 {
  165. compatible = "atmel,at91sam9260-usart";
  166. reg = <0xfff98000 0x200>;
  167. interrupts = <10 4 5>;
  168. atmel,use-dma-rx;
  169. atmel,use-dma-tx;
  170. status = "disabled";
  171. };
  172. macb0: ethernet@fffbc000 {
  173. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  174. reg = <0xfffbc000 0x100>;
  175. interrupts = <25 4 3>;
  176. status = "disabled";
  177. };
  178. i2c0: i2c@fff84000 {
  179. compatible = "atmel,at91sam9g10-i2c";
  180. reg = <0xfff84000 0x100>;
  181. interrupts = <12 4 6>;
  182. #address-cells = <1>;
  183. #size-cells = <0>;
  184. status = "disabled";
  185. };
  186. i2c1: i2c@fff88000 {
  187. compatible = "atmel,at91sam9g10-i2c";
  188. reg = <0xfff88000 0x100>;
  189. interrupts = <13 4 6>;
  190. #address-cells = <1>;
  191. #size-cells = <0>;
  192. status = "disabled";
  193. };
  194. adc0: adc@fffb0000 {
  195. compatible = "atmel,at91sam9260-adc";
  196. reg = <0xfffb0000 0x100>;
  197. interrupts = <20 4 0>;
  198. atmel,adc-use-external-triggers;
  199. atmel,adc-channels-used = <0xff>;
  200. atmel,adc-vref = <3300>;
  201. atmel,adc-num-channels = <8>;
  202. atmel,adc-startup-time = <40>;
  203. atmel,adc-channel-base = <0x30>;
  204. atmel,adc-drdy-mask = <0x10000>;
  205. atmel,adc-status-register = <0x1c>;
  206. atmel,adc-trigger-register = <0x08>;
  207. trigger@0 {
  208. trigger-name = "external-rising";
  209. trigger-value = <0x1>;
  210. trigger-external;
  211. };
  212. trigger@1 {
  213. trigger-name = "external-falling";
  214. trigger-value = <0x2>;
  215. trigger-external;
  216. };
  217. trigger@2 {
  218. trigger-name = "external-any";
  219. trigger-value = <0x3>;
  220. trigger-external;
  221. };
  222. trigger@3 {
  223. trigger-name = "continuous";
  224. trigger-value = <0x6>;
  225. };
  226. };
  227. };
  228. nand0: nand@40000000 {
  229. compatible = "atmel,at91rm9200-nand";
  230. #address-cells = <1>;
  231. #size-cells = <1>;
  232. reg = <0x40000000 0x10000000
  233. 0xffffe200 0x200
  234. >;
  235. atmel,nand-addr-offset = <21>;
  236. atmel,nand-cmd-offset = <22>;
  237. gpios = <&pioC 8 0
  238. &pioC 14 0
  239. 0
  240. >;
  241. status = "disabled";
  242. };
  243. usb0: ohci@00700000 {
  244. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  245. reg = <0x00700000 0x100000>;
  246. interrupts = <22 4 2>;
  247. status = "disabled";
  248. };
  249. usb1: ehci@00800000 {
  250. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  251. reg = <0x00800000 0x100000>;
  252. interrupts = <22 4 2>;
  253. status = "disabled";
  254. };
  255. };
  256. i2c@0 {
  257. compatible = "i2c-gpio";
  258. gpios = <&pioA 20 0 /* sda */
  259. &pioA 21 0 /* scl */
  260. >;
  261. i2c-gpio,sda-open-drain;
  262. i2c-gpio,scl-open-drain;
  263. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  264. #address-cells = <1>;
  265. #size-cells = <0>;
  266. status = "disabled";
  267. };
  268. };