netxen_nic_init.c 39 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. u32 addr;
  40. u32 data;
  41. };
  42. #define NETXEN_MAX_CRB_XFORM 60
  43. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  44. #define NETXEN_ADDR_ERROR (0xffffffff)
  45. #define crb_addr_transform(name) \
  46. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  47. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  48. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  49. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  50. uint32_t ctx, uint32_t ringid);
  51. #if 0
  52. static void netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
  53. unsigned long off, int *data)
  54. {
  55. void __iomem *addr = pci_base_offset(adapter, off);
  56. writel(*data, addr);
  57. }
  58. #endif /* 0 */
  59. static void crb_addr_transform_setup(void)
  60. {
  61. crb_addr_transform(XDMA);
  62. crb_addr_transform(TIMR);
  63. crb_addr_transform(SRE);
  64. crb_addr_transform(SQN3);
  65. crb_addr_transform(SQN2);
  66. crb_addr_transform(SQN1);
  67. crb_addr_transform(SQN0);
  68. crb_addr_transform(SQS3);
  69. crb_addr_transform(SQS2);
  70. crb_addr_transform(SQS1);
  71. crb_addr_transform(SQS0);
  72. crb_addr_transform(RPMX7);
  73. crb_addr_transform(RPMX6);
  74. crb_addr_transform(RPMX5);
  75. crb_addr_transform(RPMX4);
  76. crb_addr_transform(RPMX3);
  77. crb_addr_transform(RPMX2);
  78. crb_addr_transform(RPMX1);
  79. crb_addr_transform(RPMX0);
  80. crb_addr_transform(ROMUSB);
  81. crb_addr_transform(SN);
  82. crb_addr_transform(QMN);
  83. crb_addr_transform(QMS);
  84. crb_addr_transform(PGNI);
  85. crb_addr_transform(PGND);
  86. crb_addr_transform(PGN3);
  87. crb_addr_transform(PGN2);
  88. crb_addr_transform(PGN1);
  89. crb_addr_transform(PGN0);
  90. crb_addr_transform(PGSI);
  91. crb_addr_transform(PGSD);
  92. crb_addr_transform(PGS3);
  93. crb_addr_transform(PGS2);
  94. crb_addr_transform(PGS1);
  95. crb_addr_transform(PGS0);
  96. crb_addr_transform(PS);
  97. crb_addr_transform(PH);
  98. crb_addr_transform(NIU);
  99. crb_addr_transform(I2Q);
  100. crb_addr_transform(EG);
  101. crb_addr_transform(MN);
  102. crb_addr_transform(MS);
  103. crb_addr_transform(CAS2);
  104. crb_addr_transform(CAS1);
  105. crb_addr_transform(CAS0);
  106. crb_addr_transform(CAM);
  107. crb_addr_transform(C2C1);
  108. crb_addr_transform(C2C0);
  109. crb_addr_transform(SMB);
  110. crb_addr_transform(OCM0);
  111. crb_addr_transform(I2C0);
  112. }
  113. int netxen_init_firmware(struct netxen_adapter *adapter)
  114. {
  115. u32 state = 0, loops = 0, err = 0;
  116. /* Window 1 call */
  117. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  118. if (state == PHAN_INITIALIZE_ACK)
  119. return 0;
  120. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  121. msleep(1);
  122. /* Window 1 call */
  123. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  124. loops++;
  125. }
  126. if (loops >= 2000) {
  127. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  128. state);
  129. err = -EIO;
  130. return err;
  131. }
  132. /* Window 1 call */
  133. adapter->pci_write_normalize(adapter,
  134. CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  135. adapter->pci_write_normalize(adapter,
  136. CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  137. adapter->pci_write_normalize(adapter,
  138. CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  139. adapter->pci_write_normalize(adapter,
  140. CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  141. return err;
  142. }
  143. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  144. {
  145. struct netxen_recv_context *recv_ctx;
  146. struct nx_host_rds_ring *rds_ring;
  147. struct netxen_rx_buffer *rx_buf;
  148. int i, ctxid, ring;
  149. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  150. recv_ctx = &adapter->recv_ctx[ctxid];
  151. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  152. rds_ring = &recv_ctx->rds_rings[ring];
  153. for (i = 0; i < rds_ring->max_rx_desc_count; ++i) {
  154. rx_buf = &(rds_ring->rx_buf_arr[i]);
  155. if (rx_buf->state == NETXEN_BUFFER_FREE)
  156. continue;
  157. pci_unmap_single(adapter->pdev,
  158. rx_buf->dma,
  159. rds_ring->dma_size,
  160. PCI_DMA_FROMDEVICE);
  161. if (rx_buf->skb != NULL)
  162. dev_kfree_skb_any(rx_buf->skb);
  163. }
  164. }
  165. }
  166. }
  167. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  168. {
  169. struct netxen_cmd_buffer *cmd_buf;
  170. struct netxen_skb_frag *buffrag;
  171. int i, j;
  172. cmd_buf = adapter->cmd_buf_arr;
  173. for (i = 0; i < adapter->max_tx_desc_count; i++) {
  174. buffrag = cmd_buf->frag_array;
  175. if (buffrag->dma) {
  176. pci_unmap_single(adapter->pdev, buffrag->dma,
  177. buffrag->length, PCI_DMA_TODEVICE);
  178. buffrag->dma = 0ULL;
  179. }
  180. for (j = 0; j < cmd_buf->frag_count; j++) {
  181. buffrag++;
  182. if (buffrag->dma) {
  183. pci_unmap_page(adapter->pdev, buffrag->dma,
  184. buffrag->length,
  185. PCI_DMA_TODEVICE);
  186. buffrag->dma = 0ULL;
  187. }
  188. }
  189. /* Free the skb we received in netxen_nic_xmit_frame */
  190. if (cmd_buf->skb) {
  191. dev_kfree_skb_any(cmd_buf->skb);
  192. cmd_buf->skb = NULL;
  193. }
  194. cmd_buf++;
  195. }
  196. }
  197. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  198. {
  199. struct netxen_recv_context *recv_ctx;
  200. struct nx_host_rds_ring *rds_ring;
  201. int ctx, ring;
  202. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  203. recv_ctx = &adapter->recv_ctx[ctx];
  204. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  205. rds_ring = &recv_ctx->rds_rings[ring];
  206. if (rds_ring->rx_buf_arr) {
  207. vfree(rds_ring->rx_buf_arr);
  208. rds_ring->rx_buf_arr = NULL;
  209. }
  210. }
  211. }
  212. if (adapter->cmd_buf_arr)
  213. vfree(adapter->cmd_buf_arr);
  214. return;
  215. }
  216. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  217. {
  218. struct netxen_recv_context *recv_ctx;
  219. struct nx_host_rds_ring *rds_ring;
  220. struct netxen_rx_buffer *rx_buf;
  221. int ctx, ring, i, num_rx_bufs;
  222. struct netxen_cmd_buffer *cmd_buf_arr;
  223. struct net_device *netdev = adapter->netdev;
  224. cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE);
  225. if (cmd_buf_arr == NULL) {
  226. printk(KERN_ERR "%s: Failed to allocate cmd buffer ring\n",
  227. netdev->name);
  228. return -ENOMEM;
  229. }
  230. memset(cmd_buf_arr, 0, TX_RINGSIZE);
  231. adapter->cmd_buf_arr = cmd_buf_arr;
  232. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  233. recv_ctx = &adapter->recv_ctx[ctx];
  234. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  235. rds_ring = &recv_ctx->rds_rings[ring];
  236. switch (RCV_DESC_TYPE(ring)) {
  237. case RCV_DESC_NORMAL:
  238. rds_ring->max_rx_desc_count =
  239. adapter->max_rx_desc_count;
  240. rds_ring->flags = RCV_DESC_NORMAL;
  241. if (adapter->ahw.cut_through) {
  242. rds_ring->dma_size =
  243. NX_CT_DEFAULT_RX_BUF_LEN;
  244. rds_ring->skb_size =
  245. NX_CT_DEFAULT_RX_BUF_LEN;
  246. } else {
  247. rds_ring->dma_size = RX_DMA_MAP_LEN;
  248. rds_ring->skb_size =
  249. MAX_RX_BUFFER_LENGTH;
  250. }
  251. break;
  252. case RCV_DESC_JUMBO:
  253. rds_ring->max_rx_desc_count =
  254. adapter->max_jumbo_rx_desc_count;
  255. rds_ring->flags = RCV_DESC_JUMBO;
  256. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  257. rds_ring->dma_size =
  258. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  259. else
  260. rds_ring->dma_size =
  261. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  262. rds_ring->skb_size =
  263. rds_ring->dma_size + NET_IP_ALIGN;
  264. break;
  265. case RCV_RING_LRO:
  266. rds_ring->max_rx_desc_count =
  267. adapter->max_lro_rx_desc_count;
  268. rds_ring->flags = RCV_DESC_LRO;
  269. rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
  270. rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  271. break;
  272. }
  273. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  274. vmalloc(RCV_BUFFSIZE);
  275. if (rds_ring->rx_buf_arr == NULL) {
  276. printk(KERN_ERR "%s: Failed to allocate "
  277. "rx buffer ring %d\n",
  278. netdev->name, ring);
  279. /* free whatever was already allocated */
  280. goto err_out;
  281. }
  282. memset(rds_ring->rx_buf_arr, 0, RCV_BUFFSIZE);
  283. INIT_LIST_HEAD(&rds_ring->free_list);
  284. /*
  285. * Now go through all of them, set reference handles
  286. * and put them in the queues.
  287. */
  288. num_rx_bufs = rds_ring->max_rx_desc_count;
  289. rx_buf = rds_ring->rx_buf_arr;
  290. for (i = 0; i < num_rx_bufs; i++) {
  291. list_add_tail(&rx_buf->list,
  292. &rds_ring->free_list);
  293. rx_buf->ref_handle = i;
  294. rx_buf->state = NETXEN_BUFFER_FREE;
  295. rx_buf++;
  296. }
  297. }
  298. }
  299. return 0;
  300. err_out:
  301. netxen_free_sw_resources(adapter);
  302. return -ENOMEM;
  303. }
  304. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  305. {
  306. switch (adapter->ahw.board_type) {
  307. case NETXEN_NIC_GBE:
  308. adapter->enable_phy_interrupts =
  309. netxen_niu_gbe_enable_phy_interrupts;
  310. adapter->disable_phy_interrupts =
  311. netxen_niu_gbe_disable_phy_interrupts;
  312. adapter->macaddr_set = netxen_niu_macaddr_set;
  313. adapter->set_mtu = netxen_nic_set_mtu_gb;
  314. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  315. adapter->phy_read = netxen_niu_gbe_phy_read;
  316. adapter->phy_write = netxen_niu_gbe_phy_write;
  317. adapter->init_port = netxen_niu_gbe_init_port;
  318. adapter->stop_port = netxen_niu_disable_gbe_port;
  319. break;
  320. case NETXEN_NIC_XGBE:
  321. adapter->enable_phy_interrupts =
  322. netxen_niu_xgbe_enable_phy_interrupts;
  323. adapter->disable_phy_interrupts =
  324. netxen_niu_xgbe_disable_phy_interrupts;
  325. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  326. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  327. adapter->init_port = netxen_niu_xg_init_port;
  328. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  329. adapter->stop_port = netxen_niu_disable_xg_port;
  330. break;
  331. default:
  332. break;
  333. }
  334. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  335. adapter->set_mtu = nx_fw_cmd_set_mtu;
  336. adapter->set_promisc = netxen_p3_nic_set_promisc;
  337. }
  338. }
  339. /*
  340. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  341. * address to external PCI CRB address.
  342. */
  343. static u32 netxen_decode_crb_addr(u32 addr)
  344. {
  345. int i;
  346. u32 base_addr, offset, pci_base;
  347. crb_addr_transform_setup();
  348. pci_base = NETXEN_ADDR_ERROR;
  349. base_addr = addr & 0xfff00000;
  350. offset = addr & 0x000fffff;
  351. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  352. if (crb_addr_xform[i] == base_addr) {
  353. pci_base = i << 20;
  354. break;
  355. }
  356. }
  357. if (pci_base == NETXEN_ADDR_ERROR)
  358. return pci_base;
  359. else
  360. return (pci_base + offset);
  361. }
  362. static long rom_max_timeout = 100;
  363. static long rom_lock_timeout = 10000;
  364. #if 0
  365. static long rom_write_timeout = 700;
  366. #endif
  367. static int rom_lock(struct netxen_adapter *adapter)
  368. {
  369. int iter;
  370. u32 done = 0;
  371. int timeout = 0;
  372. while (!done) {
  373. /* acquire semaphore2 from PCI HW block */
  374. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  375. &done);
  376. if (done == 1)
  377. break;
  378. if (timeout >= rom_lock_timeout)
  379. return -EIO;
  380. timeout++;
  381. /*
  382. * Yield CPU
  383. */
  384. if (!in_atomic())
  385. schedule();
  386. else {
  387. for (iter = 0; iter < 20; iter++)
  388. cpu_relax(); /*This a nop instr on i386 */
  389. }
  390. }
  391. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  392. return 0;
  393. }
  394. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  395. {
  396. long timeout = 0;
  397. long done = 0;
  398. cond_resched();
  399. while (done == 0) {
  400. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  401. done &= 2;
  402. timeout++;
  403. if (timeout >= rom_max_timeout) {
  404. printk("Timeout reached waiting for rom done");
  405. return -EIO;
  406. }
  407. }
  408. return 0;
  409. }
  410. #if 0
  411. static int netxen_rom_wren(struct netxen_adapter *adapter)
  412. {
  413. /* Set write enable latch in ROM status register */
  414. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  415. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  416. M25P_INSTR_WREN);
  417. if (netxen_wait_rom_done(adapter)) {
  418. return -1;
  419. }
  420. return 0;
  421. }
  422. static unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
  423. unsigned int addr)
  424. {
  425. unsigned int data = 0xdeaddead;
  426. data = netxen_nic_reg_read(adapter, addr);
  427. return data;
  428. }
  429. static int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
  430. {
  431. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  432. M25P_INSTR_RDSR);
  433. if (netxen_wait_rom_done(adapter)) {
  434. return -1;
  435. }
  436. return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
  437. }
  438. #endif
  439. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  440. {
  441. u32 val;
  442. /* release semaphore2 */
  443. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  444. }
  445. #if 0
  446. static int netxen_rom_wip_poll(struct netxen_adapter *adapter)
  447. {
  448. long timeout = 0;
  449. long wip = 1;
  450. int val;
  451. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  452. while (wip != 0) {
  453. val = netxen_do_rom_rdsr(adapter);
  454. wip = val & 1;
  455. timeout++;
  456. if (timeout > rom_max_timeout) {
  457. return -1;
  458. }
  459. }
  460. return 0;
  461. }
  462. static int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
  463. int data)
  464. {
  465. if (netxen_rom_wren(adapter)) {
  466. return -1;
  467. }
  468. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  469. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  470. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  471. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  472. M25P_INSTR_PP);
  473. if (netxen_wait_rom_done(adapter)) {
  474. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  475. return -1;
  476. }
  477. return netxen_rom_wip_poll(adapter);
  478. }
  479. #endif
  480. static int do_rom_fast_read(struct netxen_adapter *adapter,
  481. int addr, int *valp)
  482. {
  483. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  484. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  485. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  486. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  487. if (netxen_wait_rom_done(adapter)) {
  488. printk("Error waiting for rom done\n");
  489. return -EIO;
  490. }
  491. /* reset abyte_cnt and dummy_byte_cnt */
  492. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  493. udelay(10);
  494. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  495. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  496. return 0;
  497. }
  498. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  499. u8 *bytes, size_t size)
  500. {
  501. int addridx;
  502. int ret = 0;
  503. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  504. int v;
  505. ret = do_rom_fast_read(adapter, addridx, &v);
  506. if (ret != 0)
  507. break;
  508. *(__le32 *)bytes = cpu_to_le32(v);
  509. bytes += 4;
  510. }
  511. return ret;
  512. }
  513. int
  514. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  515. u8 *bytes, size_t size)
  516. {
  517. int ret;
  518. ret = rom_lock(adapter);
  519. if (ret < 0)
  520. return ret;
  521. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  522. netxen_rom_unlock(adapter);
  523. return ret;
  524. }
  525. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  526. {
  527. int ret;
  528. if (rom_lock(adapter) != 0)
  529. return -EIO;
  530. ret = do_rom_fast_read(adapter, addr, valp);
  531. netxen_rom_unlock(adapter);
  532. return ret;
  533. }
  534. #if 0
  535. int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
  536. {
  537. int ret = 0;
  538. if (rom_lock(adapter) != 0) {
  539. return -1;
  540. }
  541. ret = do_rom_fast_write(adapter, addr, data);
  542. netxen_rom_unlock(adapter);
  543. return ret;
  544. }
  545. static int do_rom_fast_write_words(struct netxen_adapter *adapter,
  546. int addr, u8 *bytes, size_t size)
  547. {
  548. int addridx = addr;
  549. int ret = 0;
  550. while (addridx < (addr + size)) {
  551. int last_attempt = 0;
  552. int timeout = 0;
  553. int data;
  554. data = le32_to_cpu((*(__le32*)bytes));
  555. ret = do_rom_fast_write(adapter, addridx, data);
  556. if (ret < 0)
  557. return ret;
  558. while(1) {
  559. int data1;
  560. ret = do_rom_fast_read(adapter, addridx, &data1);
  561. if (ret < 0)
  562. return ret;
  563. if (data1 == data)
  564. break;
  565. if (timeout++ >= rom_write_timeout) {
  566. if (last_attempt++ < 4) {
  567. ret = do_rom_fast_write(adapter,
  568. addridx, data);
  569. if (ret < 0)
  570. return ret;
  571. }
  572. else {
  573. printk(KERN_INFO "Data write did not "
  574. "succeed at address 0x%x\n", addridx);
  575. break;
  576. }
  577. }
  578. }
  579. bytes += 4;
  580. addridx += 4;
  581. }
  582. return ret;
  583. }
  584. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  585. u8 *bytes, size_t size)
  586. {
  587. int ret = 0;
  588. ret = rom_lock(adapter);
  589. if (ret < 0)
  590. return ret;
  591. ret = do_rom_fast_write_words(adapter, addr, bytes, size);
  592. netxen_rom_unlock(adapter);
  593. return ret;
  594. }
  595. static int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
  596. {
  597. int ret;
  598. ret = netxen_rom_wren(adapter);
  599. if (ret < 0)
  600. return ret;
  601. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  602. netxen_crb_writelit_adapter(adapter,
  603. NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
  604. ret = netxen_wait_rom_done(adapter);
  605. if (ret < 0)
  606. return ret;
  607. return netxen_rom_wip_poll(adapter);
  608. }
  609. static int netxen_rom_rdsr(struct netxen_adapter *adapter)
  610. {
  611. int ret;
  612. ret = rom_lock(adapter);
  613. if (ret < 0)
  614. return ret;
  615. ret = netxen_do_rom_rdsr(adapter);
  616. netxen_rom_unlock(adapter);
  617. return ret;
  618. }
  619. int netxen_backup_crbinit(struct netxen_adapter *adapter)
  620. {
  621. int ret = FLASH_SUCCESS;
  622. int val;
  623. char *buffer = kmalloc(NETXEN_FLASH_SECTOR_SIZE, GFP_KERNEL);
  624. if (!buffer)
  625. return -ENOMEM;
  626. /* unlock sector 63 */
  627. val = netxen_rom_rdsr(adapter);
  628. val = val & 0xe3;
  629. ret = netxen_rom_wrsr(adapter, val);
  630. if (ret != FLASH_SUCCESS)
  631. goto out_kfree;
  632. ret = netxen_rom_wip_poll(adapter);
  633. if (ret != FLASH_SUCCESS)
  634. goto out_kfree;
  635. /* copy sector 0 to sector 63 */
  636. ret = netxen_rom_fast_read_words(adapter, NETXEN_CRBINIT_START,
  637. buffer, NETXEN_FLASH_SECTOR_SIZE);
  638. if (ret != FLASH_SUCCESS)
  639. goto out_kfree;
  640. ret = netxen_rom_fast_write_words(adapter, NETXEN_FIXED_START,
  641. buffer, NETXEN_FLASH_SECTOR_SIZE);
  642. if (ret != FLASH_SUCCESS)
  643. goto out_kfree;
  644. /* lock sector 63 */
  645. val = netxen_rom_rdsr(adapter);
  646. if (!(val & 0x8)) {
  647. val |= (0x1 << 2);
  648. /* lock sector 63 */
  649. if (netxen_rom_wrsr(adapter, val) == 0) {
  650. ret = netxen_rom_wip_poll(adapter);
  651. if (ret != FLASH_SUCCESS)
  652. goto out_kfree;
  653. /* lock SR writes */
  654. ret = netxen_rom_wip_poll(adapter);
  655. if (ret != FLASH_SUCCESS)
  656. goto out_kfree;
  657. }
  658. }
  659. out_kfree:
  660. kfree(buffer);
  661. return ret;
  662. }
  663. static int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
  664. {
  665. netxen_rom_wren(adapter);
  666. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  667. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  668. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  669. M25P_INSTR_SE);
  670. if (netxen_wait_rom_done(adapter)) {
  671. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  672. return -1;
  673. }
  674. return netxen_rom_wip_poll(adapter);
  675. }
  676. static void check_erased_flash(struct netxen_adapter *adapter, int addr)
  677. {
  678. int i;
  679. int val;
  680. int count = 0, erased_errors = 0;
  681. int range;
  682. range = (addr == NETXEN_USER_START) ?
  683. NETXEN_FIXED_START : addr + NETXEN_FLASH_SECTOR_SIZE;
  684. for (i = addr; i < range; i += 4) {
  685. netxen_rom_fast_read(adapter, i, &val);
  686. if (val != 0xffffffff)
  687. erased_errors++;
  688. count++;
  689. }
  690. if (erased_errors)
  691. printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
  692. "for sector address: %x\n", erased_errors, count, addr);
  693. }
  694. int netxen_rom_se(struct netxen_adapter *adapter, int addr)
  695. {
  696. int ret = 0;
  697. if (rom_lock(adapter) != 0) {
  698. return -1;
  699. }
  700. ret = netxen_do_rom_se(adapter, addr);
  701. netxen_rom_unlock(adapter);
  702. msleep(30);
  703. check_erased_flash(adapter, addr);
  704. return ret;
  705. }
  706. static int netxen_flash_erase_sections(struct netxen_adapter *adapter,
  707. int start, int end)
  708. {
  709. int ret = FLASH_SUCCESS;
  710. int i;
  711. for (i = start; i < end; i++) {
  712. ret = netxen_rom_se(adapter, i * NETXEN_FLASH_SECTOR_SIZE);
  713. if (ret)
  714. break;
  715. ret = netxen_rom_wip_poll(adapter);
  716. if (ret < 0)
  717. return ret;
  718. }
  719. return ret;
  720. }
  721. int
  722. netxen_flash_erase_secondary(struct netxen_adapter *adapter)
  723. {
  724. int ret = FLASH_SUCCESS;
  725. int start, end;
  726. start = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  727. end = NETXEN_USER_START / NETXEN_FLASH_SECTOR_SIZE;
  728. ret = netxen_flash_erase_sections(adapter, start, end);
  729. return ret;
  730. }
  731. int
  732. netxen_flash_erase_primary(struct netxen_adapter *adapter)
  733. {
  734. int ret = FLASH_SUCCESS;
  735. int start, end;
  736. start = NETXEN_PRIMARY_START / NETXEN_FLASH_SECTOR_SIZE;
  737. end = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  738. ret = netxen_flash_erase_sections(adapter, start, end);
  739. return ret;
  740. }
  741. void netxen_halt_pegs(struct netxen_adapter *adapter)
  742. {
  743. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
  744. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
  745. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
  746. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
  747. }
  748. int netxen_flash_unlock(struct netxen_adapter *adapter)
  749. {
  750. int ret = 0;
  751. ret = netxen_rom_wrsr(adapter, 0);
  752. if (ret < 0)
  753. return ret;
  754. ret = netxen_rom_wren(adapter);
  755. if (ret < 0)
  756. return ret;
  757. return ret;
  758. }
  759. #endif /* 0 */
  760. #define NETXEN_BOARDTYPE 0x4008
  761. #define NETXEN_BOARDNUM 0x400c
  762. #define NETXEN_CHIPNUM 0x4010
  763. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  764. {
  765. int addr, val;
  766. int i, n, init_delay = 0;
  767. struct crb_addr_pair *buf;
  768. unsigned offset;
  769. u32 off;
  770. /* resetall */
  771. rom_lock(adapter);
  772. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  773. 0xffffffff);
  774. netxen_rom_unlock(adapter);
  775. if (verbose) {
  776. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  777. printk("P2 ROM board type: 0x%08x\n", val);
  778. else
  779. printk("Could not read board type\n");
  780. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  781. printk("P2 ROM board num: 0x%08x\n", val);
  782. else
  783. printk("Could not read board number\n");
  784. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  785. printk("P2 ROM chip num: 0x%08x\n", val);
  786. else
  787. printk("Could not read chip number\n");
  788. }
  789. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  790. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  791. (n != 0xcafecafe) ||
  792. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  793. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  794. "n: %08x\n", netxen_nic_driver_name, n);
  795. return -EIO;
  796. }
  797. offset = n & 0xffffU;
  798. n = (n >> 16) & 0xffffU;
  799. } else {
  800. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  801. !(n & 0x80000000)) {
  802. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  803. "n: %08x\n", netxen_nic_driver_name, n);
  804. return -EIO;
  805. }
  806. offset = 1;
  807. n &= ~0x80000000;
  808. }
  809. if (n < 1024) {
  810. if (verbose)
  811. printk(KERN_DEBUG "%s: %d CRB init values found"
  812. " in ROM.\n", netxen_nic_driver_name, n);
  813. } else {
  814. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  815. " initialized.\n", __func__, n);
  816. return -EIO;
  817. }
  818. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  819. if (buf == NULL) {
  820. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  821. netxen_nic_driver_name);
  822. return -ENOMEM;
  823. }
  824. for (i = 0; i < n; i++) {
  825. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  826. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  827. kfree(buf);
  828. return -EIO;
  829. }
  830. buf[i].addr = addr;
  831. buf[i].data = val;
  832. if (verbose)
  833. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  834. netxen_nic_driver_name,
  835. (u32)netxen_decode_crb_addr(addr), val);
  836. }
  837. for (i = 0; i < n; i++) {
  838. off = netxen_decode_crb_addr(buf[i].addr);
  839. if (off == NETXEN_ADDR_ERROR) {
  840. printk(KERN_ERR"CRB init value out of range %x\n",
  841. buf[i].addr);
  842. continue;
  843. }
  844. off += NETXEN_PCI_CRBSPACE;
  845. /* skipping cold reboot MAGIC */
  846. if (off == NETXEN_CAM_RAM(0x1fc))
  847. continue;
  848. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  849. /* do not reset PCI */
  850. if (off == (ROMUSB_GLB + 0xbc))
  851. continue;
  852. if (off == (ROMUSB_GLB + 0xa8))
  853. continue;
  854. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  855. continue;
  856. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  857. continue;
  858. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  859. continue;
  860. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  861. buf[i].data = 0x1020;
  862. /* skip the function enable register */
  863. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  864. continue;
  865. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  866. continue;
  867. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  868. continue;
  869. }
  870. if (off == NETXEN_ADDR_ERROR) {
  871. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  872. netxen_nic_driver_name, buf[i].addr);
  873. continue;
  874. }
  875. init_delay = 1;
  876. /* After writing this register, HW needs time for CRB */
  877. /* to quiet down (else crb_window returns 0xffffffff) */
  878. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  879. init_delay = 1000;
  880. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  881. /* hold xdma in reset also */
  882. buf[i].data = NETXEN_NIC_XDMA_RESET;
  883. buf[i].data = 0x8000ff;
  884. }
  885. }
  886. adapter->hw_write_wx(adapter, off, &buf[i].data, 4);
  887. msleep(init_delay);
  888. }
  889. kfree(buf);
  890. /* disable_peg_cache_all */
  891. /* unreset_net_cache */
  892. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  893. adapter->hw_read_wx(adapter,
  894. NETXEN_ROMUSB_GLB_SW_RESET, &val, 4);
  895. netxen_crb_writelit_adapter(adapter,
  896. NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  897. }
  898. /* p2dn replyCount */
  899. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  900. /* disable_peg_cache 0 */
  901. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  902. /* disable_peg_cache 1 */
  903. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  904. /* peg_clr_all */
  905. /* peg_clr 0 */
  906. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  907. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  908. /* peg_clr 1 */
  909. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  910. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  911. /* peg_clr 2 */
  912. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  913. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  914. /* peg_clr 3 */
  915. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  916. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  917. return 0;
  918. }
  919. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  920. {
  921. uint64_t addr;
  922. uint32_t hi;
  923. uint32_t lo;
  924. adapter->dummy_dma.addr =
  925. pci_alloc_consistent(adapter->pdev,
  926. NETXEN_HOST_DUMMY_DMA_SIZE,
  927. &adapter->dummy_dma.phys_addr);
  928. if (adapter->dummy_dma.addr == NULL) {
  929. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  930. __func__);
  931. return -ENOMEM;
  932. }
  933. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  934. hi = (addr >> 32) & 0xffffffff;
  935. lo = addr & 0xffffffff;
  936. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  937. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  938. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  939. uint32_t temp = 0;
  940. adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4);
  941. }
  942. return 0;
  943. }
  944. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  945. {
  946. int i = 100;
  947. if (!adapter->dummy_dma.addr)
  948. return;
  949. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  950. do {
  951. if (dma_watchdog_shutdown_request(adapter) == 1)
  952. break;
  953. msleep(50);
  954. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  955. break;
  956. } while (--i);
  957. }
  958. if (i) {
  959. pci_free_consistent(adapter->pdev,
  960. NETXEN_HOST_DUMMY_DMA_SIZE,
  961. adapter->dummy_dma.addr,
  962. adapter->dummy_dma.phys_addr);
  963. adapter->dummy_dma.addr = NULL;
  964. } else {
  965. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  966. adapter->netdev->name);
  967. }
  968. }
  969. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  970. {
  971. u32 val = 0;
  972. int retries = 60;
  973. if (!pegtune_val) {
  974. do {
  975. val = adapter->pci_read_normalize(adapter,
  976. CRB_CMDPEG_STATE);
  977. if (val == PHAN_INITIALIZE_COMPLETE ||
  978. val == PHAN_INITIALIZE_ACK)
  979. return 0;
  980. msleep(500);
  981. } while (--retries);
  982. if (!retries) {
  983. pegtune_val = adapter->pci_read_normalize(adapter,
  984. NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
  985. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  986. "pegtune_val=%x\n", pegtune_val);
  987. return -1;
  988. }
  989. }
  990. return 0;
  991. }
  992. int netxen_receive_peg_ready(struct netxen_adapter *adapter)
  993. {
  994. u32 val = 0;
  995. int retries = 2000;
  996. do {
  997. val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE);
  998. if (val == PHAN_PEG_RCV_INITIALIZED)
  999. return 0;
  1000. msleep(10);
  1001. } while (--retries);
  1002. if (!retries) {
  1003. printk(KERN_ERR "Receive Peg initialization not "
  1004. "complete, state: 0x%x.\n", val);
  1005. return -EIO;
  1006. }
  1007. return 0;
  1008. }
  1009. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1010. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1011. {
  1012. struct netxen_rx_buffer *buffer;
  1013. struct sk_buff *skb;
  1014. buffer = &rds_ring->rx_buf_arr[index];
  1015. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1016. PCI_DMA_FROMDEVICE);
  1017. skb = buffer->skb;
  1018. if (!skb)
  1019. goto no_skb;
  1020. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1021. adapter->stats.csummed++;
  1022. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1023. } else
  1024. skb->ip_summed = CHECKSUM_NONE;
  1025. skb->dev = adapter->netdev;
  1026. buffer->skb = NULL;
  1027. no_skb:
  1028. buffer->state = NETXEN_BUFFER_FREE;
  1029. buffer->lro_current_frags = 0;
  1030. buffer->lro_expected_frags = 0;
  1031. list_add_tail(&buffer->list, &rds_ring->free_list);
  1032. return skb;
  1033. }
  1034. /*
  1035. * netxen_process_rcv() send the received packet to the protocol stack.
  1036. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  1037. * invoke the routine to send more rx buffers to the Phantom...
  1038. */
  1039. static void netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  1040. struct status_desc *desc, struct status_desc *frag_desc)
  1041. {
  1042. struct net_device *netdev = adapter->netdev;
  1043. u64 sts_data = le64_to_cpu(desc->status_desc_data);
  1044. int index = netxen_get_sts_refhandle(sts_data);
  1045. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1046. struct netxen_rx_buffer *buffer;
  1047. struct sk_buff *skb;
  1048. u32 length = netxen_get_sts_totallength(sts_data);
  1049. u32 desc_ctx;
  1050. u16 pkt_offset = 0, cksum;
  1051. struct nx_host_rds_ring *rds_ring;
  1052. desc_ctx = netxen_get_sts_type(sts_data);
  1053. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  1054. printk("%s: %s Bad Rcv descriptor ring\n",
  1055. netxen_nic_driver_name, netdev->name);
  1056. return;
  1057. }
  1058. rds_ring = &recv_ctx->rds_rings[desc_ctx];
  1059. if (unlikely(index > rds_ring->max_rx_desc_count)) {
  1060. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  1061. index, rds_ring->max_rx_desc_count);
  1062. return;
  1063. }
  1064. buffer = &rds_ring->rx_buf_arr[index];
  1065. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  1066. buffer->lro_current_frags++;
  1067. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  1068. buffer->lro_expected_frags =
  1069. netxen_get_sts_desc_lro_cnt(desc);
  1070. buffer->lro_length = length;
  1071. }
  1072. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  1073. if (buffer->lro_expected_frags != 0) {
  1074. printk("LRO: (refhandle:%x) recv frag. "
  1075. "wait for last. flags: %x expected:%d "
  1076. "have:%d\n", index,
  1077. netxen_get_sts_desc_lro_last_frag(desc),
  1078. buffer->lro_expected_frags,
  1079. buffer->lro_current_frags);
  1080. }
  1081. return;
  1082. }
  1083. }
  1084. cksum = netxen_get_sts_status(sts_data);
  1085. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1086. if (!skb)
  1087. return;
  1088. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  1089. /* True length was only available on the last pkt */
  1090. skb_put(skb, buffer->lro_length);
  1091. } else {
  1092. if (length > rds_ring->skb_size)
  1093. skb_put(skb, rds_ring->skb_size);
  1094. else
  1095. skb_put(skb, length);
  1096. pkt_offset = netxen_get_sts_pkt_offset(sts_data);
  1097. if (pkt_offset)
  1098. skb_pull(skb, pkt_offset);
  1099. }
  1100. skb->protocol = eth_type_trans(skb, netdev);
  1101. /*
  1102. * rx buffer chaining is disabled, walk and free
  1103. * any spurious rx buffer chain.
  1104. */
  1105. if (frag_desc) {
  1106. u16 i, nr_frags = desc->nr_frags;
  1107. dev_kfree_skb_any(skb);
  1108. for (i = 0; i < nr_frags; i++) {
  1109. index = le16_to_cpu(frag_desc->frag_handles[i]);
  1110. skb = netxen_process_rxbuf(adapter,
  1111. rds_ring, index, cksum);
  1112. if (skb)
  1113. dev_kfree_skb_any(skb);
  1114. }
  1115. adapter->stats.rxdropped++;
  1116. } else {
  1117. netif_receive_skb(skb);
  1118. adapter->stats.no_rcv++;
  1119. adapter->stats.rxbytes += length;
  1120. }
  1121. }
  1122. /* Process Receive status ring */
  1123. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  1124. {
  1125. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1126. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  1127. struct status_desc *desc, *frag_desc;
  1128. u32 consumer = recv_ctx->status_rx_consumer;
  1129. int count = 0, ring;
  1130. u64 sts_data;
  1131. u16 opcode;
  1132. while (count < max) {
  1133. desc = &desc_head[consumer];
  1134. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  1135. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  1136. netxen_get_sts_owner(desc));
  1137. break;
  1138. }
  1139. sts_data = le64_to_cpu(desc->status_desc_data);
  1140. opcode = netxen_get_sts_opcode(sts_data);
  1141. frag_desc = NULL;
  1142. if (opcode == NETXEN_NIC_RXPKT_DESC) {
  1143. if (desc->nr_frags) {
  1144. consumer = get_next_index(consumer,
  1145. adapter->max_rx_desc_count);
  1146. frag_desc = &desc_head[consumer];
  1147. netxen_set_sts_owner(frag_desc,
  1148. STATUS_OWNER_PHANTOM);
  1149. }
  1150. }
  1151. netxen_process_rcv(adapter, ctxid, desc, frag_desc);
  1152. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  1153. consumer = get_next_index(consumer,
  1154. adapter->max_rx_desc_count);
  1155. count++;
  1156. }
  1157. for (ring = 0; ring < adapter->max_rds_rings; ring++)
  1158. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  1159. /* update the consumer index in phantom */
  1160. if (count) {
  1161. recv_ctx->status_rx_consumer = consumer;
  1162. /* Window = 1 */
  1163. adapter->pci_write_normalize(adapter,
  1164. recv_ctx->crb_sts_consumer, consumer);
  1165. }
  1166. return count;
  1167. }
  1168. /* Process Command status ring */
  1169. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1170. {
  1171. u32 last_consumer, consumer;
  1172. int count = 0, i;
  1173. struct netxen_cmd_buffer *buffer;
  1174. struct pci_dev *pdev = adapter->pdev;
  1175. struct net_device *netdev = adapter->netdev;
  1176. struct netxen_skb_frag *frag;
  1177. int done = 0;
  1178. last_consumer = adapter->last_cmd_consumer;
  1179. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1180. while (last_consumer != consumer) {
  1181. buffer = &adapter->cmd_buf_arr[last_consumer];
  1182. if (buffer->skb) {
  1183. frag = &buffer->frag_array[0];
  1184. pci_unmap_single(pdev, frag->dma, frag->length,
  1185. PCI_DMA_TODEVICE);
  1186. frag->dma = 0ULL;
  1187. for (i = 1; i < buffer->frag_count; i++) {
  1188. frag++; /* Get the next frag */
  1189. pci_unmap_page(pdev, frag->dma, frag->length,
  1190. PCI_DMA_TODEVICE);
  1191. frag->dma = 0ULL;
  1192. }
  1193. adapter->stats.xmitfinished++;
  1194. dev_kfree_skb_any(buffer->skb);
  1195. buffer->skb = NULL;
  1196. }
  1197. last_consumer = get_next_index(last_consumer,
  1198. adapter->max_tx_desc_count);
  1199. if (++count >= MAX_STATUS_HANDLE)
  1200. break;
  1201. }
  1202. if (count) {
  1203. adapter->last_cmd_consumer = last_consumer;
  1204. smp_mb();
  1205. if (netif_queue_stopped(netdev) && netif_running(netdev)) {
  1206. netif_tx_lock(netdev);
  1207. netif_wake_queue(netdev);
  1208. smp_mb();
  1209. netif_tx_unlock(netdev);
  1210. }
  1211. }
  1212. /*
  1213. * If everything is freed up to consumer then check if the ring is full
  1214. * If the ring is full then check if more needs to be freed and
  1215. * schedule the call back again.
  1216. *
  1217. * This happens when there are 2 CPUs. One could be freeing and the
  1218. * other filling it. If the ring is full when we get out of here and
  1219. * the card has already interrupted the host then the host can miss the
  1220. * interrupt.
  1221. *
  1222. * There is still a possible race condition and the host could miss an
  1223. * interrupt. The card has to take care of this.
  1224. */
  1225. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1226. done = (last_consumer == consumer);
  1227. return (done);
  1228. }
  1229. /*
  1230. * netxen_post_rx_buffers puts buffer in the Phantom memory
  1231. */
  1232. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  1233. {
  1234. struct pci_dev *pdev = adapter->pdev;
  1235. struct sk_buff *skb;
  1236. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1237. struct nx_host_rds_ring *rds_ring = NULL;
  1238. uint producer;
  1239. struct rcv_desc *pdesc;
  1240. struct netxen_rx_buffer *buffer;
  1241. int count = 0;
  1242. netxen_ctx_msg msg = 0;
  1243. dma_addr_t dma;
  1244. struct list_head *head;
  1245. rds_ring = &recv_ctx->rds_rings[ringid];
  1246. producer = rds_ring->producer;
  1247. head = &rds_ring->free_list;
  1248. /* We can start writing rx descriptors into the phantom memory. */
  1249. while (!list_empty(head)) {
  1250. skb = dev_alloc_skb(rds_ring->skb_size);
  1251. if (unlikely(!skb)) {
  1252. break;
  1253. }
  1254. if (!adapter->ahw.cut_through)
  1255. skb_reserve(skb, 2);
  1256. dma = pci_map_single(pdev, skb->data,
  1257. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1258. if (pci_dma_mapping_error(pdev, dma)) {
  1259. dev_kfree_skb_any(skb);
  1260. break;
  1261. }
  1262. count++;
  1263. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1264. list_del(&buffer->list);
  1265. buffer->skb = skb;
  1266. buffer->state = NETXEN_BUFFER_BUSY;
  1267. buffer->dma = dma;
  1268. /* make a rcv descriptor */
  1269. pdesc = &rds_ring->desc_head[producer];
  1270. pdesc->addr_buffer = cpu_to_le64(dma);
  1271. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1272. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1273. producer = get_next_index(producer, rds_ring->max_rx_desc_count);
  1274. }
  1275. /* if we did allocate buffers, then write the count to Phantom */
  1276. if (count) {
  1277. rds_ring->producer = producer;
  1278. /* Window = 1 */
  1279. adapter->pci_write_normalize(adapter,
  1280. rds_ring->crb_rcv_producer,
  1281. (producer-1) & (rds_ring->max_rx_desc_count-1));
  1282. if (adapter->fw_major < 4) {
  1283. /*
  1284. * Write a doorbell msg to tell phanmon of change in
  1285. * receive ring producer
  1286. * Only for firmware version < 4.0.0
  1287. */
  1288. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1289. netxen_set_msg_privid(msg);
  1290. netxen_set_msg_count(msg,
  1291. ((producer -
  1292. 1) & (rds_ring->
  1293. max_rx_desc_count - 1)));
  1294. netxen_set_msg_ctxid(msg, adapter->portnum);
  1295. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1296. writel(msg,
  1297. DB_NORMALIZE(adapter,
  1298. NETXEN_RCV_PRODUCER_OFFSET));
  1299. }
  1300. }
  1301. }
  1302. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1303. uint32_t ctx, uint32_t ringid)
  1304. {
  1305. struct pci_dev *pdev = adapter->pdev;
  1306. struct sk_buff *skb;
  1307. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1308. struct nx_host_rds_ring *rds_ring = NULL;
  1309. u32 producer;
  1310. struct rcv_desc *pdesc;
  1311. struct netxen_rx_buffer *buffer;
  1312. int count = 0;
  1313. struct list_head *head;
  1314. dma_addr_t dma;
  1315. rds_ring = &recv_ctx->rds_rings[ringid];
  1316. producer = rds_ring->producer;
  1317. head = &rds_ring->free_list;
  1318. /* We can start writing rx descriptors into the phantom memory. */
  1319. while (!list_empty(head)) {
  1320. skb = dev_alloc_skb(rds_ring->skb_size);
  1321. if (unlikely(!skb)) {
  1322. break;
  1323. }
  1324. if (!adapter->ahw.cut_through)
  1325. skb_reserve(skb, 2);
  1326. dma = pci_map_single(pdev, skb->data,
  1327. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1328. if (pci_dma_mapping_error(pdev, dma)) {
  1329. dev_kfree_skb_any(skb);
  1330. break;
  1331. }
  1332. count++;
  1333. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1334. list_del(&buffer->list);
  1335. buffer->skb = skb;
  1336. buffer->state = NETXEN_BUFFER_BUSY;
  1337. buffer->dma = dma;
  1338. /* make a rcv descriptor */
  1339. pdesc = &rds_ring->desc_head[producer];
  1340. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1341. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1342. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1343. producer = get_next_index(producer, rds_ring->max_rx_desc_count);
  1344. }
  1345. /* if we did allocate buffers, then write the count to Phantom */
  1346. if (count) {
  1347. rds_ring->producer = producer;
  1348. /* Window = 1 */
  1349. adapter->pci_write_normalize(adapter,
  1350. rds_ring->crb_rcv_producer,
  1351. (producer-1) & (rds_ring->max_rx_desc_count-1));
  1352. wmb();
  1353. }
  1354. }
  1355. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1356. {
  1357. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1358. return;
  1359. }