iwl-4965.c 142 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/version.h>
  29. #include <linux/init.h>
  30. #include <linux/pci.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/delay.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/wireless.h>
  36. #include <net/mac80211.h>
  37. #include <linux/etherdevice.h>
  38. #include <asm/unaligned.h>
  39. #include "iwl-eeprom.h"
  40. #include "iwl-4965.h"
  41. #include "iwl-core.h"
  42. #include "iwl-io.h"
  43. #include "iwl-helpers.h"
  44. /* module parameters */
  45. static struct iwl_mod_params iwl4965_mod_params = {
  46. .num_of_queues = IWL_MAX_NUM_QUEUES,
  47. .enable_qos = 1,
  48. .amsdu_size_8K = 1,
  49. /* the rest are 0 by default */
  50. };
  51. static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
  52. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  53. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  54. IWL_RATE_SISO_##s##M_PLCP, \
  55. IWL_RATE_MIMO_##s##M_PLCP, \
  56. IWL_RATE_##r##M_IEEE, \
  57. IWL_RATE_##ip##M_INDEX, \
  58. IWL_RATE_##in##M_INDEX, \
  59. IWL_RATE_##rp##M_INDEX, \
  60. IWL_RATE_##rn##M_INDEX, \
  61. IWL_RATE_##pp##M_INDEX, \
  62. IWL_RATE_##np##M_INDEX }
  63. /*
  64. * Parameter order:
  65. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  66. *
  67. * If there isn't a valid next or previous rate then INV is used which
  68. * maps to IWL_RATE_INVALID
  69. *
  70. */
  71. const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
  72. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  73. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  74. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  75. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  76. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  77. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  78. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  79. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  80. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  81. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  82. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  83. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  84. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  85. };
  86. #ifdef CONFIG_IWL4965_HT
  87. static const u16 default_tid_to_tx_fifo[] = {
  88. IWL_TX_FIFO_AC1,
  89. IWL_TX_FIFO_AC0,
  90. IWL_TX_FIFO_AC0,
  91. IWL_TX_FIFO_AC1,
  92. IWL_TX_FIFO_AC2,
  93. IWL_TX_FIFO_AC2,
  94. IWL_TX_FIFO_AC3,
  95. IWL_TX_FIFO_AC3,
  96. IWL_TX_FIFO_NONE,
  97. IWL_TX_FIFO_NONE,
  98. IWL_TX_FIFO_NONE,
  99. IWL_TX_FIFO_NONE,
  100. IWL_TX_FIFO_NONE,
  101. IWL_TX_FIFO_NONE,
  102. IWL_TX_FIFO_NONE,
  103. IWL_TX_FIFO_NONE,
  104. IWL_TX_FIFO_AC3
  105. };
  106. #endif /*CONFIG_IWL4965_HT */
  107. /* check contents of special bootstrap uCode SRAM */
  108. static int iwl4965_verify_bsm(struct iwl_priv *priv)
  109. {
  110. __le32 *image = priv->ucode_boot.v_addr;
  111. u32 len = priv->ucode_boot.len;
  112. u32 reg;
  113. u32 val;
  114. IWL_DEBUG_INFO("Begin verify bsm\n");
  115. /* verify BSM SRAM contents */
  116. val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
  117. for (reg = BSM_SRAM_LOWER_BOUND;
  118. reg < BSM_SRAM_LOWER_BOUND + len;
  119. reg += sizeof(u32), image++) {
  120. val = iwl_read_prph(priv, reg);
  121. if (val != le32_to_cpu(*image)) {
  122. IWL_ERROR("BSM uCode verification failed at "
  123. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  124. BSM_SRAM_LOWER_BOUND,
  125. reg - BSM_SRAM_LOWER_BOUND, len,
  126. val, le32_to_cpu(*image));
  127. return -EIO;
  128. }
  129. }
  130. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  131. return 0;
  132. }
  133. /**
  134. * iwl4965_load_bsm - Load bootstrap instructions
  135. *
  136. * BSM operation:
  137. *
  138. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  139. * in special SRAM that does not power down during RFKILL. When powering back
  140. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  141. * the bootstrap program into the on-board processor, and starts it.
  142. *
  143. * The bootstrap program loads (via DMA) instructions and data for a new
  144. * program from host DRAM locations indicated by the host driver in the
  145. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  146. * automatically.
  147. *
  148. * When initializing the NIC, the host driver points the BSM to the
  149. * "initialize" uCode image. This uCode sets up some internal data, then
  150. * notifies host via "initialize alive" that it is complete.
  151. *
  152. * The host then replaces the BSM_DRAM_* pointer values to point to the
  153. * normal runtime uCode instructions and a backup uCode data cache buffer
  154. * (filled initially with starting data values for the on-board processor),
  155. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  156. * which begins normal operation.
  157. *
  158. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  159. * the backup data cache in DRAM before SRAM is powered down.
  160. *
  161. * When powering back up, the BSM loads the bootstrap program. This reloads
  162. * the runtime uCode instructions and the backup data cache into SRAM,
  163. * and re-launches the runtime uCode from where it left off.
  164. */
  165. static int iwl4965_load_bsm(struct iwl_priv *priv)
  166. {
  167. __le32 *image = priv->ucode_boot.v_addr;
  168. u32 len = priv->ucode_boot.len;
  169. dma_addr_t pinst;
  170. dma_addr_t pdata;
  171. u32 inst_len;
  172. u32 data_len;
  173. int i;
  174. u32 done;
  175. u32 reg_offset;
  176. int ret;
  177. IWL_DEBUG_INFO("Begin load bsm\n");
  178. /* make sure bootstrap program is no larger than BSM's SRAM size */
  179. if (len > IWL_MAX_BSM_SIZE)
  180. return -EINVAL;
  181. /* Tell bootstrap uCode where to find the "Initialize" uCode
  182. * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
  183. * NOTE: iwl4965_initialize_alive_start() will replace these values,
  184. * after the "initialize" uCode has run, to point to
  185. * runtime/protocol instructions and backup data cache. */
  186. pinst = priv->ucode_init.p_addr >> 4;
  187. pdata = priv->ucode_init_data.p_addr >> 4;
  188. inst_len = priv->ucode_init.len;
  189. data_len = priv->ucode_init_data.len;
  190. ret = iwl_grab_nic_access(priv);
  191. if (ret)
  192. return ret;
  193. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  194. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  195. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  196. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  197. /* Fill BSM memory with bootstrap instructions */
  198. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  199. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  200. reg_offset += sizeof(u32), image++)
  201. _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
  202. ret = iwl4965_verify_bsm(priv);
  203. if (ret) {
  204. iwl_release_nic_access(priv);
  205. return ret;
  206. }
  207. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  208. iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  209. iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
  210. iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  211. /* Load bootstrap code into instruction SRAM now,
  212. * to prepare to load "initialize" uCode */
  213. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
  214. /* Wait for load of bootstrap uCode to finish */
  215. for (i = 0; i < 100; i++) {
  216. done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
  217. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  218. break;
  219. udelay(10);
  220. }
  221. if (i < 100)
  222. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  223. else {
  224. IWL_ERROR("BSM write did not complete!\n");
  225. return -EIO;
  226. }
  227. /* Enable future boot loads whenever power management unit triggers it
  228. * (e.g. when powering back up after power-save shutdown) */
  229. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
  230. iwl_release_nic_access(priv);
  231. return 0;
  232. }
  233. static int iwl4965_init_drv(struct iwl_priv *priv)
  234. {
  235. int ret;
  236. int i;
  237. priv->antenna = (enum iwl4965_antenna)priv->cfg->mod_params->antenna;
  238. priv->retry_rate = 1;
  239. priv->ibss_beacon = NULL;
  240. spin_lock_init(&priv->lock);
  241. spin_lock_init(&priv->power_data.lock);
  242. spin_lock_init(&priv->sta_lock);
  243. spin_lock_init(&priv->hcmd_lock);
  244. spin_lock_init(&priv->lq_mngr.lock);
  245. priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
  246. sizeof(struct iwl4965_shared),
  247. &priv->shared_phys);
  248. if (!priv->shared_virt) {
  249. ret = -ENOMEM;
  250. goto err;
  251. }
  252. memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
  253. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
  254. INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
  255. INIT_LIST_HEAD(&priv->free_frames);
  256. mutex_init(&priv->mutex);
  257. /* Clear the driver's (not device's) station table */
  258. iwlcore_clear_stations_table(priv);
  259. priv->data_retry_limit = -1;
  260. priv->ieee_channels = NULL;
  261. priv->ieee_rates = NULL;
  262. priv->band = IEEE80211_BAND_2GHZ;
  263. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  264. priv->use_ant_b_for_management_frame = 1; /* start with ant B */
  265. priv->valid_antenna = 0x7; /* assume all 3 connected */
  266. priv->ps_mode = IWL_MIMO_PS_NONE;
  267. /* Choose which receivers/antennas to use */
  268. iwl4965_set_rxon_chain(priv);
  269. iwlcore_reset_qos(priv);
  270. priv->qos_data.qos_active = 0;
  271. priv->qos_data.qos_cap.val = 0;
  272. iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  273. priv->rates_mask = IWL_RATES_MASK;
  274. /* If power management is turned on, default to AC mode */
  275. priv->power_mode = IWL_POWER_AC;
  276. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  277. ret = iwl_init_channel_map(priv);
  278. if (ret) {
  279. IWL_ERROR("initializing regulatory failed: %d\n", ret);
  280. goto err;
  281. }
  282. ret = iwl4965_init_geos(priv);
  283. if (ret) {
  284. IWL_ERROR("initializing geos failed: %d\n", ret);
  285. goto err_free_channel_map;
  286. }
  287. ret = ieee80211_register_hw(priv->hw);
  288. if (ret) {
  289. IWL_ERROR("Failed to register network device (error %d)\n",
  290. ret);
  291. goto err_free_geos;
  292. }
  293. priv->hw->conf.beacon_int = 100;
  294. priv->mac80211_registered = 1;
  295. return 0;
  296. err_free_geos:
  297. iwl4965_free_geos(priv);
  298. err_free_channel_map:
  299. iwl_free_channel_map(priv);
  300. err:
  301. return ret;
  302. }
  303. static int is_fat_channel(__le32 rxon_flags)
  304. {
  305. return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
  306. (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
  307. }
  308. static u8 is_single_stream(struct iwl_priv *priv)
  309. {
  310. #ifdef CONFIG_IWL4965_HT
  311. if (!priv->current_ht_config.is_ht ||
  312. (priv->current_ht_config.supp_mcs_set[1] == 0) ||
  313. (priv->ps_mode == IWL_MIMO_PS_STATIC))
  314. return 1;
  315. #else
  316. return 1;
  317. #endif /*CONFIG_IWL4965_HT */
  318. return 0;
  319. }
  320. int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
  321. {
  322. int idx = 0;
  323. /* 4965 HT rate format */
  324. if (rate_n_flags & RATE_MCS_HT_MSK) {
  325. idx = (rate_n_flags & 0xff);
  326. if (idx >= IWL_RATE_MIMO_6M_PLCP)
  327. idx = idx - IWL_RATE_MIMO_6M_PLCP;
  328. idx += IWL_FIRST_OFDM_RATE;
  329. /* skip 9M not supported in ht*/
  330. if (idx >= IWL_RATE_9M_INDEX)
  331. idx += 1;
  332. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  333. return idx;
  334. /* 4965 legacy rate format, search for match in table */
  335. } else {
  336. for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
  337. if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
  338. return idx;
  339. }
  340. return -1;
  341. }
  342. /**
  343. * translate ucode response to mac80211 tx status control values
  344. */
  345. void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  346. struct ieee80211_tx_control *control)
  347. {
  348. int rate_index;
  349. control->antenna_sel_tx =
  350. ((rate_n_flags & RATE_MCS_ANT_AB_MSK) >> RATE_MCS_ANT_A_POS);
  351. if (rate_n_flags & RATE_MCS_HT_MSK)
  352. control->flags |= IEEE80211_TXCTL_OFDM_HT;
  353. if (rate_n_flags & RATE_MCS_GF_MSK)
  354. control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
  355. if (rate_n_flags & RATE_MCS_FAT_MSK)
  356. control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
  357. if (rate_n_flags & RATE_MCS_DUP_MSK)
  358. control->flags |= IEEE80211_TXCTL_DUP_DATA;
  359. if (rate_n_flags & RATE_MCS_SGI_MSK)
  360. control->flags |= IEEE80211_TXCTL_SHORT_GI;
  361. /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
  362. * IEEE80211_BAND_2GHZ band as it contains all the rates */
  363. rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
  364. if (rate_index == -1)
  365. control->tx_rate = NULL;
  366. else
  367. control->tx_rate =
  368. &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
  369. }
  370. /*
  371. * Determine how many receiver/antenna chains to use.
  372. * More provides better reception via diversity. Fewer saves power.
  373. * MIMO (dual stream) requires at least 2, but works better with 3.
  374. * This does not determine *which* chains to use, just how many.
  375. */
  376. static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
  377. u8 *idle_state, u8 *rx_state)
  378. {
  379. u8 is_single = is_single_stream(priv);
  380. u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
  381. /* # of Rx chains to use when expecting MIMO. */
  382. if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
  383. *rx_state = 2;
  384. else
  385. *rx_state = 3;
  386. /* # Rx chains when idling and maybe trying to save power */
  387. switch (priv->ps_mode) {
  388. case IWL_MIMO_PS_STATIC:
  389. case IWL_MIMO_PS_DYNAMIC:
  390. *idle_state = (is_cam) ? 2 : 1;
  391. break;
  392. case IWL_MIMO_PS_NONE:
  393. *idle_state = (is_cam) ? *rx_state : 1;
  394. break;
  395. default:
  396. *idle_state = 1;
  397. break;
  398. }
  399. return 0;
  400. }
  401. int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
  402. {
  403. int rc;
  404. unsigned long flags;
  405. spin_lock_irqsave(&priv->lock, flags);
  406. rc = iwl_grab_nic_access(priv);
  407. if (rc) {
  408. spin_unlock_irqrestore(&priv->lock, flags);
  409. return rc;
  410. }
  411. /* stop Rx DMA */
  412. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  413. rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  414. (1 << 24), 1000);
  415. if (rc < 0)
  416. IWL_ERROR("Can't stop Rx DMA.\n");
  417. iwl_release_nic_access(priv);
  418. spin_unlock_irqrestore(&priv->lock, flags);
  419. return 0;
  420. }
  421. u8 iwl4965_hw_find_station(struct iwl_priv *priv, const u8 *addr)
  422. {
  423. int i;
  424. int start = 0;
  425. int ret = IWL_INVALID_STATION;
  426. unsigned long flags;
  427. DECLARE_MAC_BUF(mac);
  428. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
  429. (priv->iw_mode == IEEE80211_IF_TYPE_AP))
  430. start = IWL_STA_ID;
  431. if (is_broadcast_ether_addr(addr))
  432. return priv->hw_setting.bcast_sta_id;
  433. spin_lock_irqsave(&priv->sta_lock, flags);
  434. for (i = start; i < priv->hw_setting.max_stations; i++)
  435. if ((priv->stations[i].used) &&
  436. (!compare_ether_addr
  437. (priv->stations[i].sta.sta.addr, addr))) {
  438. ret = i;
  439. goto out;
  440. }
  441. IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
  442. print_mac(mac, addr), priv->num_stations);
  443. out:
  444. spin_unlock_irqrestore(&priv->sta_lock, flags);
  445. return ret;
  446. }
  447. static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
  448. {
  449. int ret;
  450. unsigned long flags;
  451. spin_lock_irqsave(&priv->lock, flags);
  452. ret = iwl_grab_nic_access(priv);
  453. if (ret) {
  454. spin_unlock_irqrestore(&priv->lock, flags);
  455. return ret;
  456. }
  457. if (!pwr_max) {
  458. u32 val;
  459. ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
  460. &val);
  461. if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
  462. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  463. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  464. ~APMG_PS_CTRL_MSK_PWR_SRC);
  465. } else
  466. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  467. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  468. ~APMG_PS_CTRL_MSK_PWR_SRC);
  469. iwl_release_nic_access(priv);
  470. spin_unlock_irqrestore(&priv->lock, flags);
  471. return ret;
  472. }
  473. static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
  474. {
  475. int ret;
  476. unsigned long flags;
  477. unsigned int rb_size;
  478. spin_lock_irqsave(&priv->lock, flags);
  479. ret = iwl_grab_nic_access(priv);
  480. if (ret) {
  481. spin_unlock_irqrestore(&priv->lock, flags);
  482. return ret;
  483. }
  484. if (priv->cfg->mod_params->amsdu_size_8K)
  485. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  486. else
  487. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  488. /* Stop Rx DMA */
  489. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  490. /* Reset driver's Rx queue write index */
  491. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  492. /* Tell device where to find RBD circular buffer in DRAM */
  493. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  494. rxq->dma_addr >> 8);
  495. /* Tell device where in DRAM to update its Rx status */
  496. iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  497. (priv->shared_phys +
  498. offsetof(struct iwl4965_shared, rb_closed)) >> 4);
  499. /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
  500. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  501. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  502. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  503. rb_size |
  504. /* 0x10 << 4 | */
  505. (RX_QUEUE_SIZE_LOG <<
  506. FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
  507. /*
  508. * iwl_write32(priv,CSR_INT_COAL_REG,0);
  509. */
  510. iwl_release_nic_access(priv);
  511. spin_unlock_irqrestore(&priv->lock, flags);
  512. return 0;
  513. }
  514. /* Tell 4965 where to find the "keep warm" buffer */
  515. static int iwl4965_kw_init(struct iwl_priv *priv)
  516. {
  517. unsigned long flags;
  518. int rc;
  519. spin_lock_irqsave(&priv->lock, flags);
  520. rc = iwl_grab_nic_access(priv);
  521. if (rc)
  522. goto out;
  523. iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
  524. priv->kw.dma_addr >> 4);
  525. iwl_release_nic_access(priv);
  526. out:
  527. spin_unlock_irqrestore(&priv->lock, flags);
  528. return rc;
  529. }
  530. static int iwl4965_kw_alloc(struct iwl_priv *priv)
  531. {
  532. struct pci_dev *dev = priv->pci_dev;
  533. struct iwl4965_kw *kw = &priv->kw;
  534. kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
  535. kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
  536. if (!kw->v_addr)
  537. return -ENOMEM;
  538. return 0;
  539. }
  540. /**
  541. * iwl4965_kw_free - Free the "keep warm" buffer
  542. */
  543. static void iwl4965_kw_free(struct iwl_priv *priv)
  544. {
  545. struct pci_dev *dev = priv->pci_dev;
  546. struct iwl4965_kw *kw = &priv->kw;
  547. if (kw->v_addr) {
  548. pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
  549. memset(kw, 0, sizeof(*kw));
  550. }
  551. }
  552. /**
  553. * iwl4965_txq_ctx_reset - Reset TX queue context
  554. * Destroys all DMA structures and initialise them again
  555. *
  556. * @param priv
  557. * @return error code
  558. */
  559. static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
  560. {
  561. int rc = 0;
  562. int txq_id, slots_num;
  563. unsigned long flags;
  564. iwl4965_kw_free(priv);
  565. /* Free all tx/cmd queues and keep-warm buffer */
  566. iwl4965_hw_txq_ctx_free(priv);
  567. /* Alloc keep-warm buffer */
  568. rc = iwl4965_kw_alloc(priv);
  569. if (rc) {
  570. IWL_ERROR("Keep Warm allocation failed");
  571. goto error_kw;
  572. }
  573. spin_lock_irqsave(&priv->lock, flags);
  574. rc = iwl_grab_nic_access(priv);
  575. if (unlikely(rc)) {
  576. IWL_ERROR("TX reset failed");
  577. spin_unlock_irqrestore(&priv->lock, flags);
  578. goto error_reset;
  579. }
  580. /* Turn off all Tx DMA channels */
  581. iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
  582. iwl_release_nic_access(priv);
  583. spin_unlock_irqrestore(&priv->lock, flags);
  584. /* Tell 4965 where to find the keep-warm buffer */
  585. rc = iwl4965_kw_init(priv);
  586. if (rc) {
  587. IWL_ERROR("kw_init failed\n");
  588. goto error_reset;
  589. }
  590. /* Alloc and init all (default 16) Tx queues,
  591. * including the command queue (#4) */
  592. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
  593. slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
  594. TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
  595. rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
  596. txq_id);
  597. if (rc) {
  598. IWL_ERROR("Tx %d queue init failed\n", txq_id);
  599. goto error;
  600. }
  601. }
  602. return rc;
  603. error:
  604. iwl4965_hw_txq_ctx_free(priv);
  605. error_reset:
  606. iwl4965_kw_free(priv);
  607. error_kw:
  608. return rc;
  609. }
  610. int iwl4965_hw_nic_init(struct iwl_priv *priv)
  611. {
  612. int rc;
  613. unsigned long flags;
  614. struct iwl4965_rx_queue *rxq = &priv->rxq;
  615. u8 rev_id;
  616. u32 val;
  617. u8 val_link;
  618. iwl4965_power_init_handle(priv);
  619. /* nic_init */
  620. spin_lock_irqsave(&priv->lock, flags);
  621. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  622. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  623. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  624. rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
  625. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  626. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  627. if (rc < 0) {
  628. spin_unlock_irqrestore(&priv->lock, flags);
  629. IWL_DEBUG_INFO("Failed to init the card\n");
  630. return rc;
  631. }
  632. rc = iwl_grab_nic_access(priv);
  633. if (rc) {
  634. spin_unlock_irqrestore(&priv->lock, flags);
  635. return rc;
  636. }
  637. iwl_read_prph(priv, APMG_CLK_CTRL_REG);
  638. iwl_write_prph(priv, APMG_CLK_CTRL_REG,
  639. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  640. iwl_read_prph(priv, APMG_CLK_CTRL_REG);
  641. udelay(20);
  642. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  643. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  644. iwl_release_nic_access(priv);
  645. iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
  646. spin_unlock_irqrestore(&priv->lock, flags);
  647. /* Determine HW type */
  648. rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
  649. if (rc)
  650. return rc;
  651. IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
  652. iwl4965_nic_set_pwr_src(priv, 1);
  653. spin_lock_irqsave(&priv->lock, flags);
  654. if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
  655. pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
  656. /* Enable No Snoop field */
  657. pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
  658. val & ~(1 << 11));
  659. }
  660. spin_unlock_irqrestore(&priv->lock, flags);
  661. if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
  662. IWL_ERROR("Older EEPROM detected! Aborting.\n");
  663. return -EINVAL;
  664. }
  665. pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
  666. /* disable L1 entry -- workaround for pre-B1 */
  667. pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
  668. spin_lock_irqsave(&priv->lock, flags);
  669. /* set CSR_HW_CONFIG_REG for uCode use */
  670. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  671. CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
  672. CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  673. CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
  674. rc = iwl_grab_nic_access(priv);
  675. if (rc < 0) {
  676. spin_unlock_irqrestore(&priv->lock, flags);
  677. IWL_DEBUG_INFO("Failed to init the card\n");
  678. return rc;
  679. }
  680. iwl_read_prph(priv, APMG_PS_CTRL_REG);
  681. iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
  682. udelay(5);
  683. iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
  684. iwl_release_nic_access(priv);
  685. spin_unlock_irqrestore(&priv->lock, flags);
  686. iwl4965_hw_card_show_info(priv);
  687. /* end nic_init */
  688. /* Allocate the RX queue, or reset if it is already allocated */
  689. if (!rxq->bd) {
  690. rc = iwl4965_rx_queue_alloc(priv);
  691. if (rc) {
  692. IWL_ERROR("Unable to initialize Rx queue\n");
  693. return -ENOMEM;
  694. }
  695. } else
  696. iwl4965_rx_queue_reset(priv, rxq);
  697. iwl4965_rx_replenish(priv);
  698. iwl4965_rx_init(priv, rxq);
  699. spin_lock_irqsave(&priv->lock, flags);
  700. rxq->need_update = 1;
  701. iwl4965_rx_queue_update_write_ptr(priv, rxq);
  702. spin_unlock_irqrestore(&priv->lock, flags);
  703. /* Allocate and init all Tx and Command queues */
  704. rc = iwl4965_txq_ctx_reset(priv);
  705. if (rc)
  706. return rc;
  707. if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
  708. IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
  709. if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
  710. IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
  711. set_bit(STATUS_INIT, &priv->status);
  712. return 0;
  713. }
  714. int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
  715. {
  716. int rc = 0;
  717. u32 reg_val;
  718. unsigned long flags;
  719. spin_lock_irqsave(&priv->lock, flags);
  720. /* set stop master bit */
  721. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  722. reg_val = iwl_read32(priv, CSR_GP_CNTRL);
  723. if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
  724. (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
  725. IWL_DEBUG_INFO("Card in power save, master is already "
  726. "stopped\n");
  727. else {
  728. rc = iwl_poll_bit(priv, CSR_RESET,
  729. CSR_RESET_REG_FLAG_MASTER_DISABLED,
  730. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  731. if (rc < 0) {
  732. spin_unlock_irqrestore(&priv->lock, flags);
  733. return rc;
  734. }
  735. }
  736. spin_unlock_irqrestore(&priv->lock, flags);
  737. IWL_DEBUG_INFO("stop master\n");
  738. return rc;
  739. }
  740. /**
  741. * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
  742. */
  743. void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
  744. {
  745. int txq_id;
  746. unsigned long flags;
  747. /* Stop each Tx DMA channel, and wait for it to be idle */
  748. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
  749. spin_lock_irqsave(&priv->lock, flags);
  750. if (iwl_grab_nic_access(priv)) {
  751. spin_unlock_irqrestore(&priv->lock, flags);
  752. continue;
  753. }
  754. iwl_write_direct32(priv,
  755. IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
  756. iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
  757. IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
  758. (txq_id), 200);
  759. iwl_release_nic_access(priv);
  760. spin_unlock_irqrestore(&priv->lock, flags);
  761. }
  762. /* Deallocate memory for all Tx queues */
  763. iwl4965_hw_txq_ctx_free(priv);
  764. }
  765. int iwl4965_hw_nic_reset(struct iwl_priv *priv)
  766. {
  767. int rc = 0;
  768. unsigned long flags;
  769. iwl4965_hw_nic_stop_master(priv);
  770. spin_lock_irqsave(&priv->lock, flags);
  771. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  772. udelay(10);
  773. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  774. rc = iwl_poll_bit(priv, CSR_RESET,
  775. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  776. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
  777. udelay(10);
  778. rc = iwl_grab_nic_access(priv);
  779. if (!rc) {
  780. iwl_write_prph(priv, APMG_CLK_EN_REG,
  781. APMG_CLK_VAL_DMA_CLK_RQT |
  782. APMG_CLK_VAL_BSM_CLK_RQT);
  783. udelay(10);
  784. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  785. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  786. iwl_release_nic_access(priv);
  787. }
  788. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  789. wake_up_interruptible(&priv->wait_command_queue);
  790. spin_unlock_irqrestore(&priv->lock, flags);
  791. return rc;
  792. }
  793. #define REG_RECALIB_PERIOD (60)
  794. /**
  795. * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
  796. *
  797. * This callback is provided in order to queue the statistics_work
  798. * in work_queue context (v. softirq)
  799. *
  800. * This timer function is continually reset to execute within
  801. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  802. * was received. We need to ensure we receive the statistics in order
  803. * to update the temperature used for calibrating the TXPOWER. However,
  804. * we can't send the statistics command from softirq context (which
  805. * is the context which timers run at) so we have to queue off the
  806. * statistics_work to actually send the command to the hardware.
  807. */
  808. static void iwl4965_bg_statistics_periodic(unsigned long data)
  809. {
  810. struct iwl_priv *priv = (struct iwl_priv *)data;
  811. queue_work(priv->workqueue, &priv->statistics_work);
  812. }
  813. /**
  814. * iwl4965_bg_statistics_work - Send the statistics request to the hardware.
  815. *
  816. * This is queued by iwl4965_bg_statistics_periodic.
  817. */
  818. static void iwl4965_bg_statistics_work(struct work_struct *work)
  819. {
  820. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  821. statistics_work);
  822. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  823. return;
  824. mutex_lock(&priv->mutex);
  825. iwl4965_send_statistics_request(priv);
  826. mutex_unlock(&priv->mutex);
  827. }
  828. #define CT_LIMIT_CONST 259
  829. #define TM_CT_KILL_THRESHOLD 110
  830. void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
  831. {
  832. struct iwl4965_ct_kill_config cmd;
  833. u32 R1, R2, R3;
  834. u32 temp_th;
  835. u32 crit_temperature;
  836. unsigned long flags;
  837. int ret = 0;
  838. spin_lock_irqsave(&priv->lock, flags);
  839. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  840. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  841. spin_unlock_irqrestore(&priv->lock, flags);
  842. if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
  843. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  844. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  845. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  846. } else {
  847. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  848. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  849. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  850. }
  851. temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
  852. crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
  853. cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
  854. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  855. sizeof(cmd), &cmd);
  856. if (ret)
  857. IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
  858. else
  859. IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
  860. }
  861. #ifdef CONFIG_IWL4965_SENSITIVITY
  862. /* "false alarms" are signals that our DSP tries to lock onto,
  863. * but then determines that they are either noise, or transmissions
  864. * from a distant wireless network (also "noise", really) that get
  865. * "stepped on" by stronger transmissions within our own network.
  866. * This algorithm attempts to set a sensitivity level that is high
  867. * enough to receive all of our own network traffic, but not so
  868. * high that our DSP gets too busy trying to lock onto non-network
  869. * activity/noise. */
  870. static int iwl4965_sens_energy_cck(struct iwl_priv *priv,
  871. u32 norm_fa,
  872. u32 rx_enable_time,
  873. struct statistics_general_data *rx_info)
  874. {
  875. u32 max_nrg_cck = 0;
  876. int i = 0;
  877. u8 max_silence_rssi = 0;
  878. u32 silence_ref = 0;
  879. u8 silence_rssi_a = 0;
  880. u8 silence_rssi_b = 0;
  881. u8 silence_rssi_c = 0;
  882. u32 val;
  883. /* "false_alarms" values below are cross-multiplications to assess the
  884. * numbers of false alarms within the measured period of actual Rx
  885. * (Rx is off when we're txing), vs the min/max expected false alarms
  886. * (some should be expected if rx is sensitive enough) in a
  887. * hypothetical listening period of 200 time units (TU), 204.8 msec:
  888. *
  889. * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time
  890. *
  891. * */
  892. u32 false_alarms = norm_fa * 200 * 1024;
  893. u32 max_false_alarms = MAX_FA_CCK * rx_enable_time;
  894. u32 min_false_alarms = MIN_FA_CCK * rx_enable_time;
  895. struct iwl4965_sensitivity_data *data = NULL;
  896. data = &(priv->sensitivity_data);
  897. data->nrg_auto_corr_silence_diff = 0;
  898. /* Find max silence rssi among all 3 receivers.
  899. * This is background noise, which may include transmissions from other
  900. * networks, measured during silence before our network's beacon */
  901. silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a &
  902. ALL_BAND_FILTER) >> 8);
  903. silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b &
  904. ALL_BAND_FILTER) >> 8);
  905. silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c &
  906. ALL_BAND_FILTER) >> 8);
  907. val = max(silence_rssi_b, silence_rssi_c);
  908. max_silence_rssi = max(silence_rssi_a, (u8) val);
  909. /* Store silence rssi in 20-beacon history table */
  910. data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi;
  911. data->nrg_silence_idx++;
  912. if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L)
  913. data->nrg_silence_idx = 0;
  914. /* Find max silence rssi across 20 beacon history */
  915. for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) {
  916. val = data->nrg_silence_rssi[i];
  917. silence_ref = max(silence_ref, val);
  918. }
  919. IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n",
  920. silence_rssi_a, silence_rssi_b, silence_rssi_c,
  921. silence_ref);
  922. /* Find max rx energy (min value!) among all 3 receivers,
  923. * measured during beacon frame.
  924. * Save it in 10-beacon history table. */
  925. i = data->nrg_energy_idx;
  926. val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c);
  927. data->nrg_value[i] = min(rx_info->beacon_energy_a, val);
  928. data->nrg_energy_idx++;
  929. if (data->nrg_energy_idx >= 10)
  930. data->nrg_energy_idx = 0;
  931. /* Find min rx energy (max value) across 10 beacon history.
  932. * This is the minimum signal level that we want to receive well.
  933. * Add backoff (margin so we don't miss slightly lower energy frames).
  934. * This establishes an upper bound (min value) for energy threshold. */
  935. max_nrg_cck = data->nrg_value[0];
  936. for (i = 1; i < 10; i++)
  937. max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i]));
  938. max_nrg_cck += 6;
  939. IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n",
  940. rx_info->beacon_energy_a, rx_info->beacon_energy_b,
  941. rx_info->beacon_energy_c, max_nrg_cck - 6);
  942. /* Count number of consecutive beacons with fewer-than-desired
  943. * false alarms. */
  944. if (false_alarms < min_false_alarms)
  945. data->num_in_cck_no_fa++;
  946. else
  947. data->num_in_cck_no_fa = 0;
  948. IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n",
  949. data->num_in_cck_no_fa);
  950. /* If we got too many false alarms this time, reduce sensitivity */
  951. if (false_alarms > max_false_alarms) {
  952. IWL_DEBUG_CALIB("norm FA %u > max FA %u\n",
  953. false_alarms, max_false_alarms);
  954. IWL_DEBUG_CALIB("... reducing sensitivity\n");
  955. data->nrg_curr_state = IWL_FA_TOO_MANY;
  956. if (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK) {
  957. /* Store for "fewer than desired" on later beacon */
  958. data->nrg_silence_ref = silence_ref;
  959. /* increase energy threshold (reduce nrg value)
  960. * to decrease sensitivity */
  961. if (data->nrg_th_cck > (NRG_MAX_CCK + NRG_STEP_CCK))
  962. data->nrg_th_cck = data->nrg_th_cck
  963. - NRG_STEP_CCK;
  964. }
  965. /* increase auto_corr values to decrease sensitivity */
  966. if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK)
  967. data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1;
  968. else {
  969. val = data->auto_corr_cck + AUTO_CORR_STEP_CCK;
  970. data->auto_corr_cck = min((u32)AUTO_CORR_MAX_CCK, val);
  971. }
  972. val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK;
  973. data->auto_corr_cck_mrc = min((u32)AUTO_CORR_MAX_CCK_MRC, val);
  974. /* Else if we got fewer than desired, increase sensitivity */
  975. } else if (false_alarms < min_false_alarms) {
  976. data->nrg_curr_state = IWL_FA_TOO_FEW;
  977. /* Compare silence level with silence level for most recent
  978. * healthy number or too many false alarms */
  979. data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref -
  980. (s32)silence_ref;
  981. IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n",
  982. false_alarms, min_false_alarms,
  983. data->nrg_auto_corr_silence_diff);
  984. /* Increase value to increase sensitivity, but only if:
  985. * 1a) previous beacon did *not* have *too many* false alarms
  986. * 1b) AND there's a significant difference in Rx levels
  987. * from a previous beacon with too many, or healthy # FAs
  988. * OR 2) We've seen a lot of beacons (100) with too few
  989. * false alarms */
  990. if ((data->nrg_prev_state != IWL_FA_TOO_MANY) &&
  991. ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
  992. (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
  993. IWL_DEBUG_CALIB("... increasing sensitivity\n");
  994. /* Increase nrg value to increase sensitivity */
  995. val = data->nrg_th_cck + NRG_STEP_CCK;
  996. data->nrg_th_cck = min((u32)NRG_MIN_CCK, val);
  997. /* Decrease auto_corr values to increase sensitivity */
  998. val = data->auto_corr_cck - AUTO_CORR_STEP_CCK;
  999. data->auto_corr_cck = max((u32)AUTO_CORR_MIN_CCK, val);
  1000. val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK;
  1001. data->auto_corr_cck_mrc =
  1002. max((u32)AUTO_CORR_MIN_CCK_MRC, val);
  1003. } else
  1004. IWL_DEBUG_CALIB("... but not changing sensitivity\n");
  1005. /* Else we got a healthy number of false alarms, keep status quo */
  1006. } else {
  1007. IWL_DEBUG_CALIB(" FA in safe zone\n");
  1008. data->nrg_curr_state = IWL_FA_GOOD_RANGE;
  1009. /* Store for use in "fewer than desired" with later beacon */
  1010. data->nrg_silence_ref = silence_ref;
  1011. /* If previous beacon had too many false alarms,
  1012. * give it some extra margin by reducing sensitivity again
  1013. * (but don't go below measured energy of desired Rx) */
  1014. if (IWL_FA_TOO_MANY == data->nrg_prev_state) {
  1015. IWL_DEBUG_CALIB("... increasing margin\n");
  1016. data->nrg_th_cck -= NRG_MARGIN;
  1017. }
  1018. }
  1019. /* Make sure the energy threshold does not go above the measured
  1020. * energy of the desired Rx signals (reduced by backoff margin),
  1021. * or else we might start missing Rx frames.
  1022. * Lower value is higher energy, so we use max()!
  1023. */
  1024. data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck);
  1025. IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck);
  1026. data->nrg_prev_state = data->nrg_curr_state;
  1027. return 0;
  1028. }
  1029. static int iwl4965_sens_auto_corr_ofdm(struct iwl_priv *priv,
  1030. u32 norm_fa,
  1031. u32 rx_enable_time)
  1032. {
  1033. u32 val;
  1034. u32 false_alarms = norm_fa * 200 * 1024;
  1035. u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time;
  1036. u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time;
  1037. struct iwl4965_sensitivity_data *data = NULL;
  1038. data = &(priv->sensitivity_data);
  1039. /* If we got too many false alarms this time, reduce sensitivity */
  1040. if (false_alarms > max_false_alarms) {
  1041. IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n",
  1042. false_alarms, max_false_alarms);
  1043. val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM;
  1044. data->auto_corr_ofdm =
  1045. min((u32)AUTO_CORR_MAX_OFDM, val);
  1046. val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM;
  1047. data->auto_corr_ofdm_mrc =
  1048. min((u32)AUTO_CORR_MAX_OFDM_MRC, val);
  1049. val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM;
  1050. data->auto_corr_ofdm_x1 =
  1051. min((u32)AUTO_CORR_MAX_OFDM_X1, val);
  1052. val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM;
  1053. data->auto_corr_ofdm_mrc_x1 =
  1054. min((u32)AUTO_CORR_MAX_OFDM_MRC_X1, val);
  1055. }
  1056. /* Else if we got fewer than desired, increase sensitivity */
  1057. else if (false_alarms < min_false_alarms) {
  1058. IWL_DEBUG_CALIB("norm FA %u < min FA %u\n",
  1059. false_alarms, min_false_alarms);
  1060. val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM;
  1061. data->auto_corr_ofdm =
  1062. max((u32)AUTO_CORR_MIN_OFDM, val);
  1063. val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM;
  1064. data->auto_corr_ofdm_mrc =
  1065. max((u32)AUTO_CORR_MIN_OFDM_MRC, val);
  1066. val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM;
  1067. data->auto_corr_ofdm_x1 =
  1068. max((u32)AUTO_CORR_MIN_OFDM_X1, val);
  1069. val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM;
  1070. data->auto_corr_ofdm_mrc_x1 =
  1071. max((u32)AUTO_CORR_MIN_OFDM_MRC_X1, val);
  1072. }
  1073. else
  1074. IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n",
  1075. min_false_alarms, false_alarms, max_false_alarms);
  1076. return 0;
  1077. }
  1078. static int iwl4965_sensitivity_callback(struct iwl_priv *priv,
  1079. struct iwl_cmd *cmd, struct sk_buff *skb)
  1080. {
  1081. /* We didn't cache the SKB; let the caller free it */
  1082. return 1;
  1083. }
  1084. /* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
  1085. static int iwl4965_sensitivity_write(struct iwl_priv *priv, u8 flags)
  1086. {
  1087. struct iwl4965_sensitivity_cmd cmd ;
  1088. struct iwl4965_sensitivity_data *data = NULL;
  1089. struct iwl_host_cmd cmd_out = {
  1090. .id = SENSITIVITY_CMD,
  1091. .len = sizeof(struct iwl4965_sensitivity_cmd),
  1092. .meta.flags = flags,
  1093. .data = &cmd,
  1094. };
  1095. int ret;
  1096. data = &(priv->sensitivity_data);
  1097. memset(&cmd, 0, sizeof(cmd));
  1098. cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] =
  1099. cpu_to_le16((u16)data->auto_corr_ofdm);
  1100. cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] =
  1101. cpu_to_le16((u16)data->auto_corr_ofdm_mrc);
  1102. cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] =
  1103. cpu_to_le16((u16)data->auto_corr_ofdm_x1);
  1104. cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] =
  1105. cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1);
  1106. cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] =
  1107. cpu_to_le16((u16)data->auto_corr_cck);
  1108. cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] =
  1109. cpu_to_le16((u16)data->auto_corr_cck_mrc);
  1110. cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] =
  1111. cpu_to_le16((u16)data->nrg_th_cck);
  1112. cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] =
  1113. cpu_to_le16((u16)data->nrg_th_ofdm);
  1114. cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] =
  1115. __constant_cpu_to_le16(190);
  1116. cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] =
  1117. __constant_cpu_to_le16(390);
  1118. cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] =
  1119. __constant_cpu_to_le16(62);
  1120. IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n",
  1121. data->auto_corr_ofdm, data->auto_corr_ofdm_mrc,
  1122. data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1,
  1123. data->nrg_th_ofdm);
  1124. IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n",
  1125. data->auto_corr_cck, data->auto_corr_cck_mrc,
  1126. data->nrg_th_cck);
  1127. /* Update uCode's "work" table, and copy it to DSP */
  1128. cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE;
  1129. if (flags & CMD_ASYNC)
  1130. cmd_out.meta.u.callback = iwl4965_sensitivity_callback;
  1131. /* Don't send command to uCode if nothing has changed */
  1132. if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]),
  1133. sizeof(u16)*HD_TABLE_SIZE)) {
  1134. IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n");
  1135. return 0;
  1136. }
  1137. /* Copy table for comparison next time */
  1138. memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
  1139. sizeof(u16)*HD_TABLE_SIZE);
  1140. ret = iwl_send_cmd(priv, &cmd_out);
  1141. if (ret)
  1142. IWL_ERROR("SENSITIVITY_CMD failed\n");
  1143. return ret;
  1144. }
  1145. void iwl4965_init_sensitivity(struct iwl_priv *priv, u8 flags, u8 force)
  1146. {
  1147. struct iwl4965_sensitivity_data *data = NULL;
  1148. int i;
  1149. int ret = 0;
  1150. IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n");
  1151. if (force)
  1152. memset(&(priv->sensitivity_tbl[0]), 0,
  1153. sizeof(u16)*HD_TABLE_SIZE);
  1154. /* Clear driver's sensitivity algo data */
  1155. data = &(priv->sensitivity_data);
  1156. memset(data, 0, sizeof(struct iwl4965_sensitivity_data));
  1157. data->num_in_cck_no_fa = 0;
  1158. data->nrg_curr_state = IWL_FA_TOO_MANY;
  1159. data->nrg_prev_state = IWL_FA_TOO_MANY;
  1160. data->nrg_silence_ref = 0;
  1161. data->nrg_silence_idx = 0;
  1162. data->nrg_energy_idx = 0;
  1163. for (i = 0; i < 10; i++)
  1164. data->nrg_value[i] = 0;
  1165. for (i = 0; i < NRG_NUM_PREV_STAT_L; i++)
  1166. data->nrg_silence_rssi[i] = 0;
  1167. data->auto_corr_ofdm = 90;
  1168. data->auto_corr_ofdm_mrc = 170;
  1169. data->auto_corr_ofdm_x1 = 105;
  1170. data->auto_corr_ofdm_mrc_x1 = 220;
  1171. data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF;
  1172. data->auto_corr_cck_mrc = 200;
  1173. data->nrg_th_cck = 100;
  1174. data->nrg_th_ofdm = 100;
  1175. data->last_bad_plcp_cnt_ofdm = 0;
  1176. data->last_fa_cnt_ofdm = 0;
  1177. data->last_bad_plcp_cnt_cck = 0;
  1178. data->last_fa_cnt_cck = 0;
  1179. /* Clear prior Sensitivity command data to force send to uCode */
  1180. if (force)
  1181. memset(&(priv->sensitivity_tbl[0]), 0,
  1182. sizeof(u16)*HD_TABLE_SIZE);
  1183. ret |= iwl4965_sensitivity_write(priv, flags);
  1184. IWL_DEBUG_CALIB("<<return 0x%X\n", ret);
  1185. return;
  1186. }
  1187. /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
  1188. * Called after every association, but this runs only once!
  1189. * ... once chain noise is calibrated the first time, it's good forever. */
  1190. void iwl4965_chain_noise_reset(struct iwl_priv *priv)
  1191. {
  1192. struct iwl4965_chain_noise_data *data = NULL;
  1193. data = &(priv->chain_noise_data);
  1194. if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
  1195. struct iwl4965_calibration_cmd cmd;
  1196. memset(&cmd, 0, sizeof(cmd));
  1197. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  1198. cmd.diff_gain_a = 0;
  1199. cmd.diff_gain_b = 0;
  1200. cmd.diff_gain_c = 0;
  1201. iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
  1202. sizeof(cmd), &cmd, NULL);
  1203. msleep(4);
  1204. data->state = IWL_CHAIN_NOISE_ACCUMULATE;
  1205. IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
  1206. }
  1207. return;
  1208. }
  1209. /*
  1210. * Accumulate 20 beacons of signal and noise statistics for each of
  1211. * 3 receivers/antennas/rx-chains, then figure out:
  1212. * 1) Which antennas are connected.
  1213. * 2) Differential rx gain settings to balance the 3 receivers.
  1214. */
  1215. static void iwl4965_noise_calibration(struct iwl_priv *priv,
  1216. struct iwl4965_notif_statistics *stat_resp)
  1217. {
  1218. struct iwl4965_chain_noise_data *data = NULL;
  1219. int ret = 0;
  1220. u32 chain_noise_a;
  1221. u32 chain_noise_b;
  1222. u32 chain_noise_c;
  1223. u32 chain_sig_a;
  1224. u32 chain_sig_b;
  1225. u32 chain_sig_c;
  1226. u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
  1227. u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
  1228. u32 max_average_sig;
  1229. u16 max_average_sig_antenna_i;
  1230. u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
  1231. u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
  1232. u16 i = 0;
  1233. u16 chan_num = INITIALIZATION_VALUE;
  1234. u32 band = INITIALIZATION_VALUE;
  1235. u32 active_chains = 0;
  1236. unsigned long flags;
  1237. struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general);
  1238. data = &(priv->chain_noise_data);
  1239. /* Accumulate just the first 20 beacons after the first association,
  1240. * then we're done forever. */
  1241. if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) {
  1242. if (data->state == IWL_CHAIN_NOISE_ALIVE)
  1243. IWL_DEBUG_CALIB("Wait for noise calib reset\n");
  1244. return;
  1245. }
  1246. spin_lock_irqsave(&priv->lock, flags);
  1247. if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
  1248. IWL_DEBUG_CALIB(" << Interference data unavailable\n");
  1249. spin_unlock_irqrestore(&priv->lock, flags);
  1250. return;
  1251. }
  1252. band = (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) ? 0 : 1;
  1253. chan_num = le16_to_cpu(priv->staging_rxon.channel);
  1254. /* Make sure we accumulate data for just the associated channel
  1255. * (even if scanning). */
  1256. if ((chan_num != (le32_to_cpu(stat_resp->flag) >> 16)) ||
  1257. ((STATISTICS_REPLY_FLG_BAND_24G_MSK ==
  1258. (stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK)) && band)) {
  1259. IWL_DEBUG_CALIB("Stats not from chan=%d, band=%d\n",
  1260. chan_num, band);
  1261. spin_unlock_irqrestore(&priv->lock, flags);
  1262. return;
  1263. }
  1264. /* Accumulate beacon statistics values across 20 beacons */
  1265. chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) &
  1266. IN_BAND_FILTER;
  1267. chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) &
  1268. IN_BAND_FILTER;
  1269. chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) &
  1270. IN_BAND_FILTER;
  1271. chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER;
  1272. chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER;
  1273. chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER;
  1274. spin_unlock_irqrestore(&priv->lock, flags);
  1275. data->beacon_count++;
  1276. data->chain_noise_a = (chain_noise_a + data->chain_noise_a);
  1277. data->chain_noise_b = (chain_noise_b + data->chain_noise_b);
  1278. data->chain_noise_c = (chain_noise_c + data->chain_noise_c);
  1279. data->chain_signal_a = (chain_sig_a + data->chain_signal_a);
  1280. data->chain_signal_b = (chain_sig_b + data->chain_signal_b);
  1281. data->chain_signal_c = (chain_sig_c + data->chain_signal_c);
  1282. IWL_DEBUG_CALIB("chan=%d, band=%d, beacon=%d\n", chan_num, band,
  1283. data->beacon_count);
  1284. IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n",
  1285. chain_sig_a, chain_sig_b, chain_sig_c);
  1286. IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n",
  1287. chain_noise_a, chain_noise_b, chain_noise_c);
  1288. /* If this is the 20th beacon, determine:
  1289. * 1) Disconnected antennas (using signal strengths)
  1290. * 2) Differential gain (using silence noise) to balance receivers */
  1291. if (data->beacon_count == CAL_NUM_OF_BEACONS) {
  1292. /* Analyze signal for disconnected antenna */
  1293. average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS;
  1294. average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS;
  1295. average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS;
  1296. if (average_sig[0] >= average_sig[1]) {
  1297. max_average_sig = average_sig[0];
  1298. max_average_sig_antenna_i = 0;
  1299. active_chains = (1 << max_average_sig_antenna_i);
  1300. } else {
  1301. max_average_sig = average_sig[1];
  1302. max_average_sig_antenna_i = 1;
  1303. active_chains = (1 << max_average_sig_antenna_i);
  1304. }
  1305. if (average_sig[2] >= max_average_sig) {
  1306. max_average_sig = average_sig[2];
  1307. max_average_sig_antenna_i = 2;
  1308. active_chains = (1 << max_average_sig_antenna_i);
  1309. }
  1310. IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n",
  1311. average_sig[0], average_sig[1], average_sig[2]);
  1312. IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n",
  1313. max_average_sig, max_average_sig_antenna_i);
  1314. /* Compare signal strengths for all 3 receivers. */
  1315. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1316. if (i != max_average_sig_antenna_i) {
  1317. s32 rssi_delta = (max_average_sig -
  1318. average_sig[i]);
  1319. /* If signal is very weak, compared with
  1320. * strongest, mark it as disconnected. */
  1321. if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
  1322. data->disconn_array[i] = 1;
  1323. else
  1324. active_chains |= (1 << i);
  1325. IWL_DEBUG_CALIB("i = %d rssiDelta = %d "
  1326. "disconn_array[i] = %d\n",
  1327. i, rssi_delta, data->disconn_array[i]);
  1328. }
  1329. }
  1330. /*If both chains A & B are disconnected -
  1331. * connect B and leave A as is */
  1332. if (data->disconn_array[CHAIN_A] &&
  1333. data->disconn_array[CHAIN_B]) {
  1334. data->disconn_array[CHAIN_B] = 0;
  1335. active_chains |= (1 << CHAIN_B);
  1336. IWL_DEBUG_CALIB("both A & B chains are disconnected! "
  1337. "W/A - declare B as connected\n");
  1338. }
  1339. IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n",
  1340. active_chains);
  1341. /* Save for use within RXON, TX, SCAN commands, etc. */
  1342. priv->valid_antenna = active_chains;
  1343. /* Analyze noise for rx balance */
  1344. average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS);
  1345. average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS);
  1346. average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS);
  1347. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1348. if (!(data->disconn_array[i]) &&
  1349. (average_noise[i] <= min_average_noise)) {
  1350. /* This means that chain i is active and has
  1351. * lower noise values so far: */
  1352. min_average_noise = average_noise[i];
  1353. min_average_noise_antenna_i = i;
  1354. }
  1355. }
  1356. data->delta_gain_code[min_average_noise_antenna_i] = 0;
  1357. IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n",
  1358. average_noise[0], average_noise[1],
  1359. average_noise[2]);
  1360. IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n",
  1361. min_average_noise, min_average_noise_antenna_i);
  1362. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1363. s32 delta_g = 0;
  1364. if (!(data->disconn_array[i]) &&
  1365. (data->delta_gain_code[i] ==
  1366. CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
  1367. delta_g = average_noise[i] - min_average_noise;
  1368. data->delta_gain_code[i] = (u8)((delta_g *
  1369. 10) / 15);
  1370. if (CHAIN_NOISE_MAX_DELTA_GAIN_CODE <
  1371. data->delta_gain_code[i])
  1372. data->delta_gain_code[i] =
  1373. CHAIN_NOISE_MAX_DELTA_GAIN_CODE;
  1374. data->delta_gain_code[i] =
  1375. (data->delta_gain_code[i] | (1 << 2));
  1376. } else
  1377. data->delta_gain_code[i] = 0;
  1378. }
  1379. IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
  1380. data->delta_gain_code[0],
  1381. data->delta_gain_code[1],
  1382. data->delta_gain_code[2]);
  1383. /* Differential gain gets sent to uCode only once */
  1384. if (!data->radio_write) {
  1385. struct iwl4965_calibration_cmd cmd;
  1386. data->radio_write = 1;
  1387. memset(&cmd, 0, sizeof(cmd));
  1388. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  1389. cmd.diff_gain_a = data->delta_gain_code[0];
  1390. cmd.diff_gain_b = data->delta_gain_code[1];
  1391. cmd.diff_gain_c = data->delta_gain_code[2];
  1392. ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  1393. sizeof(cmd), &cmd);
  1394. if (ret)
  1395. IWL_DEBUG_CALIB("fail sending cmd "
  1396. "REPLY_PHY_CALIBRATION_CMD \n");
  1397. /* TODO we might want recalculate
  1398. * rx_chain in rxon cmd */
  1399. /* Mark so we run this algo only once! */
  1400. data->state = IWL_CHAIN_NOISE_CALIBRATED;
  1401. }
  1402. data->chain_noise_a = 0;
  1403. data->chain_noise_b = 0;
  1404. data->chain_noise_c = 0;
  1405. data->chain_signal_a = 0;
  1406. data->chain_signal_b = 0;
  1407. data->chain_signal_c = 0;
  1408. data->beacon_count = 0;
  1409. }
  1410. return;
  1411. }
  1412. static void iwl4965_sensitivity_calibration(struct iwl_priv *priv,
  1413. struct iwl4965_notif_statistics *resp)
  1414. {
  1415. u32 rx_enable_time;
  1416. u32 fa_cck;
  1417. u32 fa_ofdm;
  1418. u32 bad_plcp_cck;
  1419. u32 bad_plcp_ofdm;
  1420. u32 norm_fa_ofdm;
  1421. u32 norm_fa_cck;
  1422. struct iwl4965_sensitivity_data *data = NULL;
  1423. struct statistics_rx_non_phy *rx_info = &(resp->rx.general);
  1424. struct statistics_rx *statistics = &(resp->rx);
  1425. unsigned long flags;
  1426. struct statistics_general_data statis;
  1427. int ret;
  1428. data = &(priv->sensitivity_data);
  1429. if (!iwl_is_associated(priv)) {
  1430. IWL_DEBUG_CALIB("<< - not associated\n");
  1431. return;
  1432. }
  1433. spin_lock_irqsave(&priv->lock, flags);
  1434. if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
  1435. IWL_DEBUG_CALIB("<< invalid data.\n");
  1436. spin_unlock_irqrestore(&priv->lock, flags);
  1437. return;
  1438. }
  1439. /* Extract Statistics: */
  1440. rx_enable_time = le32_to_cpu(rx_info->channel_load);
  1441. fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt);
  1442. fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt);
  1443. bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err);
  1444. bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err);
  1445. statis.beacon_silence_rssi_a =
  1446. le32_to_cpu(statistics->general.beacon_silence_rssi_a);
  1447. statis.beacon_silence_rssi_b =
  1448. le32_to_cpu(statistics->general.beacon_silence_rssi_b);
  1449. statis.beacon_silence_rssi_c =
  1450. le32_to_cpu(statistics->general.beacon_silence_rssi_c);
  1451. statis.beacon_energy_a =
  1452. le32_to_cpu(statistics->general.beacon_energy_a);
  1453. statis.beacon_energy_b =
  1454. le32_to_cpu(statistics->general.beacon_energy_b);
  1455. statis.beacon_energy_c =
  1456. le32_to_cpu(statistics->general.beacon_energy_c);
  1457. spin_unlock_irqrestore(&priv->lock, flags);
  1458. IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time);
  1459. if (!rx_enable_time) {
  1460. IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n");
  1461. return;
  1462. }
  1463. /* These statistics increase monotonically, and do not reset
  1464. * at each beacon. Calculate difference from last value, or just
  1465. * use the new statistics value if it has reset or wrapped around. */
  1466. if (data->last_bad_plcp_cnt_cck > bad_plcp_cck)
  1467. data->last_bad_plcp_cnt_cck = bad_plcp_cck;
  1468. else {
  1469. bad_plcp_cck -= data->last_bad_plcp_cnt_cck;
  1470. data->last_bad_plcp_cnt_cck += bad_plcp_cck;
  1471. }
  1472. if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm)
  1473. data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm;
  1474. else {
  1475. bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm;
  1476. data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm;
  1477. }
  1478. if (data->last_fa_cnt_ofdm > fa_ofdm)
  1479. data->last_fa_cnt_ofdm = fa_ofdm;
  1480. else {
  1481. fa_ofdm -= data->last_fa_cnt_ofdm;
  1482. data->last_fa_cnt_ofdm += fa_ofdm;
  1483. }
  1484. if (data->last_fa_cnt_cck > fa_cck)
  1485. data->last_fa_cnt_cck = fa_cck;
  1486. else {
  1487. fa_cck -= data->last_fa_cnt_cck;
  1488. data->last_fa_cnt_cck += fa_cck;
  1489. }
  1490. /* Total aborted signal locks */
  1491. norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm;
  1492. norm_fa_cck = fa_cck + bad_plcp_cck;
  1493. IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck,
  1494. bad_plcp_cck, fa_ofdm, bad_plcp_ofdm);
  1495. iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
  1496. iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
  1497. ret = iwl4965_sensitivity_write(priv, CMD_ASYNC);
  1498. return;
  1499. }
  1500. static void iwl4965_bg_sensitivity_work(struct work_struct *work)
  1501. {
  1502. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1503. sensitivity_work);
  1504. mutex_lock(&priv->mutex);
  1505. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1506. test_bit(STATUS_SCANNING, &priv->status)) {
  1507. mutex_unlock(&priv->mutex);
  1508. return;
  1509. }
  1510. if (priv->start_calib) {
  1511. iwl4965_noise_calibration(priv, &priv->statistics);
  1512. if (priv->sensitivity_data.state ==
  1513. IWL_SENS_CALIB_NEED_REINIT) {
  1514. iwl4965_init_sensitivity(priv, CMD_ASYNC, 0);
  1515. priv->sensitivity_data.state = IWL_SENS_CALIB_ALLOWED;
  1516. } else
  1517. iwl4965_sensitivity_calibration(priv,
  1518. &priv->statistics);
  1519. }
  1520. mutex_unlock(&priv->mutex);
  1521. return;
  1522. }
  1523. #endif /*CONFIG_IWL4965_SENSITIVITY*/
  1524. static void iwl4965_bg_txpower_work(struct work_struct *work)
  1525. {
  1526. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1527. txpower_work);
  1528. /* If a scan happened to start before we got here
  1529. * then just return; the statistics notification will
  1530. * kick off another scheduled work to compensate for
  1531. * any temperature delta we missed here. */
  1532. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1533. test_bit(STATUS_SCANNING, &priv->status))
  1534. return;
  1535. mutex_lock(&priv->mutex);
  1536. /* Regardless of if we are assocaited, we must reconfigure the
  1537. * TX power since frames can be sent on non-radar channels while
  1538. * not associated */
  1539. iwl4965_hw_reg_send_txpower(priv);
  1540. /* Update last_temperature to keep is_calib_needed from running
  1541. * when it isn't needed... */
  1542. priv->last_temperature = priv->temperature;
  1543. mutex_unlock(&priv->mutex);
  1544. }
  1545. /*
  1546. * Acquire priv->lock before calling this function !
  1547. */
  1548. static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
  1549. {
  1550. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  1551. (index & 0xff) | (txq_id << 8));
  1552. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
  1553. }
  1554. /**
  1555. * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
  1556. * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
  1557. * @scd_retry: (1) Indicates queue will be used in aggregation mode
  1558. *
  1559. * NOTE: Acquire priv->lock before calling this function !
  1560. */
  1561. static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
  1562. struct iwl4965_tx_queue *txq,
  1563. int tx_fifo_id, int scd_retry)
  1564. {
  1565. int txq_id = txq->q.id;
  1566. /* Find out whether to activate Tx queue */
  1567. int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
  1568. /* Set up and activate */
  1569. iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  1570. (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  1571. (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
  1572. (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
  1573. (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  1574. SCD_QUEUE_STTS_REG_MSK);
  1575. txq->sched_retry = scd_retry;
  1576. IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
  1577. active ? "Activate" : "Deactivate",
  1578. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  1579. }
  1580. static const u16 default_queue_to_tx_fifo[] = {
  1581. IWL_TX_FIFO_AC3,
  1582. IWL_TX_FIFO_AC2,
  1583. IWL_TX_FIFO_AC1,
  1584. IWL_TX_FIFO_AC0,
  1585. IWL_CMD_FIFO_NUM,
  1586. IWL_TX_FIFO_HCCA_1,
  1587. IWL_TX_FIFO_HCCA_2
  1588. };
  1589. static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
  1590. {
  1591. set_bit(txq_id, &priv->txq_ctx_active_msk);
  1592. }
  1593. static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
  1594. {
  1595. clear_bit(txq_id, &priv->txq_ctx_active_msk);
  1596. }
  1597. int iwl4965_alive_notify(struct iwl_priv *priv)
  1598. {
  1599. u32 a;
  1600. int i = 0;
  1601. unsigned long flags;
  1602. int ret;
  1603. spin_lock_irqsave(&priv->lock, flags);
  1604. #ifdef CONFIG_IWL4965_SENSITIVITY
  1605. memset(&(priv->sensitivity_data), 0,
  1606. sizeof(struct iwl4965_sensitivity_data));
  1607. memset(&(priv->chain_noise_data), 0,
  1608. sizeof(struct iwl4965_chain_noise_data));
  1609. for (i = 0; i < NUM_RX_CHAINS; i++)
  1610. priv->chain_noise_data.delta_gain_code[i] =
  1611. CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
  1612. #endif /* CONFIG_IWL4965_SENSITIVITY*/
  1613. ret = iwl_grab_nic_access(priv);
  1614. if (ret) {
  1615. spin_unlock_irqrestore(&priv->lock, flags);
  1616. return ret;
  1617. }
  1618. /* Clear 4965's internal Tx Scheduler data base */
  1619. priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
  1620. a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
  1621. for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  1622. iwl_write_targ_mem(priv, a, 0);
  1623. for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
  1624. iwl_write_targ_mem(priv, a, 0);
  1625. for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
  1626. iwl_write_targ_mem(priv, a, 0);
  1627. /* Tel 4965 where to find Tx byte count tables */
  1628. iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
  1629. (priv->shared_phys +
  1630. offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
  1631. /* Disable chain mode for all queues */
  1632. iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
  1633. /* Initialize each Tx queue (including the command queue) */
  1634. for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
  1635. /* TFD circular buffer read/write indexes */
  1636. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
  1637. iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
  1638. /* Max Tx Window size for Scheduler-ACK mode */
  1639. iwl_write_targ_mem(priv, priv->scd_base_addr +
  1640. SCD_CONTEXT_QUEUE_OFFSET(i),
  1641. (SCD_WIN_SIZE <<
  1642. SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  1643. SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  1644. /* Frame limit */
  1645. iwl_write_targ_mem(priv, priv->scd_base_addr +
  1646. SCD_CONTEXT_QUEUE_OFFSET(i) +
  1647. sizeof(u32),
  1648. (SCD_FRAME_LIMIT <<
  1649. SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  1650. SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  1651. }
  1652. iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
  1653. (1 << priv->hw_setting.max_txq_num) - 1);
  1654. /* Activate all Tx DMA/FIFO channels */
  1655. iwl_write_prph(priv, IWL49_SCD_TXFACT,
  1656. SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
  1657. iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
  1658. /* Map each Tx/cmd queue to its corresponding fifo */
  1659. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  1660. int ac = default_queue_to_tx_fifo[i];
  1661. iwl4965_txq_ctx_activate(priv, i);
  1662. iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
  1663. }
  1664. iwl_release_nic_access(priv);
  1665. spin_unlock_irqrestore(&priv->lock, flags);
  1666. return ret;
  1667. }
  1668. /**
  1669. * iwl4965_hw_set_hw_setting
  1670. *
  1671. * Called when initializing driver
  1672. */
  1673. int iwl4965_hw_set_hw_setting(struct iwl_priv *priv)
  1674. {
  1675. if ((priv->cfg->mod_params->num_of_queues > IWL_MAX_NUM_QUEUES) ||
  1676. (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
  1677. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  1678. IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
  1679. return -EINVAL;
  1680. }
  1681. priv->hw_setting.max_txq_num = priv->cfg->mod_params->num_of_queues;
  1682. priv->hw_setting.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
  1683. priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
  1684. priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1685. if (priv->cfg->mod_params->amsdu_size_8K)
  1686. priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_8K;
  1687. else
  1688. priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_4K;
  1689. priv->hw_setting.max_pkt_size = priv->hw_setting.rx_buf_size - 256;
  1690. priv->hw_setting.max_stations = IWL4965_STATION_COUNT;
  1691. priv->hw_setting.bcast_sta_id = IWL4965_BROADCAST_ID;
  1692. priv->hw_setting.tx_ant_num = 2;
  1693. return 0;
  1694. }
  1695. /**
  1696. * iwl4965_hw_txq_ctx_free - Free TXQ Context
  1697. *
  1698. * Destroy all TX DMA queues and structures
  1699. */
  1700. void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
  1701. {
  1702. int txq_id;
  1703. /* Tx queues */
  1704. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
  1705. iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
  1706. /* Keep-warm buffer */
  1707. iwl4965_kw_free(priv);
  1708. }
  1709. /**
  1710. * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  1711. *
  1712. * Does NOT advance any TFD circular buffer read/write indexes
  1713. * Does NOT free the TFD itself (which is within circular buffer)
  1714. */
  1715. int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
  1716. {
  1717. struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
  1718. struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
  1719. struct pci_dev *dev = priv->pci_dev;
  1720. int i;
  1721. int counter = 0;
  1722. int index, is_odd;
  1723. /* Host command buffers stay mapped in memory, nothing to clean */
  1724. if (txq->q.id == IWL_CMD_QUEUE_NUM)
  1725. return 0;
  1726. /* Sanity check on number of chunks */
  1727. counter = IWL_GET_BITS(*bd, num_tbs);
  1728. if (counter > MAX_NUM_OF_TBS) {
  1729. IWL_ERROR("Too many chunks: %i\n", counter);
  1730. /* @todo issue fatal error, it is quite serious situation */
  1731. return 0;
  1732. }
  1733. /* Unmap chunks, if any.
  1734. * TFD info for odd chunks is different format than for even chunks. */
  1735. for (i = 0; i < counter; i++) {
  1736. index = i / 2;
  1737. is_odd = i & 0x1;
  1738. if (is_odd)
  1739. pci_unmap_single(
  1740. dev,
  1741. IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
  1742. (IWL_GET_BITS(bd->pa[index],
  1743. tb2_addr_hi20) << 16),
  1744. IWL_GET_BITS(bd->pa[index], tb2_len),
  1745. PCI_DMA_TODEVICE);
  1746. else if (i > 0)
  1747. pci_unmap_single(dev,
  1748. le32_to_cpu(bd->pa[index].tb1_addr),
  1749. IWL_GET_BITS(bd->pa[index], tb1_len),
  1750. PCI_DMA_TODEVICE);
  1751. /* Free SKB, if any, for this chunk */
  1752. if (txq->txb[txq->q.read_ptr].skb[i]) {
  1753. struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
  1754. dev_kfree_skb(skb);
  1755. txq->txb[txq->q.read_ptr].skb[i] = NULL;
  1756. }
  1757. }
  1758. return 0;
  1759. }
  1760. int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
  1761. {
  1762. IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
  1763. return -EINVAL;
  1764. }
  1765. static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
  1766. {
  1767. s32 sign = 1;
  1768. if (num < 0) {
  1769. sign = -sign;
  1770. num = -num;
  1771. }
  1772. if (denom < 0) {
  1773. sign = -sign;
  1774. denom = -denom;
  1775. }
  1776. *res = 1;
  1777. *res = ((num * 2 + denom) / (denom * 2)) * sign;
  1778. return 1;
  1779. }
  1780. /**
  1781. * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
  1782. *
  1783. * Determines power supply voltage compensation for txpower calculations.
  1784. * Returns number of 1/2-dB steps to subtract from gain table index,
  1785. * to compensate for difference between power supply voltage during
  1786. * factory measurements, vs. current power supply voltage.
  1787. *
  1788. * Voltage indication is higher for lower voltage.
  1789. * Lower voltage requires more gain (lower gain table index).
  1790. */
  1791. static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
  1792. s32 current_voltage)
  1793. {
  1794. s32 comp = 0;
  1795. if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
  1796. (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
  1797. return 0;
  1798. iwl4965_math_div_round(current_voltage - eeprom_voltage,
  1799. TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
  1800. if (current_voltage > eeprom_voltage)
  1801. comp *= 2;
  1802. if ((comp < -2) || (comp > 2))
  1803. comp = 0;
  1804. return comp;
  1805. }
  1806. static const struct iwl_channel_info *
  1807. iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
  1808. enum ieee80211_band band, u16 channel)
  1809. {
  1810. const struct iwl_channel_info *ch_info;
  1811. ch_info = iwl_get_channel_info(priv, band, channel);
  1812. if (!is_channel_valid(ch_info))
  1813. return NULL;
  1814. return ch_info;
  1815. }
  1816. static s32 iwl4965_get_tx_atten_grp(u16 channel)
  1817. {
  1818. if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
  1819. channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
  1820. return CALIB_CH_GROUP_5;
  1821. if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
  1822. channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
  1823. return CALIB_CH_GROUP_1;
  1824. if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
  1825. channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
  1826. return CALIB_CH_GROUP_2;
  1827. if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
  1828. channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
  1829. return CALIB_CH_GROUP_3;
  1830. if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
  1831. channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
  1832. return CALIB_CH_GROUP_4;
  1833. IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
  1834. return -1;
  1835. }
  1836. static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
  1837. {
  1838. s32 b = -1;
  1839. for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
  1840. if (priv->eeprom.calib_info.band_info[b].ch_from == 0)
  1841. continue;
  1842. if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from)
  1843. && (channel <= priv->eeprom.calib_info.band_info[b].ch_to))
  1844. break;
  1845. }
  1846. return b;
  1847. }
  1848. static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
  1849. {
  1850. s32 val;
  1851. if (x2 == x1)
  1852. return y1;
  1853. else {
  1854. iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
  1855. return val + y2;
  1856. }
  1857. }
  1858. /**
  1859. * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
  1860. *
  1861. * Interpolates factory measurements from the two sample channels within a
  1862. * sub-band, to apply to channel of interest. Interpolation is proportional to
  1863. * differences in channel frequencies, which is proportional to differences
  1864. * in channel number.
  1865. */
  1866. static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
  1867. struct iwl4965_eeprom_calib_ch_info *chan_info)
  1868. {
  1869. s32 s = -1;
  1870. u32 c;
  1871. u32 m;
  1872. const struct iwl4965_eeprom_calib_measure *m1;
  1873. const struct iwl4965_eeprom_calib_measure *m2;
  1874. struct iwl4965_eeprom_calib_measure *omeas;
  1875. u32 ch_i1;
  1876. u32 ch_i2;
  1877. s = iwl4965_get_sub_band(priv, channel);
  1878. if (s >= EEPROM_TX_POWER_BANDS) {
  1879. IWL_ERROR("Tx Power can not find channel %d ", channel);
  1880. return -1;
  1881. }
  1882. ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num;
  1883. ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num;
  1884. chan_info->ch_num = (u8) channel;
  1885. IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
  1886. channel, s, ch_i1, ch_i2);
  1887. for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
  1888. for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
  1889. m1 = &(priv->eeprom.calib_info.band_info[s].ch1.
  1890. measurements[c][m]);
  1891. m2 = &(priv->eeprom.calib_info.band_info[s].ch2.
  1892. measurements[c][m]);
  1893. omeas = &(chan_info->measurements[c][m]);
  1894. omeas->actual_pow =
  1895. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1896. m1->actual_pow,
  1897. ch_i2,
  1898. m2->actual_pow);
  1899. omeas->gain_idx =
  1900. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1901. m1->gain_idx, ch_i2,
  1902. m2->gain_idx);
  1903. omeas->temperature =
  1904. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1905. m1->temperature,
  1906. ch_i2,
  1907. m2->temperature);
  1908. omeas->pa_det =
  1909. (s8) iwl4965_interpolate_value(channel, ch_i1,
  1910. m1->pa_det, ch_i2,
  1911. m2->pa_det);
  1912. IWL_DEBUG_TXPOWER
  1913. ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
  1914. m1->actual_pow, m2->actual_pow, omeas->actual_pow);
  1915. IWL_DEBUG_TXPOWER
  1916. ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
  1917. m1->gain_idx, m2->gain_idx, omeas->gain_idx);
  1918. IWL_DEBUG_TXPOWER
  1919. ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
  1920. m1->pa_det, m2->pa_det, omeas->pa_det);
  1921. IWL_DEBUG_TXPOWER
  1922. ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
  1923. m1->temperature, m2->temperature,
  1924. omeas->temperature);
  1925. }
  1926. }
  1927. return 0;
  1928. }
  1929. /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
  1930. * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
  1931. static s32 back_off_table[] = {
  1932. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
  1933. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
  1934. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
  1935. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
  1936. 10 /* CCK */
  1937. };
  1938. /* Thermal compensation values for txpower for various frequency ranges ...
  1939. * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
  1940. static struct iwl4965_txpower_comp_entry {
  1941. s32 degrees_per_05db_a;
  1942. s32 degrees_per_05db_a_denom;
  1943. } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
  1944. {9, 2}, /* group 0 5.2, ch 34-43 */
  1945. {4, 1}, /* group 1 5.2, ch 44-70 */
  1946. {4, 1}, /* group 2 5.2, ch 71-124 */
  1947. {4, 1}, /* group 3 5.2, ch 125-200 */
  1948. {3, 1} /* group 4 2.4, ch all */
  1949. };
  1950. static s32 get_min_power_index(s32 rate_power_index, u32 band)
  1951. {
  1952. if (!band) {
  1953. if ((rate_power_index & 7) <= 4)
  1954. return MIN_TX_GAIN_INDEX_52GHZ_EXT;
  1955. }
  1956. return MIN_TX_GAIN_INDEX;
  1957. }
  1958. struct gain_entry {
  1959. u8 dsp;
  1960. u8 radio;
  1961. };
  1962. static const struct gain_entry gain_table[2][108] = {
  1963. /* 5.2GHz power gain index table */
  1964. {
  1965. {123, 0x3F}, /* highest txpower */
  1966. {117, 0x3F},
  1967. {110, 0x3F},
  1968. {104, 0x3F},
  1969. {98, 0x3F},
  1970. {110, 0x3E},
  1971. {104, 0x3E},
  1972. {98, 0x3E},
  1973. {110, 0x3D},
  1974. {104, 0x3D},
  1975. {98, 0x3D},
  1976. {110, 0x3C},
  1977. {104, 0x3C},
  1978. {98, 0x3C},
  1979. {110, 0x3B},
  1980. {104, 0x3B},
  1981. {98, 0x3B},
  1982. {110, 0x3A},
  1983. {104, 0x3A},
  1984. {98, 0x3A},
  1985. {110, 0x39},
  1986. {104, 0x39},
  1987. {98, 0x39},
  1988. {110, 0x38},
  1989. {104, 0x38},
  1990. {98, 0x38},
  1991. {110, 0x37},
  1992. {104, 0x37},
  1993. {98, 0x37},
  1994. {110, 0x36},
  1995. {104, 0x36},
  1996. {98, 0x36},
  1997. {110, 0x35},
  1998. {104, 0x35},
  1999. {98, 0x35},
  2000. {110, 0x34},
  2001. {104, 0x34},
  2002. {98, 0x34},
  2003. {110, 0x33},
  2004. {104, 0x33},
  2005. {98, 0x33},
  2006. {110, 0x32},
  2007. {104, 0x32},
  2008. {98, 0x32},
  2009. {110, 0x31},
  2010. {104, 0x31},
  2011. {98, 0x31},
  2012. {110, 0x30},
  2013. {104, 0x30},
  2014. {98, 0x30},
  2015. {110, 0x25},
  2016. {104, 0x25},
  2017. {98, 0x25},
  2018. {110, 0x24},
  2019. {104, 0x24},
  2020. {98, 0x24},
  2021. {110, 0x23},
  2022. {104, 0x23},
  2023. {98, 0x23},
  2024. {110, 0x22},
  2025. {104, 0x18},
  2026. {98, 0x18},
  2027. {110, 0x17},
  2028. {104, 0x17},
  2029. {98, 0x17},
  2030. {110, 0x16},
  2031. {104, 0x16},
  2032. {98, 0x16},
  2033. {110, 0x15},
  2034. {104, 0x15},
  2035. {98, 0x15},
  2036. {110, 0x14},
  2037. {104, 0x14},
  2038. {98, 0x14},
  2039. {110, 0x13},
  2040. {104, 0x13},
  2041. {98, 0x13},
  2042. {110, 0x12},
  2043. {104, 0x08},
  2044. {98, 0x08},
  2045. {110, 0x07},
  2046. {104, 0x07},
  2047. {98, 0x07},
  2048. {110, 0x06},
  2049. {104, 0x06},
  2050. {98, 0x06},
  2051. {110, 0x05},
  2052. {104, 0x05},
  2053. {98, 0x05},
  2054. {110, 0x04},
  2055. {104, 0x04},
  2056. {98, 0x04},
  2057. {110, 0x03},
  2058. {104, 0x03},
  2059. {98, 0x03},
  2060. {110, 0x02},
  2061. {104, 0x02},
  2062. {98, 0x02},
  2063. {110, 0x01},
  2064. {104, 0x01},
  2065. {98, 0x01},
  2066. {110, 0x00},
  2067. {104, 0x00},
  2068. {98, 0x00},
  2069. {93, 0x00},
  2070. {88, 0x00},
  2071. {83, 0x00},
  2072. {78, 0x00},
  2073. },
  2074. /* 2.4GHz power gain index table */
  2075. {
  2076. {110, 0x3f}, /* highest txpower */
  2077. {104, 0x3f},
  2078. {98, 0x3f},
  2079. {110, 0x3e},
  2080. {104, 0x3e},
  2081. {98, 0x3e},
  2082. {110, 0x3d},
  2083. {104, 0x3d},
  2084. {98, 0x3d},
  2085. {110, 0x3c},
  2086. {104, 0x3c},
  2087. {98, 0x3c},
  2088. {110, 0x3b},
  2089. {104, 0x3b},
  2090. {98, 0x3b},
  2091. {110, 0x3a},
  2092. {104, 0x3a},
  2093. {98, 0x3a},
  2094. {110, 0x39},
  2095. {104, 0x39},
  2096. {98, 0x39},
  2097. {110, 0x38},
  2098. {104, 0x38},
  2099. {98, 0x38},
  2100. {110, 0x37},
  2101. {104, 0x37},
  2102. {98, 0x37},
  2103. {110, 0x36},
  2104. {104, 0x36},
  2105. {98, 0x36},
  2106. {110, 0x35},
  2107. {104, 0x35},
  2108. {98, 0x35},
  2109. {110, 0x34},
  2110. {104, 0x34},
  2111. {98, 0x34},
  2112. {110, 0x33},
  2113. {104, 0x33},
  2114. {98, 0x33},
  2115. {110, 0x32},
  2116. {104, 0x32},
  2117. {98, 0x32},
  2118. {110, 0x31},
  2119. {104, 0x31},
  2120. {98, 0x31},
  2121. {110, 0x30},
  2122. {104, 0x30},
  2123. {98, 0x30},
  2124. {110, 0x6},
  2125. {104, 0x6},
  2126. {98, 0x6},
  2127. {110, 0x5},
  2128. {104, 0x5},
  2129. {98, 0x5},
  2130. {110, 0x4},
  2131. {104, 0x4},
  2132. {98, 0x4},
  2133. {110, 0x3},
  2134. {104, 0x3},
  2135. {98, 0x3},
  2136. {110, 0x2},
  2137. {104, 0x2},
  2138. {98, 0x2},
  2139. {110, 0x1},
  2140. {104, 0x1},
  2141. {98, 0x1},
  2142. {110, 0x0},
  2143. {104, 0x0},
  2144. {98, 0x0},
  2145. {97, 0},
  2146. {96, 0},
  2147. {95, 0},
  2148. {94, 0},
  2149. {93, 0},
  2150. {92, 0},
  2151. {91, 0},
  2152. {90, 0},
  2153. {89, 0},
  2154. {88, 0},
  2155. {87, 0},
  2156. {86, 0},
  2157. {85, 0},
  2158. {84, 0},
  2159. {83, 0},
  2160. {82, 0},
  2161. {81, 0},
  2162. {80, 0},
  2163. {79, 0},
  2164. {78, 0},
  2165. {77, 0},
  2166. {76, 0},
  2167. {75, 0},
  2168. {74, 0},
  2169. {73, 0},
  2170. {72, 0},
  2171. {71, 0},
  2172. {70, 0},
  2173. {69, 0},
  2174. {68, 0},
  2175. {67, 0},
  2176. {66, 0},
  2177. {65, 0},
  2178. {64, 0},
  2179. {63, 0},
  2180. {62, 0},
  2181. {61, 0},
  2182. {60, 0},
  2183. {59, 0},
  2184. }
  2185. };
  2186. static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
  2187. u8 is_fat, u8 ctrl_chan_high,
  2188. struct iwl4965_tx_power_db *tx_power_tbl)
  2189. {
  2190. u8 saturation_power;
  2191. s32 target_power;
  2192. s32 user_target_power;
  2193. s32 power_limit;
  2194. s32 current_temp;
  2195. s32 reg_limit;
  2196. s32 current_regulatory;
  2197. s32 txatten_grp = CALIB_CH_GROUP_MAX;
  2198. int i;
  2199. int c;
  2200. const struct iwl_channel_info *ch_info = NULL;
  2201. struct iwl4965_eeprom_calib_ch_info ch_eeprom_info;
  2202. const struct iwl4965_eeprom_calib_measure *measurement;
  2203. s16 voltage;
  2204. s32 init_voltage;
  2205. s32 voltage_compensation;
  2206. s32 degrees_per_05db_num;
  2207. s32 degrees_per_05db_denom;
  2208. s32 factory_temp;
  2209. s32 temperature_comp[2];
  2210. s32 factory_gain_index[2];
  2211. s32 factory_actual_pwr[2];
  2212. s32 power_index;
  2213. /* Sanity check requested level (dBm) */
  2214. if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
  2215. IWL_WARNING("Requested user TXPOWER %d below limit.\n",
  2216. priv->user_txpower_limit);
  2217. return -EINVAL;
  2218. }
  2219. if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
  2220. IWL_WARNING("Requested user TXPOWER %d above limit.\n",
  2221. priv->user_txpower_limit);
  2222. return -EINVAL;
  2223. }
  2224. /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
  2225. * are used for indexing into txpower table) */
  2226. user_target_power = 2 * priv->user_txpower_limit;
  2227. /* Get current (RXON) channel, band, width */
  2228. ch_info =
  2229. iwl4965_get_channel_txpower_info(priv, priv->band, channel);
  2230. IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
  2231. is_fat);
  2232. if (!ch_info)
  2233. return -EINVAL;
  2234. /* get txatten group, used to select 1) thermal txpower adjustment
  2235. * and 2) mimo txpower balance between Tx chains. */
  2236. txatten_grp = iwl4965_get_tx_atten_grp(channel);
  2237. if (txatten_grp < 0)
  2238. return -EINVAL;
  2239. IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
  2240. channel, txatten_grp);
  2241. if (is_fat) {
  2242. if (ctrl_chan_high)
  2243. channel -= 2;
  2244. else
  2245. channel += 2;
  2246. }
  2247. /* hardware txpower limits ...
  2248. * saturation (clipping distortion) txpowers are in half-dBm */
  2249. if (band)
  2250. saturation_power = priv->eeprom.calib_info.saturation_power24;
  2251. else
  2252. saturation_power = priv->eeprom.calib_info.saturation_power52;
  2253. if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
  2254. saturation_power > IWL_TX_POWER_SATURATION_MAX) {
  2255. if (band)
  2256. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
  2257. else
  2258. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
  2259. }
  2260. /* regulatory txpower limits ... reg_limit values are in half-dBm,
  2261. * max_power_avg values are in dBm, convert * 2 */
  2262. if (is_fat)
  2263. reg_limit = ch_info->fat_max_power_avg * 2;
  2264. else
  2265. reg_limit = ch_info->max_power_avg * 2;
  2266. if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
  2267. (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
  2268. if (band)
  2269. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
  2270. else
  2271. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
  2272. }
  2273. /* Interpolate txpower calibration values for this channel,
  2274. * based on factory calibration tests on spaced channels. */
  2275. iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
  2276. /* calculate tx gain adjustment based on power supply voltage */
  2277. voltage = priv->eeprom.calib_info.voltage;
  2278. init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
  2279. voltage_compensation =
  2280. iwl4965_get_voltage_compensation(voltage, init_voltage);
  2281. IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
  2282. init_voltage,
  2283. voltage, voltage_compensation);
  2284. /* get current temperature (Celsius) */
  2285. current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
  2286. current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
  2287. current_temp = KELVIN_TO_CELSIUS(current_temp);
  2288. /* select thermal txpower adjustment params, based on channel group
  2289. * (same frequency group used for mimo txatten adjustment) */
  2290. degrees_per_05db_num =
  2291. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
  2292. degrees_per_05db_denom =
  2293. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
  2294. /* get per-chain txpower values from factory measurements */
  2295. for (c = 0; c < 2; c++) {
  2296. measurement = &ch_eeprom_info.measurements[c][1];
  2297. /* txgain adjustment (in half-dB steps) based on difference
  2298. * between factory and current temperature */
  2299. factory_temp = measurement->temperature;
  2300. iwl4965_math_div_round((current_temp - factory_temp) *
  2301. degrees_per_05db_denom,
  2302. degrees_per_05db_num,
  2303. &temperature_comp[c]);
  2304. factory_gain_index[c] = measurement->gain_idx;
  2305. factory_actual_pwr[c] = measurement->actual_pow;
  2306. IWL_DEBUG_TXPOWER("chain = %d\n", c);
  2307. IWL_DEBUG_TXPOWER("fctry tmp %d, "
  2308. "curr tmp %d, comp %d steps\n",
  2309. factory_temp, current_temp,
  2310. temperature_comp[c]);
  2311. IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
  2312. factory_gain_index[c],
  2313. factory_actual_pwr[c]);
  2314. }
  2315. /* for each of 33 bit-rates (including 1 for CCK) */
  2316. for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
  2317. u8 is_mimo_rate;
  2318. union iwl4965_tx_power_dual_stream tx_power;
  2319. /* for mimo, reduce each chain's txpower by half
  2320. * (3dB, 6 steps), so total output power is regulatory
  2321. * compliant. */
  2322. if (i & 0x8) {
  2323. current_regulatory = reg_limit -
  2324. IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
  2325. is_mimo_rate = 1;
  2326. } else {
  2327. current_regulatory = reg_limit;
  2328. is_mimo_rate = 0;
  2329. }
  2330. /* find txpower limit, either hardware or regulatory */
  2331. power_limit = saturation_power - back_off_table[i];
  2332. if (power_limit > current_regulatory)
  2333. power_limit = current_regulatory;
  2334. /* reduce user's txpower request if necessary
  2335. * for this rate on this channel */
  2336. target_power = user_target_power;
  2337. if (target_power > power_limit)
  2338. target_power = power_limit;
  2339. IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
  2340. i, saturation_power - back_off_table[i],
  2341. current_regulatory, user_target_power,
  2342. target_power);
  2343. /* for each of 2 Tx chains (radio transmitters) */
  2344. for (c = 0; c < 2; c++) {
  2345. s32 atten_value;
  2346. if (is_mimo_rate)
  2347. atten_value =
  2348. (s32)le32_to_cpu(priv->card_alive_init.
  2349. tx_atten[txatten_grp][c]);
  2350. else
  2351. atten_value = 0;
  2352. /* calculate index; higher index means lower txpower */
  2353. power_index = (u8) (factory_gain_index[c] -
  2354. (target_power -
  2355. factory_actual_pwr[c]) -
  2356. temperature_comp[c] -
  2357. voltage_compensation +
  2358. atten_value);
  2359. /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
  2360. power_index); */
  2361. if (power_index < get_min_power_index(i, band))
  2362. power_index = get_min_power_index(i, band);
  2363. /* adjust 5 GHz index to support negative indexes */
  2364. if (!band)
  2365. power_index += 9;
  2366. /* CCK, rate 32, reduce txpower for CCK */
  2367. if (i == POWER_TABLE_CCK_ENTRY)
  2368. power_index +=
  2369. IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
  2370. /* stay within the table! */
  2371. if (power_index > 107) {
  2372. IWL_WARNING("txpower index %d > 107\n",
  2373. power_index);
  2374. power_index = 107;
  2375. }
  2376. if (power_index < 0) {
  2377. IWL_WARNING("txpower index %d < 0\n",
  2378. power_index);
  2379. power_index = 0;
  2380. }
  2381. /* fill txpower command for this rate/chain */
  2382. tx_power.s.radio_tx_gain[c] =
  2383. gain_table[band][power_index].radio;
  2384. tx_power.s.dsp_predis_atten[c] =
  2385. gain_table[band][power_index].dsp;
  2386. IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
  2387. "gain 0x%02x dsp %d\n",
  2388. c, atten_value, power_index,
  2389. tx_power.s.radio_tx_gain[c],
  2390. tx_power.s.dsp_predis_atten[c]);
  2391. }/* for each chain */
  2392. tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
  2393. }/* for each rate */
  2394. return 0;
  2395. }
  2396. /**
  2397. * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
  2398. *
  2399. * Uses the active RXON for channel, band, and characteristics (fat, high)
  2400. * The power limit is taken from priv->user_txpower_limit.
  2401. */
  2402. int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
  2403. {
  2404. struct iwl4965_txpowertable_cmd cmd = { 0 };
  2405. int ret;
  2406. u8 band = 0;
  2407. u8 is_fat = 0;
  2408. u8 ctrl_chan_high = 0;
  2409. if (test_bit(STATUS_SCANNING, &priv->status)) {
  2410. /* If this gets hit a lot, switch it to a BUG() and catch
  2411. * the stack trace to find out who is calling this during
  2412. * a scan. */
  2413. IWL_WARNING("TX Power requested while scanning!\n");
  2414. return -EAGAIN;
  2415. }
  2416. band = priv->band == IEEE80211_BAND_2GHZ;
  2417. is_fat = is_fat_channel(priv->active_rxon.flags);
  2418. if (is_fat &&
  2419. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  2420. ctrl_chan_high = 1;
  2421. cmd.band = band;
  2422. cmd.channel = priv->active_rxon.channel;
  2423. ret = iwl4965_fill_txpower_tbl(priv, band,
  2424. le16_to_cpu(priv->active_rxon.channel),
  2425. is_fat, ctrl_chan_high, &cmd.tx_power);
  2426. if (ret)
  2427. goto out;
  2428. ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
  2429. out:
  2430. return ret;
  2431. }
  2432. int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
  2433. {
  2434. int rc;
  2435. u8 band = 0;
  2436. u8 is_fat = 0;
  2437. u8 ctrl_chan_high = 0;
  2438. struct iwl4965_channel_switch_cmd cmd = { 0 };
  2439. const struct iwl_channel_info *ch_info;
  2440. band = priv->band == IEEE80211_BAND_2GHZ;
  2441. ch_info = iwl_get_channel_info(priv, priv->band, channel);
  2442. is_fat = is_fat_channel(priv->staging_rxon.flags);
  2443. if (is_fat &&
  2444. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  2445. ctrl_chan_high = 1;
  2446. cmd.band = band;
  2447. cmd.expect_beacon = 0;
  2448. cmd.channel = cpu_to_le16(channel);
  2449. cmd.rxon_flags = priv->active_rxon.flags;
  2450. cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
  2451. cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
  2452. if (ch_info)
  2453. cmd.expect_beacon = is_channel_radar(ch_info);
  2454. else
  2455. cmd.expect_beacon = 1;
  2456. rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
  2457. ctrl_chan_high, &cmd.tx_power);
  2458. if (rc) {
  2459. IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
  2460. return rc;
  2461. }
  2462. rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
  2463. return rc;
  2464. }
  2465. #define RTS_HCCA_RETRY_LIMIT 3
  2466. #define RTS_DFAULT_RETRY_LIMIT 60
  2467. void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
  2468. struct iwl_cmd *cmd,
  2469. struct ieee80211_tx_control *ctrl,
  2470. struct ieee80211_hdr *hdr, int sta_id,
  2471. int is_hcca)
  2472. {
  2473. struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
  2474. u8 rts_retry_limit = 0;
  2475. u8 data_retry_limit = 0;
  2476. u16 fc = le16_to_cpu(hdr->frame_control);
  2477. u8 rate_plcp;
  2478. u16 rate_flags = 0;
  2479. int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
  2480. rate_plcp = iwl4965_rates[rate_idx].plcp;
  2481. rts_retry_limit = (is_hcca) ?
  2482. RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
  2483. if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
  2484. rate_flags |= RATE_MCS_CCK_MSK;
  2485. if (ieee80211_is_probe_response(fc)) {
  2486. data_retry_limit = 3;
  2487. if (data_retry_limit < rts_retry_limit)
  2488. rts_retry_limit = data_retry_limit;
  2489. } else
  2490. data_retry_limit = IWL_DEFAULT_TX_RETRY;
  2491. if (priv->data_retry_limit != -1)
  2492. data_retry_limit = priv->data_retry_limit;
  2493. if (ieee80211_is_data(fc)) {
  2494. tx->initial_rate_index = 0;
  2495. tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
  2496. } else {
  2497. switch (fc & IEEE80211_FCTL_STYPE) {
  2498. case IEEE80211_STYPE_AUTH:
  2499. case IEEE80211_STYPE_DEAUTH:
  2500. case IEEE80211_STYPE_ASSOC_REQ:
  2501. case IEEE80211_STYPE_REASSOC_REQ:
  2502. if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
  2503. tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2504. tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
  2505. }
  2506. break;
  2507. default:
  2508. break;
  2509. }
  2510. /* Alternate between antenna A and B for successive frames */
  2511. if (priv->use_ant_b_for_management_frame) {
  2512. priv->use_ant_b_for_management_frame = 0;
  2513. rate_flags |= RATE_MCS_ANT_B_MSK;
  2514. } else {
  2515. priv->use_ant_b_for_management_frame = 1;
  2516. rate_flags |= RATE_MCS_ANT_A_MSK;
  2517. }
  2518. }
  2519. tx->rts_retry_limit = rts_retry_limit;
  2520. tx->data_retry_limit = data_retry_limit;
  2521. tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
  2522. }
  2523. int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
  2524. {
  2525. struct iwl4965_shared *s = priv->shared_virt;
  2526. return le32_to_cpu(s->rb_closed) & 0xFFF;
  2527. }
  2528. int iwl4965_hw_get_temperature(struct iwl_priv *priv)
  2529. {
  2530. return priv->temperature;
  2531. }
  2532. unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
  2533. struct iwl4965_frame *frame, u8 rate)
  2534. {
  2535. struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
  2536. unsigned int frame_size;
  2537. tx_beacon_cmd = &frame->u.beacon;
  2538. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  2539. tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
  2540. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2541. frame_size = iwl4965_fill_beacon_frame(priv,
  2542. tx_beacon_cmd->frame,
  2543. iwl4965_broadcast_addr,
  2544. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  2545. BUG_ON(frame_size > MAX_MPDU_SIZE);
  2546. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  2547. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  2548. tx_beacon_cmd->tx.rate_n_flags =
  2549. iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  2550. else
  2551. tx_beacon_cmd->tx.rate_n_flags =
  2552. iwl4965_hw_set_rate_n_flags(rate, 0);
  2553. tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
  2554. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
  2555. return (sizeof(*tx_beacon_cmd) + frame_size);
  2556. }
  2557. /*
  2558. * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
  2559. * given Tx queue, and enable the DMA channel used for that queue.
  2560. *
  2561. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  2562. * channels supported in hardware.
  2563. */
  2564. int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
  2565. {
  2566. int rc;
  2567. unsigned long flags;
  2568. int txq_id = txq->q.id;
  2569. spin_lock_irqsave(&priv->lock, flags);
  2570. rc = iwl_grab_nic_access(priv);
  2571. if (rc) {
  2572. spin_unlock_irqrestore(&priv->lock, flags);
  2573. return rc;
  2574. }
  2575. /* Circular buffer (TFD queue in DRAM) physical base address */
  2576. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  2577. txq->q.dma_addr >> 8);
  2578. /* Enable DMA channel, using same id as for TFD queue */
  2579. iwl_write_direct32(
  2580. priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
  2581. IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  2582. IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
  2583. iwl_release_nic_access(priv);
  2584. spin_unlock_irqrestore(&priv->lock, flags);
  2585. return 0;
  2586. }
  2587. int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
  2588. dma_addr_t addr, u16 len)
  2589. {
  2590. int index, is_odd;
  2591. struct iwl4965_tfd_frame *tfd = ptr;
  2592. u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
  2593. /* Each TFD can point to a maximum 20 Tx buffers */
  2594. if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
  2595. IWL_ERROR("Error can not send more than %d chunks\n",
  2596. MAX_NUM_OF_TBS);
  2597. return -EINVAL;
  2598. }
  2599. index = num_tbs / 2;
  2600. is_odd = num_tbs & 0x1;
  2601. if (!is_odd) {
  2602. tfd->pa[index].tb1_addr = cpu_to_le32(addr);
  2603. IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
  2604. iwl_get_dma_hi_address(addr));
  2605. IWL_SET_BITS(tfd->pa[index], tb1_len, len);
  2606. } else {
  2607. IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
  2608. (u32) (addr & 0xffff));
  2609. IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
  2610. IWL_SET_BITS(tfd->pa[index], tb2_len, len);
  2611. }
  2612. IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
  2613. return 0;
  2614. }
  2615. static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
  2616. {
  2617. u16 hw_version = priv->eeprom.board_revision_4965;
  2618. IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
  2619. ((hw_version >> 8) & 0x0F),
  2620. ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
  2621. IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
  2622. priv->eeprom.board_pba_number_4965);
  2623. }
  2624. #define IWL_TX_CRC_SIZE 4
  2625. #define IWL_TX_DELIMITER_SIZE 4
  2626. /**
  2627. * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
  2628. */
  2629. static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
  2630. struct iwl4965_tx_queue *txq,
  2631. u16 byte_cnt)
  2632. {
  2633. int len;
  2634. int txq_id = txq->q.id;
  2635. struct iwl4965_shared *shared_data = priv->shared_virt;
  2636. len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  2637. /* Set up byte count within first 256 entries */
  2638. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  2639. tfd_offset[txq->q.write_ptr], byte_cnt, len);
  2640. /* If within first 64 entries, duplicate at end */
  2641. if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
  2642. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  2643. tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
  2644. byte_cnt, len);
  2645. }
  2646. /**
  2647. * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  2648. *
  2649. * Selects how many and which Rx receivers/antennas/chains to use.
  2650. * This should not be used for scan command ... it puts data in wrong place.
  2651. */
  2652. void iwl4965_set_rxon_chain(struct iwl_priv *priv)
  2653. {
  2654. u8 is_single = is_single_stream(priv);
  2655. u8 idle_state, rx_state;
  2656. priv->staging_rxon.rx_chain = 0;
  2657. rx_state = idle_state = 3;
  2658. /* Tell uCode which antennas are actually connected.
  2659. * Before first association, we assume all antennas are connected.
  2660. * Just after first association, iwl4965_noise_calibration()
  2661. * checks which antennas actually *are* connected. */
  2662. priv->staging_rxon.rx_chain |=
  2663. cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
  2664. /* How many receivers should we use? */
  2665. iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
  2666. priv->staging_rxon.rx_chain |=
  2667. cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
  2668. priv->staging_rxon.rx_chain |=
  2669. cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
  2670. if (!is_single && (rx_state >= 2) &&
  2671. !test_bit(STATUS_POWER_PMI, &priv->status))
  2672. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  2673. else
  2674. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  2675. IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
  2676. }
  2677. /**
  2678. * sign_extend - Sign extend a value using specified bit as sign-bit
  2679. *
  2680. * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
  2681. * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
  2682. *
  2683. * @param oper value to sign extend
  2684. * @param index 0 based bit index (0<=index<32) to sign bit
  2685. */
  2686. static s32 sign_extend(u32 oper, int index)
  2687. {
  2688. u8 shift = 31 - index;
  2689. return (s32)(oper << shift) >> shift;
  2690. }
  2691. /**
  2692. * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
  2693. * @statistics: Provides the temperature reading from the uCode
  2694. *
  2695. * A return of <0 indicates bogus data in the statistics
  2696. */
  2697. int iwl4965_get_temperature(const struct iwl_priv *priv)
  2698. {
  2699. s32 temperature;
  2700. s32 vt;
  2701. s32 R1, R2, R3;
  2702. u32 R4;
  2703. if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
  2704. (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
  2705. IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
  2706. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  2707. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  2708. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  2709. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
  2710. } else {
  2711. IWL_DEBUG_TEMP("Running temperature calibration\n");
  2712. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  2713. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  2714. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  2715. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
  2716. }
  2717. /*
  2718. * Temperature is only 23 bits, so sign extend out to 32.
  2719. *
  2720. * NOTE If we haven't received a statistics notification yet
  2721. * with an updated temperature, use R4 provided to us in the
  2722. * "initialize" ALIVE response.
  2723. */
  2724. if (!test_bit(STATUS_TEMPERATURE, &priv->status))
  2725. vt = sign_extend(R4, 23);
  2726. else
  2727. vt = sign_extend(
  2728. le32_to_cpu(priv->statistics.general.temperature), 23);
  2729. IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
  2730. R1, R2, R3, vt);
  2731. if (R3 == R1) {
  2732. IWL_ERROR("Calibration conflict R1 == R3\n");
  2733. return -1;
  2734. }
  2735. /* Calculate temperature in degrees Kelvin, adjust by 97%.
  2736. * Add offset to center the adjustment around 0 degrees Centigrade. */
  2737. temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
  2738. temperature /= (R3 - R1);
  2739. temperature = (temperature * 97) / 100 +
  2740. TEMPERATURE_CALIB_KELVIN_OFFSET;
  2741. IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
  2742. KELVIN_TO_CELSIUS(temperature));
  2743. return temperature;
  2744. }
  2745. /* Adjust Txpower only if temperature variance is greater than threshold. */
  2746. #define IWL_TEMPERATURE_THRESHOLD 3
  2747. /**
  2748. * iwl4965_is_temp_calib_needed - determines if new calibration is needed
  2749. *
  2750. * If the temperature changed has changed sufficiently, then a recalibration
  2751. * is needed.
  2752. *
  2753. * Assumes caller will replace priv->last_temperature once calibration
  2754. * executed.
  2755. */
  2756. static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
  2757. {
  2758. int temp_diff;
  2759. if (!test_bit(STATUS_STATISTICS, &priv->status)) {
  2760. IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
  2761. return 0;
  2762. }
  2763. temp_diff = priv->temperature - priv->last_temperature;
  2764. /* get absolute value */
  2765. if (temp_diff < 0) {
  2766. IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
  2767. temp_diff = -temp_diff;
  2768. } else if (temp_diff == 0)
  2769. IWL_DEBUG_POWER("Same temp, \n");
  2770. else
  2771. IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
  2772. if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
  2773. IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
  2774. return 0;
  2775. }
  2776. IWL_DEBUG_POWER("Thermal txpower calib needed\n");
  2777. return 1;
  2778. }
  2779. /* Calculate noise level, based on measurements during network silence just
  2780. * before arriving beacon. This measurement can be done only if we know
  2781. * exactly when to expect beacons, therefore only when we're associated. */
  2782. static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
  2783. {
  2784. struct statistics_rx_non_phy *rx_info
  2785. = &(priv->statistics.rx.general);
  2786. int num_active_rx = 0;
  2787. int total_silence = 0;
  2788. int bcn_silence_a =
  2789. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  2790. int bcn_silence_b =
  2791. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  2792. int bcn_silence_c =
  2793. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  2794. if (bcn_silence_a) {
  2795. total_silence += bcn_silence_a;
  2796. num_active_rx++;
  2797. }
  2798. if (bcn_silence_b) {
  2799. total_silence += bcn_silence_b;
  2800. num_active_rx++;
  2801. }
  2802. if (bcn_silence_c) {
  2803. total_silence += bcn_silence_c;
  2804. num_active_rx++;
  2805. }
  2806. /* Average among active antennas */
  2807. if (num_active_rx)
  2808. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  2809. else
  2810. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2811. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  2812. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  2813. priv->last_rx_noise);
  2814. }
  2815. void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
  2816. {
  2817. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  2818. int change;
  2819. s32 temp;
  2820. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  2821. (int)sizeof(priv->statistics), pkt->len);
  2822. change = ((priv->statistics.general.temperature !=
  2823. pkt->u.stats.general.temperature) ||
  2824. ((priv->statistics.flag &
  2825. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  2826. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  2827. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  2828. set_bit(STATUS_STATISTICS, &priv->status);
  2829. /* Reschedule the statistics timer to occur in
  2830. * REG_RECALIB_PERIOD seconds to ensure we get a
  2831. * thermal update even if the uCode doesn't give
  2832. * us one */
  2833. mod_timer(&priv->statistics_periodic, jiffies +
  2834. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  2835. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  2836. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  2837. iwl4965_rx_calc_noise(priv);
  2838. #ifdef CONFIG_IWL4965_SENSITIVITY
  2839. queue_work(priv->workqueue, &priv->sensitivity_work);
  2840. #endif
  2841. }
  2842. iwl_leds_background(priv);
  2843. /* If the hardware hasn't reported a change in
  2844. * temperature then don't bother computing a
  2845. * calibrated temperature value */
  2846. if (!change)
  2847. return;
  2848. temp = iwl4965_get_temperature(priv);
  2849. if (temp < 0)
  2850. return;
  2851. if (priv->temperature != temp) {
  2852. if (priv->temperature)
  2853. IWL_DEBUG_TEMP("Temperature changed "
  2854. "from %dC to %dC\n",
  2855. KELVIN_TO_CELSIUS(priv->temperature),
  2856. KELVIN_TO_CELSIUS(temp));
  2857. else
  2858. IWL_DEBUG_TEMP("Temperature "
  2859. "initialized to %dC\n",
  2860. KELVIN_TO_CELSIUS(temp));
  2861. }
  2862. priv->temperature = temp;
  2863. set_bit(STATUS_TEMPERATURE, &priv->status);
  2864. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  2865. iwl4965_is_temp_calib_needed(priv))
  2866. queue_work(priv->workqueue, &priv->txpower_work);
  2867. }
  2868. static void iwl4965_add_radiotap(struct iwl_priv *priv,
  2869. struct sk_buff *skb,
  2870. struct iwl4965_rx_phy_res *rx_start,
  2871. struct ieee80211_rx_status *stats,
  2872. u32 ampdu_status)
  2873. {
  2874. s8 signal = stats->ssi;
  2875. s8 noise = 0;
  2876. int rate = stats->rate_idx;
  2877. u64 tsf = stats->mactime;
  2878. __le16 antenna;
  2879. __le16 phy_flags_hw = rx_start->phy_flags;
  2880. struct iwl4965_rt_rx_hdr {
  2881. struct ieee80211_radiotap_header rt_hdr;
  2882. __le64 rt_tsf; /* TSF */
  2883. u8 rt_flags; /* radiotap packet flags */
  2884. u8 rt_rate; /* rate in 500kb/s */
  2885. __le16 rt_channelMHz; /* channel in MHz */
  2886. __le16 rt_chbitmask; /* channel bitfield */
  2887. s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
  2888. s8 rt_dbmnoise;
  2889. u8 rt_antenna; /* antenna number */
  2890. } __attribute__ ((packed)) *iwl4965_rt;
  2891. /* TODO: We won't have enough headroom for HT frames. Fix it later. */
  2892. if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
  2893. if (net_ratelimit())
  2894. printk(KERN_ERR "not enough headroom [%d] for "
  2895. "radiotap head [%zd]\n",
  2896. skb_headroom(skb), sizeof(*iwl4965_rt));
  2897. return;
  2898. }
  2899. /* put radiotap header in front of 802.11 header and data */
  2900. iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
  2901. /* initialise radiotap header */
  2902. iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
  2903. iwl4965_rt->rt_hdr.it_pad = 0;
  2904. /* total header + data */
  2905. put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
  2906. &iwl4965_rt->rt_hdr.it_len);
  2907. /* Indicate all the fields we add to the radiotap header */
  2908. put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
  2909. (1 << IEEE80211_RADIOTAP_FLAGS) |
  2910. (1 << IEEE80211_RADIOTAP_RATE) |
  2911. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  2912. (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
  2913. (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
  2914. (1 << IEEE80211_RADIOTAP_ANTENNA)),
  2915. &iwl4965_rt->rt_hdr.it_present);
  2916. /* Zero the flags, we'll add to them as we go */
  2917. iwl4965_rt->rt_flags = 0;
  2918. put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
  2919. iwl4965_rt->rt_dbmsignal = signal;
  2920. iwl4965_rt->rt_dbmnoise = noise;
  2921. /* Convert the channel frequency and set the flags */
  2922. put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
  2923. if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
  2924. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  2925. IEEE80211_CHAN_5GHZ),
  2926. &iwl4965_rt->rt_chbitmask);
  2927. else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
  2928. put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
  2929. IEEE80211_CHAN_2GHZ),
  2930. &iwl4965_rt->rt_chbitmask);
  2931. else /* 802.11g */
  2932. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  2933. IEEE80211_CHAN_2GHZ),
  2934. &iwl4965_rt->rt_chbitmask);
  2935. if (rate == -1)
  2936. iwl4965_rt->rt_rate = 0;
  2937. else
  2938. iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
  2939. /*
  2940. * "antenna number"
  2941. *
  2942. * It seems that the antenna field in the phy flags value
  2943. * is actually a bitfield. This is undefined by radiotap,
  2944. * it wants an actual antenna number but I always get "7"
  2945. * for most legacy frames I receive indicating that the
  2946. * same frame was received on all three RX chains.
  2947. *
  2948. * I think this field should be removed in favour of a
  2949. * new 802.11n radiotap field "RX chains" that is defined
  2950. * as a bitmask.
  2951. */
  2952. antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
  2953. iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
  2954. /* set the preamble flag if appropriate */
  2955. if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  2956. iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
  2957. stats->flag |= RX_FLAG_RADIOTAP;
  2958. }
  2959. static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
  2960. {
  2961. /* 0 - mgmt, 1 - cnt, 2 - data */
  2962. int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
  2963. priv->rx_stats[idx].cnt++;
  2964. priv->rx_stats[idx].bytes += len;
  2965. }
  2966. static u32 iwl4965_translate_rx_status(u32 decrypt_in)
  2967. {
  2968. u32 decrypt_out = 0;
  2969. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  2970. RX_RES_STATUS_STATION_FOUND)
  2971. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  2972. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  2973. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  2974. /* packet was not encrypted */
  2975. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  2976. RX_RES_STATUS_SEC_TYPE_NONE)
  2977. return decrypt_out;
  2978. /* packet was encrypted with unknown alg */
  2979. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  2980. RX_RES_STATUS_SEC_TYPE_ERR)
  2981. return decrypt_out;
  2982. /* decryption was not done in HW */
  2983. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  2984. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  2985. return decrypt_out;
  2986. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  2987. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2988. /* alg is CCM: check MIC only */
  2989. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  2990. /* Bad MIC */
  2991. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  2992. else
  2993. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  2994. break;
  2995. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2996. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  2997. /* Bad TTAK */
  2998. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  2999. break;
  3000. }
  3001. /* fall through if TTAK OK */
  3002. default:
  3003. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  3004. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  3005. else
  3006. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  3007. break;
  3008. };
  3009. IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
  3010. decrypt_in, decrypt_out);
  3011. return decrypt_out;
  3012. }
  3013. static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
  3014. int include_phy,
  3015. struct iwl4965_rx_mem_buffer *rxb,
  3016. struct ieee80211_rx_status *stats)
  3017. {
  3018. struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
  3019. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  3020. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  3021. struct ieee80211_hdr *hdr;
  3022. u16 len;
  3023. __le32 *rx_end;
  3024. unsigned int skblen;
  3025. u32 ampdu_status;
  3026. u32 ampdu_status_legacy;
  3027. if (!include_phy && priv->last_phy_res[0])
  3028. rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  3029. if (!rx_start) {
  3030. IWL_ERROR("MPDU frame without a PHY data\n");
  3031. return;
  3032. }
  3033. if (include_phy) {
  3034. hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
  3035. rx_start->cfg_phy_cnt);
  3036. len = le16_to_cpu(rx_start->byte_count);
  3037. rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
  3038. sizeof(struct iwl4965_rx_phy_res) +
  3039. rx_start->cfg_phy_cnt + len);
  3040. } else {
  3041. struct iwl4965_rx_mpdu_res_start *amsdu =
  3042. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  3043. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  3044. sizeof(struct iwl4965_rx_mpdu_res_start));
  3045. len = le16_to_cpu(amsdu->byte_count);
  3046. rx_start->byte_count = amsdu->byte_count;
  3047. rx_end = (__le32 *) (((u8 *) hdr) + len);
  3048. }
  3049. if (len > priv->hw_setting.max_pkt_size || len < 16) {
  3050. IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
  3051. return;
  3052. }
  3053. ampdu_status = le32_to_cpu(*rx_end);
  3054. skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
  3055. if (!include_phy) {
  3056. /* New status scheme, need to translate */
  3057. ampdu_status_legacy = ampdu_status;
  3058. ampdu_status = iwl4965_translate_rx_status(ampdu_status);
  3059. }
  3060. /* start from MAC */
  3061. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  3062. skb_put(rxb->skb, len); /* end where data ends */
  3063. /* We only process data packets if the interface is open */
  3064. if (unlikely(!priv->is_open)) {
  3065. IWL_DEBUG_DROP_LIMIT
  3066. ("Dropping packet while interface is not open.\n");
  3067. return;
  3068. }
  3069. stats->flag = 0;
  3070. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  3071. if (priv->cfg->mod_params->hw_crypto)
  3072. iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
  3073. if (priv->add_radiotap)
  3074. iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
  3075. iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
  3076. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  3077. priv->alloc_rxb_skb--;
  3078. rxb->skb = NULL;
  3079. }
  3080. /* Calc max signal level (dBm) among 3 possible receivers */
  3081. static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
  3082. {
  3083. /* data from PHY/DSP regarding signal strength, etc.,
  3084. * contents are always there, not configurable by host. */
  3085. struct iwl4965_rx_non_cfg_phy *ncphy =
  3086. (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
  3087. u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
  3088. >> IWL_AGC_DB_POS;
  3089. u32 valid_antennae =
  3090. (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
  3091. >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
  3092. u8 max_rssi = 0;
  3093. u32 i;
  3094. /* Find max rssi among 3 possible receivers.
  3095. * These values are measured by the digital signal processor (DSP).
  3096. * They should stay fairly constant even as the signal strength varies,
  3097. * if the radio's automatic gain control (AGC) is working right.
  3098. * AGC value (see below) will provide the "interesting" info. */
  3099. for (i = 0; i < 3; i++)
  3100. if (valid_antennae & (1 << i))
  3101. max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
  3102. IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
  3103. ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
  3104. max_rssi, agc);
  3105. /* dBm = max_rssi dB - agc dB - constant.
  3106. * Higher AGC (higher radio gain) means lower signal. */
  3107. return (max_rssi - agc - IWL_RSSI_OFFSET);
  3108. }
  3109. #ifdef CONFIG_IWL4965_HT
  3110. void iwl4965_init_ht_hw_capab(struct iwl_priv *priv,
  3111. struct ieee80211_ht_info *ht_info,
  3112. enum ieee80211_band band)
  3113. {
  3114. ht_info->cap = 0;
  3115. memset(ht_info->supp_mcs_set, 0, 16);
  3116. ht_info->ht_supported = 1;
  3117. if (band == IEEE80211_BAND_5GHZ) {
  3118. ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
  3119. ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
  3120. ht_info->supp_mcs_set[4] = 0x01;
  3121. }
  3122. ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
  3123. ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
  3124. ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
  3125. (IWL_MIMO_PS_NONE << 2));
  3126. if (priv->cfg->mod_params->amsdu_size_8K)
  3127. ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
  3128. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  3129. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  3130. ht_info->supp_mcs_set[0] = 0xFF;
  3131. ht_info->supp_mcs_set[1] = 0xFF;
  3132. }
  3133. #endif /* CONFIG_IWL4965_HT */
  3134. static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
  3135. {
  3136. unsigned long flags;
  3137. spin_lock_irqsave(&priv->sta_lock, flags);
  3138. priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
  3139. priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
  3140. priv->stations[sta_id].sta.sta.modify_mask = 0;
  3141. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3142. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3143. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3144. }
  3145. static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
  3146. {
  3147. /* FIXME: need locking over ps_status ??? */
  3148. u8 sta_id = iwl4965_hw_find_station(priv, addr);
  3149. if (sta_id != IWL_INVALID_STATION) {
  3150. u8 sta_awake = priv->stations[sta_id].
  3151. ps_status == STA_PS_STATUS_WAKE;
  3152. if (sta_awake && ps_bit)
  3153. priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
  3154. else if (!sta_awake && !ps_bit) {
  3155. iwl4965_sta_modify_ps_wake(priv, sta_id);
  3156. priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
  3157. }
  3158. }
  3159. }
  3160. #ifdef CONFIG_IWLWIFI_DEBUG
  3161. /**
  3162. * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
  3163. *
  3164. * You may hack this function to show different aspects of received frames,
  3165. * including selective frame dumps.
  3166. * group100 parameter selects whether to show 1 out of 100 good frames.
  3167. *
  3168. * TODO: This was originally written for 3945, need to audit for
  3169. * proper operation with 4965.
  3170. */
  3171. static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  3172. struct iwl4965_rx_packet *pkt,
  3173. struct ieee80211_hdr *header, int group100)
  3174. {
  3175. u32 to_us;
  3176. u32 print_summary = 0;
  3177. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  3178. u32 hundred = 0;
  3179. u32 dataframe = 0;
  3180. u16 fc;
  3181. u16 seq_ctl;
  3182. u16 channel;
  3183. u16 phy_flags;
  3184. int rate_sym;
  3185. u16 length;
  3186. u16 status;
  3187. u16 bcn_tmr;
  3188. u32 tsf_low;
  3189. u64 tsf;
  3190. u8 rssi;
  3191. u8 agc;
  3192. u16 sig_avg;
  3193. u16 noise_diff;
  3194. struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  3195. struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  3196. struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
  3197. u8 *data = IWL_RX_DATA(pkt);
  3198. if (likely(!(iwl_debug_level & IWL_DL_RX)))
  3199. return;
  3200. /* MAC header */
  3201. fc = le16_to_cpu(header->frame_control);
  3202. seq_ctl = le16_to_cpu(header->seq_ctrl);
  3203. /* metadata */
  3204. channel = le16_to_cpu(rx_hdr->channel);
  3205. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  3206. rate_sym = rx_hdr->rate;
  3207. length = le16_to_cpu(rx_hdr->len);
  3208. /* end-of-frame status and timestamp */
  3209. status = le32_to_cpu(rx_end->status);
  3210. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  3211. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  3212. tsf = le64_to_cpu(rx_end->timestamp);
  3213. /* signal statistics */
  3214. rssi = rx_stats->rssi;
  3215. agc = rx_stats->agc;
  3216. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  3217. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  3218. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  3219. /* if data frame is to us and all is good,
  3220. * (optionally) print summary for only 1 out of every 100 */
  3221. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  3222. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  3223. dataframe = 1;
  3224. if (!group100)
  3225. print_summary = 1; /* print each frame */
  3226. else if (priv->framecnt_to_us < 100) {
  3227. priv->framecnt_to_us++;
  3228. print_summary = 0;
  3229. } else {
  3230. priv->framecnt_to_us = 0;
  3231. print_summary = 1;
  3232. hundred = 1;
  3233. }
  3234. } else {
  3235. /* print summary for all other frames */
  3236. print_summary = 1;
  3237. }
  3238. if (print_summary) {
  3239. char *title;
  3240. int rate_idx;
  3241. u32 bitrate;
  3242. if (hundred)
  3243. title = "100Frames";
  3244. else if (fc & IEEE80211_FCTL_RETRY)
  3245. title = "Retry";
  3246. else if (ieee80211_is_assoc_response(fc))
  3247. title = "AscRsp";
  3248. else if (ieee80211_is_reassoc_response(fc))
  3249. title = "RasRsp";
  3250. else if (ieee80211_is_probe_response(fc)) {
  3251. title = "PrbRsp";
  3252. print_dump = 1; /* dump frame contents */
  3253. } else if (ieee80211_is_beacon(fc)) {
  3254. title = "Beacon";
  3255. print_dump = 1; /* dump frame contents */
  3256. } else if (ieee80211_is_atim(fc))
  3257. title = "ATIM";
  3258. else if (ieee80211_is_auth(fc))
  3259. title = "Auth";
  3260. else if (ieee80211_is_deauth(fc))
  3261. title = "DeAuth";
  3262. else if (ieee80211_is_disassoc(fc))
  3263. title = "DisAssoc";
  3264. else
  3265. title = "Frame";
  3266. rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
  3267. if (unlikely(rate_idx == -1))
  3268. bitrate = 0;
  3269. else
  3270. bitrate = iwl4965_rates[rate_idx].ieee / 2;
  3271. /* print frame summary.
  3272. * MAC addresses show just the last byte (for brevity),
  3273. * but you can hack it to show more, if you'd like to. */
  3274. if (dataframe)
  3275. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  3276. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  3277. title, fc, header->addr1[5],
  3278. length, rssi, channel, bitrate);
  3279. else {
  3280. /* src/dst addresses assume managed mode */
  3281. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  3282. "src=0x%02x, rssi=%u, tim=%lu usec, "
  3283. "phy=0x%02x, chnl=%d\n",
  3284. title, fc, header->addr1[5],
  3285. header->addr3[5], rssi,
  3286. tsf_low - priv->scan_start_tsf,
  3287. phy_flags, channel);
  3288. }
  3289. }
  3290. if (print_dump)
  3291. iwl_print_hex_dump(IWL_DL_RX, data, length);
  3292. }
  3293. #else
  3294. static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  3295. struct iwl4965_rx_packet *pkt,
  3296. struct ieee80211_hdr *header,
  3297. int group100)
  3298. {
  3299. }
  3300. #endif
  3301. /* Called for REPLY_RX (legacy ABG frames), or
  3302. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  3303. static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
  3304. struct iwl4965_rx_mem_buffer *rxb)
  3305. {
  3306. struct ieee80211_hdr *header;
  3307. struct ieee80211_rx_status rx_status;
  3308. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3309. /* Use phy data (Rx signal strength, etc.) contained within
  3310. * this rx packet for legacy frames,
  3311. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  3312. int include_phy = (pkt->hdr.cmd == REPLY_RX);
  3313. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  3314. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
  3315. (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  3316. __le32 *rx_end;
  3317. unsigned int len = 0;
  3318. u16 fc;
  3319. u8 network_packet;
  3320. rx_status.mactime = le64_to_cpu(rx_start->timestamp);
  3321. rx_status.freq =
  3322. ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
  3323. rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  3324. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  3325. rx_status.rate_idx =
  3326. iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
  3327. if (rx_status.band == IEEE80211_BAND_5GHZ)
  3328. rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
  3329. rx_status.antenna = 0;
  3330. rx_status.flag = 0;
  3331. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  3332. IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
  3333. rx_start->cfg_phy_cnt);
  3334. return;
  3335. }
  3336. if (!include_phy) {
  3337. if (priv->last_phy_res[0])
  3338. rx_start = (struct iwl4965_rx_phy_res *)
  3339. &priv->last_phy_res[1];
  3340. else
  3341. rx_start = NULL;
  3342. }
  3343. if (!rx_start) {
  3344. IWL_ERROR("MPDU frame without a PHY data\n");
  3345. return;
  3346. }
  3347. if (include_phy) {
  3348. header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
  3349. + rx_start->cfg_phy_cnt);
  3350. len = le16_to_cpu(rx_start->byte_count);
  3351. rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
  3352. sizeof(struct iwl4965_rx_phy_res) + len);
  3353. } else {
  3354. struct iwl4965_rx_mpdu_res_start *amsdu =
  3355. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  3356. header = (void *)(pkt->u.raw +
  3357. sizeof(struct iwl4965_rx_mpdu_res_start));
  3358. len = le16_to_cpu(amsdu->byte_count);
  3359. rx_end = (__le32 *) (pkt->u.raw +
  3360. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  3361. }
  3362. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  3363. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  3364. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  3365. le32_to_cpu(*rx_end));
  3366. return;
  3367. }
  3368. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  3369. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  3370. rx_status.ssi = iwl4965_calc_rssi(rx_start);
  3371. /* Meaningful noise values are available only from beacon statistics,
  3372. * which are gathered only when associated, and indicate noise
  3373. * only for the associated network channel ...
  3374. * Ignore these noise values while scanning (other channels) */
  3375. if (iwl_is_associated(priv) &&
  3376. !test_bit(STATUS_SCANNING, &priv->status)) {
  3377. rx_status.noise = priv->last_rx_noise;
  3378. rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
  3379. rx_status.noise);
  3380. } else {
  3381. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  3382. rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
  3383. }
  3384. /* Reset beacon noise level if not associated. */
  3385. if (!iwl_is_associated(priv))
  3386. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  3387. /* Set "1" to report good data frames in groups of 100 */
  3388. /* FIXME: need to optimze the call: */
  3389. iwl4965_dbg_report_frame(priv, pkt, header, 1);
  3390. IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
  3391. rx_status.ssi, rx_status.noise, rx_status.signal,
  3392. (unsigned long long)rx_status.mactime);
  3393. network_packet = iwl4965_is_network_packet(priv, header);
  3394. if (network_packet) {
  3395. priv->last_rx_rssi = rx_status.ssi;
  3396. priv->last_beacon_time = priv->ucode_beacon_time;
  3397. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  3398. }
  3399. fc = le16_to_cpu(header->frame_control);
  3400. switch (fc & IEEE80211_FCTL_FTYPE) {
  3401. case IEEE80211_FTYPE_MGMT:
  3402. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  3403. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  3404. header->addr2);
  3405. iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
  3406. break;
  3407. case IEEE80211_FTYPE_CTL:
  3408. #ifdef CONFIG_IWL4965_HT
  3409. switch (fc & IEEE80211_FCTL_STYPE) {
  3410. case IEEE80211_STYPE_BACK_REQ:
  3411. IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
  3412. iwl4965_handle_data_packet(priv, 0, include_phy,
  3413. rxb, &rx_status);
  3414. break;
  3415. default:
  3416. break;
  3417. }
  3418. #endif
  3419. break;
  3420. case IEEE80211_FTYPE_DATA: {
  3421. DECLARE_MAC_BUF(mac1);
  3422. DECLARE_MAC_BUF(mac2);
  3423. DECLARE_MAC_BUF(mac3);
  3424. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  3425. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  3426. header->addr2);
  3427. if (unlikely(!network_packet))
  3428. IWL_DEBUG_DROP("Dropping (non network): "
  3429. "%s, %s, %s\n",
  3430. print_mac(mac1, header->addr1),
  3431. print_mac(mac2, header->addr2),
  3432. print_mac(mac3, header->addr3));
  3433. else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
  3434. IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
  3435. print_mac(mac1, header->addr1),
  3436. print_mac(mac2, header->addr2),
  3437. print_mac(mac3, header->addr3));
  3438. else
  3439. iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
  3440. &rx_status);
  3441. break;
  3442. }
  3443. default:
  3444. break;
  3445. }
  3446. }
  3447. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  3448. * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  3449. static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
  3450. struct iwl4965_rx_mem_buffer *rxb)
  3451. {
  3452. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3453. priv->last_phy_res[0] = 1;
  3454. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  3455. sizeof(struct iwl4965_rx_phy_res));
  3456. }
  3457. static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
  3458. struct iwl4965_rx_mem_buffer *rxb)
  3459. {
  3460. #ifdef CONFIG_IWL4965_SENSITIVITY
  3461. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3462. struct iwl4965_missed_beacon_notif *missed_beacon;
  3463. missed_beacon = &pkt->u.missed_beacon;
  3464. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  3465. IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  3466. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  3467. le32_to_cpu(missed_beacon->total_missed_becons),
  3468. le32_to_cpu(missed_beacon->num_recvd_beacons),
  3469. le32_to_cpu(missed_beacon->num_expected_beacons));
  3470. priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
  3471. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)))
  3472. queue_work(priv->workqueue, &priv->sensitivity_work);
  3473. }
  3474. #endif /*CONFIG_IWL4965_SENSITIVITY*/
  3475. }
  3476. #ifdef CONFIG_IWL4965_HT
  3477. /**
  3478. * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
  3479. */
  3480. static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
  3481. int sta_id, int tid)
  3482. {
  3483. unsigned long flags;
  3484. /* Remove "disable" flag, to enable Tx for this TID */
  3485. spin_lock_irqsave(&priv->sta_lock, flags);
  3486. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
  3487. priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
  3488. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3489. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3490. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3491. }
  3492. /**
  3493. * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
  3494. *
  3495. * Go through block-ack's bitmap of ACK'd frames, update driver's record of
  3496. * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
  3497. */
  3498. static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
  3499. struct iwl4965_ht_agg *agg,
  3500. struct iwl4965_compressed_ba_resp*
  3501. ba_resp)
  3502. {
  3503. int i, sh, ack;
  3504. u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
  3505. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  3506. u64 bitmap;
  3507. int successes = 0;
  3508. struct ieee80211_tx_status *tx_status;
  3509. if (unlikely(!agg->wait_for_ba)) {
  3510. IWL_ERROR("Received BA when not expected\n");
  3511. return -EINVAL;
  3512. }
  3513. /* Mark that the expected block-ack response arrived */
  3514. agg->wait_for_ba = 0;
  3515. IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
  3516. /* Calculate shift to align block-ack bits with our Tx window bits */
  3517. sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
  3518. if (sh < 0) /* tbw something is wrong with indices */
  3519. sh += 0x100;
  3520. /* don't use 64-bit values for now */
  3521. bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
  3522. if (agg->frame_count > (64 - sh)) {
  3523. IWL_DEBUG_TX_REPLY("more frames than bitmap size");
  3524. return -1;
  3525. }
  3526. /* check for success or failure according to the
  3527. * transmitted bitmap and block-ack bitmap */
  3528. bitmap &= agg->bitmap;
  3529. /* For each frame attempted in aggregation,
  3530. * update driver's record of tx frame's status. */
  3531. for (i = 0; i < agg->frame_count ; i++) {
  3532. ack = bitmap & (1 << i);
  3533. successes += !!ack;
  3534. IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
  3535. ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
  3536. agg->start_idx + i);
  3537. }
  3538. tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
  3539. tx_status->flags = IEEE80211_TX_STATUS_ACK;
  3540. tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
  3541. tx_status->ampdu_ack_map = successes;
  3542. tx_status->ampdu_ack_len = agg->frame_count;
  3543. iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
  3544. &tx_status->control);
  3545. IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
  3546. return 0;
  3547. }
  3548. /**
  3549. * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
  3550. */
  3551. static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
  3552. u16 txq_id)
  3553. {
  3554. /* Simply stop the queue, but don't change any configuration;
  3555. * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
  3556. iwl_write_prph(priv,
  3557. IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  3558. (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
  3559. (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
  3560. }
  3561. /**
  3562. * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
  3563. * priv->lock must be held by the caller
  3564. */
  3565. static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
  3566. u16 ssn_idx, u8 tx_fifo)
  3567. {
  3568. int ret = 0;
  3569. if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
  3570. IWL_WARNING("queue number too small: %d, must be > %d\n",
  3571. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  3572. return -EINVAL;
  3573. }
  3574. ret = iwl_grab_nic_access(priv);
  3575. if (ret)
  3576. return ret;
  3577. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  3578. iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  3579. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  3580. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  3581. /* supposes that ssn_idx is valid (!= 0xFFF) */
  3582. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  3583. iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  3584. iwl4965_txq_ctx_deactivate(priv, txq_id);
  3585. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
  3586. iwl_release_nic_access(priv);
  3587. return 0;
  3588. }
  3589. int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
  3590. u8 tid, int txq_id)
  3591. {
  3592. struct iwl4965_queue *q = &priv->txq[txq_id].q;
  3593. u8 *addr = priv->stations[sta_id].sta.sta.addr;
  3594. struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
  3595. switch (priv->stations[sta_id].tid[tid].agg.state) {
  3596. case IWL_EMPTYING_HW_QUEUE_DELBA:
  3597. /* We are reclaiming the last packet of the */
  3598. /* aggregated HW queue */
  3599. if (txq_id == tid_data->agg.txq_id &&
  3600. q->read_ptr == q->write_ptr) {
  3601. u16 ssn = SEQ_TO_SN(tid_data->seq_number);
  3602. int tx_fifo = default_tid_to_tx_fifo[tid];
  3603. IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
  3604. iwl4965_tx_queue_agg_disable(priv, txq_id,
  3605. ssn, tx_fifo);
  3606. tid_data->agg.state = IWL_AGG_OFF;
  3607. ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
  3608. }
  3609. break;
  3610. case IWL_EMPTYING_HW_QUEUE_ADDBA:
  3611. /* We are reclaiming the last packet of the queue */
  3612. if (tid_data->tfds_in_queue == 0) {
  3613. IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
  3614. tid_data->agg.state = IWL_AGG_ON;
  3615. ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
  3616. }
  3617. break;
  3618. }
  3619. return 0;
  3620. }
  3621. /**
  3622. * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
  3623. * @index -- current index
  3624. * @n_bd -- total number of entries in queue (s/b power of 2)
  3625. */
  3626. static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
  3627. {
  3628. return (index == 0) ? n_bd - 1 : index - 1;
  3629. }
  3630. /**
  3631. * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
  3632. *
  3633. * Handles block-acknowledge notification from device, which reports success
  3634. * of frames sent via aggregation.
  3635. */
  3636. static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
  3637. struct iwl4965_rx_mem_buffer *rxb)
  3638. {
  3639. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3640. struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
  3641. int index;
  3642. struct iwl4965_tx_queue *txq = NULL;
  3643. struct iwl4965_ht_agg *agg;
  3644. DECLARE_MAC_BUF(mac);
  3645. /* "flow" corresponds to Tx queue */
  3646. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  3647. /* "ssn" is start of block-ack Tx window, corresponds to index
  3648. * (in Tx queue's circular buffer) of first TFD/frame in window */
  3649. u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
  3650. if (scd_flow >= ARRAY_SIZE(priv->txq)) {
  3651. IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
  3652. return;
  3653. }
  3654. txq = &priv->txq[scd_flow];
  3655. agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
  3656. /* Find index just before block-ack window */
  3657. index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
  3658. /* TODO: Need to get this copy more safely - now good for debug */
  3659. IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
  3660. "sta_id = %d\n",
  3661. agg->wait_for_ba,
  3662. print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
  3663. ba_resp->sta_id);
  3664. IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
  3665. "%d, scd_ssn = %d\n",
  3666. ba_resp->tid,
  3667. ba_resp->seq_ctl,
  3668. (unsigned long long)le64_to_cpu(ba_resp->bitmap),
  3669. ba_resp->scd_flow,
  3670. ba_resp->scd_ssn);
  3671. IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
  3672. agg->start_idx,
  3673. (unsigned long long)agg->bitmap);
  3674. /* Update driver's record of ACK vs. not for each frame in window */
  3675. iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
  3676. /* Release all TFDs before the SSN, i.e. all TFDs in front of
  3677. * block-ack window (we assume that they've been successfully
  3678. * transmitted ... if not, it's too late anyway). */
  3679. if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
  3680. int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
  3681. priv->stations[ba_resp->sta_id].
  3682. tid[ba_resp->tid].tfds_in_queue -= freed;
  3683. if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
  3684. priv->mac80211_registered &&
  3685. agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
  3686. ieee80211_wake_queue(priv->hw, scd_flow);
  3687. iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
  3688. ba_resp->tid, scd_flow);
  3689. }
  3690. }
  3691. /**
  3692. * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
  3693. */
  3694. static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
  3695. u16 txq_id)
  3696. {
  3697. u32 tbl_dw_addr;
  3698. u32 tbl_dw;
  3699. u16 scd_q2ratid;
  3700. scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
  3701. tbl_dw_addr = priv->scd_base_addr +
  3702. SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
  3703. tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
  3704. if (txq_id & 0x1)
  3705. tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
  3706. else
  3707. tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
  3708. iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
  3709. return 0;
  3710. }
  3711. /**
  3712. * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
  3713. *
  3714. * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
  3715. * i.e. it must be one of the higher queues used for aggregation
  3716. */
  3717. static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
  3718. int tx_fifo, int sta_id, int tid,
  3719. u16 ssn_idx)
  3720. {
  3721. unsigned long flags;
  3722. int rc;
  3723. u16 ra_tid;
  3724. if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
  3725. IWL_WARNING("queue number too small: %d, must be > %d\n",
  3726. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  3727. ra_tid = BUILD_RAxTID(sta_id, tid);
  3728. /* Modify device's station table to Tx this TID */
  3729. iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
  3730. spin_lock_irqsave(&priv->lock, flags);
  3731. rc = iwl_grab_nic_access(priv);
  3732. if (rc) {
  3733. spin_unlock_irqrestore(&priv->lock, flags);
  3734. return rc;
  3735. }
  3736. /* Stop this Tx queue before configuring it */
  3737. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  3738. /* Map receiver-address / traffic-ID to this queue */
  3739. iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
  3740. /* Set this queue as a chain-building queue */
  3741. iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  3742. /* Place first TFD at index corresponding to start sequence number.
  3743. * Assumes that ssn_idx is valid (!= 0xFFF) */
  3744. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  3745. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  3746. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  3747. /* Set up Tx window size and frame limit for this queue */
  3748. iwl_write_targ_mem(priv,
  3749. priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
  3750. (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  3751. SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  3752. iwl_write_targ_mem(priv, priv->scd_base_addr +
  3753. SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
  3754. (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
  3755. & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  3756. iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  3757. /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
  3758. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
  3759. iwl_release_nic_access(priv);
  3760. spin_unlock_irqrestore(&priv->lock, flags);
  3761. return 0;
  3762. }
  3763. #endif /* CONFIG_IWL4965_HT */
  3764. /**
  3765. * iwl4965_add_station - Initialize a station's hardware rate table
  3766. *
  3767. * The uCode's station table contains a table of fallback rates
  3768. * for automatic fallback during transmission.
  3769. *
  3770. * NOTE: This sets up a default set of values. These will be replaced later
  3771. * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
  3772. * rc80211_simple.
  3773. *
  3774. * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
  3775. * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
  3776. * which requires station table entry to exist).
  3777. */
  3778. void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
  3779. {
  3780. int i, r;
  3781. struct iwl4965_link_quality_cmd link_cmd = {
  3782. .reserved1 = 0,
  3783. };
  3784. u16 rate_flags;
  3785. /* Set up the rate scaling to start at selected rate, fall back
  3786. * all the way down to 1M in IEEE order, and then spin on 1M */
  3787. if (is_ap)
  3788. r = IWL_RATE_54M_INDEX;
  3789. else if (priv->band == IEEE80211_BAND_5GHZ)
  3790. r = IWL_RATE_6M_INDEX;
  3791. else
  3792. r = IWL_RATE_1M_INDEX;
  3793. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
  3794. rate_flags = 0;
  3795. if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
  3796. rate_flags |= RATE_MCS_CCK_MSK;
  3797. /* Use Tx antenna B only */
  3798. rate_flags |= RATE_MCS_ANT_B_MSK;
  3799. rate_flags &= ~RATE_MCS_ANT_A_MSK;
  3800. link_cmd.rs_table[i].rate_n_flags =
  3801. iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
  3802. r = iwl4965_get_prev_ieee_rate(r);
  3803. }
  3804. link_cmd.general_params.single_stream_ant_msk = 2;
  3805. link_cmd.general_params.dual_stream_ant_msk = 3;
  3806. link_cmd.agg_params.agg_dis_start_th = 3;
  3807. link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
  3808. /* Update the rate scaling for control frame Tx to AP */
  3809. link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_setting.bcast_sta_id;
  3810. iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
  3811. sizeof(link_cmd), &link_cmd, NULL);
  3812. }
  3813. #ifdef CONFIG_IWL4965_HT
  3814. static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
  3815. enum ieee80211_band band,
  3816. u16 channel, u8 extension_chan_offset)
  3817. {
  3818. const struct iwl_channel_info *ch_info;
  3819. ch_info = iwl_get_channel_info(priv, band, channel);
  3820. if (!is_channel_valid(ch_info))
  3821. return 0;
  3822. if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
  3823. return 0;
  3824. if ((ch_info->fat_extension_channel == extension_chan_offset) ||
  3825. (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
  3826. return 1;
  3827. return 0;
  3828. }
  3829. static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
  3830. struct ieee80211_ht_info *sta_ht_inf)
  3831. {
  3832. struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
  3833. if ((!iwl_ht_conf->is_ht) ||
  3834. (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
  3835. (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
  3836. return 0;
  3837. if (sta_ht_inf) {
  3838. if ((!sta_ht_inf->ht_supported) ||
  3839. (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
  3840. return 0;
  3841. }
  3842. return (iwl4965_is_channel_extension(priv, priv->band,
  3843. iwl_ht_conf->control_channel,
  3844. iwl_ht_conf->extension_chan_offset));
  3845. }
  3846. void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
  3847. {
  3848. struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
  3849. u32 val;
  3850. if (!ht_info->is_ht)
  3851. return;
  3852. /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
  3853. if (iwl4965_is_fat_tx_allowed(priv, NULL))
  3854. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3855. else
  3856. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
  3857. RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
  3858. if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
  3859. IWL_DEBUG_ASSOC("control diff than current %d %d\n",
  3860. le16_to_cpu(rxon->channel),
  3861. ht_info->control_channel);
  3862. rxon->channel = cpu_to_le16(ht_info->control_channel);
  3863. return;
  3864. }
  3865. /* Note: control channel is opposite of extension channel */
  3866. switch (ht_info->extension_chan_offset) {
  3867. case IWL_EXT_CHANNEL_OFFSET_ABOVE:
  3868. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3869. break;
  3870. case IWL_EXT_CHANNEL_OFFSET_BELOW:
  3871. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3872. break;
  3873. case IWL_EXT_CHANNEL_OFFSET_NONE:
  3874. default:
  3875. rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3876. break;
  3877. }
  3878. val = ht_info->ht_protection;
  3879. rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
  3880. iwl4965_set_rxon_chain(priv);
  3881. IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
  3882. "rxon flags 0x%X operation mode :0x%X "
  3883. "extension channel offset 0x%x "
  3884. "control chan %d\n",
  3885. ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
  3886. le32_to_cpu(rxon->flags), ht_info->ht_protection,
  3887. ht_info->extension_chan_offset,
  3888. ht_info->control_channel);
  3889. return;
  3890. }
  3891. void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
  3892. struct ieee80211_ht_info *sta_ht_inf)
  3893. {
  3894. __le32 sta_flags;
  3895. u8 mimo_ps_mode;
  3896. if (!sta_ht_inf || !sta_ht_inf->ht_supported)
  3897. goto done;
  3898. mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
  3899. sta_flags = priv->stations[index].sta.station_flags;
  3900. sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
  3901. switch (mimo_ps_mode) {
  3902. case WLAN_HT_CAP_MIMO_PS_STATIC:
  3903. sta_flags |= STA_FLG_MIMO_DIS_MSK;
  3904. break;
  3905. case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
  3906. sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
  3907. break;
  3908. case WLAN_HT_CAP_MIMO_PS_DISABLED:
  3909. break;
  3910. default:
  3911. IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
  3912. break;
  3913. }
  3914. sta_flags |= cpu_to_le32(
  3915. (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
  3916. sta_flags |= cpu_to_le32(
  3917. (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
  3918. if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
  3919. sta_flags |= STA_FLG_FAT_EN_MSK;
  3920. else
  3921. sta_flags &= ~STA_FLG_FAT_EN_MSK;
  3922. priv->stations[index].sta.station_flags = sta_flags;
  3923. done:
  3924. return;
  3925. }
  3926. static void iwl4965_sta_modify_add_ba_tid(struct iwl_priv *priv,
  3927. int sta_id, int tid, u16 ssn)
  3928. {
  3929. unsigned long flags;
  3930. spin_lock_irqsave(&priv->sta_lock, flags);
  3931. priv->stations[sta_id].sta.station_flags_msk = 0;
  3932. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
  3933. priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
  3934. priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
  3935. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3936. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3937. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3938. }
  3939. static void iwl4965_sta_modify_del_ba_tid(struct iwl_priv *priv,
  3940. int sta_id, int tid)
  3941. {
  3942. unsigned long flags;
  3943. spin_lock_irqsave(&priv->sta_lock, flags);
  3944. priv->stations[sta_id].sta.station_flags_msk = 0;
  3945. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
  3946. priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
  3947. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3948. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3949. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3950. }
  3951. /*
  3952. * Find first available (lowest unused) Tx Queue, mark it "active".
  3953. * Called only when finding queue for aggregation.
  3954. * Should never return anything < 7, because they should already
  3955. * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
  3956. */
  3957. static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
  3958. {
  3959. int txq_id;
  3960. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
  3961. if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
  3962. return txq_id;
  3963. return -1;
  3964. }
  3965. static int iwl4965_mac_ht_tx_agg_start(struct ieee80211_hw *hw, const u8 *da,
  3966. u16 tid, u16 *start_seq_num)
  3967. {
  3968. struct iwl_priv *priv = hw->priv;
  3969. int sta_id;
  3970. int tx_fifo;
  3971. int txq_id;
  3972. int ssn = -1;
  3973. int ret = 0;
  3974. unsigned long flags;
  3975. struct iwl4965_tid_data *tid_data;
  3976. DECLARE_MAC_BUF(mac);
  3977. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  3978. tx_fifo = default_tid_to_tx_fifo[tid];
  3979. else
  3980. return -EINVAL;
  3981. IWL_WARNING("%s on da = %s tid = %d\n",
  3982. __func__, print_mac(mac, da), tid);
  3983. sta_id = iwl4965_hw_find_station(priv, da);
  3984. if (sta_id == IWL_INVALID_STATION)
  3985. return -ENXIO;
  3986. if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
  3987. IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
  3988. return -ENXIO;
  3989. }
  3990. txq_id = iwl4965_txq_ctx_activate_free(priv);
  3991. if (txq_id == -1)
  3992. return -ENXIO;
  3993. spin_lock_irqsave(&priv->sta_lock, flags);
  3994. tid_data = &priv->stations[sta_id].tid[tid];
  3995. ssn = SEQ_TO_SN(tid_data->seq_number);
  3996. tid_data->agg.txq_id = txq_id;
  3997. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3998. *start_seq_num = ssn;
  3999. ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
  4000. sta_id, tid, ssn);
  4001. if (ret)
  4002. return ret;
  4003. ret = 0;
  4004. if (tid_data->tfds_in_queue == 0) {
  4005. printk(KERN_ERR "HW queue is empty\n");
  4006. tid_data->agg.state = IWL_AGG_ON;
  4007. ieee80211_start_tx_ba_cb_irqsafe(hw, da, tid);
  4008. } else {
  4009. IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
  4010. tid_data->tfds_in_queue);
  4011. tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
  4012. }
  4013. return ret;
  4014. }
  4015. static int iwl4965_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, const u8 *da,
  4016. u16 tid)
  4017. {
  4018. struct iwl_priv *priv = hw->priv;
  4019. int tx_fifo_id, txq_id, sta_id, ssn = -1;
  4020. struct iwl4965_tid_data *tid_data;
  4021. int ret, write_ptr, read_ptr;
  4022. unsigned long flags;
  4023. DECLARE_MAC_BUF(mac);
  4024. if (!da) {
  4025. IWL_ERROR("da = NULL\n");
  4026. return -EINVAL;
  4027. }
  4028. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  4029. tx_fifo_id = default_tid_to_tx_fifo[tid];
  4030. else
  4031. return -EINVAL;
  4032. sta_id = iwl4965_hw_find_station(priv, da);
  4033. if (sta_id == IWL_INVALID_STATION)
  4034. return -ENXIO;
  4035. if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
  4036. IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
  4037. tid_data = &priv->stations[sta_id].tid[tid];
  4038. ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
  4039. txq_id = tid_data->agg.txq_id;
  4040. write_ptr = priv->txq[txq_id].q.write_ptr;
  4041. read_ptr = priv->txq[txq_id].q.read_ptr;
  4042. /* The queue is not empty */
  4043. if (write_ptr != read_ptr) {
  4044. IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
  4045. priv->stations[sta_id].tid[tid].agg.state =
  4046. IWL_EMPTYING_HW_QUEUE_DELBA;
  4047. return 0;
  4048. }
  4049. IWL_DEBUG_HT("HW queue empty\n");;
  4050. priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
  4051. spin_lock_irqsave(&priv->lock, flags);
  4052. ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
  4053. spin_unlock_irqrestore(&priv->lock, flags);
  4054. if (ret)
  4055. return ret;
  4056. ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, da, tid);
  4057. IWL_DEBUG_INFO("iwl4965_mac_ht_tx_agg_stop on da=%s tid=%d\n",
  4058. print_mac(mac, da), tid);
  4059. return 0;
  4060. }
  4061. int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
  4062. enum ieee80211_ampdu_mlme_action action,
  4063. const u8 *addr, u16 tid, u16 *ssn)
  4064. {
  4065. struct iwl_priv *priv = hw->priv;
  4066. int sta_id;
  4067. DECLARE_MAC_BUF(mac);
  4068. IWL_DEBUG_HT("A-MPDU action on da=%s tid=%d ",
  4069. print_mac(mac, addr), tid);
  4070. sta_id = iwl4965_hw_find_station(priv, addr);
  4071. switch (action) {
  4072. case IEEE80211_AMPDU_RX_START:
  4073. IWL_DEBUG_HT("start Rx\n");
  4074. iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, *ssn);
  4075. break;
  4076. case IEEE80211_AMPDU_RX_STOP:
  4077. IWL_DEBUG_HT("stop Rx\n");
  4078. iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid);
  4079. break;
  4080. case IEEE80211_AMPDU_TX_START:
  4081. IWL_DEBUG_HT("start Tx\n");
  4082. return iwl4965_mac_ht_tx_agg_start(hw, addr, tid, ssn);
  4083. case IEEE80211_AMPDU_TX_STOP:
  4084. IWL_DEBUG_HT("stop Tx\n");
  4085. return iwl4965_mac_ht_tx_agg_stop(hw, addr, tid);
  4086. default:
  4087. IWL_DEBUG_HT("unknown\n");
  4088. return -EINVAL;
  4089. break;
  4090. }
  4091. return 0;
  4092. }
  4093. #endif /* CONFIG_IWL4965_HT */
  4094. /* Set up 4965-specific Rx frame reply handlers */
  4095. void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
  4096. {
  4097. /* Legacy Rx frames */
  4098. priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
  4099. /* High-throughput (HT) Rx frames */
  4100. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
  4101. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
  4102. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  4103. iwl4965_rx_missed_beacon_notif;
  4104. #ifdef CONFIG_IWL4965_HT
  4105. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
  4106. #endif /* CONFIG_IWL4965_HT */
  4107. }
  4108. void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
  4109. {
  4110. INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
  4111. INIT_WORK(&priv->statistics_work, iwl4965_bg_statistics_work);
  4112. #ifdef CONFIG_IWL4965_SENSITIVITY
  4113. INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
  4114. #endif
  4115. init_timer(&priv->statistics_periodic);
  4116. priv->statistics_periodic.data = (unsigned long)priv;
  4117. priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
  4118. }
  4119. void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
  4120. {
  4121. del_timer_sync(&priv->statistics_periodic);
  4122. cancel_delayed_work(&priv->init_alive_start);
  4123. }
  4124. static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
  4125. .enqueue_hcmd = iwl4965_enqueue_hcmd,
  4126. };
  4127. static struct iwl_lib_ops iwl4965_lib = {
  4128. .init_drv = iwl4965_init_drv,
  4129. .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
  4130. .hw_nic_init = iwl4965_hw_nic_init,
  4131. .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
  4132. .alive_notify = iwl4965_alive_notify,
  4133. .load_ucode = iwl4965_load_bsm,
  4134. .eeprom_ops = {
  4135. .verify_signature = iwlcore_eeprom_verify_signature,
  4136. .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
  4137. .release_semaphore = iwlcore_eeprom_release_semaphore,
  4138. },
  4139. .radio_kill_sw = iwl4965_radio_kill_sw,
  4140. };
  4141. static struct iwl_ops iwl4965_ops = {
  4142. .lib = &iwl4965_lib,
  4143. .utils = &iwl4965_hcmd_utils,
  4144. };
  4145. static struct iwl_cfg iwl4965_agn_cfg = {
  4146. .name = "4965AGN",
  4147. .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
  4148. .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
  4149. .ops = &iwl4965_ops,
  4150. .mod_params = &iwl4965_mod_params,
  4151. };
  4152. struct pci_device_id iwl4965_hw_card_ids[] = {
  4153. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  4154. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  4155. {0}
  4156. };
  4157. MODULE_DEVICE_TABLE(pci, iwl4965_hw_card_ids);
  4158. module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
  4159. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  4160. module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
  4161. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  4162. module_param_named(hwcrypto, iwl4965_mod_params.hw_crypto, int, 0444);
  4163. MODULE_PARM_DESC(hwcrypto,
  4164. "using hardware crypto engine (default 0 [software])\n");
  4165. module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
  4166. MODULE_PARM_DESC(debug, "debug output mask");
  4167. module_param_named(
  4168. disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
  4169. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  4170. module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
  4171. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  4172. /* QoS */
  4173. module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
  4174. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  4175. module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
  4176. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");