tsi57x.c 8.1 KB

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  1. /*
  2. * RapidIO Tsi57x switch family support
  3. *
  4. * Copyright 2009-2010 Integrated Device Technology, Inc.
  5. * Alexandre Bounine <alexandre.bounine@idt.com>
  6. * - Added EM support
  7. * - Modified switch operations initialization.
  8. *
  9. * Copyright 2005 MontaVista Software, Inc.
  10. * Matt Porter <mporter@kernel.crashing.org>
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License as published by the
  14. * Free Software Foundation; either version 2 of the License, or (at your
  15. * option) any later version.
  16. */
  17. #include <linux/rio.h>
  18. #include <linux/rio_drv.h>
  19. #include <linux/rio_ids.h>
  20. #include <linux/delay.h>
  21. #include "../rio.h"
  22. /* Global (broadcast) route registers */
  23. #define SPBC_ROUTE_CFG_DESTID 0x10070
  24. #define SPBC_ROUTE_CFG_PORT 0x10074
  25. /* Per port route registers */
  26. #define SPP_ROUTE_CFG_DESTID(n) (0x11070 + 0x100*n)
  27. #define SPP_ROUTE_CFG_PORT(n) (0x11074 + 0x100*n)
  28. #define TSI578_SP_MODE(n) (0x11004 + n*0x100)
  29. #define TSI578_SP_MODE_PW_DIS 0x08000000
  30. #define TSI578_SP_CTL_INDEP(n) (0x13004 + n*0x100)
  31. #define TSI578_SP_LUT_PEINF(n) (0x13010 + n*0x100)
  32. #define TSI578_SP_CS_TX(n) (0x13014 + n*0x100)
  33. #define TSI578_SP_INT_STATUS(n) (0x13018 + n*0x100)
  34. static int
  35. tsi57x_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
  36. u16 table, u16 route_destid, u8 route_port)
  37. {
  38. if (table == RIO_GLOBAL_TABLE) {
  39. rio_mport_write_config_32(mport, destid, hopcount,
  40. SPBC_ROUTE_CFG_DESTID, route_destid);
  41. rio_mport_write_config_32(mport, destid, hopcount,
  42. SPBC_ROUTE_CFG_PORT, route_port);
  43. } else {
  44. rio_mport_write_config_32(mport, destid, hopcount,
  45. SPP_ROUTE_CFG_DESTID(table), route_destid);
  46. rio_mport_write_config_32(mport, destid, hopcount,
  47. SPP_ROUTE_CFG_PORT(table), route_port);
  48. }
  49. udelay(10);
  50. return 0;
  51. }
  52. static int
  53. tsi57x_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
  54. u16 table, u16 route_destid, u8 *route_port)
  55. {
  56. int ret = 0;
  57. u32 result;
  58. if (table == RIO_GLOBAL_TABLE) {
  59. /* Use local RT of the ingress port to avoid possible
  60. race condition */
  61. rio_mport_read_config_32(mport, destid, hopcount,
  62. RIO_SWP_INFO_CAR, &result);
  63. table = (result & RIO_SWP_INFO_PORT_NUM_MASK);
  64. }
  65. rio_mport_write_config_32(mport, destid, hopcount,
  66. SPP_ROUTE_CFG_DESTID(table), route_destid);
  67. rio_mport_read_config_32(mport, destid, hopcount,
  68. SPP_ROUTE_CFG_PORT(table), &result);
  69. *route_port = (u8)result;
  70. if (*route_port > 15)
  71. ret = -1;
  72. return ret;
  73. }
  74. static int
  75. tsi57x_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
  76. u16 table)
  77. {
  78. u32 route_idx;
  79. u32 lut_size;
  80. lut_size = (mport->sys_size) ? 0x1ff : 0xff;
  81. if (table == RIO_GLOBAL_TABLE) {
  82. rio_mport_write_config_32(mport, destid, hopcount,
  83. SPBC_ROUTE_CFG_DESTID, 0x80000000);
  84. for (route_idx = 0; route_idx <= lut_size; route_idx++)
  85. rio_mport_write_config_32(mport, destid, hopcount,
  86. SPBC_ROUTE_CFG_PORT,
  87. RIO_INVALID_ROUTE);
  88. } else {
  89. rio_mport_write_config_32(mport, destid, hopcount,
  90. SPP_ROUTE_CFG_DESTID(table), 0x80000000);
  91. for (route_idx = 0; route_idx <= lut_size; route_idx++)
  92. rio_mport_write_config_32(mport, destid, hopcount,
  93. SPP_ROUTE_CFG_PORT(table) , RIO_INVALID_ROUTE);
  94. }
  95. return 0;
  96. }
  97. static int
  98. tsi57x_em_init(struct rio_dev *rdev)
  99. {
  100. struct rio_mport *mport = rdev->net->hport;
  101. u16 destid = rdev->rswitch->destid;
  102. u8 hopcount = rdev->rswitch->hopcount;
  103. u32 regval;
  104. int portnum;
  105. pr_debug("TSI578 %s [%d:%d]\n", __func__, destid, hopcount);
  106. for (portnum = 0; portnum < 16; portnum++) {
  107. /* Make sure that Port-Writes are enabled (for all ports) */
  108. rio_mport_read_config_32(mport, destid, hopcount,
  109. TSI578_SP_MODE(portnum), &regval);
  110. rio_mport_write_config_32(mport, destid, hopcount,
  111. TSI578_SP_MODE(portnum),
  112. regval & ~TSI578_SP_MODE_PW_DIS);
  113. /* Clear all pending interrupts */
  114. rio_mport_read_config_32(mport, destid, hopcount,
  115. rdev->phys_efptr +
  116. RIO_PORT_N_ERR_STS_CSR(portnum),
  117. &regval);
  118. rio_mport_write_config_32(mport, destid, hopcount,
  119. rdev->phys_efptr +
  120. RIO_PORT_N_ERR_STS_CSR(portnum),
  121. regval & 0x07120214);
  122. rio_mport_read_config_32(mport, destid, hopcount,
  123. TSI578_SP_INT_STATUS(portnum), &regval);
  124. rio_mport_write_config_32(mport, destid, hopcount,
  125. TSI578_SP_INT_STATUS(portnum),
  126. regval & 0x000700bd);
  127. /* Enable all interrupts to allow ports to send a port-write */
  128. rio_mport_read_config_32(mport, destid, hopcount,
  129. TSI578_SP_CTL_INDEP(portnum), &regval);
  130. rio_mport_write_config_32(mport, destid, hopcount,
  131. TSI578_SP_CTL_INDEP(portnum),
  132. regval | 0x000b0000);
  133. /* Skip next (odd) port if the current port is in x4 mode */
  134. rio_mport_read_config_32(mport, destid, hopcount,
  135. rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
  136. &regval);
  137. if ((regval & RIO_PORT_N_CTL_PWIDTH) == RIO_PORT_N_CTL_PWIDTH_4)
  138. portnum++;
  139. }
  140. return 0;
  141. }
  142. static int
  143. tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
  144. {
  145. struct rio_mport *mport = rdev->net->hport;
  146. u16 destid = rdev->rswitch->destid;
  147. u8 hopcount = rdev->rswitch->hopcount;
  148. u32 intstat, err_status;
  149. int sendcount, checkcount;
  150. u8 route_port;
  151. u32 regval;
  152. rio_mport_read_config_32(mport, destid, hopcount,
  153. rdev->phys_efptr + RIO_PORT_N_ERR_STS_CSR(portnum),
  154. &err_status);
  155. if ((err_status & RIO_PORT_N_ERR_STS_PORT_OK) &&
  156. (err_status & (RIO_PORT_N_ERR_STS_PW_OUT_ES |
  157. RIO_PORT_N_ERR_STS_PW_INP_ES))) {
  158. /* Remove any queued packets by locking/unlocking port */
  159. rio_mport_read_config_32(mport, destid, hopcount,
  160. rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
  161. &regval);
  162. if (!(regval & RIO_PORT_N_CTL_LOCKOUT)) {
  163. rio_mport_write_config_32(mport, destid, hopcount,
  164. rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
  165. regval | RIO_PORT_N_CTL_LOCKOUT);
  166. udelay(50);
  167. rio_mport_write_config_32(mport, destid, hopcount,
  168. rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
  169. regval);
  170. }
  171. /* Read from link maintenance response register to clear
  172. * valid bit
  173. */
  174. rio_mport_read_config_32(mport, destid, hopcount,
  175. rdev->phys_efptr + RIO_PORT_N_MNT_RSP_CSR(portnum),
  176. &regval);
  177. /* Send a Packet-Not-Accepted/Link-Request-Input-Status control
  178. * symbol to recover from IES/OES
  179. */
  180. sendcount = 3;
  181. while (sendcount) {
  182. rio_mport_write_config_32(mport, destid, hopcount,
  183. TSI578_SP_CS_TX(portnum), 0x40fc8000);
  184. checkcount = 3;
  185. while (checkcount--) {
  186. udelay(50);
  187. rio_mport_read_config_32(
  188. mport, destid, hopcount,
  189. rdev->phys_efptr +
  190. RIO_PORT_N_MNT_RSP_CSR(portnum),
  191. &regval);
  192. if (regval & RIO_PORT_N_MNT_RSP_RVAL)
  193. goto exit_es;
  194. }
  195. sendcount--;
  196. }
  197. }
  198. exit_es:
  199. /* Clear implementation specific error status bits */
  200. rio_mport_read_config_32(mport, destid, hopcount,
  201. TSI578_SP_INT_STATUS(portnum), &intstat);
  202. pr_debug("TSI578[%x:%x] SP%d_INT_STATUS=0x%08x\n",
  203. destid, hopcount, portnum, intstat);
  204. if (intstat & 0x10000) {
  205. rio_mport_read_config_32(mport, destid, hopcount,
  206. TSI578_SP_LUT_PEINF(portnum), &regval);
  207. regval = (mport->sys_size) ? (regval >> 16) : (regval >> 24);
  208. route_port = rdev->rswitch->route_table[regval];
  209. pr_debug("RIO: TSI578[%s] P%d LUT Parity Error (destID=%d)\n",
  210. rio_name(rdev), portnum, regval);
  211. tsi57x_route_add_entry(mport, destid, hopcount,
  212. RIO_GLOBAL_TABLE, regval, route_port);
  213. }
  214. rio_mport_write_config_32(mport, destid, hopcount,
  215. TSI578_SP_INT_STATUS(portnum),
  216. intstat & 0x000700bd);
  217. return 0;
  218. }
  219. static int tsi57x_switch_init(struct rio_dev *rdev, int do_enum)
  220. {
  221. pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
  222. rdev->rswitch->add_entry = tsi57x_route_add_entry;
  223. rdev->rswitch->get_entry = tsi57x_route_get_entry;
  224. rdev->rswitch->clr_table = tsi57x_route_clr_table;
  225. rdev->rswitch->em_init = tsi57x_em_init;
  226. rdev->rswitch->em_handle = tsi57x_em_handler;
  227. return 0;
  228. }
  229. DECLARE_RIO_SWITCH_INIT(RIO_VID_TUNDRA, RIO_DID_TSI572, tsi57x_switch_init);
  230. DECLARE_RIO_SWITCH_INIT(RIO_VID_TUNDRA, RIO_DID_TSI574, tsi57x_switch_init);
  231. DECLARE_RIO_SWITCH_INIT(RIO_VID_TUNDRA, RIO_DID_TSI577, tsi57x_switch_init);
  232. DECLARE_RIO_SWITCH_INIT(RIO_VID_TUNDRA, RIO_DID_TSI578, tsi57x_switch_init);