src.c 1.9 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879
  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/smp.h>
  17. #include <asm/unified.h>
  18. #define SRC_SCR 0x000
  19. #define SRC_GPR1 0x020
  20. #define BP_SRC_SCR_WARM_RESET_ENABLE 0
  21. #define BP_SRC_SCR_CORE1_RST 14
  22. #define BP_SRC_SCR_CORE1_ENABLE 22
  23. static void __iomem *src_base;
  24. #ifndef CONFIG_SMP
  25. #define cpu_logical_map(cpu) 0
  26. #endif
  27. void imx_enable_cpu(int cpu, bool enable)
  28. {
  29. u32 mask, val;
  30. cpu = cpu_logical_map(cpu);
  31. mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
  32. val = readl_relaxed(src_base + SRC_SCR);
  33. val = enable ? val | mask : val & ~mask;
  34. writel_relaxed(val, src_base + SRC_SCR);
  35. }
  36. void imx_set_cpu_jump(int cpu, void *jump_addr)
  37. {
  38. cpu = cpu_logical_map(cpu);
  39. writel_relaxed(BSYM(virt_to_phys(jump_addr)),
  40. src_base + SRC_GPR1 + cpu * 8);
  41. }
  42. void imx_src_prepare_restart(void)
  43. {
  44. u32 val;
  45. /* clear enable bits of secondary cores */
  46. val = readl_relaxed(src_base + SRC_SCR);
  47. val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
  48. writel_relaxed(val, src_base + SRC_SCR);
  49. /* clear persistent entry register of primary core */
  50. writel_relaxed(0, src_base + SRC_GPR1);
  51. }
  52. void __init imx_src_init(void)
  53. {
  54. struct device_node *np;
  55. u32 val;
  56. np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
  57. src_base = of_iomap(np, 0);
  58. WARN_ON(!src_base);
  59. /*
  60. * force warm reset sources to generate cold reset
  61. * for a more reliable restart
  62. */
  63. val = readl_relaxed(src_base + SRC_SCR);
  64. val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
  65. writel_relaxed(val, src_base + SRC_SCR);
  66. }