pm-sh7372.c 11 KB

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  1. /*
  2. * sh7372 Power management support
  3. *
  4. * Copyright (C) 2011 Magnus Damm
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/pm.h>
  11. #include <linux/suspend.h>
  12. #include <linux/cpuidle.h>
  13. #include <linux/module.h>
  14. #include <linux/list.h>
  15. #include <linux/err.h>
  16. #include <linux/slab.h>
  17. #include <linux/pm_clock.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/delay.h>
  20. #include <linux/irq.h>
  21. #include <linux/bitrev.h>
  22. #include <linux/console.h>
  23. #include <asm/system.h>
  24. #include <asm/io.h>
  25. #include <asm/tlbflush.h>
  26. #include <asm/suspend.h>
  27. #include <mach/common.h>
  28. #include <mach/sh7372.h>
  29. /* DBG */
  30. #define DBGREG1 0xe6100020
  31. #define DBGREG9 0xe6100040
  32. /* CPGA */
  33. #define SYSTBCR 0xe6150024
  34. #define MSTPSR0 0xe6150030
  35. #define MSTPSR1 0xe6150038
  36. #define MSTPSR2 0xe6150040
  37. #define MSTPSR3 0xe6150048
  38. #define MSTPSR4 0xe615004c
  39. #define PLLC01STPCR 0xe61500c8
  40. /* SYSC */
  41. #define SPDCR 0xe6180008
  42. #define SWUCR 0xe6180014
  43. #define SBAR 0xe6180020
  44. #define WUPRMSK 0xe6180028
  45. #define WUPSMSK 0xe618002c
  46. #define WUPSMSK2 0xe6180048
  47. #define PSTR 0xe6180080
  48. #define WUPSFAC 0xe6180098
  49. #define IRQCR 0xe618022c
  50. #define IRQCR2 0xe6180238
  51. #define IRQCR3 0xe6180244
  52. #define IRQCR4 0xe6180248
  53. #define PDNSEL 0xe6180254
  54. /* INTC */
  55. #define ICR1A 0xe6900000
  56. #define ICR2A 0xe6900004
  57. #define ICR3A 0xe6900008
  58. #define ICR4A 0xe690000c
  59. #define INTMSK00A 0xe6900040
  60. #define INTMSK10A 0xe6900044
  61. #define INTMSK20A 0xe6900048
  62. #define INTMSK30A 0xe690004c
  63. /* MFIS */
  64. #define SMFRAM 0xe6a70000
  65. /* AP-System Core */
  66. #define APARMBAREA 0xe6f10020
  67. #define PSTR_RETRIES 100
  68. #define PSTR_DELAY_US 10
  69. #ifdef CONFIG_PM
  70. static int pd_power_down(struct generic_pm_domain *genpd)
  71. {
  72. struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
  73. unsigned int mask = 1 << sh7372_pd->bit_shift;
  74. if (sh7372_pd->suspend)
  75. sh7372_pd->suspend();
  76. if (sh7372_pd->stay_on)
  77. return 0;
  78. if (__raw_readl(PSTR) & mask) {
  79. unsigned int retry_count;
  80. __raw_writel(mask, SPDCR);
  81. for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
  82. if (!(__raw_readl(SPDCR) & mask))
  83. break;
  84. cpu_relax();
  85. }
  86. }
  87. if (!sh7372_pd->no_debug)
  88. pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
  89. mask, __raw_readl(PSTR));
  90. return 0;
  91. }
  92. static int pd_power_up(struct generic_pm_domain *genpd)
  93. {
  94. struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
  95. unsigned int mask = 1 << sh7372_pd->bit_shift;
  96. unsigned int retry_count;
  97. int ret = 0;
  98. if (sh7372_pd->stay_on)
  99. goto out;
  100. if (__raw_readl(PSTR) & mask)
  101. goto out;
  102. __raw_writel(mask, SWUCR);
  103. for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
  104. if (!(__raw_readl(SWUCR) & mask))
  105. break;
  106. if (retry_count > PSTR_RETRIES)
  107. udelay(PSTR_DELAY_US);
  108. else
  109. cpu_relax();
  110. }
  111. if (!retry_count)
  112. ret = -EIO;
  113. if (!sh7372_pd->no_debug)
  114. pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
  115. mask, __raw_readl(PSTR));
  116. out:
  117. if (ret == 0 && sh7372_pd->resume)
  118. sh7372_pd->resume();
  119. return ret;
  120. }
  121. static void sh7372_a4r_suspend(void)
  122. {
  123. sh7372_intcs_suspend();
  124. __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
  125. }
  126. static bool pd_active_wakeup(struct device *dev)
  127. {
  128. return true;
  129. }
  130. static bool sh7372_power_down_forbidden(struct dev_pm_domain *domain)
  131. {
  132. return false;
  133. }
  134. struct dev_power_governor sh7372_always_on_gov = {
  135. .power_down_ok = sh7372_power_down_forbidden,
  136. };
  137. void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
  138. {
  139. struct generic_pm_domain *genpd = &sh7372_pd->genpd;
  140. pm_genpd_init(genpd, sh7372_pd->gov, false);
  141. genpd->stop_device = pm_clk_suspend;
  142. genpd->start_device = pm_clk_resume;
  143. genpd->dev_irq_safe = true;
  144. genpd->active_wakeup = pd_active_wakeup;
  145. genpd->power_off = pd_power_down;
  146. genpd->power_on = pd_power_up;
  147. genpd->power_on(&sh7372_pd->genpd);
  148. }
  149. void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
  150. struct platform_device *pdev)
  151. {
  152. struct device *dev = &pdev->dev;
  153. pm_genpd_add_device(&sh7372_pd->genpd, dev);
  154. if (pm_clk_no_clocks(dev))
  155. pm_clk_add(dev, NULL);
  156. }
  157. void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
  158. struct sh7372_pm_domain *sh7372_sd)
  159. {
  160. pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd);
  161. }
  162. struct sh7372_pm_domain sh7372_a4lc = {
  163. .bit_shift = 1,
  164. };
  165. struct sh7372_pm_domain sh7372_a4mp = {
  166. .bit_shift = 2,
  167. };
  168. struct sh7372_pm_domain sh7372_d4 = {
  169. .bit_shift = 3,
  170. };
  171. struct sh7372_pm_domain sh7372_a4r = {
  172. .bit_shift = 5,
  173. .gov = &sh7372_always_on_gov,
  174. .suspend = sh7372_a4r_suspend,
  175. .resume = sh7372_intcs_resume,
  176. .stay_on = true,
  177. };
  178. struct sh7372_pm_domain sh7372_a3rv = {
  179. .bit_shift = 6,
  180. };
  181. struct sh7372_pm_domain sh7372_a3ri = {
  182. .bit_shift = 8,
  183. };
  184. struct sh7372_pm_domain sh7372_a3sp = {
  185. .bit_shift = 11,
  186. .gov = &sh7372_always_on_gov,
  187. .no_debug = true,
  188. };
  189. struct sh7372_pm_domain sh7372_a3sg = {
  190. .bit_shift = 13,
  191. };
  192. #endif /* CONFIG_PM */
  193. #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
  194. static int sh7372_do_idle_core_standby(unsigned long unused)
  195. {
  196. cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
  197. return 0;
  198. }
  199. static void sh7372_enter_core_standby(void)
  200. {
  201. /* set reset vector, translate 4k */
  202. __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR);
  203. __raw_writel(0, APARMBAREA);
  204. /* enter sleep mode with SYSTBCR to 0x10 */
  205. __raw_writel(0x10, SYSTBCR);
  206. cpu_suspend(0, sh7372_do_idle_core_standby);
  207. __raw_writel(0, SYSTBCR);
  208. /* disable reset vector translation */
  209. __raw_writel(0, SBAR);
  210. }
  211. #endif
  212. #ifdef CONFIG_SUSPEND
  213. static void sh7372_enter_a3sm_common(int pllc0_on)
  214. {
  215. /* set reset vector, translate 4k */
  216. __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR);
  217. __raw_writel(0, APARMBAREA);
  218. if (pllc0_on)
  219. __raw_writel(0, PLLC01STPCR);
  220. else
  221. __raw_writel(1 << 28, PLLC01STPCR);
  222. __raw_writel(0, PDNSEL); /* power-down A3SM only, not A4S */
  223. __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */
  224. cpu_suspend(0, sh7372_do_idle_a3sm);
  225. __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */
  226. /* disable reset vector translation */
  227. __raw_writel(0, SBAR);
  228. }
  229. static int sh7372_a3sm_valid(unsigned long *mskp, unsigned long *msk2p)
  230. {
  231. unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4;
  232. unsigned long msk, msk2;
  233. /* check active clocks to determine potential wakeup sources */
  234. mstpsr0 = __raw_readl(MSTPSR0);
  235. if ((mstpsr0 & 0x00000003) != 0x00000003) {
  236. pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0);
  237. return 0;
  238. }
  239. mstpsr1 = __raw_readl(MSTPSR1);
  240. if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) {
  241. pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1);
  242. return 0;
  243. }
  244. mstpsr2 = __raw_readl(MSTPSR2);
  245. if ((mstpsr2 & 0x000741ff) != 0x000741ff) {
  246. pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2);
  247. return 0;
  248. }
  249. mstpsr3 = __raw_readl(MSTPSR3);
  250. if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) {
  251. pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3);
  252. return 0;
  253. }
  254. mstpsr4 = __raw_readl(MSTPSR4);
  255. if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) {
  256. pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4);
  257. return 0;
  258. }
  259. msk = 0;
  260. msk2 = 0;
  261. /* make bitmaps of limited number of wakeup sources */
  262. if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */
  263. msk |= 1 << 31;
  264. if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */
  265. msk |= 1 << 21;
  266. if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */
  267. msk |= 1 << 2;
  268. if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */
  269. msk |= 1 << 1;
  270. if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */
  271. msk |= 1 << 1;
  272. if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */
  273. msk |= 1 << 1;
  274. if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */
  275. msk2 |= 1 << 17;
  276. *mskp = msk;
  277. *msk2p = msk2;
  278. return 1;
  279. }
  280. static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
  281. {
  282. u16 tmp, irqcr1, irqcr2;
  283. int k;
  284. irqcr1 = 0;
  285. irqcr2 = 0;
  286. /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
  287. for (k = 0; k <= 7; k++) {
  288. tmp = (icr >> ((7 - k) * 4)) & 0xf;
  289. irqcr1 |= (tmp & 0x03) << (k * 2);
  290. irqcr2 |= (tmp >> 2) << (k * 2);
  291. }
  292. *irqcr1p = irqcr1;
  293. *irqcr2p = irqcr2;
  294. }
  295. static void sh7372_setup_a3sm(unsigned long msk, unsigned long msk2)
  296. {
  297. u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
  298. unsigned long tmp;
  299. /* read IRQ0A -> IRQ15A mask */
  300. tmp = bitrev8(__raw_readb(INTMSK00A));
  301. tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
  302. /* setup WUPSMSK from clocks and external IRQ mask */
  303. msk = (~msk & 0xc030000f) | (tmp << 4);
  304. __raw_writel(msk, WUPSMSK);
  305. /* propage level/edge trigger for external IRQ 0->15 */
  306. sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
  307. sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
  308. __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
  309. __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
  310. /* read IRQ16A -> IRQ31A mask */
  311. tmp = bitrev8(__raw_readb(INTMSK20A));
  312. tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
  313. /* setup WUPSMSK2 from clocks and external IRQ mask */
  314. msk2 = (~msk2 & 0x00030000) | tmp;
  315. __raw_writel(msk2, WUPSMSK2);
  316. /* propage level/edge trigger for external IRQ 16->31 */
  317. sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
  318. sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
  319. __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
  320. __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
  321. }
  322. #endif
  323. #ifdef CONFIG_CPU_IDLE
  324. static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
  325. {
  326. struct cpuidle_state *state;
  327. int i = dev->state_count;
  328. state = &dev->states[i];
  329. snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
  330. strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
  331. state->exit_latency = 10;
  332. state->target_residency = 20 + 10;
  333. state->power_usage = 1; /* perhaps not */
  334. state->flags = 0;
  335. state->flags |= CPUIDLE_FLAG_TIME_VALID;
  336. shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
  337. dev->state_count = i + 1;
  338. }
  339. static void sh7372_cpuidle_init(void)
  340. {
  341. shmobile_cpuidle_setup = sh7372_cpuidle_setup;
  342. }
  343. #else
  344. static void sh7372_cpuidle_init(void) {}
  345. #endif
  346. #ifdef CONFIG_SUSPEND
  347. static int sh7372_enter_suspend(suspend_state_t suspend_state)
  348. {
  349. unsigned long msk, msk2;
  350. /* check active clocks to determine potential wakeup sources */
  351. if (sh7372_a3sm_valid(&msk, &msk2)) {
  352. /* convert INTC mask and sense to SYSC mask and sense */
  353. sh7372_setup_a3sm(msk, msk2);
  354. /* enter A3SM sleep with PLLC0 off */
  355. pr_debug("entering A3SM\n");
  356. sh7372_enter_a3sm_common(0);
  357. } else {
  358. /* default to Core Standby that supports all wakeup sources */
  359. pr_debug("entering Core Standby\n");
  360. sh7372_enter_core_standby();
  361. }
  362. return 0;
  363. }
  364. static void sh7372_suspend_init(void)
  365. {
  366. shmobile_suspend_ops.enter = sh7372_enter_suspend;
  367. }
  368. #else
  369. static void sh7372_suspend_init(void) {}
  370. #endif
  371. void __init sh7372_pm_init(void)
  372. {
  373. /* enable DBG hardware block to kick SYSC */
  374. __raw_writel(0x0000a500, DBGREG9);
  375. __raw_writel(0x0000a501, DBGREG9);
  376. __raw_writel(0x00000000, DBGREG1);
  377. /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
  378. __raw_writel(0, PDNSEL);
  379. /* serial consoles make use of SCIF hardware located in A3SP,
  380. * keep such power domain on if "no_console_suspend" is set.
  381. */
  382. sh7372_a3sp.stay_on = !console_suspend_enabled;
  383. sh7372_suspend_init();
  384. sh7372_cpuidle_init();
  385. }