microcode_amd.c 8.4 KB

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  1. /*
  2. * AMD CPU Microcode Update Driver for Linux
  3. * Copyright (C) 2008 Advanced Micro Devices Inc.
  4. *
  5. * Author: Peter Oruba <peter.oruba@amd.com>
  6. *
  7. * Based on work by:
  8. * Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
  9. *
  10. * This driver allows to upgrade microcode on AMD
  11. * family 0x10 and 0x11 processors.
  12. *
  13. * Licensed under the terms of the GNU General Public
  14. * License version 2. See file COPYING for details.
  15. */
  16. #include <linux/firmware.h>
  17. #include <linux/pci_ids.h>
  18. #include <linux/uaccess.h>
  19. #include <linux/vmalloc.h>
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <linux/pci.h>
  23. #include <asm/microcode.h>
  24. #include <asm/processor.h>
  25. #include <asm/msr.h>
  26. MODULE_DESCRIPTION("AMD Microcode Update Driver");
  27. MODULE_AUTHOR("Peter Oruba");
  28. MODULE_LICENSE("GPL v2");
  29. #define UCODE_MAGIC 0x00414d44
  30. #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
  31. #define UCODE_UCODE_TYPE 0x00000001
  32. const struct firmware *firmware;
  33. static int supported_cpu;
  34. struct equiv_cpu_entry {
  35. u32 installed_cpu;
  36. u32 fixed_errata_mask;
  37. u32 fixed_errata_compare;
  38. u16 equiv_cpu;
  39. u16 res;
  40. } __attribute__((packed));
  41. struct microcode_header_amd {
  42. u32 data_code;
  43. u32 patch_id;
  44. u16 mc_patch_data_id;
  45. u8 mc_patch_data_len;
  46. u8 init_flag;
  47. u32 mc_patch_data_checksum;
  48. u32 nb_dev_id;
  49. u32 sb_dev_id;
  50. u16 processor_rev_id;
  51. u8 nb_rev_id;
  52. u8 sb_rev_id;
  53. u8 bios_api_rev;
  54. u8 reserved1[3];
  55. u32 match_reg[8];
  56. } __attribute__((packed));
  57. struct microcode_amd {
  58. struct microcode_header_amd hdr;
  59. unsigned int mpb[0];
  60. };
  61. #define UCODE_MAX_SIZE 2048
  62. #define UCODE_CONTAINER_SECTION_HDR 8
  63. #define UCODE_CONTAINER_HEADER_SIZE 12
  64. static struct equiv_cpu_entry *equiv_cpu_table;
  65. static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
  66. {
  67. u32 dummy;
  68. if (!supported_cpu)
  69. return -1;
  70. memset(csig, 0, sizeof(*csig));
  71. rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy);
  72. pr_info("microcode: CPU%d: patch_level=0x%x\n", cpu, csig->rev);
  73. return 0;
  74. }
  75. static int get_matching_microcode(int cpu, void *mc, int rev)
  76. {
  77. struct microcode_header_amd *mc_header = mc;
  78. unsigned int current_cpu_id;
  79. u16 equiv_cpu_id = 0;
  80. unsigned int i = 0;
  81. BUG_ON(equiv_cpu_table == NULL);
  82. current_cpu_id = cpuid_eax(0x00000001);
  83. while (equiv_cpu_table[i].installed_cpu != 0) {
  84. if (current_cpu_id == equiv_cpu_table[i].installed_cpu) {
  85. equiv_cpu_id = equiv_cpu_table[i].equiv_cpu;
  86. break;
  87. }
  88. i++;
  89. }
  90. if (!equiv_cpu_id)
  91. return 0;
  92. if (mc_header->processor_rev_id != equiv_cpu_id)
  93. return 0;
  94. /* ucode might be chipset specific -- currently we don't support this */
  95. if (mc_header->nb_dev_id || mc_header->sb_dev_id) {
  96. pr_err(KERN_ERR "microcode: CPU%d: loading of chipset "
  97. "specific code not yet supported\n", cpu);
  98. return 0;
  99. }
  100. if (mc_header->patch_id <= rev)
  101. return 0;
  102. return 1;
  103. }
  104. static int apply_microcode_amd(int cpu)
  105. {
  106. u32 rev, dummy;
  107. int cpu_num = raw_smp_processor_id();
  108. struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
  109. struct microcode_amd *mc_amd = uci->mc;
  110. /* We should bind the task to the CPU */
  111. BUG_ON(cpu_num != cpu);
  112. if (mc_amd == NULL)
  113. return 0;
  114. wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
  115. /* get patch id after patching */
  116. rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
  117. /* check current patch id and patch's id for match */
  118. if (rev != mc_amd->hdr.patch_id) {
  119. pr_err("microcode: CPU%d: update failed "
  120. "(for patch_level=0x%x)\n", cpu, mc_amd->hdr.patch_id);
  121. return -1;
  122. }
  123. pr_info("microcode: CPU%d: updated (new patch_level=0x%x)\n", cpu, rev);
  124. uci->cpu_sig.rev = rev;
  125. return 0;
  126. }
  127. static int get_ucode_data(void *to, const u8 *from, size_t n)
  128. {
  129. memcpy(to, from, n);
  130. return 0;
  131. }
  132. static void *
  133. get_next_ucode(const u8 *buf, unsigned int size, unsigned int *mc_size)
  134. {
  135. unsigned int total_size;
  136. u8 section_hdr[UCODE_CONTAINER_SECTION_HDR];
  137. void *mc;
  138. if (get_ucode_data(section_hdr, buf, UCODE_CONTAINER_SECTION_HDR))
  139. return NULL;
  140. if (section_hdr[0] != UCODE_UCODE_TYPE) {
  141. pr_err("microcode: error: invalid type field in "
  142. "container file section header\n");
  143. return NULL;
  144. }
  145. total_size = (unsigned long) (section_hdr[4] + (section_hdr[5] << 8));
  146. if (total_size > size || total_size > UCODE_MAX_SIZE) {
  147. pr_err("microcode: error: size mismatch\n");
  148. return NULL;
  149. }
  150. mc = vmalloc(UCODE_MAX_SIZE);
  151. if (mc) {
  152. memset(mc, 0, UCODE_MAX_SIZE);
  153. if (get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR,
  154. total_size)) {
  155. vfree(mc);
  156. mc = NULL;
  157. } else
  158. *mc_size = total_size + UCODE_CONTAINER_SECTION_HDR;
  159. }
  160. return mc;
  161. }
  162. static int install_equiv_cpu_table(const u8 *buf)
  163. {
  164. u8 *container_hdr[UCODE_CONTAINER_HEADER_SIZE];
  165. unsigned int *buf_pos = (unsigned int *)container_hdr;
  166. unsigned long size;
  167. if (get_ucode_data(&container_hdr, buf, UCODE_CONTAINER_HEADER_SIZE))
  168. return 0;
  169. size = buf_pos[2];
  170. if (buf_pos[1] != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
  171. pr_err("microcode: error: invalid type field in "
  172. "container file section header\n");
  173. return 0;
  174. }
  175. equiv_cpu_table = (struct equiv_cpu_entry *) vmalloc(size);
  176. if (!equiv_cpu_table) {
  177. pr_err("microcode: failed to allocate equivalent CPU table\n");
  178. return 0;
  179. }
  180. buf += UCODE_CONTAINER_HEADER_SIZE;
  181. if (get_ucode_data(equiv_cpu_table, buf, size)) {
  182. vfree(equiv_cpu_table);
  183. return 0;
  184. }
  185. return size + UCODE_CONTAINER_HEADER_SIZE; /* add header length */
  186. }
  187. static void free_equiv_cpu_table(void)
  188. {
  189. vfree(equiv_cpu_table);
  190. equiv_cpu_table = NULL;
  191. }
  192. static enum ucode_state
  193. generic_load_microcode(int cpu, const u8 *data, size_t size)
  194. {
  195. struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
  196. const u8 *ucode_ptr = data;
  197. void *new_mc = NULL;
  198. void *mc;
  199. int new_rev = uci->cpu_sig.rev;
  200. unsigned int leftover;
  201. unsigned long offset;
  202. enum ucode_state state = UCODE_OK;
  203. offset = install_equiv_cpu_table(ucode_ptr);
  204. if (!offset) {
  205. pr_err("microcode: failed to create equivalent cpu table\n");
  206. return UCODE_ERROR;
  207. }
  208. ucode_ptr += offset;
  209. leftover = size - offset;
  210. while (leftover) {
  211. unsigned int uninitialized_var(mc_size);
  212. struct microcode_header_amd *mc_header;
  213. mc = get_next_ucode(ucode_ptr, leftover, &mc_size);
  214. if (!mc)
  215. break;
  216. mc_header = (struct microcode_header_amd *)mc;
  217. if (get_matching_microcode(cpu, mc, new_rev)) {
  218. vfree(new_mc);
  219. new_rev = mc_header->patch_id;
  220. new_mc = mc;
  221. } else
  222. vfree(mc);
  223. ucode_ptr += mc_size;
  224. leftover -= mc_size;
  225. }
  226. if (new_mc) {
  227. if (!leftover) {
  228. vfree(uci->mc);
  229. uci->mc = new_mc;
  230. pr_debug("microcode: CPU%d found a matching microcode "
  231. "update with version 0x%x (current=0x%x)\n",
  232. cpu, new_rev, uci->cpu_sig.rev);
  233. } else {
  234. vfree(new_mc);
  235. state = UCODE_ERROR;
  236. }
  237. } else
  238. state = UCODE_NFOUND;
  239. free_equiv_cpu_table();
  240. return state;
  241. }
  242. static enum ucode_state request_microcode_fw(int cpu, struct device *device)
  243. {
  244. enum ucode_state ret;
  245. if (firmware == NULL)
  246. return UCODE_NFOUND;
  247. if (*(u32 *)firmware->data != UCODE_MAGIC) {
  248. pr_err("microcode: invalid UCODE_MAGIC (0x%08x)\n",
  249. *(u32 *)firmware->data);
  250. return UCODE_ERROR;
  251. }
  252. ret = generic_load_microcode(cpu, firmware->data, firmware->size);
  253. return ret;
  254. }
  255. static enum ucode_state
  256. request_microcode_user(int cpu, const void __user *buf, size_t size)
  257. {
  258. pr_info("microcode: AMD microcode update via "
  259. "/dev/cpu/microcode not supported\n");
  260. return UCODE_ERROR;
  261. }
  262. static void microcode_fini_cpu_amd(int cpu)
  263. {
  264. struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
  265. vfree(uci->mc);
  266. uci->mc = NULL;
  267. }
  268. void init_microcode_amd(struct device *device)
  269. {
  270. const char *fw_name = "amd-ucode/microcode_amd.bin";
  271. struct cpuinfo_x86 *c = &boot_cpu_data;
  272. WARN_ON(c->x86_vendor != X86_VENDOR_AMD);
  273. if (c->x86 < 0x10) {
  274. pr_warning("microcode: AMD CPU family 0x%x not supported\n",
  275. c->x86);
  276. return;
  277. }
  278. supported_cpu = 1;
  279. if (request_firmware(&firmware, fw_name, device))
  280. pr_err("microcode: failed to load file %s\n", fw_name);
  281. }
  282. void fini_microcode_amd(void)
  283. {
  284. release_firmware(firmware);
  285. }
  286. static struct microcode_ops microcode_amd_ops = {
  287. .init = init_microcode_amd,
  288. .fini = fini_microcode_amd,
  289. .request_microcode_user = request_microcode_user,
  290. .request_microcode_fw = request_microcode_fw,
  291. .collect_cpu_info = collect_cpu_info_amd,
  292. .apply_microcode = apply_microcode_amd,
  293. .microcode_fini_cpu = microcode_fini_cpu_amd,
  294. };
  295. struct microcode_ops * __init init_amd_microcode(void)
  296. {
  297. return &microcode_amd_ops;
  298. }