socfpga.c 2.7 KB

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  1. /*
  2. * Copyright (C) 2012 Altera Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include <linux/dw_apb_timer.h>
  18. #include <linux/irqchip.h>
  19. #include <linux/of_address.h>
  20. #include <linux/of_irq.h>
  21. #include <linux/of_platform.h>
  22. #include <asm/hardware/cache-l2x0.h>
  23. #include <asm/mach/arch.h>
  24. #include <asm/mach/map.h>
  25. #include "core.h"
  26. void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
  27. void __iomem *sys_manager_base_addr;
  28. void __iomem *rst_manager_base_addr;
  29. static struct map_desc scu_io_desc __initdata = {
  30. .virtual = SOCFPGA_SCU_VIRT_BASE,
  31. .pfn = 0, /* run-time */
  32. .length = SZ_8K,
  33. .type = MT_DEVICE,
  34. };
  35. static struct map_desc uart_io_desc __initdata = {
  36. .virtual = 0xfec02000,
  37. .pfn = __phys_to_pfn(0xffc02000),
  38. .length = SZ_8K,
  39. .type = MT_DEVICE,
  40. };
  41. static void __init socfpga_scu_map_io(void)
  42. {
  43. unsigned long base;
  44. /* Get SCU base */
  45. asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
  46. scu_io_desc.pfn = __phys_to_pfn(base);
  47. iotable_init(&scu_io_desc, 1);
  48. }
  49. static void __init socfpga_map_io(void)
  50. {
  51. socfpga_scu_map_io();
  52. iotable_init(&uart_io_desc, 1);
  53. early_printk("Early printk initialized\n");
  54. }
  55. void __init socfpga_sysmgr_init(void)
  56. {
  57. struct device_node *np;
  58. np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
  59. sys_manager_base_addr = of_iomap(np, 0);
  60. np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
  61. rst_manager_base_addr = of_iomap(np, 0);
  62. }
  63. static void __init socfpga_init_irq(void)
  64. {
  65. irqchip_init();
  66. socfpga_sysmgr_init();
  67. }
  68. static void socfpga_cyclone5_restart(char mode, const char *cmd)
  69. {
  70. /* TODO: */
  71. }
  72. static void __init socfpga_cyclone5_init(void)
  73. {
  74. l2x0_of_init(0, ~0UL);
  75. of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
  76. socfpga_init_clocks();
  77. }
  78. static const char *altera_dt_match[] = {
  79. "altr,socfpga",
  80. "altr,socfpga-cyclone5",
  81. NULL
  82. };
  83. DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
  84. .smp = smp_ops(socfpga_smp_ops),
  85. .map_io = socfpga_map_io,
  86. .init_irq = socfpga_init_irq,
  87. .timer = &dw_apb_timer,
  88. .init_machine = socfpga_cyclone5_init,
  89. .restart = socfpga_cyclone5_restart,
  90. .dt_compat = altera_dt_match,
  91. MACHINE_END