qla_init.c 146 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_gbl.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <linux/vmalloc.h>
  12. #include "qla_devtbl.h"
  13. #ifdef CONFIG_SPARC
  14. #include <asm/prom.h>
  15. #endif
  16. /*
  17. * QLogic ISP2x00 Hardware Support Function Prototypes.
  18. */
  19. static int qla2x00_isp_firmware(scsi_qla_host_t *);
  20. static int qla2x00_setup_chip(scsi_qla_host_t *);
  21. static int qla2x00_init_rings(scsi_qla_host_t *);
  22. static int qla2x00_fw_ready(scsi_qla_host_t *);
  23. static int qla2x00_configure_hba(scsi_qla_host_t *);
  24. static int qla2x00_configure_loop(scsi_qla_host_t *);
  25. static int qla2x00_configure_local_loop(scsi_qla_host_t *);
  26. static int qla2x00_configure_fabric(scsi_qla_host_t *);
  27. static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
  28. static int qla2x00_device_resync(scsi_qla_host_t *);
  29. static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
  30. uint16_t *);
  31. static int qla2x00_restart_isp(scsi_qla_host_t *);
  32. static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
  33. static int qla84xx_init_chip(scsi_qla_host_t *);
  34. static int qla25xx_init_queues(struct qla_hw_data *);
  35. /* SRB Extensions ---------------------------------------------------------- */
  36. static void
  37. qla2x00_ctx_sp_timeout(unsigned long __data)
  38. {
  39. srb_t *sp = (srb_t *)__data;
  40. struct srb_ctx *ctx;
  41. struct srb_iocb *iocb;
  42. fc_port_t *fcport = sp->fcport;
  43. struct qla_hw_data *ha = fcport->vha->hw;
  44. struct req_que *req;
  45. unsigned long flags;
  46. spin_lock_irqsave(&ha->hardware_lock, flags);
  47. req = ha->req_q_map[0];
  48. req->outstanding_cmds[sp->handle] = NULL;
  49. ctx = sp->ctx;
  50. iocb = ctx->u.iocb_cmd;
  51. iocb->timeout(sp);
  52. iocb->free(sp);
  53. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  54. }
  55. static void
  56. qla2x00_ctx_sp_free(srb_t *sp)
  57. {
  58. struct srb_ctx *ctx = sp->ctx;
  59. struct srb_iocb *iocb = ctx->u.iocb_cmd;
  60. struct scsi_qla_host *vha = sp->fcport->vha;
  61. del_timer(&iocb->timer);
  62. kfree(iocb);
  63. kfree(ctx);
  64. mempool_free(sp, sp->fcport->vha->hw->srb_mempool);
  65. QLA_VHA_MARK_NOT_BUSY(vha);
  66. }
  67. inline srb_t *
  68. qla2x00_get_ctx_sp(scsi_qla_host_t *vha, fc_port_t *fcport, size_t size,
  69. unsigned long tmo)
  70. {
  71. srb_t *sp = NULL;
  72. struct qla_hw_data *ha = vha->hw;
  73. struct srb_ctx *ctx;
  74. struct srb_iocb *iocb;
  75. uint8_t bail;
  76. QLA_VHA_MARK_BUSY(vha, bail);
  77. if (bail)
  78. return NULL;
  79. sp = mempool_alloc(ha->srb_mempool, GFP_KERNEL);
  80. if (!sp)
  81. goto done;
  82. ctx = kzalloc(size, GFP_KERNEL);
  83. if (!ctx) {
  84. mempool_free(sp, ha->srb_mempool);
  85. sp = NULL;
  86. goto done;
  87. }
  88. iocb = kzalloc(sizeof(struct srb_iocb), GFP_KERNEL);
  89. if (!iocb) {
  90. mempool_free(sp, ha->srb_mempool);
  91. sp = NULL;
  92. kfree(ctx);
  93. goto done;
  94. }
  95. memset(sp, 0, sizeof(*sp));
  96. sp->fcport = fcport;
  97. sp->ctx = ctx;
  98. ctx->iocbs = 1;
  99. ctx->u.iocb_cmd = iocb;
  100. iocb->free = qla2x00_ctx_sp_free;
  101. init_timer(&iocb->timer);
  102. if (!tmo)
  103. goto done;
  104. iocb->timer.expires = jiffies + tmo * HZ;
  105. iocb->timer.data = (unsigned long)sp;
  106. iocb->timer.function = qla2x00_ctx_sp_timeout;
  107. add_timer(&iocb->timer);
  108. done:
  109. if (!sp)
  110. QLA_VHA_MARK_NOT_BUSY(vha);
  111. return sp;
  112. }
  113. /* Asynchronous Login/Logout Routines -------------------------------------- */
  114. static inline unsigned long
  115. qla2x00_get_async_timeout(struct scsi_qla_host *vha)
  116. {
  117. unsigned long tmo;
  118. struct qla_hw_data *ha = vha->hw;
  119. /* Firmware should use switch negotiated r_a_tov for timeout. */
  120. tmo = ha->r_a_tov / 10 * 2;
  121. if (!IS_FWI2_CAPABLE(ha)) {
  122. /*
  123. * Except for earlier ISPs where the timeout is seeded from the
  124. * initialization control block.
  125. */
  126. tmo = ha->login_timeout;
  127. }
  128. return tmo;
  129. }
  130. static void
  131. qla2x00_async_iocb_timeout(srb_t *sp)
  132. {
  133. fc_port_t *fcport = sp->fcport;
  134. struct srb_ctx *ctx = sp->ctx;
  135. ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
  136. "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
  137. ctx->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
  138. fcport->d_id.b.al_pa);
  139. fcport->flags &= ~FCF_ASYNC_SENT;
  140. if (ctx->type == SRB_LOGIN_CMD) {
  141. struct srb_iocb *lio = ctx->u.iocb_cmd;
  142. qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
  143. /* Retry as needed. */
  144. lio->u.logio.data[0] = MBS_COMMAND_ERROR;
  145. lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  146. QLA_LOGIO_LOGIN_RETRIED : 0;
  147. qla2x00_post_async_login_done_work(fcport->vha, fcport,
  148. lio->u.logio.data);
  149. }
  150. }
  151. static void
  152. qla2x00_async_login_ctx_done(srb_t *sp)
  153. {
  154. struct srb_ctx *ctx = sp->ctx;
  155. struct srb_iocb *lio = ctx->u.iocb_cmd;
  156. qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
  157. lio->u.logio.data);
  158. lio->free(sp);
  159. }
  160. int
  161. qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
  162. uint16_t *data)
  163. {
  164. srb_t *sp;
  165. struct srb_ctx *ctx;
  166. struct srb_iocb *lio;
  167. int rval;
  168. rval = QLA_FUNCTION_FAILED;
  169. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  170. qla2x00_get_async_timeout(vha) + 2);
  171. if (!sp)
  172. goto done;
  173. ctx = sp->ctx;
  174. ctx->type = SRB_LOGIN_CMD;
  175. ctx->name = "login";
  176. lio = ctx->u.iocb_cmd;
  177. lio->timeout = qla2x00_async_iocb_timeout;
  178. lio->done = qla2x00_async_login_ctx_done;
  179. lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
  180. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  181. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  182. rval = qla2x00_start_sp(sp);
  183. if (rval != QLA_SUCCESS)
  184. goto done_free_sp;
  185. ql_dbg(ql_dbg_disc, vha, 0x2072,
  186. "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
  187. "retries=%d.\n", sp->handle, fcport->loop_id,
  188. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  189. fcport->login_retry);
  190. return rval;
  191. done_free_sp:
  192. lio->free(sp);
  193. done:
  194. return rval;
  195. }
  196. static void
  197. qla2x00_async_logout_ctx_done(srb_t *sp)
  198. {
  199. struct srb_ctx *ctx = sp->ctx;
  200. struct srb_iocb *lio = ctx->u.iocb_cmd;
  201. qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
  202. lio->u.logio.data);
  203. lio->free(sp);
  204. }
  205. int
  206. qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
  207. {
  208. srb_t *sp;
  209. struct srb_ctx *ctx;
  210. struct srb_iocb *lio;
  211. int rval;
  212. rval = QLA_FUNCTION_FAILED;
  213. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  214. qla2x00_get_async_timeout(vha) + 2);
  215. if (!sp)
  216. goto done;
  217. ctx = sp->ctx;
  218. ctx->type = SRB_LOGOUT_CMD;
  219. ctx->name = "logout";
  220. lio = ctx->u.iocb_cmd;
  221. lio->timeout = qla2x00_async_iocb_timeout;
  222. lio->done = qla2x00_async_logout_ctx_done;
  223. rval = qla2x00_start_sp(sp);
  224. if (rval != QLA_SUCCESS)
  225. goto done_free_sp;
  226. ql_dbg(ql_dbg_disc, vha, 0x2070,
  227. "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
  228. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  229. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  230. return rval;
  231. done_free_sp:
  232. lio->free(sp);
  233. done:
  234. return rval;
  235. }
  236. static void
  237. qla2x00_async_adisc_ctx_done(srb_t *sp)
  238. {
  239. struct srb_ctx *ctx = sp->ctx;
  240. struct srb_iocb *lio = ctx->u.iocb_cmd;
  241. qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
  242. lio->u.logio.data);
  243. lio->free(sp);
  244. }
  245. int
  246. qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
  247. uint16_t *data)
  248. {
  249. srb_t *sp;
  250. struct srb_ctx *ctx;
  251. struct srb_iocb *lio;
  252. int rval;
  253. rval = QLA_FUNCTION_FAILED;
  254. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  255. qla2x00_get_async_timeout(vha) + 2);
  256. if (!sp)
  257. goto done;
  258. ctx = sp->ctx;
  259. ctx->type = SRB_ADISC_CMD;
  260. ctx->name = "adisc";
  261. lio = ctx->u.iocb_cmd;
  262. lio->timeout = qla2x00_async_iocb_timeout;
  263. lio->done = qla2x00_async_adisc_ctx_done;
  264. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  265. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  266. rval = qla2x00_start_sp(sp);
  267. if (rval != QLA_SUCCESS)
  268. goto done_free_sp;
  269. ql_dbg(ql_dbg_disc, vha, 0x206f,
  270. "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
  271. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  272. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  273. return rval;
  274. done_free_sp:
  275. lio->free(sp);
  276. done:
  277. return rval;
  278. }
  279. static void
  280. qla2x00_async_tm_cmd_ctx_done(srb_t *sp)
  281. {
  282. struct srb_ctx *ctx = sp->ctx;
  283. struct srb_iocb *iocb = (struct srb_iocb *)ctx->u.iocb_cmd;
  284. qla2x00_async_tm_cmd_done(sp->fcport->vha, sp->fcport, iocb);
  285. iocb->free(sp);
  286. }
  287. int
  288. qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
  289. uint32_t tag)
  290. {
  291. struct scsi_qla_host *vha = fcport->vha;
  292. srb_t *sp;
  293. struct srb_ctx *ctx;
  294. struct srb_iocb *tcf;
  295. int rval;
  296. rval = QLA_FUNCTION_FAILED;
  297. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  298. qla2x00_get_async_timeout(vha) + 2);
  299. if (!sp)
  300. goto done;
  301. ctx = sp->ctx;
  302. ctx->type = SRB_TM_CMD;
  303. ctx->name = "tmf";
  304. tcf = ctx->u.iocb_cmd;
  305. tcf->u.tmf.flags = flags;
  306. tcf->u.tmf.lun = lun;
  307. tcf->u.tmf.data = tag;
  308. tcf->timeout = qla2x00_async_iocb_timeout;
  309. tcf->done = qla2x00_async_tm_cmd_ctx_done;
  310. rval = qla2x00_start_sp(sp);
  311. if (rval != QLA_SUCCESS)
  312. goto done_free_sp;
  313. ql_dbg(ql_dbg_taskm, vha, 0x802f,
  314. "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
  315. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  316. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  317. return rval;
  318. done_free_sp:
  319. tcf->free(sp);
  320. done:
  321. return rval;
  322. }
  323. void
  324. qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  325. uint16_t *data)
  326. {
  327. int rval;
  328. switch (data[0]) {
  329. case MBS_COMMAND_COMPLETE:
  330. /*
  331. * Driver must validate login state - If PRLI not complete,
  332. * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
  333. * requests.
  334. */
  335. rval = qla2x00_get_port_database(vha, fcport, 0);
  336. if (rval != QLA_SUCCESS) {
  337. qla2x00_post_async_logout_work(vha, fcport, NULL);
  338. qla2x00_post_async_login_work(vha, fcport, NULL);
  339. break;
  340. }
  341. if (fcport->flags & FCF_FCP2_DEVICE) {
  342. qla2x00_post_async_adisc_work(vha, fcport, data);
  343. break;
  344. }
  345. qla2x00_update_fcport(vha, fcport);
  346. break;
  347. case MBS_COMMAND_ERROR:
  348. fcport->flags &= ~FCF_ASYNC_SENT;
  349. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  350. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  351. else
  352. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  353. break;
  354. case MBS_PORT_ID_USED:
  355. fcport->loop_id = data[1];
  356. qla2x00_post_async_logout_work(vha, fcport, NULL);
  357. qla2x00_post_async_login_work(vha, fcport, NULL);
  358. break;
  359. case MBS_LOOP_ID_USED:
  360. fcport->loop_id++;
  361. rval = qla2x00_find_new_loop_id(vha, fcport);
  362. if (rval != QLA_SUCCESS) {
  363. fcport->flags &= ~FCF_ASYNC_SENT;
  364. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  365. break;
  366. }
  367. qla2x00_post_async_login_work(vha, fcport, NULL);
  368. break;
  369. }
  370. return;
  371. }
  372. void
  373. qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  374. uint16_t *data)
  375. {
  376. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  377. return;
  378. }
  379. void
  380. qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  381. uint16_t *data)
  382. {
  383. if (data[0] == MBS_COMMAND_COMPLETE) {
  384. qla2x00_update_fcport(vha, fcport);
  385. return;
  386. }
  387. /* Retry login. */
  388. fcport->flags &= ~FCF_ASYNC_SENT;
  389. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  390. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  391. else
  392. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  393. return;
  394. }
  395. void
  396. qla2x00_async_tm_cmd_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  397. struct srb_iocb *iocb)
  398. {
  399. int rval;
  400. uint32_t flags;
  401. uint16_t lun;
  402. flags = iocb->u.tmf.flags;
  403. lun = (uint16_t)iocb->u.tmf.lun;
  404. /* Issue Marker IOCB */
  405. rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
  406. vha->hw->rsp_q_map[0], fcport->loop_id, lun,
  407. flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
  408. if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
  409. ql_dbg(ql_dbg_taskm, vha, 0x8030,
  410. "TM IOCB failed (%x).\n", rval);
  411. }
  412. return;
  413. }
  414. /****************************************************************************/
  415. /* QLogic ISP2x00 Hardware Support Functions. */
  416. /****************************************************************************/
  417. /*
  418. * qla2x00_initialize_adapter
  419. * Initialize board.
  420. *
  421. * Input:
  422. * ha = adapter block pointer.
  423. *
  424. * Returns:
  425. * 0 = success
  426. */
  427. int
  428. qla2x00_initialize_adapter(scsi_qla_host_t *vha)
  429. {
  430. int rval;
  431. struct qla_hw_data *ha = vha->hw;
  432. struct req_que *req = ha->req_q_map[0];
  433. /* Clear adapter flags. */
  434. vha->flags.online = 0;
  435. ha->flags.chip_reset_done = 0;
  436. vha->flags.reset_active = 0;
  437. ha->flags.pci_channel_io_perm_failure = 0;
  438. ha->flags.eeh_busy = 0;
  439. ha->flags.thermal_supported = 1;
  440. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  441. atomic_set(&vha->loop_state, LOOP_DOWN);
  442. vha->device_flags = DFLG_NO_CABLE;
  443. vha->dpc_flags = 0;
  444. vha->flags.management_server_logged_in = 0;
  445. vha->marker_needed = 0;
  446. ha->isp_abort_cnt = 0;
  447. ha->beacon_blink_led = 0;
  448. set_bit(0, ha->req_qid_map);
  449. set_bit(0, ha->rsp_qid_map);
  450. ql_dbg(ql_dbg_init, vha, 0x0040,
  451. "Configuring PCI space...\n");
  452. rval = ha->isp_ops->pci_config(vha);
  453. if (rval) {
  454. ql_log(ql_log_warn, vha, 0x0044,
  455. "Unable to configure PCI space.\n");
  456. return (rval);
  457. }
  458. ha->isp_ops->reset_chip(vha);
  459. rval = qla2xxx_get_flash_info(vha);
  460. if (rval) {
  461. ql_log(ql_log_fatal, vha, 0x004f,
  462. "Unable to validate FLASH data.\n");
  463. return (rval);
  464. }
  465. ha->isp_ops->get_flash_version(vha, req->ring);
  466. ql_dbg(ql_dbg_init, vha, 0x0061,
  467. "Configure NVRAM parameters...\n");
  468. ha->isp_ops->nvram_config(vha);
  469. if (ha->flags.disable_serdes) {
  470. /* Mask HBA via NVRAM settings? */
  471. ql_log(ql_log_info, vha, 0x0077,
  472. "Masking HBA WWPN "
  473. "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
  474. vha->port_name[0], vha->port_name[1],
  475. vha->port_name[2], vha->port_name[3],
  476. vha->port_name[4], vha->port_name[5],
  477. vha->port_name[6], vha->port_name[7]);
  478. return QLA_FUNCTION_FAILED;
  479. }
  480. ql_dbg(ql_dbg_init, vha, 0x0078,
  481. "Verifying loaded RISC code...\n");
  482. if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
  483. rval = ha->isp_ops->chip_diag(vha);
  484. if (rval)
  485. return (rval);
  486. rval = qla2x00_setup_chip(vha);
  487. if (rval)
  488. return (rval);
  489. }
  490. if (IS_QLA84XX(ha)) {
  491. ha->cs84xx = qla84xx_get_chip(vha);
  492. if (!ha->cs84xx) {
  493. ql_log(ql_log_warn, vha, 0x00d0,
  494. "Unable to configure ISP84XX.\n");
  495. return QLA_FUNCTION_FAILED;
  496. }
  497. }
  498. rval = qla2x00_init_rings(vha);
  499. ha->flags.chip_reset_done = 1;
  500. if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
  501. /* Issue verify 84xx FW IOCB to complete 84xx initialization */
  502. rval = qla84xx_init_chip(vha);
  503. if (rval != QLA_SUCCESS) {
  504. ql_log(ql_log_warn, vha, 0x00d4,
  505. "Unable to initialize ISP84XX.\n");
  506. qla84xx_put_chip(vha);
  507. }
  508. }
  509. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
  510. qla24xx_read_fcp_prio_cfg(vha);
  511. return (rval);
  512. }
  513. /**
  514. * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
  515. * @ha: HA context
  516. *
  517. * Returns 0 on success.
  518. */
  519. int
  520. qla2100_pci_config(scsi_qla_host_t *vha)
  521. {
  522. uint16_t w;
  523. unsigned long flags;
  524. struct qla_hw_data *ha = vha->hw;
  525. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  526. pci_set_master(ha->pdev);
  527. pci_try_set_mwi(ha->pdev);
  528. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  529. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  530. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  531. pci_disable_rom(ha->pdev);
  532. /* Get PCI bus information. */
  533. spin_lock_irqsave(&ha->hardware_lock, flags);
  534. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  535. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  536. return QLA_SUCCESS;
  537. }
  538. /**
  539. * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
  540. * @ha: HA context
  541. *
  542. * Returns 0 on success.
  543. */
  544. int
  545. qla2300_pci_config(scsi_qla_host_t *vha)
  546. {
  547. uint16_t w;
  548. unsigned long flags = 0;
  549. uint32_t cnt;
  550. struct qla_hw_data *ha = vha->hw;
  551. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  552. pci_set_master(ha->pdev);
  553. pci_try_set_mwi(ha->pdev);
  554. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  555. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  556. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  557. w &= ~PCI_COMMAND_INTX_DISABLE;
  558. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  559. /*
  560. * If this is a 2300 card and not 2312, reset the
  561. * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
  562. * the 2310 also reports itself as a 2300 so we need to get the
  563. * fb revision level -- a 6 indicates it really is a 2300 and
  564. * not a 2310.
  565. */
  566. if (IS_QLA2300(ha)) {
  567. spin_lock_irqsave(&ha->hardware_lock, flags);
  568. /* Pause RISC. */
  569. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  570. for (cnt = 0; cnt < 30000; cnt++) {
  571. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
  572. break;
  573. udelay(10);
  574. }
  575. /* Select FPM registers. */
  576. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  577. RD_REG_WORD(&reg->ctrl_status);
  578. /* Get the fb rev level */
  579. ha->fb_rev = RD_FB_CMD_REG(ha, reg);
  580. if (ha->fb_rev == FPM_2300)
  581. pci_clear_mwi(ha->pdev);
  582. /* Deselect FPM registers. */
  583. WRT_REG_WORD(&reg->ctrl_status, 0x0);
  584. RD_REG_WORD(&reg->ctrl_status);
  585. /* Release RISC module. */
  586. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  587. for (cnt = 0; cnt < 30000; cnt++) {
  588. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
  589. break;
  590. udelay(10);
  591. }
  592. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  593. }
  594. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  595. pci_disable_rom(ha->pdev);
  596. /* Get PCI bus information. */
  597. spin_lock_irqsave(&ha->hardware_lock, flags);
  598. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  599. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  600. return QLA_SUCCESS;
  601. }
  602. /**
  603. * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
  604. * @ha: HA context
  605. *
  606. * Returns 0 on success.
  607. */
  608. int
  609. qla24xx_pci_config(scsi_qla_host_t *vha)
  610. {
  611. uint16_t w;
  612. unsigned long flags = 0;
  613. struct qla_hw_data *ha = vha->hw;
  614. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  615. pci_set_master(ha->pdev);
  616. pci_try_set_mwi(ha->pdev);
  617. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  618. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  619. w &= ~PCI_COMMAND_INTX_DISABLE;
  620. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  621. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  622. /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
  623. if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
  624. pcix_set_mmrbc(ha->pdev, 2048);
  625. /* PCIe -- adjust Maximum Read Request Size (2048). */
  626. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  627. pcie_set_readrq(ha->pdev, 2048);
  628. pci_disable_rom(ha->pdev);
  629. ha->chip_revision = ha->pdev->revision;
  630. /* Get PCI bus information. */
  631. spin_lock_irqsave(&ha->hardware_lock, flags);
  632. ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
  633. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  634. return QLA_SUCCESS;
  635. }
  636. /**
  637. * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
  638. * @ha: HA context
  639. *
  640. * Returns 0 on success.
  641. */
  642. int
  643. qla25xx_pci_config(scsi_qla_host_t *vha)
  644. {
  645. uint16_t w;
  646. struct qla_hw_data *ha = vha->hw;
  647. pci_set_master(ha->pdev);
  648. pci_try_set_mwi(ha->pdev);
  649. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  650. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  651. w &= ~PCI_COMMAND_INTX_DISABLE;
  652. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  653. /* PCIe -- adjust Maximum Read Request Size (2048). */
  654. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  655. pcie_set_readrq(ha->pdev, 2048);
  656. pci_disable_rom(ha->pdev);
  657. ha->chip_revision = ha->pdev->revision;
  658. return QLA_SUCCESS;
  659. }
  660. /**
  661. * qla2x00_isp_firmware() - Choose firmware image.
  662. * @ha: HA context
  663. *
  664. * Returns 0 on success.
  665. */
  666. static int
  667. qla2x00_isp_firmware(scsi_qla_host_t *vha)
  668. {
  669. int rval;
  670. uint16_t loop_id, topo, sw_cap;
  671. uint8_t domain, area, al_pa;
  672. struct qla_hw_data *ha = vha->hw;
  673. /* Assume loading risc code */
  674. rval = QLA_FUNCTION_FAILED;
  675. if (ha->flags.disable_risc_code_load) {
  676. ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
  677. /* Verify checksum of loaded RISC code. */
  678. rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
  679. if (rval == QLA_SUCCESS) {
  680. /* And, verify we are not in ROM code. */
  681. rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
  682. &area, &domain, &topo, &sw_cap);
  683. }
  684. }
  685. if (rval)
  686. ql_dbg(ql_dbg_init, vha, 0x007a,
  687. "**** Load RISC code ****.\n");
  688. return (rval);
  689. }
  690. /**
  691. * qla2x00_reset_chip() - Reset ISP chip.
  692. * @ha: HA context
  693. *
  694. * Returns 0 on success.
  695. */
  696. void
  697. qla2x00_reset_chip(scsi_qla_host_t *vha)
  698. {
  699. unsigned long flags = 0;
  700. struct qla_hw_data *ha = vha->hw;
  701. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  702. uint32_t cnt;
  703. uint16_t cmd;
  704. if (unlikely(pci_channel_offline(ha->pdev)))
  705. return;
  706. ha->isp_ops->disable_intrs(ha);
  707. spin_lock_irqsave(&ha->hardware_lock, flags);
  708. /* Turn off master enable */
  709. cmd = 0;
  710. pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
  711. cmd &= ~PCI_COMMAND_MASTER;
  712. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  713. if (!IS_QLA2100(ha)) {
  714. /* Pause RISC. */
  715. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  716. if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
  717. for (cnt = 0; cnt < 30000; cnt++) {
  718. if ((RD_REG_WORD(&reg->hccr) &
  719. HCCR_RISC_PAUSE) != 0)
  720. break;
  721. udelay(100);
  722. }
  723. } else {
  724. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  725. udelay(10);
  726. }
  727. /* Select FPM registers. */
  728. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  729. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  730. /* FPM Soft Reset. */
  731. WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
  732. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  733. /* Toggle Fpm Reset. */
  734. if (!IS_QLA2200(ha)) {
  735. WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
  736. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  737. }
  738. /* Select frame buffer registers. */
  739. WRT_REG_WORD(&reg->ctrl_status, 0x10);
  740. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  741. /* Reset frame buffer FIFOs. */
  742. if (IS_QLA2200(ha)) {
  743. WRT_FB_CMD_REG(ha, reg, 0xa000);
  744. RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
  745. } else {
  746. WRT_FB_CMD_REG(ha, reg, 0x00fc);
  747. /* Read back fb_cmd until zero or 3 seconds max */
  748. for (cnt = 0; cnt < 3000; cnt++) {
  749. if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
  750. break;
  751. udelay(100);
  752. }
  753. }
  754. /* Select RISC module registers. */
  755. WRT_REG_WORD(&reg->ctrl_status, 0);
  756. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  757. /* Reset RISC processor. */
  758. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  759. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  760. /* Release RISC processor. */
  761. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  762. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  763. }
  764. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  765. WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
  766. /* Reset ISP chip. */
  767. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  768. /* Wait for RISC to recover from reset. */
  769. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  770. /*
  771. * It is necessary to for a delay here since the card doesn't
  772. * respond to PCI reads during a reset. On some architectures
  773. * this will result in an MCA.
  774. */
  775. udelay(20);
  776. for (cnt = 30000; cnt; cnt--) {
  777. if ((RD_REG_WORD(&reg->ctrl_status) &
  778. CSR_ISP_SOFT_RESET) == 0)
  779. break;
  780. udelay(100);
  781. }
  782. } else
  783. udelay(10);
  784. /* Reset RISC processor. */
  785. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  786. WRT_REG_WORD(&reg->semaphore, 0);
  787. /* Release RISC processor. */
  788. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  789. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  790. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  791. for (cnt = 0; cnt < 30000; cnt++) {
  792. if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
  793. break;
  794. udelay(100);
  795. }
  796. } else
  797. udelay(100);
  798. /* Turn on master enable */
  799. cmd |= PCI_COMMAND_MASTER;
  800. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  801. /* Disable RISC pause on FPM parity error. */
  802. if (!IS_QLA2100(ha)) {
  803. WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
  804. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  805. }
  806. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  807. }
  808. /**
  809. * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
  810. *
  811. * Returns 0 on success.
  812. */
  813. int
  814. qla81xx_reset_mpi(scsi_qla_host_t *vha)
  815. {
  816. uint16_t mb[4] = {0x1010, 0, 1, 0};
  817. return qla81xx_write_mpi_register(vha, mb);
  818. }
  819. /**
  820. * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
  821. * @ha: HA context
  822. *
  823. * Returns 0 on success.
  824. */
  825. static inline void
  826. qla24xx_reset_risc(scsi_qla_host_t *vha)
  827. {
  828. unsigned long flags = 0;
  829. struct qla_hw_data *ha = vha->hw;
  830. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  831. uint32_t cnt, d2;
  832. uint16_t wd;
  833. static int abts_cnt; /* ISP abort retry counts */
  834. spin_lock_irqsave(&ha->hardware_lock, flags);
  835. /* Reset RISC. */
  836. WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  837. for (cnt = 0; cnt < 30000; cnt++) {
  838. if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
  839. break;
  840. udelay(10);
  841. }
  842. WRT_REG_DWORD(&reg->ctrl_status,
  843. CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  844. pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
  845. udelay(100);
  846. /* Wait for firmware to complete NVRAM accesses. */
  847. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  848. for (cnt = 10000 ; cnt && d2; cnt--) {
  849. udelay(5);
  850. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  851. barrier();
  852. }
  853. /* Wait for soft-reset to complete. */
  854. d2 = RD_REG_DWORD(&reg->ctrl_status);
  855. for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
  856. udelay(5);
  857. d2 = RD_REG_DWORD(&reg->ctrl_status);
  858. barrier();
  859. }
  860. /* If required, do an MPI FW reset now */
  861. if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
  862. if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
  863. if (++abts_cnt < 5) {
  864. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  865. set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
  866. } else {
  867. /*
  868. * We exhausted the ISP abort retries. We have to
  869. * set the board offline.
  870. */
  871. abts_cnt = 0;
  872. vha->flags.online = 0;
  873. }
  874. }
  875. }
  876. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  877. RD_REG_DWORD(&reg->hccr);
  878. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  879. RD_REG_DWORD(&reg->hccr);
  880. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
  881. RD_REG_DWORD(&reg->hccr);
  882. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  883. for (cnt = 6000000 ; cnt && d2; cnt--) {
  884. udelay(5);
  885. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  886. barrier();
  887. }
  888. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  889. if (IS_NOPOLLING_TYPE(ha))
  890. ha->isp_ops->enable_intrs(ha);
  891. }
  892. /**
  893. * qla24xx_reset_chip() - Reset ISP24xx chip.
  894. * @ha: HA context
  895. *
  896. * Returns 0 on success.
  897. */
  898. void
  899. qla24xx_reset_chip(scsi_qla_host_t *vha)
  900. {
  901. struct qla_hw_data *ha = vha->hw;
  902. if (pci_channel_offline(ha->pdev) &&
  903. ha->flags.pci_channel_io_perm_failure) {
  904. return;
  905. }
  906. ha->isp_ops->disable_intrs(ha);
  907. /* Perform RISC reset. */
  908. qla24xx_reset_risc(vha);
  909. }
  910. /**
  911. * qla2x00_chip_diag() - Test chip for proper operation.
  912. * @ha: HA context
  913. *
  914. * Returns 0 on success.
  915. */
  916. int
  917. qla2x00_chip_diag(scsi_qla_host_t *vha)
  918. {
  919. int rval;
  920. struct qla_hw_data *ha = vha->hw;
  921. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  922. unsigned long flags = 0;
  923. uint16_t data;
  924. uint32_t cnt;
  925. uint16_t mb[5];
  926. struct req_que *req = ha->req_q_map[0];
  927. /* Assume a failed state */
  928. rval = QLA_FUNCTION_FAILED;
  929. ql_dbg(ql_dbg_init, vha, 0x007b,
  930. "Testing device at %lx.\n", (u_long)&reg->flash_address);
  931. spin_lock_irqsave(&ha->hardware_lock, flags);
  932. /* Reset ISP chip. */
  933. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  934. /*
  935. * We need to have a delay here since the card will not respond while
  936. * in reset causing an MCA on some architectures.
  937. */
  938. udelay(20);
  939. data = qla2x00_debounce_register(&reg->ctrl_status);
  940. for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
  941. udelay(5);
  942. data = RD_REG_WORD(&reg->ctrl_status);
  943. barrier();
  944. }
  945. if (!cnt)
  946. goto chip_diag_failed;
  947. ql_dbg(ql_dbg_init, vha, 0x007c,
  948. "Reset register cleared by chip reset.\n");
  949. /* Reset RISC processor. */
  950. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  951. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  952. /* Workaround for QLA2312 PCI parity error */
  953. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  954. data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
  955. for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
  956. udelay(5);
  957. data = RD_MAILBOX_REG(ha, reg, 0);
  958. barrier();
  959. }
  960. } else
  961. udelay(10);
  962. if (!cnt)
  963. goto chip_diag_failed;
  964. /* Check product ID of chip */
  965. ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
  966. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  967. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  968. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  969. mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
  970. if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
  971. mb[3] != PROD_ID_3) {
  972. ql_log(ql_log_warn, vha, 0x0062,
  973. "Wrong product ID = 0x%x,0x%x,0x%x.\n",
  974. mb[1], mb[2], mb[3]);
  975. goto chip_diag_failed;
  976. }
  977. ha->product_id[0] = mb[1];
  978. ha->product_id[1] = mb[2];
  979. ha->product_id[2] = mb[3];
  980. ha->product_id[3] = mb[4];
  981. /* Adjust fw RISC transfer size */
  982. if (req->length > 1024)
  983. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
  984. else
  985. ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
  986. req->length;
  987. if (IS_QLA2200(ha) &&
  988. RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
  989. /* Limit firmware transfer size with a 2200A */
  990. ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
  991. ha->device_type |= DT_ISP2200A;
  992. ha->fw_transfer_size = 128;
  993. }
  994. /* Wrap Incoming Mailboxes Test. */
  995. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  996. ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
  997. rval = qla2x00_mbx_reg_test(vha);
  998. if (rval)
  999. ql_log(ql_log_warn, vha, 0x0080,
  1000. "Failed mailbox send register test.\n");
  1001. else
  1002. /* Flag a successful rval */
  1003. rval = QLA_SUCCESS;
  1004. spin_lock_irqsave(&ha->hardware_lock, flags);
  1005. chip_diag_failed:
  1006. if (rval)
  1007. ql_log(ql_log_info, vha, 0x0081,
  1008. "Chip diagnostics **** FAILED ****.\n");
  1009. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1010. return (rval);
  1011. }
  1012. /**
  1013. * qla24xx_chip_diag() - Test ISP24xx for proper operation.
  1014. * @ha: HA context
  1015. *
  1016. * Returns 0 on success.
  1017. */
  1018. int
  1019. qla24xx_chip_diag(scsi_qla_host_t *vha)
  1020. {
  1021. int rval;
  1022. struct qla_hw_data *ha = vha->hw;
  1023. struct req_que *req = ha->req_q_map[0];
  1024. if (IS_QLA82XX(ha))
  1025. return QLA_SUCCESS;
  1026. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  1027. rval = qla2x00_mbx_reg_test(vha);
  1028. if (rval) {
  1029. ql_log(ql_log_warn, vha, 0x0082,
  1030. "Failed mailbox send register test.\n");
  1031. } else {
  1032. /* Flag a successful rval */
  1033. rval = QLA_SUCCESS;
  1034. }
  1035. return rval;
  1036. }
  1037. void
  1038. qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
  1039. {
  1040. int rval;
  1041. uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
  1042. eft_size, fce_size, mq_size;
  1043. dma_addr_t tc_dma;
  1044. void *tc;
  1045. struct qla_hw_data *ha = vha->hw;
  1046. struct req_que *req = ha->req_q_map[0];
  1047. struct rsp_que *rsp = ha->rsp_q_map[0];
  1048. if (ha->fw_dump) {
  1049. ql_dbg(ql_dbg_init, vha, 0x00bd,
  1050. "Firmware dump already allocated.\n");
  1051. return;
  1052. }
  1053. ha->fw_dumped = 0;
  1054. fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
  1055. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  1056. fixed_size = sizeof(struct qla2100_fw_dump);
  1057. } else if (IS_QLA23XX(ha)) {
  1058. fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
  1059. mem_size = (ha->fw_memory_size - 0x11000 + 1) *
  1060. sizeof(uint16_t);
  1061. } else if (IS_FWI2_CAPABLE(ha)) {
  1062. if (IS_QLA81XX(ha))
  1063. fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
  1064. else if (IS_QLA25XX(ha))
  1065. fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
  1066. else
  1067. fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
  1068. mem_size = (ha->fw_memory_size - 0x100000 + 1) *
  1069. sizeof(uint32_t);
  1070. if (ha->mqenable) {
  1071. mq_size = sizeof(struct qla2xxx_mq_chain);
  1072. /*
  1073. * Allocate maximum buffer size for all queues.
  1074. * Resizing must be done at end-of-dump processing.
  1075. */
  1076. mq_size += ha->max_req_queues *
  1077. (req->length * sizeof(request_t));
  1078. mq_size += ha->max_rsp_queues *
  1079. (rsp->length * sizeof(response_t));
  1080. }
  1081. /* Allocate memory for Fibre Channel Event Buffer. */
  1082. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))
  1083. goto try_eft;
  1084. tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
  1085. GFP_KERNEL);
  1086. if (!tc) {
  1087. ql_log(ql_log_warn, vha, 0x00be,
  1088. "Unable to allocate (%d KB) for FCE.\n",
  1089. FCE_SIZE / 1024);
  1090. goto try_eft;
  1091. }
  1092. memset(tc, 0, FCE_SIZE);
  1093. rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
  1094. ha->fce_mb, &ha->fce_bufs);
  1095. if (rval) {
  1096. ql_log(ql_log_warn, vha, 0x00bf,
  1097. "Unable to initialize FCE (%d).\n", rval);
  1098. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
  1099. tc_dma);
  1100. ha->flags.fce_enabled = 0;
  1101. goto try_eft;
  1102. }
  1103. ql_dbg(ql_dbg_init, vha, 0x00c0,
  1104. "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
  1105. fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
  1106. ha->flags.fce_enabled = 1;
  1107. ha->fce_dma = tc_dma;
  1108. ha->fce = tc;
  1109. try_eft:
  1110. /* Allocate memory for Extended Trace Buffer. */
  1111. tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
  1112. GFP_KERNEL);
  1113. if (!tc) {
  1114. ql_log(ql_log_warn, vha, 0x00c1,
  1115. "Unable to allocate (%d KB) for EFT.\n",
  1116. EFT_SIZE / 1024);
  1117. goto cont_alloc;
  1118. }
  1119. memset(tc, 0, EFT_SIZE);
  1120. rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
  1121. if (rval) {
  1122. ql_log(ql_log_warn, vha, 0x00c2,
  1123. "Unable to initialize EFT (%d).\n", rval);
  1124. dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
  1125. tc_dma);
  1126. goto cont_alloc;
  1127. }
  1128. ql_dbg(ql_dbg_init, vha, 0x00c3,
  1129. "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
  1130. eft_size = EFT_SIZE;
  1131. ha->eft_dma = tc_dma;
  1132. ha->eft = tc;
  1133. }
  1134. cont_alloc:
  1135. req_q_size = req->length * sizeof(request_t);
  1136. rsp_q_size = rsp->length * sizeof(response_t);
  1137. dump_size = offsetof(struct qla2xxx_fw_dump, isp);
  1138. dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
  1139. ha->chain_offset = dump_size;
  1140. dump_size += mq_size + fce_size;
  1141. ha->fw_dump = vmalloc(dump_size);
  1142. if (!ha->fw_dump) {
  1143. ql_log(ql_log_warn, vha, 0x00c4,
  1144. "Unable to allocate (%d KB) for firmware dump.\n",
  1145. dump_size / 1024);
  1146. if (ha->fce) {
  1147. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  1148. ha->fce_dma);
  1149. ha->fce = NULL;
  1150. ha->fce_dma = 0;
  1151. }
  1152. if (ha->eft) {
  1153. dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
  1154. ha->eft_dma);
  1155. ha->eft = NULL;
  1156. ha->eft_dma = 0;
  1157. }
  1158. return;
  1159. }
  1160. ql_dbg(ql_dbg_init, vha, 0x00c5,
  1161. "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
  1162. ha->fw_dump_len = dump_size;
  1163. ha->fw_dump->signature[0] = 'Q';
  1164. ha->fw_dump->signature[1] = 'L';
  1165. ha->fw_dump->signature[2] = 'G';
  1166. ha->fw_dump->signature[3] = 'C';
  1167. ha->fw_dump->version = __constant_htonl(1);
  1168. ha->fw_dump->fixed_size = htonl(fixed_size);
  1169. ha->fw_dump->mem_size = htonl(mem_size);
  1170. ha->fw_dump->req_q_size = htonl(req_q_size);
  1171. ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
  1172. ha->fw_dump->eft_size = htonl(eft_size);
  1173. ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
  1174. ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
  1175. ha->fw_dump->header_size =
  1176. htonl(offsetof(struct qla2xxx_fw_dump, isp));
  1177. }
  1178. static int
  1179. qla81xx_mpi_sync(scsi_qla_host_t *vha)
  1180. {
  1181. #define MPS_MASK 0xe0
  1182. int rval;
  1183. uint16_t dc;
  1184. uint32_t dw;
  1185. if (!IS_QLA81XX(vha->hw))
  1186. return QLA_SUCCESS;
  1187. rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
  1188. if (rval != QLA_SUCCESS) {
  1189. ql_log(ql_log_warn, vha, 0x0105,
  1190. "Unable to acquire semaphore.\n");
  1191. goto done;
  1192. }
  1193. pci_read_config_word(vha->hw->pdev, 0x54, &dc);
  1194. rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
  1195. if (rval != QLA_SUCCESS) {
  1196. ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
  1197. goto done_release;
  1198. }
  1199. dc &= MPS_MASK;
  1200. if (dc == (dw & MPS_MASK))
  1201. goto done_release;
  1202. dw &= ~MPS_MASK;
  1203. dw |= dc;
  1204. rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
  1205. if (rval != QLA_SUCCESS) {
  1206. ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
  1207. }
  1208. done_release:
  1209. rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
  1210. if (rval != QLA_SUCCESS) {
  1211. ql_log(ql_log_warn, vha, 0x006d,
  1212. "Unable to release semaphore.\n");
  1213. }
  1214. done:
  1215. return rval;
  1216. }
  1217. /**
  1218. * qla2x00_setup_chip() - Load and start RISC firmware.
  1219. * @ha: HA context
  1220. *
  1221. * Returns 0 on success.
  1222. */
  1223. static int
  1224. qla2x00_setup_chip(scsi_qla_host_t *vha)
  1225. {
  1226. int rval;
  1227. uint32_t srisc_address = 0;
  1228. struct qla_hw_data *ha = vha->hw;
  1229. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1230. unsigned long flags;
  1231. uint16_t fw_major_version;
  1232. if (IS_QLA82XX(ha)) {
  1233. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1234. if (rval == QLA_SUCCESS) {
  1235. qla2x00_stop_firmware(vha);
  1236. goto enable_82xx_npiv;
  1237. } else
  1238. goto failed;
  1239. }
  1240. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1241. /* Disable SRAM, Instruction RAM and GP RAM parity. */
  1242. spin_lock_irqsave(&ha->hardware_lock, flags);
  1243. WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
  1244. RD_REG_WORD(&reg->hccr);
  1245. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1246. }
  1247. qla81xx_mpi_sync(vha);
  1248. /* Load firmware sequences */
  1249. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1250. if (rval == QLA_SUCCESS) {
  1251. ql_dbg(ql_dbg_init, vha, 0x00c9,
  1252. "Verifying Checksum of loaded RISC code.\n");
  1253. rval = qla2x00_verify_checksum(vha, srisc_address);
  1254. if (rval == QLA_SUCCESS) {
  1255. /* Start firmware execution. */
  1256. ql_dbg(ql_dbg_init, vha, 0x00ca,
  1257. "Starting firmware.\n");
  1258. rval = qla2x00_execute_fw(vha, srisc_address);
  1259. /* Retrieve firmware information. */
  1260. if (rval == QLA_SUCCESS) {
  1261. enable_82xx_npiv:
  1262. fw_major_version = ha->fw_major_version;
  1263. if (IS_QLA82XX(ha))
  1264. qla82xx_check_md_needed(vha);
  1265. else {
  1266. rval = qla2x00_get_fw_version(vha,
  1267. &ha->fw_major_version,
  1268. &ha->fw_minor_version,
  1269. &ha->fw_subminor_version,
  1270. &ha->fw_attributes,
  1271. &ha->fw_memory_size,
  1272. ha->mpi_version,
  1273. &ha->mpi_capabilities,
  1274. ha->phy_version);
  1275. }
  1276. if (rval != QLA_SUCCESS)
  1277. goto failed;
  1278. ha->flags.npiv_supported = 0;
  1279. if (IS_QLA2XXX_MIDTYPE(ha) &&
  1280. (ha->fw_attributes & BIT_2)) {
  1281. ha->flags.npiv_supported = 1;
  1282. if ((!ha->max_npiv_vports) ||
  1283. ((ha->max_npiv_vports + 1) %
  1284. MIN_MULTI_ID_FABRIC))
  1285. ha->max_npiv_vports =
  1286. MIN_MULTI_ID_FABRIC - 1;
  1287. }
  1288. qla2x00_get_resource_cnts(vha, NULL,
  1289. &ha->fw_xcb_count, NULL, NULL,
  1290. &ha->max_npiv_vports, NULL);
  1291. if (!fw_major_version && ql2xallocfwdump
  1292. && !IS_QLA82XX(ha))
  1293. qla2x00_alloc_fw_dump(vha);
  1294. }
  1295. } else {
  1296. ql_log(ql_log_fatal, vha, 0x00cd,
  1297. "ISP Firmware failed checksum.\n");
  1298. goto failed;
  1299. }
  1300. }
  1301. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1302. /* Enable proper parity. */
  1303. spin_lock_irqsave(&ha->hardware_lock, flags);
  1304. if (IS_QLA2300(ha))
  1305. /* SRAM parity */
  1306. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
  1307. else
  1308. /* SRAM, Instruction RAM and GP RAM parity */
  1309. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
  1310. RD_REG_WORD(&reg->hccr);
  1311. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1312. }
  1313. if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
  1314. uint32_t size;
  1315. rval = qla81xx_fac_get_sector_size(vha, &size);
  1316. if (rval == QLA_SUCCESS) {
  1317. ha->flags.fac_supported = 1;
  1318. ha->fdt_block_size = size << 2;
  1319. } else {
  1320. ql_log(ql_log_warn, vha, 0x00ce,
  1321. "Unsupported FAC firmware (%d.%02d.%02d).\n",
  1322. ha->fw_major_version, ha->fw_minor_version,
  1323. ha->fw_subminor_version);
  1324. }
  1325. }
  1326. failed:
  1327. if (rval) {
  1328. ql_log(ql_log_fatal, vha, 0x00cf,
  1329. "Setup chip ****FAILED****.\n");
  1330. }
  1331. return (rval);
  1332. }
  1333. /**
  1334. * qla2x00_init_response_q_entries() - Initializes response queue entries.
  1335. * @ha: HA context
  1336. *
  1337. * Beginning of request ring has initialization control block already built
  1338. * by nvram config routine.
  1339. *
  1340. * Returns 0 on success.
  1341. */
  1342. void
  1343. qla2x00_init_response_q_entries(struct rsp_que *rsp)
  1344. {
  1345. uint16_t cnt;
  1346. response_t *pkt;
  1347. rsp->ring_ptr = rsp->ring;
  1348. rsp->ring_index = 0;
  1349. rsp->status_srb = NULL;
  1350. pkt = rsp->ring_ptr;
  1351. for (cnt = 0; cnt < rsp->length; cnt++) {
  1352. pkt->signature = RESPONSE_PROCESSED;
  1353. pkt++;
  1354. }
  1355. }
  1356. /**
  1357. * qla2x00_update_fw_options() - Read and process firmware options.
  1358. * @ha: HA context
  1359. *
  1360. * Returns 0 on success.
  1361. */
  1362. void
  1363. qla2x00_update_fw_options(scsi_qla_host_t *vha)
  1364. {
  1365. uint16_t swing, emphasis, tx_sens, rx_sens;
  1366. struct qla_hw_data *ha = vha->hw;
  1367. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  1368. qla2x00_get_fw_options(vha, ha->fw_options);
  1369. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  1370. return;
  1371. /* Serial Link options. */
  1372. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
  1373. "Serial link options.\n");
  1374. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
  1375. (uint8_t *)&ha->fw_seriallink_options,
  1376. sizeof(ha->fw_seriallink_options));
  1377. ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
  1378. if (ha->fw_seriallink_options[3] & BIT_2) {
  1379. ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
  1380. /* 1G settings */
  1381. swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
  1382. emphasis = (ha->fw_seriallink_options[2] &
  1383. (BIT_4 | BIT_3)) >> 3;
  1384. tx_sens = ha->fw_seriallink_options[0] &
  1385. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1386. rx_sens = (ha->fw_seriallink_options[0] &
  1387. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1388. ha->fw_options[10] = (emphasis << 14) | (swing << 8);
  1389. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1390. if (rx_sens == 0x0)
  1391. rx_sens = 0x3;
  1392. ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
  1393. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1394. ha->fw_options[10] |= BIT_5 |
  1395. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1396. (tx_sens & (BIT_1 | BIT_0));
  1397. /* 2G settings */
  1398. swing = (ha->fw_seriallink_options[2] &
  1399. (BIT_7 | BIT_6 | BIT_5)) >> 5;
  1400. emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
  1401. tx_sens = ha->fw_seriallink_options[1] &
  1402. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1403. rx_sens = (ha->fw_seriallink_options[1] &
  1404. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1405. ha->fw_options[11] = (emphasis << 14) | (swing << 8);
  1406. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1407. if (rx_sens == 0x0)
  1408. rx_sens = 0x3;
  1409. ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
  1410. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1411. ha->fw_options[11] |= BIT_5 |
  1412. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1413. (tx_sens & (BIT_1 | BIT_0));
  1414. }
  1415. /* FCP2 options. */
  1416. /* Return command IOCBs without waiting for an ABTS to complete. */
  1417. ha->fw_options[3] |= BIT_13;
  1418. /* LED scheme. */
  1419. if (ha->flags.enable_led_scheme)
  1420. ha->fw_options[2] |= BIT_12;
  1421. /* Detect ISP6312. */
  1422. if (IS_QLA6312(ha))
  1423. ha->fw_options[2] |= BIT_13;
  1424. /* Update firmware options. */
  1425. qla2x00_set_fw_options(vha, ha->fw_options);
  1426. }
  1427. void
  1428. qla24xx_update_fw_options(scsi_qla_host_t *vha)
  1429. {
  1430. int rval;
  1431. struct qla_hw_data *ha = vha->hw;
  1432. if (IS_QLA82XX(ha))
  1433. return;
  1434. /* Update Serial Link options. */
  1435. if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
  1436. return;
  1437. rval = qla2x00_set_serdes_params(vha,
  1438. le16_to_cpu(ha->fw_seriallink_options24[1]),
  1439. le16_to_cpu(ha->fw_seriallink_options24[2]),
  1440. le16_to_cpu(ha->fw_seriallink_options24[3]));
  1441. if (rval != QLA_SUCCESS) {
  1442. ql_log(ql_log_warn, vha, 0x0104,
  1443. "Unable to update Serial Link options (%x).\n", rval);
  1444. }
  1445. }
  1446. void
  1447. qla2x00_config_rings(struct scsi_qla_host *vha)
  1448. {
  1449. struct qla_hw_data *ha = vha->hw;
  1450. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1451. struct req_que *req = ha->req_q_map[0];
  1452. struct rsp_que *rsp = ha->rsp_q_map[0];
  1453. /* Setup ring parameters in initialization control block. */
  1454. ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
  1455. ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
  1456. ha->init_cb->request_q_length = cpu_to_le16(req->length);
  1457. ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
  1458. ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1459. ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1460. ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1461. ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1462. WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
  1463. WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
  1464. WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
  1465. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
  1466. RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
  1467. }
  1468. void
  1469. qla24xx_config_rings(struct scsi_qla_host *vha)
  1470. {
  1471. struct qla_hw_data *ha = vha->hw;
  1472. device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
  1473. struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
  1474. struct qla_msix_entry *msix;
  1475. struct init_cb_24xx *icb;
  1476. uint16_t rid = 0;
  1477. struct req_que *req = ha->req_q_map[0];
  1478. struct rsp_que *rsp = ha->rsp_q_map[0];
  1479. /* Setup ring parameters in initialization control block. */
  1480. icb = (struct init_cb_24xx *)ha->init_cb;
  1481. icb->request_q_outpointer = __constant_cpu_to_le16(0);
  1482. icb->response_q_inpointer = __constant_cpu_to_le16(0);
  1483. icb->request_q_length = cpu_to_le16(req->length);
  1484. icb->response_q_length = cpu_to_le16(rsp->length);
  1485. icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1486. icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1487. icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1488. icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1489. if (ha->mqenable) {
  1490. icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
  1491. icb->rid = __constant_cpu_to_le16(rid);
  1492. if (ha->flags.msix_enabled) {
  1493. msix = &ha->msix_entries[1];
  1494. ql_dbg(ql_dbg_init, vha, 0x00fd,
  1495. "Registering vector 0x%x for base que.\n",
  1496. msix->entry);
  1497. icb->msix = cpu_to_le16(msix->entry);
  1498. }
  1499. /* Use alternate PCI bus number */
  1500. if (MSB(rid))
  1501. icb->firmware_options_2 |=
  1502. __constant_cpu_to_le32(BIT_19);
  1503. /* Use alternate PCI devfn */
  1504. if (LSB(rid))
  1505. icb->firmware_options_2 |=
  1506. __constant_cpu_to_le32(BIT_18);
  1507. /* Use Disable MSIX Handshake mode for capable adapters */
  1508. if (IS_MSIX_NACK_CAPABLE(ha)) {
  1509. icb->firmware_options_2 &=
  1510. __constant_cpu_to_le32(~BIT_22);
  1511. ha->flags.disable_msix_handshake = 1;
  1512. ql_dbg(ql_dbg_init, vha, 0x00fe,
  1513. "MSIX Handshake Disable Mode turned on.\n");
  1514. } else {
  1515. icb->firmware_options_2 |=
  1516. __constant_cpu_to_le32(BIT_22);
  1517. }
  1518. icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
  1519. WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
  1520. WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
  1521. WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
  1522. WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
  1523. } else {
  1524. WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
  1525. WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
  1526. WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
  1527. WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
  1528. }
  1529. /* PCI posting */
  1530. RD_REG_DWORD(&ioreg->hccr);
  1531. }
  1532. /**
  1533. * qla2x00_init_rings() - Initializes firmware.
  1534. * @ha: HA context
  1535. *
  1536. * Beginning of request ring has initialization control block already built
  1537. * by nvram config routine.
  1538. *
  1539. * Returns 0 on success.
  1540. */
  1541. static int
  1542. qla2x00_init_rings(scsi_qla_host_t *vha)
  1543. {
  1544. int rval;
  1545. unsigned long flags = 0;
  1546. int cnt, que;
  1547. struct qla_hw_data *ha = vha->hw;
  1548. struct req_que *req;
  1549. struct rsp_que *rsp;
  1550. struct scsi_qla_host *vp;
  1551. struct mid_init_cb_24xx *mid_init_cb =
  1552. (struct mid_init_cb_24xx *) ha->init_cb;
  1553. spin_lock_irqsave(&ha->hardware_lock, flags);
  1554. /* Clear outstanding commands array. */
  1555. for (que = 0; que < ha->max_req_queues; que++) {
  1556. req = ha->req_q_map[que];
  1557. if (!req)
  1558. continue;
  1559. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++)
  1560. req->outstanding_cmds[cnt] = NULL;
  1561. req->current_outstanding_cmd = 1;
  1562. /* Initialize firmware. */
  1563. req->ring_ptr = req->ring;
  1564. req->ring_index = 0;
  1565. req->cnt = req->length;
  1566. }
  1567. for (que = 0; que < ha->max_rsp_queues; que++) {
  1568. rsp = ha->rsp_q_map[que];
  1569. if (!rsp)
  1570. continue;
  1571. /* Initialize response queue entries */
  1572. qla2x00_init_response_q_entries(rsp);
  1573. }
  1574. spin_lock(&ha->vport_slock);
  1575. /* Clear RSCN queue. */
  1576. list_for_each_entry(vp, &ha->vp_list, list) {
  1577. vp->rscn_in_ptr = 0;
  1578. vp->rscn_out_ptr = 0;
  1579. }
  1580. spin_unlock(&ha->vport_slock);
  1581. ha->isp_ops->config_rings(vha);
  1582. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1583. /* Update any ISP specific firmware options before initialization. */
  1584. ha->isp_ops->update_fw_options(vha);
  1585. ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
  1586. if (ha->flags.npiv_supported) {
  1587. if (ha->operating_mode == LOOP)
  1588. ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
  1589. mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
  1590. }
  1591. if (IS_FWI2_CAPABLE(ha)) {
  1592. mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
  1593. mid_init_cb->init_cb.execution_throttle =
  1594. cpu_to_le16(ha->fw_xcb_count);
  1595. }
  1596. rval = qla2x00_init_firmware(vha, ha->init_cb_size);
  1597. if (rval) {
  1598. ql_log(ql_log_fatal, vha, 0x00d2,
  1599. "Init Firmware **** FAILED ****.\n");
  1600. } else {
  1601. ql_dbg(ql_dbg_init, vha, 0x00d3,
  1602. "Init Firmware -- success.\n");
  1603. }
  1604. return (rval);
  1605. }
  1606. /**
  1607. * qla2x00_fw_ready() - Waits for firmware ready.
  1608. * @ha: HA context
  1609. *
  1610. * Returns 0 on success.
  1611. */
  1612. static int
  1613. qla2x00_fw_ready(scsi_qla_host_t *vha)
  1614. {
  1615. int rval;
  1616. unsigned long wtime, mtime, cs84xx_time;
  1617. uint16_t min_wait; /* Minimum wait time if loop is down */
  1618. uint16_t wait_time; /* Wait time if loop is coming ready */
  1619. uint16_t state[5];
  1620. struct qla_hw_data *ha = vha->hw;
  1621. rval = QLA_SUCCESS;
  1622. /* 20 seconds for loop down. */
  1623. min_wait = 20;
  1624. /*
  1625. * Firmware should take at most one RATOV to login, plus 5 seconds for
  1626. * our own processing.
  1627. */
  1628. if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
  1629. wait_time = min_wait;
  1630. }
  1631. /* Min wait time if loop down */
  1632. mtime = jiffies + (min_wait * HZ);
  1633. /* wait time before firmware ready */
  1634. wtime = jiffies + (wait_time * HZ);
  1635. /* Wait for ISP to finish LIP */
  1636. if (!vha->flags.init_done)
  1637. ql_log(ql_log_info, vha, 0x801e,
  1638. "Waiting for LIP to complete.\n");
  1639. do {
  1640. rval = qla2x00_get_firmware_state(vha, state);
  1641. if (rval == QLA_SUCCESS) {
  1642. if (state[0] < FSTATE_LOSS_OF_SYNC) {
  1643. vha->device_flags &= ~DFLG_NO_CABLE;
  1644. }
  1645. if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
  1646. ql_dbg(ql_dbg_taskm, vha, 0x801f,
  1647. "fw_state=%x 84xx=%x.\n", state[0],
  1648. state[2]);
  1649. if ((state[2] & FSTATE_LOGGED_IN) &&
  1650. (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
  1651. ql_dbg(ql_dbg_taskm, vha, 0x8028,
  1652. "Sending verify iocb.\n");
  1653. cs84xx_time = jiffies;
  1654. rval = qla84xx_init_chip(vha);
  1655. if (rval != QLA_SUCCESS) {
  1656. ql_log(ql_log_warn,
  1657. vha, 0x8007,
  1658. "Init chip failed.\n");
  1659. break;
  1660. }
  1661. /* Add time taken to initialize. */
  1662. cs84xx_time = jiffies - cs84xx_time;
  1663. wtime += cs84xx_time;
  1664. mtime += cs84xx_time;
  1665. ql_dbg(ql_dbg_taskm, vha, 0x8008,
  1666. "Increasing wait time by %ld. "
  1667. "New time %ld.\n", cs84xx_time,
  1668. wtime);
  1669. }
  1670. } else if (state[0] == FSTATE_READY) {
  1671. ql_dbg(ql_dbg_taskm, vha, 0x8037,
  1672. "F/W Ready - OK.\n");
  1673. qla2x00_get_retry_cnt(vha, &ha->retry_count,
  1674. &ha->login_timeout, &ha->r_a_tov);
  1675. rval = QLA_SUCCESS;
  1676. break;
  1677. }
  1678. rval = QLA_FUNCTION_FAILED;
  1679. if (atomic_read(&vha->loop_down_timer) &&
  1680. state[0] != FSTATE_READY) {
  1681. /* Loop down. Timeout on min_wait for states
  1682. * other than Wait for Login.
  1683. */
  1684. if (time_after_eq(jiffies, mtime)) {
  1685. ql_log(ql_log_info, vha, 0x8038,
  1686. "Cable is unplugged...\n");
  1687. vha->device_flags |= DFLG_NO_CABLE;
  1688. break;
  1689. }
  1690. }
  1691. } else {
  1692. /* Mailbox cmd failed. Timeout on min_wait. */
  1693. if (time_after_eq(jiffies, mtime) ||
  1694. ha->flags.isp82xx_fw_hung)
  1695. break;
  1696. }
  1697. if (time_after_eq(jiffies, wtime))
  1698. break;
  1699. /* Delay for a while */
  1700. msleep(500);
  1701. } while (1);
  1702. ql_dbg(ql_dbg_taskm, vha, 0x803a,
  1703. "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
  1704. state[1], state[2], state[3], state[4], jiffies);
  1705. if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
  1706. ql_log(ql_log_warn, vha, 0x803b,
  1707. "Firmware ready **** FAILED ****.\n");
  1708. }
  1709. return (rval);
  1710. }
  1711. /*
  1712. * qla2x00_configure_hba
  1713. * Setup adapter context.
  1714. *
  1715. * Input:
  1716. * ha = adapter state pointer.
  1717. *
  1718. * Returns:
  1719. * 0 = success
  1720. *
  1721. * Context:
  1722. * Kernel context.
  1723. */
  1724. static int
  1725. qla2x00_configure_hba(scsi_qla_host_t *vha)
  1726. {
  1727. int rval;
  1728. uint16_t loop_id;
  1729. uint16_t topo;
  1730. uint16_t sw_cap;
  1731. uint8_t al_pa;
  1732. uint8_t area;
  1733. uint8_t domain;
  1734. char connect_type[22];
  1735. struct qla_hw_data *ha = vha->hw;
  1736. /* Get host addresses. */
  1737. rval = qla2x00_get_adapter_id(vha,
  1738. &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
  1739. if (rval != QLA_SUCCESS) {
  1740. if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
  1741. IS_QLA8XXX_TYPE(ha) ||
  1742. (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
  1743. ql_dbg(ql_dbg_disc, vha, 0x2008,
  1744. "Loop is in a transition state.\n");
  1745. } else {
  1746. ql_log(ql_log_warn, vha, 0x2009,
  1747. "Unable to get host loop ID.\n");
  1748. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1749. }
  1750. return (rval);
  1751. }
  1752. if (topo == 4) {
  1753. ql_log(ql_log_info, vha, 0x200a,
  1754. "Cannot get topology - retrying.\n");
  1755. return (QLA_FUNCTION_FAILED);
  1756. }
  1757. vha->loop_id = loop_id;
  1758. /* initialize */
  1759. ha->min_external_loopid = SNS_FIRST_LOOP_ID;
  1760. ha->operating_mode = LOOP;
  1761. ha->switch_cap = 0;
  1762. switch (topo) {
  1763. case 0:
  1764. ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
  1765. ha->current_topology = ISP_CFG_NL;
  1766. strcpy(connect_type, "(Loop)");
  1767. break;
  1768. case 1:
  1769. ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
  1770. ha->switch_cap = sw_cap;
  1771. ha->current_topology = ISP_CFG_FL;
  1772. strcpy(connect_type, "(FL_Port)");
  1773. break;
  1774. case 2:
  1775. ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
  1776. ha->operating_mode = P2P;
  1777. ha->current_topology = ISP_CFG_N;
  1778. strcpy(connect_type, "(N_Port-to-N_Port)");
  1779. break;
  1780. case 3:
  1781. ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
  1782. ha->switch_cap = sw_cap;
  1783. ha->operating_mode = P2P;
  1784. ha->current_topology = ISP_CFG_F;
  1785. strcpy(connect_type, "(F_Port)");
  1786. break;
  1787. default:
  1788. ql_dbg(ql_dbg_disc, vha, 0x200f,
  1789. "HBA in unknown topology %x, using NL.\n", topo);
  1790. ha->current_topology = ISP_CFG_NL;
  1791. strcpy(connect_type, "(Loop)");
  1792. break;
  1793. }
  1794. /* Save Host port and loop ID. */
  1795. /* byte order - Big Endian */
  1796. vha->d_id.b.domain = domain;
  1797. vha->d_id.b.area = area;
  1798. vha->d_id.b.al_pa = al_pa;
  1799. if (!vha->flags.init_done)
  1800. ql_log(ql_log_info, vha, 0x2010,
  1801. "Topology - %s, Host Loop address 0x%x.\n",
  1802. connect_type, vha->loop_id);
  1803. if (rval) {
  1804. ql_log(ql_log_warn, vha, 0x2011,
  1805. "%s FAILED\n", __func__);
  1806. } else {
  1807. ql_dbg(ql_dbg_disc, vha, 0x2012,
  1808. "%s success\n", __func__);
  1809. }
  1810. return(rval);
  1811. }
  1812. inline void
  1813. qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
  1814. char *def)
  1815. {
  1816. char *st, *en;
  1817. uint16_t index;
  1818. struct qla_hw_data *ha = vha->hw;
  1819. int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
  1820. !IS_QLA8XXX_TYPE(ha);
  1821. if (memcmp(model, BINZERO, len) != 0) {
  1822. strncpy(ha->model_number, model, len);
  1823. st = en = ha->model_number;
  1824. en += len - 1;
  1825. while (en > st) {
  1826. if (*en != 0x20 && *en != 0x00)
  1827. break;
  1828. *en-- = '\0';
  1829. }
  1830. index = (ha->pdev->subsystem_device & 0xff);
  1831. if (use_tbl &&
  1832. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1833. index < QLA_MODEL_NAMES)
  1834. strncpy(ha->model_desc,
  1835. qla2x00_model_name[index * 2 + 1],
  1836. sizeof(ha->model_desc) - 1);
  1837. } else {
  1838. index = (ha->pdev->subsystem_device & 0xff);
  1839. if (use_tbl &&
  1840. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1841. index < QLA_MODEL_NAMES) {
  1842. strcpy(ha->model_number,
  1843. qla2x00_model_name[index * 2]);
  1844. strncpy(ha->model_desc,
  1845. qla2x00_model_name[index * 2 + 1],
  1846. sizeof(ha->model_desc) - 1);
  1847. } else {
  1848. strcpy(ha->model_number, def);
  1849. }
  1850. }
  1851. if (IS_FWI2_CAPABLE(ha))
  1852. qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
  1853. sizeof(ha->model_desc));
  1854. }
  1855. /* On sparc systems, obtain port and node WWN from firmware
  1856. * properties.
  1857. */
  1858. static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
  1859. {
  1860. #ifdef CONFIG_SPARC
  1861. struct qla_hw_data *ha = vha->hw;
  1862. struct pci_dev *pdev = ha->pdev;
  1863. struct device_node *dp = pci_device_to_OF_node(pdev);
  1864. const u8 *val;
  1865. int len;
  1866. val = of_get_property(dp, "port-wwn", &len);
  1867. if (val && len >= WWN_SIZE)
  1868. memcpy(nv->port_name, val, WWN_SIZE);
  1869. val = of_get_property(dp, "node-wwn", &len);
  1870. if (val && len >= WWN_SIZE)
  1871. memcpy(nv->node_name, val, WWN_SIZE);
  1872. #endif
  1873. }
  1874. /*
  1875. * NVRAM configuration for ISP 2xxx
  1876. *
  1877. * Input:
  1878. * ha = adapter block pointer.
  1879. *
  1880. * Output:
  1881. * initialization control block in response_ring
  1882. * host adapters parameters in host adapter block
  1883. *
  1884. * Returns:
  1885. * 0 = success.
  1886. */
  1887. int
  1888. qla2x00_nvram_config(scsi_qla_host_t *vha)
  1889. {
  1890. int rval;
  1891. uint8_t chksum = 0;
  1892. uint16_t cnt;
  1893. uint8_t *dptr1, *dptr2;
  1894. struct qla_hw_data *ha = vha->hw;
  1895. init_cb_t *icb = ha->init_cb;
  1896. nvram_t *nv = ha->nvram;
  1897. uint8_t *ptr = ha->nvram;
  1898. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1899. rval = QLA_SUCCESS;
  1900. /* Determine NVRAM starting address. */
  1901. ha->nvram_size = sizeof(nvram_t);
  1902. ha->nvram_base = 0;
  1903. if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
  1904. if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
  1905. ha->nvram_base = 0x80;
  1906. /* Get NVRAM data and calculate checksum. */
  1907. ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
  1908. for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
  1909. chksum += *ptr++;
  1910. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
  1911. "Contents of NVRAM.\n");
  1912. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
  1913. (uint8_t *)nv, ha->nvram_size);
  1914. /* Bad NVRAM data, set defaults parameters. */
  1915. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
  1916. nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
  1917. /* Reset NVRAM data. */
  1918. ql_log(ql_log_warn, vha, 0x0064,
  1919. "Inconisistent NVRAM "
  1920. "detected: checksum=0x%x id=%c version=0x%x.\n",
  1921. chksum, nv->id[0], nv->nvram_version);
  1922. ql_log(ql_log_warn, vha, 0x0065,
  1923. "Falling back to "
  1924. "functioning (yet invalid -- WWPN) defaults.\n");
  1925. /*
  1926. * Set default initialization control block.
  1927. */
  1928. memset(nv, 0, ha->nvram_size);
  1929. nv->parameter_block_version = ICB_VERSION;
  1930. if (IS_QLA23XX(ha)) {
  1931. nv->firmware_options[0] = BIT_2 | BIT_1;
  1932. nv->firmware_options[1] = BIT_7 | BIT_5;
  1933. nv->add_firmware_options[0] = BIT_5;
  1934. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1935. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1936. nv->special_options[1] = BIT_7;
  1937. } else if (IS_QLA2200(ha)) {
  1938. nv->firmware_options[0] = BIT_2 | BIT_1;
  1939. nv->firmware_options[1] = BIT_7 | BIT_5;
  1940. nv->add_firmware_options[0] = BIT_5;
  1941. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1942. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1943. } else if (IS_QLA2100(ha)) {
  1944. nv->firmware_options[0] = BIT_3 | BIT_1;
  1945. nv->firmware_options[1] = BIT_5;
  1946. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1947. }
  1948. nv->max_iocb_allocation = __constant_cpu_to_le16(256);
  1949. nv->execution_throttle = __constant_cpu_to_le16(16);
  1950. nv->retry_count = 8;
  1951. nv->retry_delay = 1;
  1952. nv->port_name[0] = 33;
  1953. nv->port_name[3] = 224;
  1954. nv->port_name[4] = 139;
  1955. qla2xxx_nvram_wwn_from_ofw(vha, nv);
  1956. nv->login_timeout = 4;
  1957. /*
  1958. * Set default host adapter parameters
  1959. */
  1960. nv->host_p[1] = BIT_2;
  1961. nv->reset_delay = 5;
  1962. nv->port_down_retry_count = 8;
  1963. nv->max_luns_per_target = __constant_cpu_to_le16(8);
  1964. nv->link_down_timeout = 60;
  1965. rval = 1;
  1966. }
  1967. #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
  1968. /*
  1969. * The SN2 does not provide BIOS emulation which means you can't change
  1970. * potentially bogus BIOS settings. Force the use of default settings
  1971. * for link rate and frame size. Hope that the rest of the settings
  1972. * are valid.
  1973. */
  1974. if (ia64_platform_is("sn2")) {
  1975. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1976. if (IS_QLA23XX(ha))
  1977. nv->special_options[1] = BIT_7;
  1978. }
  1979. #endif
  1980. /* Reset Initialization control block */
  1981. memset(icb, 0, ha->init_cb_size);
  1982. /*
  1983. * Setup driver NVRAM options.
  1984. */
  1985. nv->firmware_options[0] |= (BIT_6 | BIT_1);
  1986. nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
  1987. nv->firmware_options[1] |= (BIT_5 | BIT_0);
  1988. nv->firmware_options[1] &= ~BIT_4;
  1989. if (IS_QLA23XX(ha)) {
  1990. nv->firmware_options[0] |= BIT_2;
  1991. nv->firmware_options[0] &= ~BIT_3;
  1992. nv->firmware_options[0] &= ~BIT_6;
  1993. nv->add_firmware_options[1] |= BIT_5 | BIT_4;
  1994. if (IS_QLA2300(ha)) {
  1995. if (ha->fb_rev == FPM_2310) {
  1996. strcpy(ha->model_number, "QLA2310");
  1997. } else {
  1998. strcpy(ha->model_number, "QLA2300");
  1999. }
  2000. } else {
  2001. qla2x00_set_model_info(vha, nv->model_number,
  2002. sizeof(nv->model_number), "QLA23xx");
  2003. }
  2004. } else if (IS_QLA2200(ha)) {
  2005. nv->firmware_options[0] |= BIT_2;
  2006. /*
  2007. * 'Point-to-point preferred, else loop' is not a safe
  2008. * connection mode setting.
  2009. */
  2010. if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
  2011. (BIT_5 | BIT_4)) {
  2012. /* Force 'loop preferred, else point-to-point'. */
  2013. nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
  2014. nv->add_firmware_options[0] |= BIT_5;
  2015. }
  2016. strcpy(ha->model_number, "QLA22xx");
  2017. } else /*if (IS_QLA2100(ha))*/ {
  2018. strcpy(ha->model_number, "QLA2100");
  2019. }
  2020. /*
  2021. * Copy over NVRAM RISC parameter block to initialization control block.
  2022. */
  2023. dptr1 = (uint8_t *)icb;
  2024. dptr2 = (uint8_t *)&nv->parameter_block_version;
  2025. cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
  2026. while (cnt--)
  2027. *dptr1++ = *dptr2++;
  2028. /* Copy 2nd half. */
  2029. dptr1 = (uint8_t *)icb->add_firmware_options;
  2030. cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
  2031. while (cnt--)
  2032. *dptr1++ = *dptr2++;
  2033. /* Use alternate WWN? */
  2034. if (nv->host_p[1] & BIT_7) {
  2035. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  2036. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  2037. }
  2038. /* Prepare nodename */
  2039. if ((icb->firmware_options[1] & BIT_6) == 0) {
  2040. /*
  2041. * Firmware will apply the following mask if the nodename was
  2042. * not provided.
  2043. */
  2044. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  2045. icb->node_name[0] &= 0xF0;
  2046. }
  2047. /*
  2048. * Set host adapter parameters.
  2049. */
  2050. /*
  2051. * BIT_7 in the host-parameters section allows for modification to
  2052. * internal driver logging.
  2053. */
  2054. if (nv->host_p[0] & BIT_7)
  2055. ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
  2056. ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
  2057. /* Always load RISC code on non ISP2[12]00 chips. */
  2058. if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
  2059. ha->flags.disable_risc_code_load = 0;
  2060. ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
  2061. ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
  2062. ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
  2063. ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
  2064. ha->flags.disable_serdes = 0;
  2065. ha->operating_mode =
  2066. (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
  2067. memcpy(ha->fw_seriallink_options, nv->seriallink_options,
  2068. sizeof(ha->fw_seriallink_options));
  2069. /* save HBA serial number */
  2070. ha->serial0 = icb->port_name[5];
  2071. ha->serial1 = icb->port_name[6];
  2072. ha->serial2 = icb->port_name[7];
  2073. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  2074. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  2075. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  2076. ha->retry_count = nv->retry_count;
  2077. /* Set minimum login_timeout to 4 seconds. */
  2078. if (nv->login_timeout != ql2xlogintimeout)
  2079. nv->login_timeout = ql2xlogintimeout;
  2080. if (nv->login_timeout < 4)
  2081. nv->login_timeout = 4;
  2082. ha->login_timeout = nv->login_timeout;
  2083. icb->login_timeout = nv->login_timeout;
  2084. /* Set minimum RATOV to 100 tenths of a second. */
  2085. ha->r_a_tov = 100;
  2086. ha->loop_reset_delay = nv->reset_delay;
  2087. /* Link Down Timeout = 0:
  2088. *
  2089. * When Port Down timer expires we will start returning
  2090. * I/O's to OS with "DID_NO_CONNECT".
  2091. *
  2092. * Link Down Timeout != 0:
  2093. *
  2094. * The driver waits for the link to come up after link down
  2095. * before returning I/Os to OS with "DID_NO_CONNECT".
  2096. */
  2097. if (nv->link_down_timeout == 0) {
  2098. ha->loop_down_abort_time =
  2099. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  2100. } else {
  2101. ha->link_down_timeout = nv->link_down_timeout;
  2102. ha->loop_down_abort_time =
  2103. (LOOP_DOWN_TIME - ha->link_down_timeout);
  2104. }
  2105. /*
  2106. * Need enough time to try and get the port back.
  2107. */
  2108. ha->port_down_retry_count = nv->port_down_retry_count;
  2109. if (qlport_down_retry)
  2110. ha->port_down_retry_count = qlport_down_retry;
  2111. /* Set login_retry_count */
  2112. ha->login_retry_count = nv->retry_count;
  2113. if (ha->port_down_retry_count == nv->port_down_retry_count &&
  2114. ha->port_down_retry_count > 3)
  2115. ha->login_retry_count = ha->port_down_retry_count;
  2116. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  2117. ha->login_retry_count = ha->port_down_retry_count;
  2118. if (ql2xloginretrycount)
  2119. ha->login_retry_count = ql2xloginretrycount;
  2120. icb->lun_enables = __constant_cpu_to_le16(0);
  2121. icb->command_resource_count = 0;
  2122. icb->immediate_notify_resource_count = 0;
  2123. icb->timeout = __constant_cpu_to_le16(0);
  2124. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2125. /* Enable RIO */
  2126. icb->firmware_options[0] &= ~BIT_3;
  2127. icb->add_firmware_options[0] &=
  2128. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2129. icb->add_firmware_options[0] |= BIT_2;
  2130. icb->response_accumulation_timer = 3;
  2131. icb->interrupt_delay_timer = 5;
  2132. vha->flags.process_response_queue = 1;
  2133. } else {
  2134. /* Enable ZIO. */
  2135. if (!vha->flags.init_done) {
  2136. ha->zio_mode = icb->add_firmware_options[0] &
  2137. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2138. ha->zio_timer = icb->interrupt_delay_timer ?
  2139. icb->interrupt_delay_timer: 2;
  2140. }
  2141. icb->add_firmware_options[0] &=
  2142. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2143. vha->flags.process_response_queue = 0;
  2144. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  2145. ha->zio_mode = QLA_ZIO_MODE_6;
  2146. ql_log(ql_log_info, vha, 0x0068,
  2147. "ZIO mode %d enabled; timer delay (%d us).\n",
  2148. ha->zio_mode, ha->zio_timer * 100);
  2149. icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
  2150. icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
  2151. vha->flags.process_response_queue = 1;
  2152. }
  2153. }
  2154. if (rval) {
  2155. ql_log(ql_log_warn, vha, 0x0069,
  2156. "NVRAM configuration failed.\n");
  2157. }
  2158. return (rval);
  2159. }
  2160. static void
  2161. qla2x00_rport_del(void *data)
  2162. {
  2163. fc_port_t *fcport = data;
  2164. struct fc_rport *rport;
  2165. unsigned long flags;
  2166. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2167. rport = fcport->drport ? fcport->drport: fcport->rport;
  2168. fcport->drport = NULL;
  2169. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2170. if (rport)
  2171. fc_remote_port_delete(rport);
  2172. }
  2173. /**
  2174. * qla2x00_alloc_fcport() - Allocate a generic fcport.
  2175. * @ha: HA context
  2176. * @flags: allocation flags
  2177. *
  2178. * Returns a pointer to the allocated fcport, or NULL, if none available.
  2179. */
  2180. fc_port_t *
  2181. qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
  2182. {
  2183. fc_port_t *fcport;
  2184. fcport = kzalloc(sizeof(fc_port_t), flags);
  2185. if (!fcport)
  2186. return NULL;
  2187. /* Setup fcport template structure. */
  2188. fcport->vha = vha;
  2189. fcport->vp_idx = vha->vp_idx;
  2190. fcport->port_type = FCT_UNKNOWN;
  2191. fcport->loop_id = FC_NO_LOOP_ID;
  2192. qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
  2193. fcport->supported_classes = FC_COS_UNSPECIFIED;
  2194. return fcport;
  2195. }
  2196. /*
  2197. * qla2x00_configure_loop
  2198. * Updates Fibre Channel Device Database with what is actually on loop.
  2199. *
  2200. * Input:
  2201. * ha = adapter block pointer.
  2202. *
  2203. * Returns:
  2204. * 0 = success.
  2205. * 1 = error.
  2206. * 2 = database was full and device was not configured.
  2207. */
  2208. static int
  2209. qla2x00_configure_loop(scsi_qla_host_t *vha)
  2210. {
  2211. int rval;
  2212. unsigned long flags, save_flags;
  2213. struct qla_hw_data *ha = vha->hw;
  2214. rval = QLA_SUCCESS;
  2215. /* Get Initiator ID */
  2216. if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
  2217. rval = qla2x00_configure_hba(vha);
  2218. if (rval != QLA_SUCCESS) {
  2219. ql_dbg(ql_dbg_disc, vha, 0x2013,
  2220. "Unable to configure HBA.\n");
  2221. return (rval);
  2222. }
  2223. }
  2224. save_flags = flags = vha->dpc_flags;
  2225. ql_dbg(ql_dbg_disc, vha, 0x2014,
  2226. "Configure loop -- dpc flags = 0x%lx.\n", flags);
  2227. /*
  2228. * If we have both an RSCN and PORT UPDATE pending then handle them
  2229. * both at the same time.
  2230. */
  2231. clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2232. clear_bit(RSCN_UPDATE, &vha->dpc_flags);
  2233. qla2x00_get_data_rate(vha);
  2234. /* Determine what we need to do */
  2235. if (ha->current_topology == ISP_CFG_FL &&
  2236. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2237. vha->flags.rscn_queue_overflow = 1;
  2238. set_bit(RSCN_UPDATE, &flags);
  2239. } else if (ha->current_topology == ISP_CFG_F &&
  2240. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2241. vha->flags.rscn_queue_overflow = 1;
  2242. set_bit(RSCN_UPDATE, &flags);
  2243. clear_bit(LOCAL_LOOP_UPDATE, &flags);
  2244. } else if (ha->current_topology == ISP_CFG_N) {
  2245. clear_bit(RSCN_UPDATE, &flags);
  2246. } else if (!vha->flags.online ||
  2247. (test_bit(ABORT_ISP_ACTIVE, &flags))) {
  2248. vha->flags.rscn_queue_overflow = 1;
  2249. set_bit(RSCN_UPDATE, &flags);
  2250. set_bit(LOCAL_LOOP_UPDATE, &flags);
  2251. }
  2252. if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
  2253. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2254. ql_dbg(ql_dbg_disc, vha, 0x2015,
  2255. "Loop resync needed, failing.\n");
  2256. rval = QLA_FUNCTION_FAILED;
  2257. }
  2258. else
  2259. rval = qla2x00_configure_local_loop(vha);
  2260. }
  2261. if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
  2262. if (LOOP_TRANSITION(vha)) {
  2263. ql_dbg(ql_dbg_disc, vha, 0x201e,
  2264. "Needs RSCN update and loop transition.\n");
  2265. rval = QLA_FUNCTION_FAILED;
  2266. }
  2267. else
  2268. rval = qla2x00_configure_fabric(vha);
  2269. }
  2270. if (rval == QLA_SUCCESS) {
  2271. if (atomic_read(&vha->loop_down_timer) ||
  2272. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2273. rval = QLA_FUNCTION_FAILED;
  2274. } else {
  2275. atomic_set(&vha->loop_state, LOOP_READY);
  2276. ql_dbg(ql_dbg_disc, vha, 0x2069,
  2277. "LOOP READY.\n");
  2278. }
  2279. }
  2280. if (rval) {
  2281. ql_dbg(ql_dbg_disc, vha, 0x206a,
  2282. "%s *** FAILED ***.\n", __func__);
  2283. } else {
  2284. ql_dbg(ql_dbg_disc, vha, 0x206b,
  2285. "%s: exiting normally.\n", __func__);
  2286. }
  2287. /* Restore state if a resync event occurred during processing */
  2288. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2289. if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
  2290. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2291. if (test_bit(RSCN_UPDATE, &save_flags)) {
  2292. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  2293. if (!IS_ALOGIO_CAPABLE(ha))
  2294. vha->flags.rscn_queue_overflow = 1;
  2295. }
  2296. }
  2297. return (rval);
  2298. }
  2299. /*
  2300. * qla2x00_configure_local_loop
  2301. * Updates Fibre Channel Device Database with local loop devices.
  2302. *
  2303. * Input:
  2304. * ha = adapter block pointer.
  2305. *
  2306. * Returns:
  2307. * 0 = success.
  2308. */
  2309. static int
  2310. qla2x00_configure_local_loop(scsi_qla_host_t *vha)
  2311. {
  2312. int rval, rval2;
  2313. int found_devs;
  2314. int found;
  2315. fc_port_t *fcport, *new_fcport;
  2316. uint16_t index;
  2317. uint16_t entries;
  2318. char *id_iter;
  2319. uint16_t loop_id;
  2320. uint8_t domain, area, al_pa;
  2321. struct qla_hw_data *ha = vha->hw;
  2322. found_devs = 0;
  2323. new_fcport = NULL;
  2324. entries = MAX_FIBRE_DEVICES;
  2325. ql_dbg(ql_dbg_disc, vha, 0x2016,
  2326. "Getting FCAL position map.\n");
  2327. if (ql2xextended_error_logging & ql_dbg_disc)
  2328. qla2x00_get_fcal_position_map(vha, NULL);
  2329. /* Get list of logged in devices. */
  2330. memset(ha->gid_list, 0, GID_LIST_SIZE);
  2331. rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
  2332. &entries);
  2333. if (rval != QLA_SUCCESS)
  2334. goto cleanup_allocation;
  2335. ql_dbg(ql_dbg_disc, vha, 0x2017,
  2336. "Entries in ID list (%d).\n", entries);
  2337. ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
  2338. (uint8_t *)ha->gid_list,
  2339. entries * sizeof(struct gid_list_info));
  2340. /* Allocate temporary fcport for any new fcports discovered. */
  2341. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2342. if (new_fcport == NULL) {
  2343. ql_log(ql_log_warn, vha, 0x2018,
  2344. "Memory allocation failed for fcport.\n");
  2345. rval = QLA_MEMORY_ALLOC_FAILED;
  2346. goto cleanup_allocation;
  2347. }
  2348. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2349. /*
  2350. * Mark local devices that were present with FCF_DEVICE_LOST for now.
  2351. */
  2352. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2353. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2354. fcport->port_type != FCT_BROADCAST &&
  2355. (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2356. ql_dbg(ql_dbg_disc, vha, 0x2019,
  2357. "Marking port lost loop_id=0x%04x.\n",
  2358. fcport->loop_id);
  2359. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2360. }
  2361. }
  2362. /* Add devices to port list. */
  2363. id_iter = (char *)ha->gid_list;
  2364. for (index = 0; index < entries; index++) {
  2365. domain = ((struct gid_list_info *)id_iter)->domain;
  2366. area = ((struct gid_list_info *)id_iter)->area;
  2367. al_pa = ((struct gid_list_info *)id_iter)->al_pa;
  2368. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  2369. loop_id = (uint16_t)
  2370. ((struct gid_list_info *)id_iter)->loop_id_2100;
  2371. else
  2372. loop_id = le16_to_cpu(
  2373. ((struct gid_list_info *)id_iter)->loop_id);
  2374. id_iter += ha->gid_list_info_size;
  2375. /* Bypass reserved domain fields. */
  2376. if ((domain & 0xf0) == 0xf0)
  2377. continue;
  2378. /* Bypass if not same domain and area of adapter. */
  2379. if (area && domain &&
  2380. (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
  2381. continue;
  2382. /* Bypass invalid local loop ID. */
  2383. if (loop_id > LAST_LOCAL_LOOP_ID)
  2384. continue;
  2385. /* Fill in member data. */
  2386. new_fcport->d_id.b.domain = domain;
  2387. new_fcport->d_id.b.area = area;
  2388. new_fcport->d_id.b.al_pa = al_pa;
  2389. new_fcport->loop_id = loop_id;
  2390. new_fcport->vp_idx = vha->vp_idx;
  2391. rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
  2392. if (rval2 != QLA_SUCCESS) {
  2393. ql_dbg(ql_dbg_disc, vha, 0x201a,
  2394. "Failed to retrieve fcport information "
  2395. "-- get_port_database=%x, loop_id=0x%04x.\n",
  2396. rval2, new_fcport->loop_id);
  2397. ql_dbg(ql_dbg_disc, vha, 0x201b,
  2398. "Scheduling resync.\n");
  2399. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2400. continue;
  2401. }
  2402. /* Check for matching device in port list. */
  2403. found = 0;
  2404. fcport = NULL;
  2405. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2406. if (memcmp(new_fcport->port_name, fcport->port_name,
  2407. WWN_SIZE))
  2408. continue;
  2409. fcport->flags &= ~FCF_FABRIC_DEVICE;
  2410. fcport->loop_id = new_fcport->loop_id;
  2411. fcport->port_type = new_fcport->port_type;
  2412. fcport->d_id.b24 = new_fcport->d_id.b24;
  2413. memcpy(fcport->node_name, new_fcport->node_name,
  2414. WWN_SIZE);
  2415. found++;
  2416. break;
  2417. }
  2418. if (!found) {
  2419. /* New device, add to fcports list. */
  2420. if (vha->vp_idx) {
  2421. new_fcport->vha = vha;
  2422. new_fcport->vp_idx = vha->vp_idx;
  2423. }
  2424. list_add_tail(&new_fcport->list, &vha->vp_fcports);
  2425. /* Allocate a new replacement fcport. */
  2426. fcport = new_fcport;
  2427. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2428. if (new_fcport == NULL) {
  2429. ql_log(ql_log_warn, vha, 0x201c,
  2430. "Failed to allocate memory for fcport.\n");
  2431. rval = QLA_MEMORY_ALLOC_FAILED;
  2432. goto cleanup_allocation;
  2433. }
  2434. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2435. }
  2436. /* Base iIDMA settings on HBA port speed. */
  2437. fcport->fp_speed = ha->link_data_rate;
  2438. qla2x00_update_fcport(vha, fcport);
  2439. found_devs++;
  2440. }
  2441. cleanup_allocation:
  2442. kfree(new_fcport);
  2443. if (rval != QLA_SUCCESS) {
  2444. ql_dbg(ql_dbg_disc, vha, 0x201d,
  2445. "Configure local loop error exit: rval=%x.\n", rval);
  2446. }
  2447. return (rval);
  2448. }
  2449. static void
  2450. qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2451. {
  2452. #define LS_UNKNOWN 2
  2453. static char *link_speeds[] = { "1", "2", "?", "4", "8", "10" };
  2454. char *link_speed;
  2455. int rval;
  2456. uint16_t mb[4];
  2457. struct qla_hw_data *ha = vha->hw;
  2458. if (!IS_IIDMA_CAPABLE(ha))
  2459. return;
  2460. if (atomic_read(&fcport->state) != FCS_ONLINE)
  2461. return;
  2462. if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
  2463. fcport->fp_speed > ha->link_data_rate)
  2464. return;
  2465. rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
  2466. mb);
  2467. if (rval != QLA_SUCCESS) {
  2468. ql_dbg(ql_dbg_disc, vha, 0x2004,
  2469. "Unable to adjust iIDMA "
  2470. "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
  2471. "%04x.\n", fcport->port_name[0], fcport->port_name[1],
  2472. fcport->port_name[2], fcport->port_name[3],
  2473. fcport->port_name[4], fcport->port_name[5],
  2474. fcport->port_name[6], fcport->port_name[7], rval,
  2475. fcport->fp_speed, mb[0], mb[1]);
  2476. } else {
  2477. link_speed = link_speeds[LS_UNKNOWN];
  2478. if (fcport->fp_speed < 5)
  2479. link_speed = link_speeds[fcport->fp_speed];
  2480. else if (fcport->fp_speed == 0x13)
  2481. link_speed = link_speeds[5];
  2482. ql_dbg(ql_dbg_disc, vha, 0x2005,
  2483. "iIDMA adjusted to %s GB/s "
  2484. "on %02x%02x%02x%02x%02x%02x%02x%02x.\n", link_speed,
  2485. fcport->port_name[0], fcport->port_name[1],
  2486. fcport->port_name[2], fcport->port_name[3],
  2487. fcport->port_name[4], fcport->port_name[5],
  2488. fcport->port_name[6], fcport->port_name[7]);
  2489. }
  2490. }
  2491. static void
  2492. qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
  2493. {
  2494. struct fc_rport_identifiers rport_ids;
  2495. struct fc_rport *rport;
  2496. unsigned long flags;
  2497. qla2x00_rport_del(fcport);
  2498. rport_ids.node_name = wwn_to_u64(fcport->node_name);
  2499. rport_ids.port_name = wwn_to_u64(fcport->port_name);
  2500. rport_ids.port_id = fcport->d_id.b.domain << 16 |
  2501. fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
  2502. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2503. fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
  2504. if (!rport) {
  2505. ql_log(ql_log_warn, vha, 0x2006,
  2506. "Unable to allocate fc remote port.\n");
  2507. return;
  2508. }
  2509. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2510. *((fc_port_t **)rport->dd_data) = fcport;
  2511. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2512. rport->supported_classes = fcport->supported_classes;
  2513. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2514. if (fcport->port_type == FCT_INITIATOR)
  2515. rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
  2516. if (fcport->port_type == FCT_TARGET)
  2517. rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
  2518. fc_remote_port_rolechg(rport, rport_ids.roles);
  2519. }
  2520. /*
  2521. * qla2x00_update_fcport
  2522. * Updates device on list.
  2523. *
  2524. * Input:
  2525. * ha = adapter block pointer.
  2526. * fcport = port structure pointer.
  2527. *
  2528. * Return:
  2529. * 0 - Success
  2530. * BIT_0 - error
  2531. *
  2532. * Context:
  2533. * Kernel context.
  2534. */
  2535. void
  2536. qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2537. {
  2538. fcport->vha = vha;
  2539. fcport->login_retry = 0;
  2540. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  2541. qla2x00_iidma_fcport(vha, fcport);
  2542. qla24xx_update_fcport_fcp_prio(vha, fcport);
  2543. qla2x00_reg_remote_port(vha, fcport);
  2544. qla2x00_set_fcport_state(fcport, FCS_ONLINE);
  2545. }
  2546. /*
  2547. * qla2x00_configure_fabric
  2548. * Setup SNS devices with loop ID's.
  2549. *
  2550. * Input:
  2551. * ha = adapter block pointer.
  2552. *
  2553. * Returns:
  2554. * 0 = success.
  2555. * BIT_0 = error
  2556. */
  2557. static int
  2558. qla2x00_configure_fabric(scsi_qla_host_t *vha)
  2559. {
  2560. int rval, rval2;
  2561. fc_port_t *fcport, *fcptemp;
  2562. uint16_t next_loopid;
  2563. uint16_t mb[MAILBOX_REGISTER_COUNT];
  2564. uint16_t loop_id;
  2565. LIST_HEAD(new_fcports);
  2566. struct qla_hw_data *ha = vha->hw;
  2567. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2568. /* If FL port exists, then SNS is present */
  2569. if (IS_FWI2_CAPABLE(ha))
  2570. loop_id = NPH_F_PORT;
  2571. else
  2572. loop_id = SNS_FL_PORT;
  2573. rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
  2574. if (rval != QLA_SUCCESS) {
  2575. ql_dbg(ql_dbg_disc, vha, 0x201f,
  2576. "MBX_GET_PORT_NAME failed, No FL Port.\n");
  2577. vha->device_flags &= ~SWITCH_FOUND;
  2578. return (QLA_SUCCESS);
  2579. }
  2580. vha->device_flags |= SWITCH_FOUND;
  2581. /* Mark devices that need re-synchronization. */
  2582. rval2 = qla2x00_device_resync(vha);
  2583. if (rval2 == QLA_RSCNS_HANDLED) {
  2584. /* No point doing the scan, just continue. */
  2585. return (QLA_SUCCESS);
  2586. }
  2587. do {
  2588. /* FDMI support. */
  2589. if (ql2xfdmienable &&
  2590. test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
  2591. qla2x00_fdmi_register(vha);
  2592. /* Ensure we are logged into the SNS. */
  2593. if (IS_FWI2_CAPABLE(ha))
  2594. loop_id = NPH_SNS;
  2595. else
  2596. loop_id = SIMPLE_NAME_SERVER;
  2597. ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
  2598. 0xfc, mb, BIT_1 | BIT_0);
  2599. if (mb[0] != MBS_COMMAND_COMPLETE) {
  2600. ql_dbg(ql_dbg_disc, vha, 0x2042,
  2601. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
  2602. "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
  2603. mb[2], mb[6], mb[7]);
  2604. return (QLA_SUCCESS);
  2605. }
  2606. if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
  2607. if (qla2x00_rft_id(vha)) {
  2608. /* EMPTY */
  2609. ql_dbg(ql_dbg_disc, vha, 0x2045,
  2610. "Register FC-4 TYPE failed.\n");
  2611. }
  2612. if (qla2x00_rff_id(vha)) {
  2613. /* EMPTY */
  2614. ql_dbg(ql_dbg_disc, vha, 0x2049,
  2615. "Register FC-4 Features failed.\n");
  2616. }
  2617. if (qla2x00_rnn_id(vha)) {
  2618. /* EMPTY */
  2619. ql_dbg(ql_dbg_disc, vha, 0x204f,
  2620. "Register Node Name failed.\n");
  2621. } else if (qla2x00_rsnn_nn(vha)) {
  2622. /* EMPTY */
  2623. ql_dbg(ql_dbg_disc, vha, 0x2053,
  2624. "Register Symobilic Node Name failed.\n");
  2625. }
  2626. }
  2627. rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
  2628. if (rval != QLA_SUCCESS)
  2629. break;
  2630. /*
  2631. * Logout all previous fabric devices marked lost, except
  2632. * FCP2 devices.
  2633. */
  2634. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2635. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2636. break;
  2637. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
  2638. continue;
  2639. if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
  2640. qla2x00_mark_device_lost(vha, fcport,
  2641. ql2xplogiabsentdevice, 0);
  2642. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2643. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2644. fcport->port_type != FCT_INITIATOR &&
  2645. fcport->port_type != FCT_BROADCAST) {
  2646. ha->isp_ops->fabric_logout(vha,
  2647. fcport->loop_id,
  2648. fcport->d_id.b.domain,
  2649. fcport->d_id.b.area,
  2650. fcport->d_id.b.al_pa);
  2651. fcport->loop_id = FC_NO_LOOP_ID;
  2652. }
  2653. }
  2654. }
  2655. /* Starting free loop ID. */
  2656. next_loopid = ha->min_external_loopid;
  2657. /*
  2658. * Scan through our port list and login entries that need to be
  2659. * logged in.
  2660. */
  2661. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2662. if (atomic_read(&vha->loop_down_timer) ||
  2663. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2664. break;
  2665. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
  2666. (fcport->flags & FCF_LOGIN_NEEDED) == 0)
  2667. continue;
  2668. if (fcport->loop_id == FC_NO_LOOP_ID) {
  2669. fcport->loop_id = next_loopid;
  2670. rval = qla2x00_find_new_loop_id(
  2671. base_vha, fcport);
  2672. if (rval != QLA_SUCCESS) {
  2673. /* Ran out of IDs to use */
  2674. break;
  2675. }
  2676. }
  2677. /* Login and update database */
  2678. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2679. }
  2680. /* Exit if out of loop IDs. */
  2681. if (rval != QLA_SUCCESS) {
  2682. break;
  2683. }
  2684. /*
  2685. * Login and add the new devices to our port list.
  2686. */
  2687. list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
  2688. if (atomic_read(&vha->loop_down_timer) ||
  2689. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2690. break;
  2691. /* Find a new loop ID to use. */
  2692. fcport->loop_id = next_loopid;
  2693. rval = qla2x00_find_new_loop_id(base_vha, fcport);
  2694. if (rval != QLA_SUCCESS) {
  2695. /* Ran out of IDs to use */
  2696. break;
  2697. }
  2698. /* Login and update database */
  2699. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2700. if (vha->vp_idx) {
  2701. fcport->vha = vha;
  2702. fcport->vp_idx = vha->vp_idx;
  2703. }
  2704. list_move_tail(&fcport->list, &vha->vp_fcports);
  2705. }
  2706. } while (0);
  2707. /* Free all new device structures not processed. */
  2708. list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
  2709. list_del(&fcport->list);
  2710. kfree(fcport);
  2711. }
  2712. if (rval) {
  2713. ql_dbg(ql_dbg_disc, vha, 0x2068,
  2714. "Configure fabric error exit rval=%d.\n", rval);
  2715. }
  2716. return (rval);
  2717. }
  2718. /*
  2719. * qla2x00_find_all_fabric_devs
  2720. *
  2721. * Input:
  2722. * ha = adapter block pointer.
  2723. * dev = database device entry pointer.
  2724. *
  2725. * Returns:
  2726. * 0 = success.
  2727. *
  2728. * Context:
  2729. * Kernel context.
  2730. */
  2731. static int
  2732. qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
  2733. struct list_head *new_fcports)
  2734. {
  2735. int rval;
  2736. uint16_t loop_id;
  2737. fc_port_t *fcport, *new_fcport, *fcptemp;
  2738. int found;
  2739. sw_info_t *swl;
  2740. int swl_idx;
  2741. int first_dev, last_dev;
  2742. port_id_t wrap = {}, nxt_d_id;
  2743. struct qla_hw_data *ha = vha->hw;
  2744. struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
  2745. struct scsi_qla_host *tvp;
  2746. rval = QLA_SUCCESS;
  2747. /* Try GID_PT to get device list, else GAN. */
  2748. swl = kcalloc(MAX_FIBRE_DEVICES, sizeof(sw_info_t), GFP_KERNEL);
  2749. if (!swl) {
  2750. /*EMPTY*/
  2751. ql_dbg(ql_dbg_disc, vha, 0x2054,
  2752. "GID_PT allocations failed, fallback on GA_NXT.\n");
  2753. } else {
  2754. if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
  2755. kfree(swl);
  2756. swl = NULL;
  2757. } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
  2758. kfree(swl);
  2759. swl = NULL;
  2760. } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
  2761. kfree(swl);
  2762. swl = NULL;
  2763. } else if (ql2xiidmaenable &&
  2764. qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
  2765. qla2x00_gpsc(vha, swl);
  2766. }
  2767. /* If other queries succeeded probe for FC-4 type */
  2768. if (swl)
  2769. qla2x00_gff_id(vha, swl);
  2770. }
  2771. swl_idx = 0;
  2772. /* Allocate temporary fcport for any new fcports discovered. */
  2773. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2774. if (new_fcport == NULL) {
  2775. ql_log(ql_log_warn, vha, 0x205e,
  2776. "Failed to allocate memory for fcport.\n");
  2777. kfree(swl);
  2778. return (QLA_MEMORY_ALLOC_FAILED);
  2779. }
  2780. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2781. /* Set start port ID scan at adapter ID. */
  2782. first_dev = 1;
  2783. last_dev = 0;
  2784. /* Starting free loop ID. */
  2785. loop_id = ha->min_external_loopid;
  2786. for (; loop_id <= ha->max_loop_id; loop_id++) {
  2787. if (qla2x00_is_reserved_id(vha, loop_id))
  2788. continue;
  2789. if (ha->current_topology == ISP_CFG_FL &&
  2790. (atomic_read(&vha->loop_down_timer) ||
  2791. LOOP_TRANSITION(vha))) {
  2792. atomic_set(&vha->loop_down_timer, 0);
  2793. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2794. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2795. break;
  2796. }
  2797. if (swl != NULL) {
  2798. if (last_dev) {
  2799. wrap.b24 = new_fcport->d_id.b24;
  2800. } else {
  2801. new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
  2802. memcpy(new_fcport->node_name,
  2803. swl[swl_idx].node_name, WWN_SIZE);
  2804. memcpy(new_fcport->port_name,
  2805. swl[swl_idx].port_name, WWN_SIZE);
  2806. memcpy(new_fcport->fabric_port_name,
  2807. swl[swl_idx].fabric_port_name, WWN_SIZE);
  2808. new_fcport->fp_speed = swl[swl_idx].fp_speed;
  2809. new_fcport->fc4_type = swl[swl_idx].fc4_type;
  2810. if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
  2811. last_dev = 1;
  2812. }
  2813. swl_idx++;
  2814. }
  2815. } else {
  2816. /* Send GA_NXT to the switch */
  2817. rval = qla2x00_ga_nxt(vha, new_fcport);
  2818. if (rval != QLA_SUCCESS) {
  2819. ql_log(ql_log_warn, vha, 0x2064,
  2820. "SNS scan failed -- assuming "
  2821. "zero-entry result.\n");
  2822. list_for_each_entry_safe(fcport, fcptemp,
  2823. new_fcports, list) {
  2824. list_del(&fcport->list);
  2825. kfree(fcport);
  2826. }
  2827. rval = QLA_SUCCESS;
  2828. break;
  2829. }
  2830. }
  2831. /* If wrap on switch device list, exit. */
  2832. if (first_dev) {
  2833. wrap.b24 = new_fcport->d_id.b24;
  2834. first_dev = 0;
  2835. } else if (new_fcport->d_id.b24 == wrap.b24) {
  2836. ql_dbg(ql_dbg_disc, vha, 0x2065,
  2837. "Device wrap (%02x%02x%02x).\n",
  2838. new_fcport->d_id.b.domain,
  2839. new_fcport->d_id.b.area,
  2840. new_fcport->d_id.b.al_pa);
  2841. break;
  2842. }
  2843. /* Bypass if same physical adapter. */
  2844. if (new_fcport->d_id.b24 == base_vha->d_id.b24)
  2845. continue;
  2846. /* Bypass virtual ports of the same host. */
  2847. found = 0;
  2848. if (ha->num_vhosts) {
  2849. unsigned long flags;
  2850. spin_lock_irqsave(&ha->vport_slock, flags);
  2851. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2852. if (new_fcport->d_id.b24 == vp->d_id.b24) {
  2853. found = 1;
  2854. break;
  2855. }
  2856. }
  2857. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2858. if (found)
  2859. continue;
  2860. }
  2861. /* Bypass if same domain and area of adapter. */
  2862. if (((new_fcport->d_id.b24 & 0xffff00) ==
  2863. (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
  2864. ISP_CFG_FL)
  2865. continue;
  2866. /* Bypass reserved domain fields. */
  2867. if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
  2868. continue;
  2869. /* Bypass ports whose FCP-4 type is not FCP_SCSI */
  2870. if (ql2xgffidenable &&
  2871. (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
  2872. new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
  2873. continue;
  2874. /* Locate matching device in database. */
  2875. found = 0;
  2876. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2877. if (memcmp(new_fcport->port_name, fcport->port_name,
  2878. WWN_SIZE))
  2879. continue;
  2880. found++;
  2881. /* Update port state. */
  2882. memcpy(fcport->fabric_port_name,
  2883. new_fcport->fabric_port_name, WWN_SIZE);
  2884. fcport->fp_speed = new_fcport->fp_speed;
  2885. /*
  2886. * If address the same and state FCS_ONLINE, nothing
  2887. * changed.
  2888. */
  2889. if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
  2890. atomic_read(&fcport->state) == FCS_ONLINE) {
  2891. break;
  2892. }
  2893. /*
  2894. * If device was not a fabric device before.
  2895. */
  2896. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2897. fcport->d_id.b24 = new_fcport->d_id.b24;
  2898. fcport->loop_id = FC_NO_LOOP_ID;
  2899. fcport->flags |= (FCF_FABRIC_DEVICE |
  2900. FCF_LOGIN_NEEDED);
  2901. break;
  2902. }
  2903. /*
  2904. * Port ID changed or device was marked to be updated;
  2905. * Log it out if still logged in and mark it for
  2906. * relogin later.
  2907. */
  2908. fcport->d_id.b24 = new_fcport->d_id.b24;
  2909. fcport->flags |= FCF_LOGIN_NEEDED;
  2910. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2911. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2912. fcport->port_type != FCT_INITIATOR &&
  2913. fcport->port_type != FCT_BROADCAST) {
  2914. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  2915. fcport->d_id.b.domain, fcport->d_id.b.area,
  2916. fcport->d_id.b.al_pa);
  2917. fcport->loop_id = FC_NO_LOOP_ID;
  2918. }
  2919. break;
  2920. }
  2921. if (found)
  2922. continue;
  2923. /* If device was not in our fcports list, then add it. */
  2924. list_add_tail(&new_fcport->list, new_fcports);
  2925. /* Allocate a new replacement fcport. */
  2926. nxt_d_id.b24 = new_fcport->d_id.b24;
  2927. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2928. if (new_fcport == NULL) {
  2929. ql_log(ql_log_warn, vha, 0x2066,
  2930. "Memory allocation failed for fcport.\n");
  2931. kfree(swl);
  2932. return (QLA_MEMORY_ALLOC_FAILED);
  2933. }
  2934. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2935. new_fcport->d_id.b24 = nxt_d_id.b24;
  2936. }
  2937. kfree(swl);
  2938. kfree(new_fcport);
  2939. return (rval);
  2940. }
  2941. /*
  2942. * qla2x00_find_new_loop_id
  2943. * Scan through our port list and find a new usable loop ID.
  2944. *
  2945. * Input:
  2946. * ha: adapter state pointer.
  2947. * dev: port structure pointer.
  2948. *
  2949. * Returns:
  2950. * qla2x00 local function return status code.
  2951. *
  2952. * Context:
  2953. * Kernel context.
  2954. */
  2955. int
  2956. qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
  2957. {
  2958. int rval;
  2959. int found;
  2960. fc_port_t *fcport;
  2961. uint16_t first_loop_id;
  2962. struct qla_hw_data *ha = vha->hw;
  2963. struct scsi_qla_host *vp;
  2964. struct scsi_qla_host *tvp;
  2965. unsigned long flags = 0;
  2966. rval = QLA_SUCCESS;
  2967. /* Save starting loop ID. */
  2968. first_loop_id = dev->loop_id;
  2969. for (;;) {
  2970. /* Skip loop ID if already used by adapter. */
  2971. if (dev->loop_id == vha->loop_id)
  2972. dev->loop_id++;
  2973. /* Skip reserved loop IDs. */
  2974. while (qla2x00_is_reserved_id(vha, dev->loop_id))
  2975. dev->loop_id++;
  2976. /* Reset loop ID if passed the end. */
  2977. if (dev->loop_id > ha->max_loop_id) {
  2978. /* first loop ID. */
  2979. dev->loop_id = ha->min_external_loopid;
  2980. }
  2981. /* Check for loop ID being already in use. */
  2982. found = 0;
  2983. fcport = NULL;
  2984. spin_lock_irqsave(&ha->vport_slock, flags);
  2985. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2986. list_for_each_entry(fcport, &vp->vp_fcports, list) {
  2987. if (fcport->loop_id == dev->loop_id &&
  2988. fcport != dev) {
  2989. /* ID possibly in use */
  2990. found++;
  2991. break;
  2992. }
  2993. }
  2994. if (found)
  2995. break;
  2996. }
  2997. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2998. /* If not in use then it is free to use. */
  2999. if (!found) {
  3000. break;
  3001. }
  3002. /* ID in use. Try next value. */
  3003. dev->loop_id++;
  3004. /* If wrap around. No free ID to use. */
  3005. if (dev->loop_id == first_loop_id) {
  3006. dev->loop_id = FC_NO_LOOP_ID;
  3007. rval = QLA_FUNCTION_FAILED;
  3008. break;
  3009. }
  3010. }
  3011. return (rval);
  3012. }
  3013. /*
  3014. * qla2x00_device_resync
  3015. * Marks devices in the database that needs resynchronization.
  3016. *
  3017. * Input:
  3018. * ha = adapter block pointer.
  3019. *
  3020. * Context:
  3021. * Kernel context.
  3022. */
  3023. static int
  3024. qla2x00_device_resync(scsi_qla_host_t *vha)
  3025. {
  3026. int rval;
  3027. uint32_t mask;
  3028. fc_port_t *fcport;
  3029. uint32_t rscn_entry;
  3030. uint8_t rscn_out_iter;
  3031. uint8_t format;
  3032. port_id_t d_id = {};
  3033. rval = QLA_RSCNS_HANDLED;
  3034. while (vha->rscn_out_ptr != vha->rscn_in_ptr ||
  3035. vha->flags.rscn_queue_overflow) {
  3036. rscn_entry = vha->rscn_queue[vha->rscn_out_ptr];
  3037. format = MSB(MSW(rscn_entry));
  3038. d_id.b.domain = LSB(MSW(rscn_entry));
  3039. d_id.b.area = MSB(LSW(rscn_entry));
  3040. d_id.b.al_pa = LSB(LSW(rscn_entry));
  3041. ql_dbg(ql_dbg_disc, vha, 0x2020,
  3042. "RSCN queue entry[%d] = [%02x/%02x%02x%02x].\n",
  3043. vha->rscn_out_ptr, format, d_id.b.domain, d_id.b.area,
  3044. d_id.b.al_pa);
  3045. vha->rscn_out_ptr++;
  3046. if (vha->rscn_out_ptr == MAX_RSCN_COUNT)
  3047. vha->rscn_out_ptr = 0;
  3048. /* Skip duplicate entries. */
  3049. for (rscn_out_iter = vha->rscn_out_ptr;
  3050. !vha->flags.rscn_queue_overflow &&
  3051. rscn_out_iter != vha->rscn_in_ptr;
  3052. rscn_out_iter = (rscn_out_iter ==
  3053. (MAX_RSCN_COUNT - 1)) ? 0: rscn_out_iter + 1) {
  3054. if (rscn_entry != vha->rscn_queue[rscn_out_iter])
  3055. break;
  3056. ql_dbg(ql_dbg_disc, vha, 0x2021,
  3057. "Skipping duplicate RSCN queue entry found at "
  3058. "[%d].\n", rscn_out_iter);
  3059. vha->rscn_out_ptr = rscn_out_iter;
  3060. }
  3061. /* Queue overflow, set switch default case. */
  3062. if (vha->flags.rscn_queue_overflow) {
  3063. ql_dbg(ql_dbg_disc, vha, 0x2022,
  3064. "device_resync: rscn overflow.\n");
  3065. format = 3;
  3066. vha->flags.rscn_queue_overflow = 0;
  3067. }
  3068. switch (format) {
  3069. case 0:
  3070. mask = 0xffffff;
  3071. break;
  3072. case 1:
  3073. mask = 0xffff00;
  3074. break;
  3075. case 2:
  3076. mask = 0xff0000;
  3077. break;
  3078. default:
  3079. mask = 0x0;
  3080. d_id.b24 = 0;
  3081. vha->rscn_out_ptr = vha->rscn_in_ptr;
  3082. break;
  3083. }
  3084. rval = QLA_SUCCESS;
  3085. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3086. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
  3087. (fcport->d_id.b24 & mask) != d_id.b24 ||
  3088. fcport->port_type == FCT_BROADCAST)
  3089. continue;
  3090. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  3091. if (format != 3 ||
  3092. fcport->port_type != FCT_INITIATOR) {
  3093. qla2x00_mark_device_lost(vha, fcport,
  3094. 0, 0);
  3095. }
  3096. }
  3097. }
  3098. }
  3099. return (rval);
  3100. }
  3101. /*
  3102. * qla2x00_fabric_dev_login
  3103. * Login fabric target device and update FC port database.
  3104. *
  3105. * Input:
  3106. * ha: adapter state pointer.
  3107. * fcport: port structure list pointer.
  3108. * next_loopid: contains value of a new loop ID that can be used
  3109. * by the next login attempt.
  3110. *
  3111. * Returns:
  3112. * qla2x00 local function return status code.
  3113. *
  3114. * Context:
  3115. * Kernel context.
  3116. */
  3117. static int
  3118. qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  3119. uint16_t *next_loopid)
  3120. {
  3121. int rval;
  3122. int retry;
  3123. uint8_t opts;
  3124. struct qla_hw_data *ha = vha->hw;
  3125. rval = QLA_SUCCESS;
  3126. retry = 0;
  3127. if (IS_ALOGIO_CAPABLE(ha)) {
  3128. if (fcport->flags & FCF_ASYNC_SENT)
  3129. return rval;
  3130. fcport->flags |= FCF_ASYNC_SENT;
  3131. rval = qla2x00_post_async_login_work(vha, fcport, NULL);
  3132. if (!rval)
  3133. return rval;
  3134. }
  3135. fcport->flags &= ~FCF_ASYNC_SENT;
  3136. rval = qla2x00_fabric_login(vha, fcport, next_loopid);
  3137. if (rval == QLA_SUCCESS) {
  3138. /* Send an ADISC to FCP2 devices.*/
  3139. opts = 0;
  3140. if (fcport->flags & FCF_FCP2_DEVICE)
  3141. opts |= BIT_1;
  3142. rval = qla2x00_get_port_database(vha, fcport, opts);
  3143. if (rval != QLA_SUCCESS) {
  3144. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3145. fcport->d_id.b.domain, fcport->d_id.b.area,
  3146. fcport->d_id.b.al_pa);
  3147. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3148. } else {
  3149. qla2x00_update_fcport(vha, fcport);
  3150. }
  3151. }
  3152. return (rval);
  3153. }
  3154. /*
  3155. * qla2x00_fabric_login
  3156. * Issue fabric login command.
  3157. *
  3158. * Input:
  3159. * ha = adapter block pointer.
  3160. * device = pointer to FC device type structure.
  3161. *
  3162. * Returns:
  3163. * 0 - Login successfully
  3164. * 1 - Login failed
  3165. * 2 - Initiator device
  3166. * 3 - Fatal error
  3167. */
  3168. int
  3169. qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  3170. uint16_t *next_loopid)
  3171. {
  3172. int rval;
  3173. int retry;
  3174. uint16_t tmp_loopid;
  3175. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3176. struct qla_hw_data *ha = vha->hw;
  3177. retry = 0;
  3178. tmp_loopid = 0;
  3179. for (;;) {
  3180. ql_dbg(ql_dbg_disc, vha, 0x2000,
  3181. "Trying Fabric Login w/loop id 0x%04x for port "
  3182. "%02x%02x%02x.\n",
  3183. fcport->loop_id, fcport->d_id.b.domain,
  3184. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3185. /* Login fcport on switch. */
  3186. ha->isp_ops->fabric_login(vha, fcport->loop_id,
  3187. fcport->d_id.b.domain, fcport->d_id.b.area,
  3188. fcport->d_id.b.al_pa, mb, BIT_0);
  3189. if (mb[0] == MBS_PORT_ID_USED) {
  3190. /*
  3191. * Device has another loop ID. The firmware team
  3192. * recommends the driver perform an implicit login with
  3193. * the specified ID again. The ID we just used is save
  3194. * here so we return with an ID that can be tried by
  3195. * the next login.
  3196. */
  3197. retry++;
  3198. tmp_loopid = fcport->loop_id;
  3199. fcport->loop_id = mb[1];
  3200. ql_dbg(ql_dbg_disc, vha, 0x2001,
  3201. "Fabric Login: port in use - next loop "
  3202. "id=0x%04x, port id= %02x%02x%02x.\n",
  3203. fcport->loop_id, fcport->d_id.b.domain,
  3204. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3205. } else if (mb[0] == MBS_COMMAND_COMPLETE) {
  3206. /*
  3207. * Login succeeded.
  3208. */
  3209. if (retry) {
  3210. /* A retry occurred before. */
  3211. *next_loopid = tmp_loopid;
  3212. } else {
  3213. /*
  3214. * No retry occurred before. Just increment the
  3215. * ID value for next login.
  3216. */
  3217. *next_loopid = (fcport->loop_id + 1);
  3218. }
  3219. if (mb[1] & BIT_0) {
  3220. fcport->port_type = FCT_INITIATOR;
  3221. } else {
  3222. fcport->port_type = FCT_TARGET;
  3223. if (mb[1] & BIT_1) {
  3224. fcport->flags |= FCF_FCP2_DEVICE;
  3225. }
  3226. }
  3227. if (mb[10] & BIT_0)
  3228. fcport->supported_classes |= FC_COS_CLASS2;
  3229. if (mb[10] & BIT_1)
  3230. fcport->supported_classes |= FC_COS_CLASS3;
  3231. rval = QLA_SUCCESS;
  3232. break;
  3233. } else if (mb[0] == MBS_LOOP_ID_USED) {
  3234. /*
  3235. * Loop ID already used, try next loop ID.
  3236. */
  3237. fcport->loop_id++;
  3238. rval = qla2x00_find_new_loop_id(vha, fcport);
  3239. if (rval != QLA_SUCCESS) {
  3240. /* Ran out of loop IDs to use */
  3241. break;
  3242. }
  3243. } else if (mb[0] == MBS_COMMAND_ERROR) {
  3244. /*
  3245. * Firmware possibly timed out during login. If NO
  3246. * retries are left to do then the device is declared
  3247. * dead.
  3248. */
  3249. *next_loopid = fcport->loop_id;
  3250. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3251. fcport->d_id.b.domain, fcport->d_id.b.area,
  3252. fcport->d_id.b.al_pa);
  3253. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3254. rval = 1;
  3255. break;
  3256. } else {
  3257. /*
  3258. * unrecoverable / not handled error
  3259. */
  3260. ql_dbg(ql_dbg_disc, vha, 0x2002,
  3261. "Failed=%x port_id=%02x%02x%02x loop_id=%x "
  3262. "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
  3263. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  3264. fcport->loop_id, jiffies);
  3265. *next_loopid = fcport->loop_id;
  3266. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3267. fcport->d_id.b.domain, fcport->d_id.b.area,
  3268. fcport->d_id.b.al_pa);
  3269. fcport->loop_id = FC_NO_LOOP_ID;
  3270. fcport->login_retry = 0;
  3271. rval = 3;
  3272. break;
  3273. }
  3274. }
  3275. return (rval);
  3276. }
  3277. /*
  3278. * qla2x00_local_device_login
  3279. * Issue local device login command.
  3280. *
  3281. * Input:
  3282. * ha = adapter block pointer.
  3283. * loop_id = loop id of device to login to.
  3284. *
  3285. * Returns (Where's the #define!!!!):
  3286. * 0 - Login successfully
  3287. * 1 - Login failed
  3288. * 3 - Fatal error
  3289. */
  3290. int
  3291. qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
  3292. {
  3293. int rval;
  3294. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3295. memset(mb, 0, sizeof(mb));
  3296. rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
  3297. if (rval == QLA_SUCCESS) {
  3298. /* Interrogate mailbox registers for any errors */
  3299. if (mb[0] == MBS_COMMAND_ERROR)
  3300. rval = 1;
  3301. else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
  3302. /* device not in PCB table */
  3303. rval = 3;
  3304. }
  3305. return (rval);
  3306. }
  3307. /*
  3308. * qla2x00_loop_resync
  3309. * Resync with fibre channel devices.
  3310. *
  3311. * Input:
  3312. * ha = adapter block pointer.
  3313. *
  3314. * Returns:
  3315. * 0 = success
  3316. */
  3317. int
  3318. qla2x00_loop_resync(scsi_qla_host_t *vha)
  3319. {
  3320. int rval = QLA_SUCCESS;
  3321. uint32_t wait_time;
  3322. struct req_que *req;
  3323. struct rsp_que *rsp;
  3324. if (vha->hw->flags.cpu_affinity_enabled)
  3325. req = vha->hw->req_q_map[0];
  3326. else
  3327. req = vha->req;
  3328. rsp = req->rsp;
  3329. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3330. if (vha->flags.online) {
  3331. if (!(rval = qla2x00_fw_ready(vha))) {
  3332. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3333. wait_time = 256;
  3334. do {
  3335. /* Issue a marker after FW becomes ready. */
  3336. qla2x00_marker(vha, req, rsp, 0, 0,
  3337. MK_SYNC_ALL);
  3338. vha->marker_needed = 0;
  3339. /* Remap devices on Loop. */
  3340. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3341. qla2x00_configure_loop(vha);
  3342. wait_time--;
  3343. } while (!atomic_read(&vha->loop_down_timer) &&
  3344. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3345. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3346. &vha->dpc_flags)));
  3347. }
  3348. }
  3349. if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3350. return (QLA_FUNCTION_FAILED);
  3351. if (rval)
  3352. ql_dbg(ql_dbg_disc, vha, 0x206c,
  3353. "%s *** FAILED ***.\n", __func__);
  3354. return (rval);
  3355. }
  3356. /*
  3357. * qla2x00_perform_loop_resync
  3358. * Description: This function will set the appropriate flags and call
  3359. * qla2x00_loop_resync. If successful loop will be resynced
  3360. * Arguments : scsi_qla_host_t pointer
  3361. * returm : Success or Failure
  3362. */
  3363. int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
  3364. {
  3365. int32_t rval = 0;
  3366. if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
  3367. /*Configure the flags so that resync happens properly*/
  3368. atomic_set(&ha->loop_down_timer, 0);
  3369. if (!(ha->device_flags & DFLG_NO_CABLE)) {
  3370. atomic_set(&ha->loop_state, LOOP_UP);
  3371. set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
  3372. set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
  3373. set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
  3374. rval = qla2x00_loop_resync(ha);
  3375. } else
  3376. atomic_set(&ha->loop_state, LOOP_DEAD);
  3377. clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
  3378. }
  3379. return rval;
  3380. }
  3381. void
  3382. qla2x00_update_fcports(scsi_qla_host_t *base_vha)
  3383. {
  3384. fc_port_t *fcport;
  3385. struct scsi_qla_host *vha;
  3386. struct qla_hw_data *ha = base_vha->hw;
  3387. unsigned long flags;
  3388. spin_lock_irqsave(&ha->vport_slock, flags);
  3389. /* Go with deferred removal of rport references. */
  3390. list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
  3391. atomic_inc(&vha->vref_count);
  3392. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3393. if (fcport->drport &&
  3394. atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
  3395. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3396. qla2x00_rport_del(fcport);
  3397. spin_lock_irqsave(&ha->vport_slock, flags);
  3398. }
  3399. }
  3400. atomic_dec(&vha->vref_count);
  3401. }
  3402. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3403. }
  3404. /*
  3405. * qla82xx_quiescent_state_cleanup
  3406. * Description: This function will block the new I/Os
  3407. * Its not aborting any I/Os as context
  3408. * is not destroyed during quiescence
  3409. * Arguments: scsi_qla_host_t
  3410. * return : void
  3411. */
  3412. void
  3413. qla82xx_quiescent_state_cleanup(scsi_qla_host_t *vha)
  3414. {
  3415. struct qla_hw_data *ha = vha->hw;
  3416. struct scsi_qla_host *vp;
  3417. ql_dbg(ql_dbg_p3p, vha, 0xb002,
  3418. "Performing ISP error recovery - ha=%p.\n", ha);
  3419. atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
  3420. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3421. atomic_set(&vha->loop_state, LOOP_DOWN);
  3422. qla2x00_mark_all_devices_lost(vha, 0);
  3423. list_for_each_entry(vp, &ha->vp_list, list)
  3424. qla2x00_mark_all_devices_lost(vha, 0);
  3425. } else {
  3426. if (!atomic_read(&vha->loop_down_timer))
  3427. atomic_set(&vha->loop_down_timer,
  3428. LOOP_DOWN_TIME);
  3429. }
  3430. /* Wait for pending cmds to complete */
  3431. qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
  3432. }
  3433. void
  3434. qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
  3435. {
  3436. struct qla_hw_data *ha = vha->hw;
  3437. struct scsi_qla_host *vp;
  3438. unsigned long flags;
  3439. fc_port_t *fcport;
  3440. /* For ISP82XX, driver waits for completion of the commands.
  3441. * online flag should be set.
  3442. */
  3443. if (!IS_QLA82XX(ha))
  3444. vha->flags.online = 0;
  3445. ha->flags.chip_reset_done = 0;
  3446. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3447. ha->qla_stats.total_isp_aborts++;
  3448. ql_log(ql_log_info, vha, 0x00af,
  3449. "Performing ISP error recovery - ha=%p.\n", ha);
  3450. /* For ISP82XX, reset_chip is just disabling interrupts.
  3451. * Driver waits for the completion of the commands.
  3452. * the interrupts need to be enabled.
  3453. */
  3454. if (!IS_QLA82XX(ha))
  3455. ha->isp_ops->reset_chip(vha);
  3456. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  3457. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3458. atomic_set(&vha->loop_state, LOOP_DOWN);
  3459. qla2x00_mark_all_devices_lost(vha, 0);
  3460. spin_lock_irqsave(&ha->vport_slock, flags);
  3461. list_for_each_entry(vp, &ha->vp_list, list) {
  3462. atomic_inc(&vp->vref_count);
  3463. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3464. qla2x00_mark_all_devices_lost(vp, 0);
  3465. spin_lock_irqsave(&ha->vport_slock, flags);
  3466. atomic_dec(&vp->vref_count);
  3467. }
  3468. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3469. } else {
  3470. if (!atomic_read(&vha->loop_down_timer))
  3471. atomic_set(&vha->loop_down_timer,
  3472. LOOP_DOWN_TIME);
  3473. }
  3474. /* Clear all async request states across all VPs. */
  3475. list_for_each_entry(fcport, &vha->vp_fcports, list)
  3476. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3477. spin_lock_irqsave(&ha->vport_slock, flags);
  3478. list_for_each_entry(vp, &ha->vp_list, list) {
  3479. atomic_inc(&vp->vref_count);
  3480. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3481. list_for_each_entry(fcport, &vp->vp_fcports, list)
  3482. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3483. spin_lock_irqsave(&ha->vport_slock, flags);
  3484. atomic_dec(&vp->vref_count);
  3485. }
  3486. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3487. if (!ha->flags.eeh_busy) {
  3488. /* Make sure for ISP 82XX IO DMA is complete */
  3489. if (IS_QLA82XX(ha)) {
  3490. qla82xx_chip_reset_cleanup(vha);
  3491. ql_log(ql_log_info, vha, 0x00b4,
  3492. "Done chip reset cleanup.\n");
  3493. /* Done waiting for pending commands.
  3494. * Reset the online flag.
  3495. */
  3496. vha->flags.online = 0;
  3497. }
  3498. /* Requeue all commands in outstanding command list. */
  3499. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3500. }
  3501. }
  3502. /*
  3503. * qla2x00_abort_isp
  3504. * Resets ISP and aborts all outstanding commands.
  3505. *
  3506. * Input:
  3507. * ha = adapter block pointer.
  3508. *
  3509. * Returns:
  3510. * 0 = success
  3511. */
  3512. int
  3513. qla2x00_abort_isp(scsi_qla_host_t *vha)
  3514. {
  3515. int rval;
  3516. uint8_t status = 0;
  3517. struct qla_hw_data *ha = vha->hw;
  3518. struct scsi_qla_host *vp;
  3519. struct req_que *req = ha->req_q_map[0];
  3520. unsigned long flags;
  3521. if (vha->flags.online) {
  3522. qla2x00_abort_isp_cleanup(vha);
  3523. if (unlikely(pci_channel_offline(ha->pdev) &&
  3524. ha->flags.pci_channel_io_perm_failure)) {
  3525. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3526. status = 0;
  3527. return status;
  3528. }
  3529. ha->isp_ops->get_flash_version(vha, req->ring);
  3530. ha->isp_ops->nvram_config(vha);
  3531. if (!qla2x00_restart_isp(vha)) {
  3532. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3533. if (!atomic_read(&vha->loop_down_timer)) {
  3534. /*
  3535. * Issue marker command only when we are going
  3536. * to start the I/O .
  3537. */
  3538. vha->marker_needed = 1;
  3539. }
  3540. vha->flags.online = 1;
  3541. ha->isp_ops->enable_intrs(ha);
  3542. ha->isp_abort_cnt = 0;
  3543. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3544. if (IS_QLA81XX(ha))
  3545. qla2x00_get_fw_version(vha,
  3546. &ha->fw_major_version,
  3547. &ha->fw_minor_version,
  3548. &ha->fw_subminor_version,
  3549. &ha->fw_attributes, &ha->fw_memory_size,
  3550. ha->mpi_version, &ha->mpi_capabilities,
  3551. ha->phy_version);
  3552. if (ha->fce) {
  3553. ha->flags.fce_enabled = 1;
  3554. memset(ha->fce, 0,
  3555. fce_calc_size(ha->fce_bufs));
  3556. rval = qla2x00_enable_fce_trace(vha,
  3557. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  3558. &ha->fce_bufs);
  3559. if (rval) {
  3560. ql_log(ql_log_warn, vha, 0x8033,
  3561. "Unable to reinitialize FCE "
  3562. "(%d).\n", rval);
  3563. ha->flags.fce_enabled = 0;
  3564. }
  3565. }
  3566. if (ha->eft) {
  3567. memset(ha->eft, 0, EFT_SIZE);
  3568. rval = qla2x00_enable_eft_trace(vha,
  3569. ha->eft_dma, EFT_NUM_BUFFERS);
  3570. if (rval) {
  3571. ql_log(ql_log_warn, vha, 0x8034,
  3572. "Unable to reinitialize EFT "
  3573. "(%d).\n", rval);
  3574. }
  3575. }
  3576. } else { /* failed the ISP abort */
  3577. vha->flags.online = 1;
  3578. if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  3579. if (ha->isp_abort_cnt == 0) {
  3580. ql_log(ql_log_fatal, vha, 0x8035,
  3581. "ISP error recover failed - "
  3582. "board disabled.\n");
  3583. /*
  3584. * The next call disables the board
  3585. * completely.
  3586. */
  3587. ha->isp_ops->reset_adapter(vha);
  3588. vha->flags.online = 0;
  3589. clear_bit(ISP_ABORT_RETRY,
  3590. &vha->dpc_flags);
  3591. status = 0;
  3592. } else { /* schedule another ISP abort */
  3593. ha->isp_abort_cnt--;
  3594. ql_dbg(ql_dbg_taskm, vha, 0x8020,
  3595. "ISP abort - retry remaining %d.\n",
  3596. ha->isp_abort_cnt);
  3597. status = 1;
  3598. }
  3599. } else {
  3600. ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
  3601. ql_dbg(ql_dbg_taskm, vha, 0x8021,
  3602. "ISP error recovery - retrying (%d) "
  3603. "more times.\n", ha->isp_abort_cnt);
  3604. set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3605. status = 1;
  3606. }
  3607. }
  3608. }
  3609. if (!status) {
  3610. ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
  3611. spin_lock_irqsave(&ha->vport_slock, flags);
  3612. list_for_each_entry(vp, &ha->vp_list, list) {
  3613. if (vp->vp_idx) {
  3614. atomic_inc(&vp->vref_count);
  3615. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3616. qla2x00_vp_abort_isp(vp);
  3617. spin_lock_irqsave(&ha->vport_slock, flags);
  3618. atomic_dec(&vp->vref_count);
  3619. }
  3620. }
  3621. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3622. } else {
  3623. ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
  3624. __func__);
  3625. }
  3626. return(status);
  3627. }
  3628. /*
  3629. * qla2x00_restart_isp
  3630. * restarts the ISP after a reset
  3631. *
  3632. * Input:
  3633. * ha = adapter block pointer.
  3634. *
  3635. * Returns:
  3636. * 0 = success
  3637. */
  3638. static int
  3639. qla2x00_restart_isp(scsi_qla_host_t *vha)
  3640. {
  3641. int status = 0;
  3642. uint32_t wait_time;
  3643. struct qla_hw_data *ha = vha->hw;
  3644. struct req_que *req = ha->req_q_map[0];
  3645. struct rsp_que *rsp = ha->rsp_q_map[0];
  3646. /* If firmware needs to be loaded */
  3647. if (qla2x00_isp_firmware(vha)) {
  3648. vha->flags.online = 0;
  3649. status = ha->isp_ops->chip_diag(vha);
  3650. if (!status)
  3651. status = qla2x00_setup_chip(vha);
  3652. }
  3653. if (!status && !(status = qla2x00_init_rings(vha))) {
  3654. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3655. ha->flags.chip_reset_done = 1;
  3656. /* Initialize the queues in use */
  3657. qla25xx_init_queues(ha);
  3658. status = qla2x00_fw_ready(vha);
  3659. if (!status) {
  3660. ql_dbg(ql_dbg_taskm, vha, 0x8031,
  3661. "Start configure loop status = %d.\n", status);
  3662. /* Issue a marker after FW becomes ready. */
  3663. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  3664. vha->flags.online = 1;
  3665. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3666. wait_time = 256;
  3667. do {
  3668. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3669. qla2x00_configure_loop(vha);
  3670. wait_time--;
  3671. } while (!atomic_read(&vha->loop_down_timer) &&
  3672. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3673. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3674. &vha->dpc_flags)));
  3675. }
  3676. /* if no cable then assume it's good */
  3677. if ((vha->device_flags & DFLG_NO_CABLE))
  3678. status = 0;
  3679. ql_dbg(ql_dbg_taskm, vha, 0x8032,
  3680. "Configure loop done, status = 0x%x.\n", status);
  3681. }
  3682. return (status);
  3683. }
  3684. static int
  3685. qla25xx_init_queues(struct qla_hw_data *ha)
  3686. {
  3687. struct rsp_que *rsp = NULL;
  3688. struct req_que *req = NULL;
  3689. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  3690. int ret = -1;
  3691. int i;
  3692. for (i = 1; i < ha->max_rsp_queues; i++) {
  3693. rsp = ha->rsp_q_map[i];
  3694. if (rsp) {
  3695. rsp->options &= ~BIT_0;
  3696. ret = qla25xx_init_rsp_que(base_vha, rsp);
  3697. if (ret != QLA_SUCCESS)
  3698. ql_dbg(ql_dbg_init, base_vha, 0x00ff,
  3699. "%s Rsp que: %d init failed.\n",
  3700. __func__, rsp->id);
  3701. else
  3702. ql_dbg(ql_dbg_init, base_vha, 0x0100,
  3703. "%s Rsp que: %d inited.\n",
  3704. __func__, rsp->id);
  3705. }
  3706. }
  3707. for (i = 1; i < ha->max_req_queues; i++) {
  3708. req = ha->req_q_map[i];
  3709. if (req) {
  3710. /* Clear outstanding commands array. */
  3711. req->options &= ~BIT_0;
  3712. ret = qla25xx_init_req_que(base_vha, req);
  3713. if (ret != QLA_SUCCESS)
  3714. ql_dbg(ql_dbg_init, base_vha, 0x0101,
  3715. "%s Req que: %d init failed.\n",
  3716. __func__, req->id);
  3717. else
  3718. ql_dbg(ql_dbg_init, base_vha, 0x0102,
  3719. "%s Req que: %d inited.\n",
  3720. __func__, req->id);
  3721. }
  3722. }
  3723. return ret;
  3724. }
  3725. /*
  3726. * qla2x00_reset_adapter
  3727. * Reset adapter.
  3728. *
  3729. * Input:
  3730. * ha = adapter block pointer.
  3731. */
  3732. void
  3733. qla2x00_reset_adapter(scsi_qla_host_t *vha)
  3734. {
  3735. unsigned long flags = 0;
  3736. struct qla_hw_data *ha = vha->hw;
  3737. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3738. vha->flags.online = 0;
  3739. ha->isp_ops->disable_intrs(ha);
  3740. spin_lock_irqsave(&ha->hardware_lock, flags);
  3741. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  3742. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3743. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  3744. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3745. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3746. }
  3747. void
  3748. qla24xx_reset_adapter(scsi_qla_host_t *vha)
  3749. {
  3750. unsigned long flags = 0;
  3751. struct qla_hw_data *ha = vha->hw;
  3752. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3753. if (IS_QLA82XX(ha))
  3754. return;
  3755. vha->flags.online = 0;
  3756. ha->isp_ops->disable_intrs(ha);
  3757. spin_lock_irqsave(&ha->hardware_lock, flags);
  3758. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  3759. RD_REG_DWORD(&reg->hccr);
  3760. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  3761. RD_REG_DWORD(&reg->hccr);
  3762. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3763. if (IS_NOPOLLING_TYPE(ha))
  3764. ha->isp_ops->enable_intrs(ha);
  3765. }
  3766. /* On sparc systems, obtain port and node WWN from firmware
  3767. * properties.
  3768. */
  3769. static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
  3770. struct nvram_24xx *nv)
  3771. {
  3772. #ifdef CONFIG_SPARC
  3773. struct qla_hw_data *ha = vha->hw;
  3774. struct pci_dev *pdev = ha->pdev;
  3775. struct device_node *dp = pci_device_to_OF_node(pdev);
  3776. const u8 *val;
  3777. int len;
  3778. val = of_get_property(dp, "port-wwn", &len);
  3779. if (val && len >= WWN_SIZE)
  3780. memcpy(nv->port_name, val, WWN_SIZE);
  3781. val = of_get_property(dp, "node-wwn", &len);
  3782. if (val && len >= WWN_SIZE)
  3783. memcpy(nv->node_name, val, WWN_SIZE);
  3784. #endif
  3785. }
  3786. int
  3787. qla24xx_nvram_config(scsi_qla_host_t *vha)
  3788. {
  3789. int rval;
  3790. struct init_cb_24xx *icb;
  3791. struct nvram_24xx *nv;
  3792. uint32_t *dptr;
  3793. uint8_t *dptr1, *dptr2;
  3794. uint32_t chksum;
  3795. uint16_t cnt;
  3796. struct qla_hw_data *ha = vha->hw;
  3797. rval = QLA_SUCCESS;
  3798. icb = (struct init_cb_24xx *)ha->init_cb;
  3799. nv = ha->nvram;
  3800. /* Determine NVRAM starting address. */
  3801. if (ha->flags.port0) {
  3802. ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
  3803. ha->vpd_base = FA_NVRAM_VPD0_ADDR;
  3804. } else {
  3805. ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
  3806. ha->vpd_base = FA_NVRAM_VPD1_ADDR;
  3807. }
  3808. ha->nvram_size = sizeof(struct nvram_24xx);
  3809. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  3810. if (IS_QLA82XX(ha))
  3811. ha->vpd_size = FA_VPD_SIZE_82XX;
  3812. /* Get VPD data into cache */
  3813. ha->vpd = ha->nvram + VPD_OFFSET;
  3814. ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
  3815. ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
  3816. /* Get NVRAM data into cache and calculate checksum. */
  3817. dptr = (uint32_t *)nv;
  3818. ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
  3819. ha->nvram_size);
  3820. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  3821. chksum += le32_to_cpu(*dptr++);
  3822. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
  3823. "Contents of NVRAM\n");
  3824. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
  3825. (uint8_t *)nv, ha->nvram_size);
  3826. /* Bad NVRAM data, set defaults parameters. */
  3827. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  3828. || nv->id[3] != ' ' ||
  3829. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  3830. /* Reset NVRAM data. */
  3831. ql_log(ql_log_warn, vha, 0x006b,
  3832. "Inconisistent NVRAM detected: checksum=0x%x id=%c "
  3833. "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
  3834. ql_log(ql_log_warn, vha, 0x006c,
  3835. "Falling back to functioning (yet invalid -- WWPN) "
  3836. "defaults.\n");
  3837. /*
  3838. * Set default initialization control block.
  3839. */
  3840. memset(nv, 0, ha->nvram_size);
  3841. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  3842. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  3843. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  3844. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3845. nv->exchange_count = __constant_cpu_to_le16(0);
  3846. nv->hard_address = __constant_cpu_to_le16(124);
  3847. nv->port_name[0] = 0x21;
  3848. nv->port_name[1] = 0x00 + ha->port_no;
  3849. nv->port_name[2] = 0x00;
  3850. nv->port_name[3] = 0xe0;
  3851. nv->port_name[4] = 0x8b;
  3852. nv->port_name[5] = 0x1c;
  3853. nv->port_name[6] = 0x55;
  3854. nv->port_name[7] = 0x86;
  3855. nv->node_name[0] = 0x20;
  3856. nv->node_name[1] = 0x00;
  3857. nv->node_name[2] = 0x00;
  3858. nv->node_name[3] = 0xe0;
  3859. nv->node_name[4] = 0x8b;
  3860. nv->node_name[5] = 0x1c;
  3861. nv->node_name[6] = 0x55;
  3862. nv->node_name[7] = 0x86;
  3863. qla24xx_nvram_wwn_from_ofw(vha, nv);
  3864. nv->login_retry_count = __constant_cpu_to_le16(8);
  3865. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  3866. nv->login_timeout = __constant_cpu_to_le16(0);
  3867. nv->firmware_options_1 =
  3868. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  3869. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  3870. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  3871. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  3872. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  3873. nv->efi_parameters = __constant_cpu_to_le32(0);
  3874. nv->reset_delay = 5;
  3875. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  3876. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  3877. nv->link_down_timeout = __constant_cpu_to_le16(30);
  3878. rval = 1;
  3879. }
  3880. /* Reset Initialization control block */
  3881. memset(icb, 0, ha->init_cb_size);
  3882. /* Copy 1st segment. */
  3883. dptr1 = (uint8_t *)icb;
  3884. dptr2 = (uint8_t *)&nv->version;
  3885. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  3886. while (cnt--)
  3887. *dptr1++ = *dptr2++;
  3888. icb->login_retry_count = nv->login_retry_count;
  3889. icb->link_down_on_nos = nv->link_down_on_nos;
  3890. /* Copy 2nd segment. */
  3891. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  3892. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  3893. cnt = (uint8_t *)&icb->reserved_3 -
  3894. (uint8_t *)&icb->interrupt_delay_timer;
  3895. while (cnt--)
  3896. *dptr1++ = *dptr2++;
  3897. /*
  3898. * Setup driver NVRAM options.
  3899. */
  3900. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  3901. "QLA2462");
  3902. /* Use alternate WWN? */
  3903. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  3904. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  3905. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  3906. }
  3907. /* Prepare nodename */
  3908. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  3909. /*
  3910. * Firmware will apply the following mask if the nodename was
  3911. * not provided.
  3912. */
  3913. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  3914. icb->node_name[0] &= 0xF0;
  3915. }
  3916. /* Set host adapter parameters. */
  3917. ha->flags.disable_risc_code_load = 0;
  3918. ha->flags.enable_lip_reset = 0;
  3919. ha->flags.enable_lip_full_login =
  3920. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  3921. ha->flags.enable_target_reset =
  3922. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  3923. ha->flags.enable_led_scheme = 0;
  3924. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  3925. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  3926. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  3927. memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
  3928. sizeof(ha->fw_seriallink_options24));
  3929. /* save HBA serial number */
  3930. ha->serial0 = icb->port_name[5];
  3931. ha->serial1 = icb->port_name[6];
  3932. ha->serial2 = icb->port_name[7];
  3933. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  3934. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  3935. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3936. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  3937. /* Set minimum login_timeout to 4 seconds. */
  3938. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  3939. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  3940. if (le16_to_cpu(nv->login_timeout) < 4)
  3941. nv->login_timeout = __constant_cpu_to_le16(4);
  3942. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  3943. icb->login_timeout = nv->login_timeout;
  3944. /* Set minimum RATOV to 100 tenths of a second. */
  3945. ha->r_a_tov = 100;
  3946. ha->loop_reset_delay = nv->reset_delay;
  3947. /* Link Down Timeout = 0:
  3948. *
  3949. * When Port Down timer expires we will start returning
  3950. * I/O's to OS with "DID_NO_CONNECT".
  3951. *
  3952. * Link Down Timeout != 0:
  3953. *
  3954. * The driver waits for the link to come up after link down
  3955. * before returning I/Os to OS with "DID_NO_CONNECT".
  3956. */
  3957. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  3958. ha->loop_down_abort_time =
  3959. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  3960. } else {
  3961. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  3962. ha->loop_down_abort_time =
  3963. (LOOP_DOWN_TIME - ha->link_down_timeout);
  3964. }
  3965. /* Need enough time to try and get the port back. */
  3966. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  3967. if (qlport_down_retry)
  3968. ha->port_down_retry_count = qlport_down_retry;
  3969. /* Set login_retry_count */
  3970. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  3971. if (ha->port_down_retry_count ==
  3972. le16_to_cpu(nv->port_down_retry_count) &&
  3973. ha->port_down_retry_count > 3)
  3974. ha->login_retry_count = ha->port_down_retry_count;
  3975. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  3976. ha->login_retry_count = ha->port_down_retry_count;
  3977. if (ql2xloginretrycount)
  3978. ha->login_retry_count = ql2xloginretrycount;
  3979. /* Enable ZIO. */
  3980. if (!vha->flags.init_done) {
  3981. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  3982. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  3983. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  3984. le16_to_cpu(icb->interrupt_delay_timer): 2;
  3985. }
  3986. icb->firmware_options_2 &= __constant_cpu_to_le32(
  3987. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  3988. vha->flags.process_response_queue = 0;
  3989. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  3990. ha->zio_mode = QLA_ZIO_MODE_6;
  3991. ql_log(ql_log_info, vha, 0x006f,
  3992. "ZIO mode %d enabled; timer delay (%d us).\n",
  3993. ha->zio_mode, ha->zio_timer * 100);
  3994. icb->firmware_options_2 |= cpu_to_le32(
  3995. (uint32_t)ha->zio_mode);
  3996. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  3997. vha->flags.process_response_queue = 1;
  3998. }
  3999. if (rval) {
  4000. ql_log(ql_log_warn, vha, 0x0070,
  4001. "NVRAM configuration failed.\n");
  4002. }
  4003. return (rval);
  4004. }
  4005. static int
  4006. qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
  4007. uint32_t faddr)
  4008. {
  4009. int rval = QLA_SUCCESS;
  4010. int segments, fragment;
  4011. uint32_t *dcode, dlen;
  4012. uint32_t risc_addr;
  4013. uint32_t risc_size;
  4014. uint32_t i;
  4015. struct qla_hw_data *ha = vha->hw;
  4016. struct req_que *req = ha->req_q_map[0];
  4017. ql_dbg(ql_dbg_init, vha, 0x008b,
  4018. "FW: Loading firmware from flash (%x).\n", faddr);
  4019. rval = QLA_SUCCESS;
  4020. segments = FA_RISC_CODE_SEGMENTS;
  4021. dcode = (uint32_t *)req->ring;
  4022. *srisc_addr = 0;
  4023. /* Validate firmware image by checking version. */
  4024. qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
  4025. for (i = 0; i < 4; i++)
  4026. dcode[i] = be32_to_cpu(dcode[i]);
  4027. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  4028. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  4029. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  4030. dcode[3] == 0)) {
  4031. ql_log(ql_log_fatal, vha, 0x008c,
  4032. "Unable to verify the integrity of flash firmware "
  4033. "image.\n");
  4034. ql_log(ql_log_fatal, vha, 0x008d,
  4035. "Firmware data: %08x %08x %08x %08x.\n",
  4036. dcode[0], dcode[1], dcode[2], dcode[3]);
  4037. return QLA_FUNCTION_FAILED;
  4038. }
  4039. while (segments && rval == QLA_SUCCESS) {
  4040. /* Read segment's load information. */
  4041. qla24xx_read_flash_data(vha, dcode, faddr, 4);
  4042. risc_addr = be32_to_cpu(dcode[2]);
  4043. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  4044. risc_size = be32_to_cpu(dcode[3]);
  4045. fragment = 0;
  4046. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4047. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  4048. if (dlen > risc_size)
  4049. dlen = risc_size;
  4050. ql_dbg(ql_dbg_init, vha, 0x008e,
  4051. "Loading risc segment@ risc addr %x "
  4052. "number of dwords 0x%x offset 0x%x.\n",
  4053. risc_addr, dlen, faddr);
  4054. qla24xx_read_flash_data(vha, dcode, faddr, dlen);
  4055. for (i = 0; i < dlen; i++)
  4056. dcode[i] = swab32(dcode[i]);
  4057. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4058. dlen);
  4059. if (rval) {
  4060. ql_log(ql_log_fatal, vha, 0x008f,
  4061. "Failed to load segment %d of firmware.\n",
  4062. fragment);
  4063. break;
  4064. }
  4065. faddr += dlen;
  4066. risc_addr += dlen;
  4067. risc_size -= dlen;
  4068. fragment++;
  4069. }
  4070. /* Next segment. */
  4071. segments--;
  4072. }
  4073. return rval;
  4074. }
  4075. #define QLA_FW_URL "ftp://ftp.qlogic.com/outgoing/linux/firmware/"
  4076. int
  4077. qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4078. {
  4079. int rval;
  4080. int i, fragment;
  4081. uint16_t *wcode, *fwcode;
  4082. uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
  4083. struct fw_blob *blob;
  4084. struct qla_hw_data *ha = vha->hw;
  4085. struct req_que *req = ha->req_q_map[0];
  4086. /* Load firmware blob. */
  4087. blob = qla2x00_request_firmware(vha);
  4088. if (!blob) {
  4089. ql_log(ql_log_info, vha, 0x0083,
  4090. "Fimware image unavailable.\n");
  4091. ql_log(ql_log_info, vha, 0x0084,
  4092. "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
  4093. return QLA_FUNCTION_FAILED;
  4094. }
  4095. rval = QLA_SUCCESS;
  4096. wcode = (uint16_t *)req->ring;
  4097. *srisc_addr = 0;
  4098. fwcode = (uint16_t *)blob->fw->data;
  4099. fwclen = 0;
  4100. /* Validate firmware image by checking version. */
  4101. if (blob->fw->size < 8 * sizeof(uint16_t)) {
  4102. ql_log(ql_log_fatal, vha, 0x0085,
  4103. "Unable to verify integrity of firmware image (%Zd).\n",
  4104. blob->fw->size);
  4105. goto fail_fw_integrity;
  4106. }
  4107. for (i = 0; i < 4; i++)
  4108. wcode[i] = be16_to_cpu(fwcode[i + 4]);
  4109. if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
  4110. wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
  4111. wcode[2] == 0 && wcode[3] == 0)) {
  4112. ql_log(ql_log_fatal, vha, 0x0086,
  4113. "Unable to verify integrity of firmware image.\n");
  4114. ql_log(ql_log_fatal, vha, 0x0087,
  4115. "Firmware data: %04x %04x %04x %04x.\n",
  4116. wcode[0], wcode[1], wcode[2], wcode[3]);
  4117. goto fail_fw_integrity;
  4118. }
  4119. seg = blob->segs;
  4120. while (*seg && rval == QLA_SUCCESS) {
  4121. risc_addr = *seg;
  4122. *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
  4123. risc_size = be16_to_cpu(fwcode[3]);
  4124. /* Validate firmware image size. */
  4125. fwclen += risc_size * sizeof(uint16_t);
  4126. if (blob->fw->size < fwclen) {
  4127. ql_log(ql_log_fatal, vha, 0x0088,
  4128. "Unable to verify integrity of firmware image "
  4129. "(%Zd).\n", blob->fw->size);
  4130. goto fail_fw_integrity;
  4131. }
  4132. fragment = 0;
  4133. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4134. wlen = (uint16_t)(ha->fw_transfer_size >> 1);
  4135. if (wlen > risc_size)
  4136. wlen = risc_size;
  4137. ql_dbg(ql_dbg_init, vha, 0x0089,
  4138. "Loading risc segment@ risc addr %x number of "
  4139. "words 0x%x.\n", risc_addr, wlen);
  4140. for (i = 0; i < wlen; i++)
  4141. wcode[i] = swab16(fwcode[i]);
  4142. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4143. wlen);
  4144. if (rval) {
  4145. ql_log(ql_log_fatal, vha, 0x008a,
  4146. "Failed to load segment %d of firmware.\n",
  4147. fragment);
  4148. break;
  4149. }
  4150. fwcode += wlen;
  4151. risc_addr += wlen;
  4152. risc_size -= wlen;
  4153. fragment++;
  4154. }
  4155. /* Next segment. */
  4156. seg++;
  4157. }
  4158. return rval;
  4159. fail_fw_integrity:
  4160. return QLA_FUNCTION_FAILED;
  4161. }
  4162. static int
  4163. qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4164. {
  4165. int rval;
  4166. int segments, fragment;
  4167. uint32_t *dcode, dlen;
  4168. uint32_t risc_addr;
  4169. uint32_t risc_size;
  4170. uint32_t i;
  4171. struct fw_blob *blob;
  4172. uint32_t *fwcode, fwclen;
  4173. struct qla_hw_data *ha = vha->hw;
  4174. struct req_que *req = ha->req_q_map[0];
  4175. /* Load firmware blob. */
  4176. blob = qla2x00_request_firmware(vha);
  4177. if (!blob) {
  4178. ql_log(ql_log_warn, vha, 0x0090,
  4179. "Fimware image unavailable.\n");
  4180. ql_log(ql_log_warn, vha, 0x0091,
  4181. "Firmware images can be retrieved from: "
  4182. QLA_FW_URL ".\n");
  4183. return QLA_FUNCTION_FAILED;
  4184. }
  4185. ql_dbg(ql_dbg_init, vha, 0x0092,
  4186. "FW: Loading via request-firmware.\n");
  4187. rval = QLA_SUCCESS;
  4188. segments = FA_RISC_CODE_SEGMENTS;
  4189. dcode = (uint32_t *)req->ring;
  4190. *srisc_addr = 0;
  4191. fwcode = (uint32_t *)blob->fw->data;
  4192. fwclen = 0;
  4193. /* Validate firmware image by checking version. */
  4194. if (blob->fw->size < 8 * sizeof(uint32_t)) {
  4195. ql_log(ql_log_fatal, vha, 0x0093,
  4196. "Unable to verify integrity of firmware image (%Zd).\n",
  4197. blob->fw->size);
  4198. goto fail_fw_integrity;
  4199. }
  4200. for (i = 0; i < 4; i++)
  4201. dcode[i] = be32_to_cpu(fwcode[i + 4]);
  4202. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  4203. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  4204. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  4205. dcode[3] == 0)) {
  4206. ql_log(ql_log_fatal, vha, 0x0094,
  4207. "Unable to verify integrity of firmware image (%Zd).\n",
  4208. blob->fw->size);
  4209. ql_log(ql_log_fatal, vha, 0x0095,
  4210. "Firmware data: %08x %08x %08x %08x.\n",
  4211. dcode[0], dcode[1], dcode[2], dcode[3]);
  4212. goto fail_fw_integrity;
  4213. }
  4214. while (segments && rval == QLA_SUCCESS) {
  4215. risc_addr = be32_to_cpu(fwcode[2]);
  4216. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  4217. risc_size = be32_to_cpu(fwcode[3]);
  4218. /* Validate firmware image size. */
  4219. fwclen += risc_size * sizeof(uint32_t);
  4220. if (blob->fw->size < fwclen) {
  4221. ql_log(ql_log_fatal, vha, 0x0096,
  4222. "Unable to verify integrity of firmware image "
  4223. "(%Zd).\n", blob->fw->size);
  4224. goto fail_fw_integrity;
  4225. }
  4226. fragment = 0;
  4227. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4228. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  4229. if (dlen > risc_size)
  4230. dlen = risc_size;
  4231. ql_dbg(ql_dbg_init, vha, 0x0097,
  4232. "Loading risc segment@ risc addr %x "
  4233. "number of dwords 0x%x.\n", risc_addr, dlen);
  4234. for (i = 0; i < dlen; i++)
  4235. dcode[i] = swab32(fwcode[i]);
  4236. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4237. dlen);
  4238. if (rval) {
  4239. ql_log(ql_log_fatal, vha, 0x0098,
  4240. "Failed to load segment %d of firmware.\n",
  4241. fragment);
  4242. break;
  4243. }
  4244. fwcode += dlen;
  4245. risc_addr += dlen;
  4246. risc_size -= dlen;
  4247. fragment++;
  4248. }
  4249. /* Next segment. */
  4250. segments--;
  4251. }
  4252. return rval;
  4253. fail_fw_integrity:
  4254. return QLA_FUNCTION_FAILED;
  4255. }
  4256. int
  4257. qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4258. {
  4259. int rval;
  4260. if (ql2xfwloadbin == 1)
  4261. return qla81xx_load_risc(vha, srisc_addr);
  4262. /*
  4263. * FW Load priority:
  4264. * 1) Firmware via request-firmware interface (.bin file).
  4265. * 2) Firmware residing in flash.
  4266. */
  4267. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4268. if (rval == QLA_SUCCESS)
  4269. return rval;
  4270. return qla24xx_load_risc_flash(vha, srisc_addr,
  4271. vha->hw->flt_region_fw);
  4272. }
  4273. int
  4274. qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4275. {
  4276. int rval;
  4277. struct qla_hw_data *ha = vha->hw;
  4278. if (ql2xfwloadbin == 2)
  4279. goto try_blob_fw;
  4280. /*
  4281. * FW Load priority:
  4282. * 1) Firmware residing in flash.
  4283. * 2) Firmware via request-firmware interface (.bin file).
  4284. * 3) Golden-Firmware residing in flash -- limited operation.
  4285. */
  4286. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
  4287. if (rval == QLA_SUCCESS)
  4288. return rval;
  4289. try_blob_fw:
  4290. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4291. if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
  4292. return rval;
  4293. ql_log(ql_log_info, vha, 0x0099,
  4294. "Attempting to fallback to golden firmware.\n");
  4295. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
  4296. if (rval != QLA_SUCCESS)
  4297. return rval;
  4298. ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
  4299. ha->flags.running_gold_fw = 1;
  4300. return rval;
  4301. }
  4302. void
  4303. qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
  4304. {
  4305. int ret, retries;
  4306. struct qla_hw_data *ha = vha->hw;
  4307. if (ha->flags.pci_channel_io_perm_failure)
  4308. return;
  4309. if (!IS_FWI2_CAPABLE(ha))
  4310. return;
  4311. if (!ha->fw_major_version)
  4312. return;
  4313. ret = qla2x00_stop_firmware(vha);
  4314. for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
  4315. ret != QLA_INVALID_COMMAND && retries ; retries--) {
  4316. ha->isp_ops->reset_chip(vha);
  4317. if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
  4318. continue;
  4319. if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
  4320. continue;
  4321. ql_log(ql_log_info, vha, 0x8015,
  4322. "Attempting retry of stop-firmware command.\n");
  4323. ret = qla2x00_stop_firmware(vha);
  4324. }
  4325. }
  4326. int
  4327. qla24xx_configure_vhba(scsi_qla_host_t *vha)
  4328. {
  4329. int rval = QLA_SUCCESS;
  4330. uint16_t mb[MAILBOX_REGISTER_COUNT];
  4331. struct qla_hw_data *ha = vha->hw;
  4332. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  4333. struct req_que *req;
  4334. struct rsp_que *rsp;
  4335. if (!vha->vp_idx)
  4336. return -EINVAL;
  4337. rval = qla2x00_fw_ready(base_vha);
  4338. if (ha->flags.cpu_affinity_enabled)
  4339. req = ha->req_q_map[0];
  4340. else
  4341. req = vha->req;
  4342. rsp = req->rsp;
  4343. if (rval == QLA_SUCCESS) {
  4344. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4345. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4346. }
  4347. vha->flags.management_server_logged_in = 0;
  4348. /* Login to SNS first */
  4349. ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, BIT_1);
  4350. if (mb[0] != MBS_COMMAND_COMPLETE) {
  4351. ql_dbg(ql_dbg_init, vha, 0x0103,
  4352. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
  4353. "mb[6]=%x mb[7]=%x.\n",
  4354. NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
  4355. return (QLA_FUNCTION_FAILED);
  4356. }
  4357. atomic_set(&vha->loop_down_timer, 0);
  4358. atomic_set(&vha->loop_state, LOOP_UP);
  4359. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4360. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  4361. rval = qla2x00_loop_resync(base_vha);
  4362. return rval;
  4363. }
  4364. /* 84XX Support **************************************************************/
  4365. static LIST_HEAD(qla_cs84xx_list);
  4366. static DEFINE_MUTEX(qla_cs84xx_mutex);
  4367. static struct qla_chip_state_84xx *
  4368. qla84xx_get_chip(struct scsi_qla_host *vha)
  4369. {
  4370. struct qla_chip_state_84xx *cs84xx;
  4371. struct qla_hw_data *ha = vha->hw;
  4372. mutex_lock(&qla_cs84xx_mutex);
  4373. /* Find any shared 84xx chip. */
  4374. list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
  4375. if (cs84xx->bus == ha->pdev->bus) {
  4376. kref_get(&cs84xx->kref);
  4377. goto done;
  4378. }
  4379. }
  4380. cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
  4381. if (!cs84xx)
  4382. goto done;
  4383. kref_init(&cs84xx->kref);
  4384. spin_lock_init(&cs84xx->access_lock);
  4385. mutex_init(&cs84xx->fw_update_mutex);
  4386. cs84xx->bus = ha->pdev->bus;
  4387. list_add_tail(&cs84xx->list, &qla_cs84xx_list);
  4388. done:
  4389. mutex_unlock(&qla_cs84xx_mutex);
  4390. return cs84xx;
  4391. }
  4392. static void
  4393. __qla84xx_chip_release(struct kref *kref)
  4394. {
  4395. struct qla_chip_state_84xx *cs84xx =
  4396. container_of(kref, struct qla_chip_state_84xx, kref);
  4397. mutex_lock(&qla_cs84xx_mutex);
  4398. list_del(&cs84xx->list);
  4399. mutex_unlock(&qla_cs84xx_mutex);
  4400. kfree(cs84xx);
  4401. }
  4402. void
  4403. qla84xx_put_chip(struct scsi_qla_host *vha)
  4404. {
  4405. struct qla_hw_data *ha = vha->hw;
  4406. if (ha->cs84xx)
  4407. kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
  4408. }
  4409. static int
  4410. qla84xx_init_chip(scsi_qla_host_t *vha)
  4411. {
  4412. int rval;
  4413. uint16_t status[2];
  4414. struct qla_hw_data *ha = vha->hw;
  4415. mutex_lock(&ha->cs84xx->fw_update_mutex);
  4416. rval = qla84xx_verify_chip(vha, status);
  4417. mutex_unlock(&ha->cs84xx->fw_update_mutex);
  4418. return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
  4419. QLA_SUCCESS;
  4420. }
  4421. /* 81XX Support **************************************************************/
  4422. int
  4423. qla81xx_nvram_config(scsi_qla_host_t *vha)
  4424. {
  4425. int rval;
  4426. struct init_cb_81xx *icb;
  4427. struct nvram_81xx *nv;
  4428. uint32_t *dptr;
  4429. uint8_t *dptr1, *dptr2;
  4430. uint32_t chksum;
  4431. uint16_t cnt;
  4432. struct qla_hw_data *ha = vha->hw;
  4433. rval = QLA_SUCCESS;
  4434. icb = (struct init_cb_81xx *)ha->init_cb;
  4435. nv = ha->nvram;
  4436. /* Determine NVRAM starting address. */
  4437. ha->nvram_size = sizeof(struct nvram_81xx);
  4438. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  4439. /* Get VPD data into cache */
  4440. ha->vpd = ha->nvram + VPD_OFFSET;
  4441. ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
  4442. ha->vpd_size);
  4443. /* Get NVRAM data into cache and calculate checksum. */
  4444. ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
  4445. ha->nvram_size);
  4446. dptr = (uint32_t *)nv;
  4447. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  4448. chksum += le32_to_cpu(*dptr++);
  4449. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
  4450. "Contents of NVRAM:\n");
  4451. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
  4452. (uint8_t *)nv, ha->nvram_size);
  4453. /* Bad NVRAM data, set defaults parameters. */
  4454. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  4455. || nv->id[3] != ' ' ||
  4456. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  4457. /* Reset NVRAM data. */
  4458. ql_log(ql_log_info, vha, 0x0073,
  4459. "Inconisistent NVRAM detected: checksum=0x%x id=%c "
  4460. "version=0x%x.\n", chksum, nv->id[0],
  4461. le16_to_cpu(nv->nvram_version));
  4462. ql_log(ql_log_info, vha, 0x0074,
  4463. "Falling back to functioning (yet invalid -- WWPN) "
  4464. "defaults.\n");
  4465. /*
  4466. * Set default initialization control block.
  4467. */
  4468. memset(nv, 0, ha->nvram_size);
  4469. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  4470. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  4471. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  4472. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4473. nv->exchange_count = __constant_cpu_to_le16(0);
  4474. nv->port_name[0] = 0x21;
  4475. nv->port_name[1] = 0x00 + ha->port_no;
  4476. nv->port_name[2] = 0x00;
  4477. nv->port_name[3] = 0xe0;
  4478. nv->port_name[4] = 0x8b;
  4479. nv->port_name[5] = 0x1c;
  4480. nv->port_name[6] = 0x55;
  4481. nv->port_name[7] = 0x86;
  4482. nv->node_name[0] = 0x20;
  4483. nv->node_name[1] = 0x00;
  4484. nv->node_name[2] = 0x00;
  4485. nv->node_name[3] = 0xe0;
  4486. nv->node_name[4] = 0x8b;
  4487. nv->node_name[5] = 0x1c;
  4488. nv->node_name[6] = 0x55;
  4489. nv->node_name[7] = 0x86;
  4490. nv->login_retry_count = __constant_cpu_to_le16(8);
  4491. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  4492. nv->login_timeout = __constant_cpu_to_le16(0);
  4493. nv->firmware_options_1 =
  4494. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  4495. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  4496. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  4497. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  4498. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  4499. nv->efi_parameters = __constant_cpu_to_le32(0);
  4500. nv->reset_delay = 5;
  4501. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  4502. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  4503. nv->link_down_timeout = __constant_cpu_to_le16(30);
  4504. nv->enode_mac[0] = 0x00;
  4505. nv->enode_mac[1] = 0x02;
  4506. nv->enode_mac[2] = 0x03;
  4507. nv->enode_mac[3] = 0x04;
  4508. nv->enode_mac[4] = 0x05;
  4509. nv->enode_mac[5] = 0x06 + ha->port_no;
  4510. rval = 1;
  4511. }
  4512. /* Reset Initialization control block */
  4513. memset(icb, 0, ha->init_cb_size);
  4514. /* Copy 1st segment. */
  4515. dptr1 = (uint8_t *)icb;
  4516. dptr2 = (uint8_t *)&nv->version;
  4517. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  4518. while (cnt--)
  4519. *dptr1++ = *dptr2++;
  4520. icb->login_retry_count = nv->login_retry_count;
  4521. /* Copy 2nd segment. */
  4522. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  4523. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  4524. cnt = (uint8_t *)&icb->reserved_5 -
  4525. (uint8_t *)&icb->interrupt_delay_timer;
  4526. while (cnt--)
  4527. *dptr1++ = *dptr2++;
  4528. memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
  4529. /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
  4530. if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
  4531. icb->enode_mac[0] = 0x01;
  4532. icb->enode_mac[1] = 0x02;
  4533. icb->enode_mac[2] = 0x03;
  4534. icb->enode_mac[3] = 0x04;
  4535. icb->enode_mac[4] = 0x05;
  4536. icb->enode_mac[5] = 0x06 + ha->port_no;
  4537. }
  4538. /* Use extended-initialization control block. */
  4539. memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
  4540. /*
  4541. * Setup driver NVRAM options.
  4542. */
  4543. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  4544. "QLE8XXX");
  4545. /* Use alternate WWN? */
  4546. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  4547. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  4548. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  4549. }
  4550. /* Prepare nodename */
  4551. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  4552. /*
  4553. * Firmware will apply the following mask if the nodename was
  4554. * not provided.
  4555. */
  4556. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  4557. icb->node_name[0] &= 0xF0;
  4558. }
  4559. /* Set host adapter parameters. */
  4560. ha->flags.disable_risc_code_load = 0;
  4561. ha->flags.enable_lip_reset = 0;
  4562. ha->flags.enable_lip_full_login =
  4563. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  4564. ha->flags.enable_target_reset =
  4565. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  4566. ha->flags.enable_led_scheme = 0;
  4567. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  4568. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  4569. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  4570. /* save HBA serial number */
  4571. ha->serial0 = icb->port_name[5];
  4572. ha->serial1 = icb->port_name[6];
  4573. ha->serial2 = icb->port_name[7];
  4574. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  4575. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  4576. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4577. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  4578. /* Set minimum login_timeout to 4 seconds. */
  4579. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  4580. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  4581. if (le16_to_cpu(nv->login_timeout) < 4)
  4582. nv->login_timeout = __constant_cpu_to_le16(4);
  4583. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  4584. icb->login_timeout = nv->login_timeout;
  4585. /* Set minimum RATOV to 100 tenths of a second. */
  4586. ha->r_a_tov = 100;
  4587. ha->loop_reset_delay = nv->reset_delay;
  4588. /* Link Down Timeout = 0:
  4589. *
  4590. * When Port Down timer expires we will start returning
  4591. * I/O's to OS with "DID_NO_CONNECT".
  4592. *
  4593. * Link Down Timeout != 0:
  4594. *
  4595. * The driver waits for the link to come up after link down
  4596. * before returning I/Os to OS with "DID_NO_CONNECT".
  4597. */
  4598. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  4599. ha->loop_down_abort_time =
  4600. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  4601. } else {
  4602. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  4603. ha->loop_down_abort_time =
  4604. (LOOP_DOWN_TIME - ha->link_down_timeout);
  4605. }
  4606. /* Need enough time to try and get the port back. */
  4607. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  4608. if (qlport_down_retry)
  4609. ha->port_down_retry_count = qlport_down_retry;
  4610. /* Set login_retry_count */
  4611. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  4612. if (ha->port_down_retry_count ==
  4613. le16_to_cpu(nv->port_down_retry_count) &&
  4614. ha->port_down_retry_count > 3)
  4615. ha->login_retry_count = ha->port_down_retry_count;
  4616. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  4617. ha->login_retry_count = ha->port_down_retry_count;
  4618. if (ql2xloginretrycount)
  4619. ha->login_retry_count = ql2xloginretrycount;
  4620. /* Enable ZIO. */
  4621. if (!vha->flags.init_done) {
  4622. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  4623. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  4624. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  4625. le16_to_cpu(icb->interrupt_delay_timer): 2;
  4626. }
  4627. icb->firmware_options_2 &= __constant_cpu_to_le32(
  4628. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  4629. vha->flags.process_response_queue = 0;
  4630. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  4631. ha->zio_mode = QLA_ZIO_MODE_6;
  4632. ql_log(ql_log_info, vha, 0x0075,
  4633. "ZIO mode %d enabled; timer delay (%d us).\n",
  4634. ha->zio_mode,
  4635. ha->zio_timer * 100);
  4636. icb->firmware_options_2 |= cpu_to_le32(
  4637. (uint32_t)ha->zio_mode);
  4638. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  4639. vha->flags.process_response_queue = 1;
  4640. }
  4641. if (rval) {
  4642. ql_log(ql_log_warn, vha, 0x0076,
  4643. "NVRAM configuration failed.\n");
  4644. }
  4645. return (rval);
  4646. }
  4647. int
  4648. qla82xx_restart_isp(scsi_qla_host_t *vha)
  4649. {
  4650. int status, rval;
  4651. uint32_t wait_time;
  4652. struct qla_hw_data *ha = vha->hw;
  4653. struct req_que *req = ha->req_q_map[0];
  4654. struct rsp_que *rsp = ha->rsp_q_map[0];
  4655. struct scsi_qla_host *vp;
  4656. unsigned long flags;
  4657. status = qla2x00_init_rings(vha);
  4658. if (!status) {
  4659. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4660. ha->flags.chip_reset_done = 1;
  4661. status = qla2x00_fw_ready(vha);
  4662. if (!status) {
  4663. ql_log(ql_log_info, vha, 0x803c,
  4664. "Start configure loop, status =%d.\n", status);
  4665. /* Issue a marker after FW becomes ready. */
  4666. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4667. vha->flags.online = 1;
  4668. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  4669. wait_time = 256;
  4670. do {
  4671. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4672. qla2x00_configure_loop(vha);
  4673. wait_time--;
  4674. } while (!atomic_read(&vha->loop_down_timer) &&
  4675. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
  4676. wait_time &&
  4677. (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
  4678. }
  4679. /* if no cable then assume it's good */
  4680. if ((vha->device_flags & DFLG_NO_CABLE))
  4681. status = 0;
  4682. ql_log(ql_log_info, vha, 0x8000,
  4683. "Configure loop done, status = 0x%x.\n", status);
  4684. }
  4685. if (!status) {
  4686. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4687. if (!atomic_read(&vha->loop_down_timer)) {
  4688. /*
  4689. * Issue marker command only when we are going
  4690. * to start the I/O .
  4691. */
  4692. vha->marker_needed = 1;
  4693. }
  4694. vha->flags.online = 1;
  4695. ha->isp_ops->enable_intrs(ha);
  4696. ha->isp_abort_cnt = 0;
  4697. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  4698. /* Update the firmware version */
  4699. status = qla82xx_check_md_needed(vha);
  4700. if (ha->fce) {
  4701. ha->flags.fce_enabled = 1;
  4702. memset(ha->fce, 0,
  4703. fce_calc_size(ha->fce_bufs));
  4704. rval = qla2x00_enable_fce_trace(vha,
  4705. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  4706. &ha->fce_bufs);
  4707. if (rval) {
  4708. ql_log(ql_log_warn, vha, 0x8001,
  4709. "Unable to reinitialize FCE (%d).\n",
  4710. rval);
  4711. ha->flags.fce_enabled = 0;
  4712. }
  4713. }
  4714. if (ha->eft) {
  4715. memset(ha->eft, 0, EFT_SIZE);
  4716. rval = qla2x00_enable_eft_trace(vha,
  4717. ha->eft_dma, EFT_NUM_BUFFERS);
  4718. if (rval) {
  4719. ql_log(ql_log_warn, vha, 0x8010,
  4720. "Unable to reinitialize EFT (%d).\n",
  4721. rval);
  4722. }
  4723. }
  4724. }
  4725. if (!status) {
  4726. ql_dbg(ql_dbg_taskm, vha, 0x8011,
  4727. "qla82xx_restart_isp succeeded.\n");
  4728. spin_lock_irqsave(&ha->vport_slock, flags);
  4729. list_for_each_entry(vp, &ha->vp_list, list) {
  4730. if (vp->vp_idx) {
  4731. atomic_inc(&vp->vref_count);
  4732. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4733. qla2x00_vp_abort_isp(vp);
  4734. spin_lock_irqsave(&ha->vport_slock, flags);
  4735. atomic_dec(&vp->vref_count);
  4736. }
  4737. }
  4738. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4739. } else {
  4740. ql_log(ql_log_warn, vha, 0x8016,
  4741. "qla82xx_restart_isp **** FAILED ****.\n");
  4742. }
  4743. return status;
  4744. }
  4745. void
  4746. qla81xx_update_fw_options(scsi_qla_host_t *vha)
  4747. {
  4748. struct qla_hw_data *ha = vha->hw;
  4749. if (!ql2xetsenable)
  4750. return;
  4751. /* Enable ETS Burst. */
  4752. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  4753. ha->fw_options[2] |= BIT_9;
  4754. qla2x00_set_fw_options(vha, ha->fw_options);
  4755. }
  4756. /*
  4757. * qla24xx_get_fcp_prio
  4758. * Gets the fcp cmd priority value for the logged in port.
  4759. * Looks for a match of the port descriptors within
  4760. * each of the fcp prio config entries. If a match is found,
  4761. * the tag (priority) value is returned.
  4762. *
  4763. * Input:
  4764. * vha = scsi host structure pointer.
  4765. * fcport = port structure pointer.
  4766. *
  4767. * Return:
  4768. * non-zero (if found)
  4769. * -1 (if not found)
  4770. *
  4771. * Context:
  4772. * Kernel context
  4773. */
  4774. static int
  4775. qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4776. {
  4777. int i, entries;
  4778. uint8_t pid_match, wwn_match;
  4779. int priority;
  4780. uint32_t pid1, pid2;
  4781. uint64_t wwn1, wwn2;
  4782. struct qla_fcp_prio_entry *pri_entry;
  4783. struct qla_hw_data *ha = vha->hw;
  4784. if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
  4785. return -1;
  4786. priority = -1;
  4787. entries = ha->fcp_prio_cfg->num_entries;
  4788. pri_entry = &ha->fcp_prio_cfg->entry[0];
  4789. for (i = 0; i < entries; i++) {
  4790. pid_match = wwn_match = 0;
  4791. if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
  4792. pri_entry++;
  4793. continue;
  4794. }
  4795. /* check source pid for a match */
  4796. if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
  4797. pid1 = pri_entry->src_pid & INVALID_PORT_ID;
  4798. pid2 = vha->d_id.b24 & INVALID_PORT_ID;
  4799. if (pid1 == INVALID_PORT_ID)
  4800. pid_match++;
  4801. else if (pid1 == pid2)
  4802. pid_match++;
  4803. }
  4804. /* check destination pid for a match */
  4805. if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
  4806. pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
  4807. pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
  4808. if (pid1 == INVALID_PORT_ID)
  4809. pid_match++;
  4810. else if (pid1 == pid2)
  4811. pid_match++;
  4812. }
  4813. /* check source WWN for a match */
  4814. if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
  4815. wwn1 = wwn_to_u64(vha->port_name);
  4816. wwn2 = wwn_to_u64(pri_entry->src_wwpn);
  4817. if (wwn2 == (uint64_t)-1)
  4818. wwn_match++;
  4819. else if (wwn1 == wwn2)
  4820. wwn_match++;
  4821. }
  4822. /* check destination WWN for a match */
  4823. if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
  4824. wwn1 = wwn_to_u64(fcport->port_name);
  4825. wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
  4826. if (wwn2 == (uint64_t)-1)
  4827. wwn_match++;
  4828. else if (wwn1 == wwn2)
  4829. wwn_match++;
  4830. }
  4831. if (pid_match == 2 || wwn_match == 2) {
  4832. /* Found a matching entry */
  4833. if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
  4834. priority = pri_entry->tag;
  4835. break;
  4836. }
  4837. pri_entry++;
  4838. }
  4839. return priority;
  4840. }
  4841. /*
  4842. * qla24xx_update_fcport_fcp_prio
  4843. * Activates fcp priority for the logged in fc port
  4844. *
  4845. * Input:
  4846. * vha = scsi host structure pointer.
  4847. * fcp = port structure pointer.
  4848. *
  4849. * Return:
  4850. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4851. *
  4852. * Context:
  4853. * Kernel context.
  4854. */
  4855. int
  4856. qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4857. {
  4858. int ret;
  4859. int priority;
  4860. uint16_t mb[5];
  4861. if (fcport->port_type != FCT_TARGET ||
  4862. fcport->loop_id == FC_NO_LOOP_ID)
  4863. return QLA_FUNCTION_FAILED;
  4864. priority = qla24xx_get_fcp_prio(vha, fcport);
  4865. if (priority < 0)
  4866. return QLA_FUNCTION_FAILED;
  4867. if (IS_QLA82XX(vha->hw)) {
  4868. fcport->fcp_prio = priority & 0xf;
  4869. return QLA_SUCCESS;
  4870. }
  4871. ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
  4872. if (ret == QLA_SUCCESS) {
  4873. if (fcport->fcp_prio != priority)
  4874. ql_dbg(ql_dbg_user, vha, 0x709e,
  4875. "Updated FCP_CMND priority - value=%d loop_id=%d "
  4876. "port_id=%02x%02x%02x.\n", priority,
  4877. fcport->loop_id, fcport->d_id.b.domain,
  4878. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  4879. fcport->fcp_prio = priority & 0xf;
  4880. } else
  4881. ql_dbg(ql_dbg_user, vha, 0x704f,
  4882. "Unable to update FCP_CMND priority - ret=0x%x for "
  4883. "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
  4884. fcport->d_id.b.domain, fcport->d_id.b.area,
  4885. fcport->d_id.b.al_pa);
  4886. return ret;
  4887. }
  4888. /*
  4889. * qla24xx_update_all_fcp_prio
  4890. * Activates fcp priority for all the logged in ports
  4891. *
  4892. * Input:
  4893. * ha = adapter block pointer.
  4894. *
  4895. * Return:
  4896. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4897. *
  4898. * Context:
  4899. * Kernel context.
  4900. */
  4901. int
  4902. qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
  4903. {
  4904. int ret;
  4905. fc_port_t *fcport;
  4906. ret = QLA_FUNCTION_FAILED;
  4907. /* We need to set priority for all logged in ports */
  4908. list_for_each_entry(fcport, &vha->vp_fcports, list)
  4909. ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
  4910. return ret;
  4911. }