vitesse.c 6.0 KB

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  1. /*
  2. * Driver for Vitesse PHYs
  3. *
  4. * Author: Kriston Carson
  5. *
  6. * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/mii.h>
  17. #include <linux/ethtool.h>
  18. #include <linux/phy.h>
  19. /* Vitesse Extended Control Register 1 */
  20. #define MII_VSC8244_EXT_CON1 0x17
  21. #define MII_VSC8244_EXTCON1_INIT 0x0000
  22. #define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00
  23. #define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300
  24. #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
  25. #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
  26. /* Vitesse Interrupt Mask Register */
  27. #define MII_VSC8244_IMASK 0x19
  28. #define MII_VSC8244_IMASK_IEN 0x8000
  29. #define MII_VSC8244_IMASK_SPEED 0x4000
  30. #define MII_VSC8244_IMASK_LINK 0x2000
  31. #define MII_VSC8244_IMASK_DUPLEX 0x1000
  32. #define MII_VSC8244_IMASK_MASK 0xf000
  33. #define MII_VSC8221_IMASK_MASK 0xa000
  34. /* Vitesse Interrupt Status Register */
  35. #define MII_VSC8244_ISTAT 0x1a
  36. #define MII_VSC8244_ISTAT_STATUS 0x8000
  37. #define MII_VSC8244_ISTAT_SPEED 0x4000
  38. #define MII_VSC8244_ISTAT_LINK 0x2000
  39. #define MII_VSC8244_ISTAT_DUPLEX 0x1000
  40. /* Vitesse Auxiliary Control/Status Register */
  41. #define MII_VSC8244_AUX_CONSTAT 0x1c
  42. #define MII_VSC8244_AUXCONSTAT_INIT 0x0000
  43. #define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
  44. #define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
  45. #define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
  46. #define MII_VSC8244_AUXCONSTAT_100 0x0008
  47. #define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */
  48. #define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
  49. #define PHY_ID_VSC8234 0x000fc620
  50. #define PHY_ID_VSC8244 0x000fc6c0
  51. #define PHY_ID_VSC8221 0x000fc550
  52. #define PHY_ID_VSC8211 0x000fc4b0
  53. MODULE_DESCRIPTION("Vitesse PHY driver");
  54. MODULE_AUTHOR("Kriston Carson");
  55. MODULE_LICENSE("GPL");
  56. static int vsc824x_add_skew(struct phy_device *phydev)
  57. {
  58. int err;
  59. int extcon;
  60. extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
  61. if (extcon < 0)
  62. return extcon;
  63. extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
  64. MII_VSC8244_EXTCON1_RX_SKEW_MASK);
  65. extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
  66. MII_VSC8244_EXTCON1_RX_SKEW);
  67. err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
  68. return err;
  69. }
  70. static int vsc824x_config_init(struct phy_device *phydev)
  71. {
  72. int err;
  73. err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
  74. MII_VSC8244_AUXCONSTAT_INIT);
  75. if (err < 0)
  76. return err;
  77. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
  78. err = vsc824x_add_skew(phydev);
  79. return err;
  80. }
  81. static int vsc824x_ack_interrupt(struct phy_device *phydev)
  82. {
  83. int err = 0;
  84. /* Don't bother to ACK the interrupts if interrupts
  85. * are disabled. The 824x cannot clear the interrupts
  86. * if they are disabled.
  87. */
  88. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  89. err = phy_read(phydev, MII_VSC8244_ISTAT);
  90. return (err < 0) ? err : 0;
  91. }
  92. static int vsc82xx_config_intr(struct phy_device *phydev)
  93. {
  94. int err;
  95. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  96. err = phy_write(phydev, MII_VSC8244_IMASK,
  97. (phydev->drv->phy_id == PHY_ID_VSC8234 ||
  98. phydev->drv->phy_id == PHY_ID_VSC8244) ?
  99. MII_VSC8244_IMASK_MASK :
  100. MII_VSC8221_IMASK_MASK);
  101. else {
  102. /* The Vitesse PHY cannot clear the interrupt
  103. * once it has disabled them, so we clear them first
  104. */
  105. err = phy_read(phydev, MII_VSC8244_ISTAT);
  106. if (err < 0)
  107. return err;
  108. err = phy_write(phydev, MII_VSC8244_IMASK, 0);
  109. }
  110. return err;
  111. }
  112. static int vsc8221_config_init(struct phy_device *phydev)
  113. {
  114. int err;
  115. err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
  116. MII_VSC8221_AUXCONSTAT_INIT);
  117. return err;
  118. /* Perhaps we should set EXT_CON1 based on the interface?
  119. * Options are 802.3Z SerDes or SGMII
  120. */
  121. }
  122. /* Vitesse 82xx */
  123. static struct phy_driver vsc82xx_driver[] = {
  124. {
  125. .phy_id = PHY_ID_VSC8234,
  126. .name = "Vitesse VSC8234",
  127. .phy_id_mask = 0x000ffff0,
  128. .features = PHY_GBIT_FEATURES,
  129. .flags = PHY_HAS_INTERRUPT,
  130. .config_init = &vsc824x_config_init,
  131. .config_aneg = &genphy_config_aneg,
  132. .read_status = &genphy_read_status,
  133. .ack_interrupt = &vsc824x_ack_interrupt,
  134. .config_intr = &vsc82xx_config_intr,
  135. .driver = { .owner = THIS_MODULE,},
  136. }, {
  137. .phy_id = PHY_ID_VSC8244,
  138. .name = "Vitesse VSC8244",
  139. .phy_id_mask = 0x000fffc0,
  140. .features = PHY_GBIT_FEATURES,
  141. .flags = PHY_HAS_INTERRUPT,
  142. .config_init = &vsc824x_config_init,
  143. .config_aneg = &genphy_config_aneg,
  144. .read_status = &genphy_read_status,
  145. .ack_interrupt = &vsc824x_ack_interrupt,
  146. .config_intr = &vsc82xx_config_intr,
  147. .driver = { .owner = THIS_MODULE,},
  148. }, {
  149. /* Vitesse 8221 */
  150. .phy_id = PHY_ID_VSC8221,
  151. .phy_id_mask = 0x000ffff0,
  152. .name = "Vitesse VSC8221",
  153. .features = PHY_GBIT_FEATURES,
  154. .flags = PHY_HAS_INTERRUPT,
  155. .config_init = &vsc8221_config_init,
  156. .config_aneg = &genphy_config_aneg,
  157. .read_status = &genphy_read_status,
  158. .ack_interrupt = &vsc824x_ack_interrupt,
  159. .config_intr = &vsc82xx_config_intr,
  160. .driver = { .owner = THIS_MODULE,},
  161. }, {
  162. /* Vitesse 8211 */
  163. .phy_id = PHY_ID_VSC8211,
  164. .phy_id_mask = 0x000ffff0,
  165. .name = "Vitesse VSC8211",
  166. .features = PHY_GBIT_FEATURES,
  167. .flags = PHY_HAS_INTERRUPT,
  168. .config_init = &vsc8221_config_init,
  169. .config_aneg = &genphy_config_aneg,
  170. .read_status = &genphy_read_status,
  171. .ack_interrupt = &vsc824x_ack_interrupt,
  172. .config_intr = &vsc82xx_config_intr,
  173. .driver = { .owner = THIS_MODULE,},
  174. } };
  175. static int __init vsc82xx_init(void)
  176. {
  177. return phy_drivers_register(vsc82xx_driver,
  178. ARRAY_SIZE(vsc82xx_driver));
  179. }
  180. static void __exit vsc82xx_exit(void)
  181. {
  182. return phy_drivers_unregister(vsc82xx_driver,
  183. ARRAY_SIZE(vsc82xx_driver));
  184. }
  185. module_init(vsc82xx_init);
  186. module_exit(vsc82xx_exit);
  187. static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
  188. { PHY_ID_VSC8234, 0x000ffff0 },
  189. { PHY_ID_VSC8244, 0x000fffc0 },
  190. { PHY_ID_VSC8221, 0x000ffff0 },
  191. { PHY_ID_VSC8211, 0x000ffff0 },
  192. { }
  193. };
  194. MODULE_DEVICE_TABLE(mdio, vitesse_tbl);