em28xx-core.c 29 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194
  1. /*
  2. em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
  3. Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
  4. Markus Rechberger <mrechberger@gmail.com>
  5. Mauro Carvalho Chehab <mchehab@infradead.org>
  6. Sascha Sommer <saschasommer@freenet.de>
  7. This program is free software; you can redistribute it and/or modify
  8. it under the terms of the GNU General Public License as published by
  9. the Free Software Foundation; either version 2 of the License, or
  10. (at your option) any later version.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <linux/init.h>
  20. #include <linux/list.h>
  21. #include <linux/module.h>
  22. #include <linux/usb.h>
  23. #include <linux/vmalloc.h>
  24. #include <media/v4l2-common.h>
  25. #include "em28xx.h"
  26. /* #define ENABLE_DEBUG_ISOC_FRAMES */
  27. static unsigned int core_debug;
  28. module_param(core_debug, int, 0644);
  29. MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
  30. #define em28xx_coredbg(fmt, arg...) do {\
  31. if (core_debug) \
  32. printk(KERN_INFO "%s %s :"fmt, \
  33. dev->name, __func__ , ##arg); } while (0)
  34. static unsigned int reg_debug;
  35. module_param(reg_debug, int, 0644);
  36. MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
  37. #define em28xx_regdbg(fmt, arg...) do {\
  38. if (reg_debug) \
  39. printk(KERN_INFO "%s %s :"fmt, \
  40. dev->name, __func__ , ##arg); } while (0)
  41. static int alt = EM28XX_PINOUT;
  42. module_param(alt, int, 0644);
  43. MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
  44. /* FIXME */
  45. #define em28xx_isocdbg(fmt, arg...) do {\
  46. if (core_debug) \
  47. printk(KERN_INFO "%s %s :"fmt, \
  48. dev->name, __func__ , ##arg); } while (0)
  49. /*
  50. * em28xx_read_reg_req()
  51. * reads data from the usb device specifying bRequest
  52. */
  53. int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
  54. char *buf, int len)
  55. {
  56. int ret;
  57. int pipe = usb_rcvctrlpipe(dev->udev, 0);
  58. if (dev->state & DEV_DISCONNECTED)
  59. return -ENODEV;
  60. if (len > URB_MAX_CTRL_SIZE)
  61. return -EINVAL;
  62. if (reg_debug) {
  63. printk(KERN_DEBUG "(pipe 0x%08x): "
  64. "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
  65. pipe,
  66. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  67. req, 0, 0,
  68. reg & 0xff, reg >> 8,
  69. len & 0xff, len >> 8);
  70. }
  71. mutex_lock(&dev->ctrl_urb_lock);
  72. ret = usb_control_msg(dev->udev, pipe, req,
  73. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  74. 0x0000, reg, dev->urb_buf, len, HZ);
  75. if (ret < 0) {
  76. if (reg_debug)
  77. printk(" failed!\n");
  78. mutex_unlock(&dev->ctrl_urb_lock);
  79. return ret;
  80. }
  81. if (len)
  82. memcpy(buf, dev->urb_buf, len);
  83. mutex_unlock(&dev->ctrl_urb_lock);
  84. if (reg_debug) {
  85. int byte;
  86. printk("<<<");
  87. for (byte = 0; byte < len; byte++)
  88. printk(" %02x", (unsigned char)buf[byte]);
  89. printk("\n");
  90. }
  91. return ret;
  92. }
  93. /*
  94. * em28xx_read_reg_req()
  95. * reads data from the usb device specifying bRequest
  96. */
  97. int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
  98. {
  99. int ret;
  100. u8 val;
  101. ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
  102. if (ret < 0)
  103. return ret;
  104. return val;
  105. }
  106. int em28xx_read_reg(struct em28xx *dev, u16 reg)
  107. {
  108. return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
  109. }
  110. /*
  111. * em28xx_write_regs_req()
  112. * sends data to the usb device, specifying bRequest
  113. */
  114. int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
  115. int len)
  116. {
  117. int ret;
  118. int pipe = usb_sndctrlpipe(dev->udev, 0);
  119. if (dev->state & DEV_DISCONNECTED)
  120. return -ENODEV;
  121. if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
  122. return -EINVAL;
  123. if (reg_debug) {
  124. int byte;
  125. printk(KERN_DEBUG "(pipe 0x%08x): "
  126. "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
  127. pipe,
  128. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  129. req, 0, 0,
  130. reg & 0xff, reg >> 8,
  131. len & 0xff, len >> 8);
  132. for (byte = 0; byte < len; byte++)
  133. printk(" %02x", (unsigned char)buf[byte]);
  134. printk("\n");
  135. }
  136. mutex_lock(&dev->ctrl_urb_lock);
  137. memcpy(dev->urb_buf, buf, len);
  138. ret = usb_control_msg(dev->udev, pipe, req,
  139. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  140. 0x0000, reg, dev->urb_buf, len, HZ);
  141. mutex_unlock(&dev->ctrl_urb_lock);
  142. if (dev->wait_after_write)
  143. msleep(dev->wait_after_write);
  144. return ret;
  145. }
  146. int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
  147. {
  148. int rc;
  149. rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
  150. /* Stores GPO/GPIO values at the cache, if changed
  151. Only write values should be stored, since input on a GPIO
  152. register will return the input bits.
  153. Not sure what happens on reading GPO register.
  154. */
  155. if (rc >= 0) {
  156. if (reg == dev->reg_gpo_num)
  157. dev->reg_gpo = buf[0];
  158. else if (reg == dev->reg_gpio_num)
  159. dev->reg_gpio = buf[0];
  160. }
  161. return rc;
  162. }
  163. /* Write a single register */
  164. int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
  165. {
  166. return em28xx_write_regs(dev, reg, &val, 1);
  167. }
  168. /*
  169. * em28xx_write_reg_bits()
  170. * sets only some bits (specified by bitmask) of a register, by first reading
  171. * the actual value
  172. */
  173. static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
  174. u8 bitmask)
  175. {
  176. int oldval;
  177. u8 newval;
  178. /* Uses cache for gpo/gpio registers */
  179. if (reg == dev->reg_gpo_num)
  180. oldval = dev->reg_gpo;
  181. else if (reg == dev->reg_gpio_num)
  182. oldval = dev->reg_gpio;
  183. else
  184. oldval = em28xx_read_reg(dev, reg);
  185. if (oldval < 0)
  186. return oldval;
  187. newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
  188. return em28xx_write_regs(dev, reg, &newval, 1);
  189. }
  190. /*
  191. * em28xx_is_ac97_ready()
  192. * Checks if ac97 is ready
  193. */
  194. static int em28xx_is_ac97_ready(struct em28xx *dev)
  195. {
  196. int ret, i;
  197. /* Wait up to 50 ms for AC97 command to complete */
  198. for (i = 0; i < 10; i++, msleep(5)) {
  199. ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
  200. if (ret < 0)
  201. return ret;
  202. if (!(ret & 0x01))
  203. return 0;
  204. }
  205. em28xx_warn("AC97 command still being executed: not handled properly!\n");
  206. return -EBUSY;
  207. }
  208. /*
  209. * em28xx_read_ac97()
  210. * write a 16 bit value to the specified AC97 address (LSB first!)
  211. */
  212. int em28xx_read_ac97(struct em28xx *dev, u8 reg)
  213. {
  214. int ret;
  215. u8 addr = (reg & 0x7f) | 0x80;
  216. u16 val;
  217. ret = em28xx_is_ac97_ready(dev);
  218. if (ret < 0)
  219. return ret;
  220. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  221. if (ret < 0)
  222. return ret;
  223. ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
  224. (u8 *)&val, sizeof(val));
  225. if (ret < 0)
  226. return ret;
  227. return le16_to_cpu(val);
  228. }
  229. /*
  230. * em28xx_write_ac97()
  231. * write a 16 bit value to the specified AC97 address (LSB first!)
  232. */
  233. int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
  234. {
  235. int ret;
  236. u8 addr = reg & 0x7f;
  237. __le16 value;
  238. value = cpu_to_le16(val);
  239. ret = em28xx_is_ac97_ready(dev);
  240. if (ret < 0)
  241. return ret;
  242. ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
  243. if (ret < 0)
  244. return ret;
  245. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  246. if (ret < 0)
  247. return ret;
  248. return 0;
  249. }
  250. struct em28xx_vol_table {
  251. enum em28xx_amux mux;
  252. u8 reg;
  253. };
  254. static struct em28xx_vol_table inputs[] = {
  255. { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
  256. { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
  257. { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
  258. { EM28XX_AMUX_MIC, AC97_MIC_VOL },
  259. { EM28XX_AMUX_CD, AC97_CD_VOL },
  260. { EM28XX_AMUX_AUX, AC97_AUX_VOL },
  261. { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
  262. };
  263. static int set_ac97_input(struct em28xx *dev)
  264. {
  265. int ret, i;
  266. enum em28xx_amux amux = dev->ctl_ainput;
  267. /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
  268. em28xx should point to LINE IN, while AC97 should use VIDEO
  269. */
  270. if (amux == EM28XX_AMUX_VIDEO2)
  271. amux = EM28XX_AMUX_VIDEO;
  272. /* Mute all entres but the one that were selected */
  273. for (i = 0; i < ARRAY_SIZE(inputs); i++) {
  274. if (amux == inputs[i].mux)
  275. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
  276. else
  277. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
  278. if (ret < 0)
  279. em28xx_warn("couldn't setup AC97 register %d\n",
  280. inputs[i].reg);
  281. }
  282. return 0;
  283. }
  284. static int em28xx_set_audio_source(struct em28xx *dev)
  285. {
  286. int ret;
  287. u8 input;
  288. if (dev->board.is_em2800) {
  289. if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
  290. input = EM2800_AUDIO_SRC_TUNER;
  291. else
  292. input = EM2800_AUDIO_SRC_LINE;
  293. ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
  294. if (ret < 0)
  295. return ret;
  296. }
  297. if (dev->board.has_msp34xx)
  298. input = EM28XX_AUDIO_SRC_TUNER;
  299. else {
  300. switch (dev->ctl_ainput) {
  301. case EM28XX_AMUX_VIDEO:
  302. input = EM28XX_AUDIO_SRC_TUNER;
  303. break;
  304. default:
  305. input = EM28XX_AUDIO_SRC_LINE;
  306. break;
  307. }
  308. }
  309. if (dev->board.mute_gpio && dev->mute)
  310. em28xx_gpio_set(dev, dev->board.mute_gpio);
  311. else
  312. em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  313. ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
  314. if (ret < 0)
  315. return ret;
  316. msleep(5);
  317. switch (dev->audio_mode.ac97) {
  318. case EM28XX_NO_AC97:
  319. break;
  320. default:
  321. ret = set_ac97_input(dev);
  322. }
  323. return ret;
  324. }
  325. static const struct em28xx_vol_table outputs[] = {
  326. { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
  327. { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
  328. { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
  329. { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
  330. { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
  331. };
  332. int em28xx_audio_analog_set(struct em28xx *dev)
  333. {
  334. int ret, i;
  335. u8 xclk;
  336. if (!dev->audio_mode.has_audio)
  337. return 0;
  338. /* It is assumed that all devices use master volume for output.
  339. It would be possible to use also line output.
  340. */
  341. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  342. /* Mute all outputs */
  343. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  344. ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
  345. if (ret < 0)
  346. em28xx_warn("couldn't setup AC97 register %d\n",
  347. outputs[i].reg);
  348. }
  349. }
  350. xclk = dev->board.xclk & 0x7f;
  351. if (!dev->mute)
  352. xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
  353. ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
  354. if (ret < 0)
  355. return ret;
  356. msleep(10);
  357. /* Selects the proper audio input */
  358. ret = em28xx_set_audio_source(dev);
  359. /* Sets volume */
  360. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  361. int vol;
  362. em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200);
  363. em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031);
  364. em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80);
  365. /* LSB: left channel - both channels with the same level */
  366. vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
  367. /* Mute device, if needed */
  368. if (dev->mute)
  369. vol |= 0x8000;
  370. /* Sets volume */
  371. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  372. if (dev->ctl_aoutput & outputs[i].mux)
  373. ret = em28xx_write_ac97(dev, outputs[i].reg,
  374. vol);
  375. if (ret < 0)
  376. em28xx_warn("couldn't setup AC97 register %d\n",
  377. outputs[i].reg);
  378. }
  379. if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
  380. int sel = ac97_return_record_select(dev->ctl_aoutput);
  381. /* Use the same input for both left and right
  382. channels */
  383. sel |= (sel << 8);
  384. em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel);
  385. }
  386. }
  387. return ret;
  388. }
  389. EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
  390. int em28xx_audio_setup(struct em28xx *dev)
  391. {
  392. int vid1, vid2, feat, cfg;
  393. u32 vid;
  394. if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874) {
  395. /* Digital only device - don't load any alsa module */
  396. dev->audio_mode.has_audio = 0;
  397. dev->has_audio_class = 0;
  398. dev->has_alsa_audio = 0;
  399. return 0;
  400. }
  401. /* If device doesn't support Usb Audio Class, use vendor class */
  402. if (!dev->has_audio_class)
  403. dev->has_alsa_audio = 1;
  404. dev->audio_mode.has_audio = 1;
  405. /* See how this device is configured */
  406. cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
  407. em28xx_info("Config register raw data: 0x%02x\n", cfg);
  408. if (cfg < 0) {
  409. /* Register read error? */
  410. cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
  411. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
  412. /* The device doesn't have vendor audio at all */
  413. dev->has_alsa_audio = 0;
  414. dev->audio_mode.has_audio = 0;
  415. return 0;
  416. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  417. EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
  418. em28xx_info("I2S Audio (3 sample rates)\n");
  419. dev->audio_mode.i2s_3rates = 1;
  420. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  421. EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
  422. em28xx_info("I2S Audio (5 sample rates)\n");
  423. dev->audio_mode.i2s_5rates = 1;
  424. }
  425. if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
  426. /* Skip the code that does AC97 vendor detection */
  427. dev->audio_mode.ac97 = EM28XX_NO_AC97;
  428. goto init_audio;
  429. }
  430. dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
  431. vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
  432. if (vid1 < 0) {
  433. /* Device likely doesn't support AC97 */
  434. em28xx_warn("AC97 chip type couldn't be determined\n");
  435. goto init_audio;
  436. }
  437. vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
  438. if (vid2 < 0)
  439. goto init_audio;
  440. vid = vid1 << 16 | vid2;
  441. dev->audio_mode.ac97_vendor_id = vid;
  442. em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
  443. feat = em28xx_read_ac97(dev, AC97_RESET);
  444. if (feat < 0)
  445. goto init_audio;
  446. dev->audio_mode.ac97_feat = feat;
  447. em28xx_warn("AC97 features = 0x%04x\n", feat);
  448. /* Try to identify what audio processor we have */
  449. if ((vid == 0xffffffff) && (feat == 0x6a90))
  450. dev->audio_mode.ac97 = EM28XX_AC97_EM202;
  451. else if ((vid >> 8) == 0x838476)
  452. dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
  453. init_audio:
  454. /* Reports detected AC97 processor */
  455. switch (dev->audio_mode.ac97) {
  456. case EM28XX_NO_AC97:
  457. em28xx_info("No AC97 audio processor\n");
  458. break;
  459. case EM28XX_AC97_EM202:
  460. em28xx_info("Empia 202 AC97 audio processor detected\n");
  461. break;
  462. case EM28XX_AC97_SIGMATEL:
  463. em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
  464. dev->audio_mode.ac97_vendor_id & 0xff);
  465. break;
  466. case EM28XX_AC97_OTHER:
  467. em28xx_warn("Unknown AC97 audio processor detected!\n");
  468. break;
  469. default:
  470. break;
  471. }
  472. return em28xx_audio_analog_set(dev);
  473. }
  474. EXPORT_SYMBOL_GPL(em28xx_audio_setup);
  475. int em28xx_colorlevels_set_default(struct em28xx *dev)
  476. {
  477. em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
  478. em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
  479. em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
  480. em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
  481. em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
  482. em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
  483. em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
  484. em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
  485. em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
  486. em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
  487. em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
  488. em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
  489. return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
  490. }
  491. int em28xx_capture_start(struct em28xx *dev, int start)
  492. {
  493. int rc;
  494. if (dev->chip_id == CHIP_ID_EM2874) {
  495. /* The Transport Stream Enable Register moved in em2874 */
  496. if (!start) {
  497. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  498. 0x00,
  499. EM2874_TS1_CAPTURE_ENABLE);
  500. return rc;
  501. }
  502. /* Enable Transport Stream */
  503. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  504. EM2874_TS1_CAPTURE_ENABLE,
  505. EM2874_TS1_CAPTURE_ENABLE);
  506. return rc;
  507. }
  508. /* FIXME: which is the best order? */
  509. /* video registers are sampled by VREF */
  510. rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
  511. start ? 0x10 : 0x00, 0x10);
  512. if (rc < 0)
  513. return rc;
  514. if (!start) {
  515. /* disable video capture */
  516. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
  517. return rc;
  518. }
  519. /* enable video capture */
  520. rc = em28xx_write_reg(dev, 0x48, 0x00);
  521. if (dev->mode == EM28XX_ANALOG_MODE)
  522. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
  523. else
  524. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
  525. msleep(6);
  526. return rc;
  527. }
  528. int em28xx_set_outfmt(struct em28xx *dev)
  529. {
  530. int ret;
  531. ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
  532. dev->format->reg | 0x20, 0xff);
  533. if (ret < 0)
  534. return ret;
  535. ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, dev->vinmode);
  536. if (ret < 0)
  537. return ret;
  538. return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, dev->vinctl);
  539. }
  540. static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
  541. u8 ymin, u8 ymax)
  542. {
  543. em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
  544. xmin, ymin, xmax, ymax);
  545. em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
  546. em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
  547. em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
  548. return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
  549. }
  550. static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
  551. u16 width, u16 height)
  552. {
  553. u8 cwidth = width;
  554. u8 cheight = height;
  555. u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
  556. em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
  557. (width | (overflow & 2) << 7),
  558. (height | (overflow & 1) << 8));
  559. em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
  560. em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
  561. em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
  562. em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
  563. return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
  564. }
  565. static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
  566. {
  567. u8 mode;
  568. /* the em2800 scaler only supports scaling down to 50% */
  569. if (dev->board.is_em2800) {
  570. mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
  571. } else {
  572. u8 buf[2];
  573. buf[0] = h;
  574. buf[1] = h >> 8;
  575. em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
  576. buf[0] = v;
  577. buf[1] = v >> 8;
  578. em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
  579. /* it seems that both H and V scalers must be active
  580. to work correctly */
  581. mode = (h || v) ? 0x30 : 0x00;
  582. }
  583. return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
  584. }
  585. /* FIXME: this only function read values from dev */
  586. int em28xx_resolution_set(struct em28xx *dev)
  587. {
  588. int width, height;
  589. width = norm_maxw(dev);
  590. height = norm_maxh(dev) >> 1;
  591. em28xx_set_outfmt(dev);
  592. em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
  593. em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
  594. return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
  595. }
  596. int em28xx_set_alternate(struct em28xx *dev)
  597. {
  598. int errCode, prev_alt = dev->alt;
  599. int i;
  600. unsigned int min_pkt_size = dev->width * 2 + 4;
  601. /* When image size is bigger than a certain value,
  602. the frame size should be increased, otherwise, only
  603. green screen will be received.
  604. */
  605. if (dev->width * 2 * dev->height > 720 * 240 * 2)
  606. min_pkt_size *= 2;
  607. for (i = 0; i < dev->num_alt; i++) {
  608. /* stop when the selected alt setting offers enough bandwidth */
  609. if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
  610. dev->alt = i;
  611. break;
  612. /* otherwise make sure that we end up with the maximum bandwidth
  613. because the min_pkt_size equation might be wrong...
  614. */
  615. } else if (dev->alt_max_pkt_size[i] >
  616. dev->alt_max_pkt_size[dev->alt])
  617. dev->alt = i;
  618. }
  619. if (dev->alt != prev_alt) {
  620. em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
  621. min_pkt_size, dev->alt);
  622. dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
  623. em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
  624. dev->alt, dev->max_pkt_size);
  625. errCode = usb_set_interface(dev->udev, 0, dev->alt);
  626. if (errCode < 0) {
  627. em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
  628. dev->alt, errCode);
  629. return errCode;
  630. }
  631. }
  632. return 0;
  633. }
  634. int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
  635. {
  636. int rc = 0;
  637. if (!gpio)
  638. return rc;
  639. if (dev->mode != EM28XX_SUSPEND) {
  640. em28xx_write_reg(dev, 0x48, 0x00);
  641. if (dev->mode == EM28XX_ANALOG_MODE)
  642. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
  643. else
  644. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
  645. msleep(6);
  646. }
  647. /* Send GPIO reset sequences specified at board entry */
  648. while (gpio->sleep >= 0) {
  649. if (gpio->reg >= 0) {
  650. rc = em28xx_write_reg_bits(dev,
  651. gpio->reg,
  652. gpio->val,
  653. gpio->mask);
  654. if (rc < 0)
  655. return rc;
  656. }
  657. if (gpio->sleep > 0)
  658. msleep(gpio->sleep);
  659. gpio++;
  660. }
  661. return rc;
  662. }
  663. int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
  664. {
  665. if (dev->mode == set_mode)
  666. return 0;
  667. if (set_mode == EM28XX_SUSPEND) {
  668. dev->mode = set_mode;
  669. /* FIXME: add suspend support for ac97 */
  670. return em28xx_gpio_set(dev, dev->board.suspend_gpio);
  671. }
  672. dev->mode = set_mode;
  673. if (dev->mode == EM28XX_DIGITAL_MODE)
  674. return em28xx_gpio_set(dev, dev->board.dvb_gpio);
  675. else
  676. return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  677. }
  678. EXPORT_SYMBOL_GPL(em28xx_set_mode);
  679. /* ------------------------------------------------------------------
  680. URB control
  681. ------------------------------------------------------------------*/
  682. /*
  683. * IRQ callback, called by URB callback
  684. */
  685. static void em28xx_irq_callback(struct urb *urb)
  686. {
  687. struct em28xx_dmaqueue *dma_q = urb->context;
  688. struct em28xx *dev = container_of(dma_q, struct em28xx, vidq);
  689. int rc, i;
  690. switch (urb->status) {
  691. case 0: /* success */
  692. case -ETIMEDOUT: /* NAK */
  693. break;
  694. case -ECONNRESET: /* kill */
  695. case -ENOENT:
  696. case -ESHUTDOWN:
  697. return;
  698. default: /* error */
  699. em28xx_isocdbg("urb completition error %d.\n", urb->status);
  700. break;
  701. }
  702. /* Copy data from URB */
  703. spin_lock(&dev->slock);
  704. rc = dev->isoc_ctl.isoc_copy(dev, urb);
  705. spin_unlock(&dev->slock);
  706. /* Reset urb buffers */
  707. for (i = 0; i < urb->number_of_packets; i++) {
  708. urb->iso_frame_desc[i].status = 0;
  709. urb->iso_frame_desc[i].actual_length = 0;
  710. }
  711. urb->status = 0;
  712. urb->status = usb_submit_urb(urb, GFP_ATOMIC);
  713. if (urb->status) {
  714. em28xx_isocdbg("urb resubmit failed (error=%i)\n",
  715. urb->status);
  716. }
  717. }
  718. /*
  719. * Stop and Deallocate URBs
  720. */
  721. void em28xx_uninit_isoc(struct em28xx *dev)
  722. {
  723. struct urb *urb;
  724. int i;
  725. em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
  726. dev->isoc_ctl.nfields = -1;
  727. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  728. urb = dev->isoc_ctl.urb[i];
  729. if (urb) {
  730. if (!irqs_disabled())
  731. usb_kill_urb(urb);
  732. else
  733. usb_unlink_urb(urb);
  734. if (dev->isoc_ctl.transfer_buffer[i]) {
  735. usb_buffer_free(dev->udev,
  736. urb->transfer_buffer_length,
  737. dev->isoc_ctl.transfer_buffer[i],
  738. urb->transfer_dma);
  739. }
  740. usb_free_urb(urb);
  741. dev->isoc_ctl.urb[i] = NULL;
  742. }
  743. dev->isoc_ctl.transfer_buffer[i] = NULL;
  744. }
  745. kfree(dev->isoc_ctl.urb);
  746. kfree(dev->isoc_ctl.transfer_buffer);
  747. dev->isoc_ctl.urb = NULL;
  748. dev->isoc_ctl.transfer_buffer = NULL;
  749. dev->isoc_ctl.num_bufs = 0;
  750. em28xx_capture_start(dev, 0);
  751. }
  752. EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
  753. /*
  754. * Allocate URBs and start IRQ
  755. */
  756. int em28xx_init_isoc(struct em28xx *dev, int max_packets,
  757. int num_bufs, int max_pkt_size,
  758. int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
  759. {
  760. struct em28xx_dmaqueue *dma_q = &dev->vidq;
  761. int i;
  762. int sb_size, pipe;
  763. struct urb *urb;
  764. int j, k;
  765. int rc;
  766. em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
  767. /* De-allocates all pending stuff */
  768. em28xx_uninit_isoc(dev);
  769. dev->isoc_ctl.isoc_copy = isoc_copy;
  770. dev->isoc_ctl.num_bufs = num_bufs;
  771. dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
  772. if (!dev->isoc_ctl.urb) {
  773. em28xx_errdev("cannot alloc memory for usb buffers\n");
  774. return -ENOMEM;
  775. }
  776. dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
  777. GFP_KERNEL);
  778. if (!dev->isoc_ctl.transfer_buffer) {
  779. em28xx_errdev("cannot allocate memory for usb transfer\n");
  780. kfree(dev->isoc_ctl.urb);
  781. return -ENOMEM;
  782. }
  783. dev->isoc_ctl.max_pkt_size = max_pkt_size;
  784. dev->isoc_ctl.buf = NULL;
  785. sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
  786. /* allocate urbs and transfer buffers */
  787. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  788. urb = usb_alloc_urb(max_packets, GFP_KERNEL);
  789. if (!urb) {
  790. em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
  791. em28xx_uninit_isoc(dev);
  792. return -ENOMEM;
  793. }
  794. dev->isoc_ctl.urb[i] = urb;
  795. dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev,
  796. sb_size, GFP_KERNEL, &urb->transfer_dma);
  797. if (!dev->isoc_ctl.transfer_buffer[i]) {
  798. em28xx_err("unable to allocate %i bytes for transfer"
  799. " buffer %i%s\n",
  800. sb_size, i,
  801. in_interrupt() ? " while in int" : "");
  802. em28xx_uninit_isoc(dev);
  803. return -ENOMEM;
  804. }
  805. memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
  806. /* FIXME: this is a hack - should be
  807. 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
  808. should also be using 'desc.bInterval'
  809. */
  810. pipe = usb_rcvisocpipe(dev->udev,
  811. dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
  812. usb_fill_int_urb(urb, dev->udev, pipe,
  813. dev->isoc_ctl.transfer_buffer[i], sb_size,
  814. em28xx_irq_callback, dma_q, 1);
  815. urb->number_of_packets = max_packets;
  816. urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
  817. k = 0;
  818. for (j = 0; j < max_packets; j++) {
  819. urb->iso_frame_desc[j].offset = k;
  820. urb->iso_frame_desc[j].length =
  821. dev->isoc_ctl.max_pkt_size;
  822. k += dev->isoc_ctl.max_pkt_size;
  823. }
  824. }
  825. init_waitqueue_head(&dma_q->wq);
  826. em28xx_capture_start(dev, 1);
  827. /* submit urbs and enables IRQ */
  828. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  829. rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
  830. if (rc) {
  831. em28xx_err("submit of urb %i failed (error=%i)\n", i,
  832. rc);
  833. em28xx_uninit_isoc(dev);
  834. return rc;
  835. }
  836. }
  837. return 0;
  838. }
  839. EXPORT_SYMBOL_GPL(em28xx_init_isoc);
  840. /* Determine the packet size for the DVB stream for the given device
  841. (underlying value programmed into the eeprom) */
  842. int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev)
  843. {
  844. unsigned int chip_cfg2;
  845. unsigned int packet_size = 564;
  846. if (dev->chip_id == CHIP_ID_EM2874) {
  847. /* FIXME - for now assume 564 like it was before, but the
  848. em2874 code should be added to return the proper value... */
  849. packet_size = 564;
  850. } else {
  851. /* TS max packet size stored in bits 1-0 of R01 */
  852. chip_cfg2 = em28xx_read_reg(dev, EM28XX_R01_CHIPCFG2);
  853. switch (chip_cfg2 & EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK) {
  854. case EM28XX_CHIPCFG2_TS_PACKETSIZE_188:
  855. packet_size = 188;
  856. break;
  857. case EM28XX_CHIPCFG2_TS_PACKETSIZE_376:
  858. packet_size = 376;
  859. break;
  860. case EM28XX_CHIPCFG2_TS_PACKETSIZE_564:
  861. packet_size = 564;
  862. break;
  863. case EM28XX_CHIPCFG2_TS_PACKETSIZE_752:
  864. packet_size = 752;
  865. break;
  866. }
  867. }
  868. em28xx_coredbg("dvb max packet size=%d\n", packet_size);
  869. return packet_size;
  870. }
  871. EXPORT_SYMBOL_GPL(em28xx_isoc_dvb_max_packetsize);
  872. /*
  873. * em28xx_wake_i2c()
  874. * configure i2c attached devices
  875. */
  876. void em28xx_wake_i2c(struct em28xx *dev)
  877. {
  878. v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
  879. v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
  880. INPUT(dev->ctl_input)->vmux, 0, 0);
  881. v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
  882. }
  883. /*
  884. * Device control list
  885. */
  886. static LIST_HEAD(em28xx_devlist);
  887. static DEFINE_MUTEX(em28xx_devlist_mutex);
  888. struct em28xx *em28xx_get_device(int minor,
  889. enum v4l2_buf_type *fh_type,
  890. int *has_radio)
  891. {
  892. struct em28xx *h, *dev = NULL;
  893. *fh_type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  894. *has_radio = 0;
  895. mutex_lock(&em28xx_devlist_mutex);
  896. list_for_each_entry(h, &em28xx_devlist, devlist) {
  897. if (h->vdev->minor == minor)
  898. dev = h;
  899. if (h->vbi_dev->minor == minor) {
  900. dev = h;
  901. *fh_type = V4L2_BUF_TYPE_VBI_CAPTURE;
  902. }
  903. if (h->radio_dev &&
  904. h->radio_dev->minor == minor) {
  905. dev = h;
  906. *has_radio = 1;
  907. }
  908. }
  909. mutex_unlock(&em28xx_devlist_mutex);
  910. return dev;
  911. }
  912. /*
  913. * em28xx_realease_resources()
  914. * unregisters the v4l2,i2c and usb devices
  915. * called when the device gets disconected or at module unload
  916. */
  917. void em28xx_remove_from_devlist(struct em28xx *dev)
  918. {
  919. mutex_lock(&em28xx_devlist_mutex);
  920. list_del(&dev->devlist);
  921. mutex_unlock(&em28xx_devlist_mutex);
  922. };
  923. void em28xx_add_into_devlist(struct em28xx *dev)
  924. {
  925. mutex_lock(&em28xx_devlist_mutex);
  926. list_add_tail(&dev->devlist, &em28xx_devlist);
  927. mutex_unlock(&em28xx_devlist_mutex);
  928. };
  929. /*
  930. * Extension interface
  931. */
  932. static LIST_HEAD(em28xx_extension_devlist);
  933. static DEFINE_MUTEX(em28xx_extension_devlist_lock);
  934. int em28xx_register_extension(struct em28xx_ops *ops)
  935. {
  936. struct em28xx *dev = NULL;
  937. mutex_lock(&em28xx_devlist_mutex);
  938. mutex_lock(&em28xx_extension_devlist_lock);
  939. list_add_tail(&ops->next, &em28xx_extension_devlist);
  940. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  941. if (dev)
  942. ops->init(dev);
  943. }
  944. printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
  945. mutex_unlock(&em28xx_extension_devlist_lock);
  946. mutex_unlock(&em28xx_devlist_mutex);
  947. return 0;
  948. }
  949. EXPORT_SYMBOL(em28xx_register_extension);
  950. void em28xx_unregister_extension(struct em28xx_ops *ops)
  951. {
  952. struct em28xx *dev = NULL;
  953. mutex_lock(&em28xx_devlist_mutex);
  954. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  955. if (dev)
  956. ops->fini(dev);
  957. }
  958. mutex_lock(&em28xx_extension_devlist_lock);
  959. printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
  960. list_del(&ops->next);
  961. mutex_unlock(&em28xx_extension_devlist_lock);
  962. mutex_unlock(&em28xx_devlist_mutex);
  963. }
  964. EXPORT_SYMBOL(em28xx_unregister_extension);
  965. void em28xx_init_extension(struct em28xx *dev)
  966. {
  967. struct em28xx_ops *ops = NULL;
  968. mutex_lock(&em28xx_extension_devlist_lock);
  969. if (!list_empty(&em28xx_extension_devlist)) {
  970. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  971. if (ops->init)
  972. ops->init(dev);
  973. }
  974. }
  975. mutex_unlock(&em28xx_extension_devlist_lock);
  976. }
  977. void em28xx_close_extension(struct em28xx *dev)
  978. {
  979. struct em28xx_ops *ops = NULL;
  980. mutex_lock(&em28xx_extension_devlist_lock);
  981. if (!list_empty(&em28xx_extension_devlist)) {
  982. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  983. if (ops->fini)
  984. ops->fini(dev);
  985. }
  986. }
  987. mutex_unlock(&em28xx_extension_devlist_lock);
  988. }