main.c 57 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_set_assoc_state(struct ath_softc *sc,
  21. struct ieee80211_vif *vif);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  57. {
  58. bool pending = false;
  59. spin_lock_bh(&txq->axq_lock);
  60. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  61. pending = true;
  62. spin_unlock_bh(&txq->axq_lock);
  63. return pending;
  64. }
  65. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  66. {
  67. unsigned long flags;
  68. bool ret;
  69. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  70. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  71. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  72. return ret;
  73. }
  74. void ath9k_ps_wakeup(struct ath_softc *sc)
  75. {
  76. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  77. unsigned long flags;
  78. enum ath9k_power_mode power_mode;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. if (++sc->ps_usecount != 1)
  81. goto unlock;
  82. power_mode = sc->sc_ah->power_mode;
  83. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  84. /*
  85. * While the hardware is asleep, the cycle counters contain no
  86. * useful data. Better clear them now so that they don't mess up
  87. * survey data results.
  88. */
  89. if (power_mode != ATH9K_PM_AWAKE) {
  90. spin_lock(&common->cc_lock);
  91. ath_hw_cycle_counters_update(common);
  92. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  93. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  94. spin_unlock(&common->cc_lock);
  95. }
  96. unlock:
  97. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  98. }
  99. void ath9k_ps_restore(struct ath_softc *sc)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. enum ath9k_power_mode mode;
  103. unsigned long flags;
  104. bool reset;
  105. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  106. if (--sc->ps_usecount != 0)
  107. goto unlock;
  108. if (sc->ps_idle) {
  109. ath9k_hw_setrxabort(sc->sc_ah, 1);
  110. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  111. mode = ATH9K_PM_FULL_SLEEP;
  112. } else if (sc->ps_enabled &&
  113. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  114. PS_WAIT_FOR_CAB |
  115. PS_WAIT_FOR_PSPOLL_DATA |
  116. PS_WAIT_FOR_TX_ACK |
  117. PS_WAIT_FOR_ANI))) {
  118. mode = ATH9K_PM_NETWORK_SLEEP;
  119. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  120. ath9k_btcoex_stop_gen_timer(sc);
  121. } else {
  122. goto unlock;
  123. }
  124. spin_lock(&common->cc_lock);
  125. ath_hw_cycle_counters_update(common);
  126. spin_unlock(&common->cc_lock);
  127. ath9k_hw_setpower(sc->sc_ah, mode);
  128. unlock:
  129. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  130. }
  131. static void __ath_cancel_work(struct ath_softc *sc)
  132. {
  133. cancel_work_sync(&sc->paprd_work);
  134. cancel_work_sync(&sc->hw_check_work);
  135. cancel_delayed_work_sync(&sc->tx_complete_work);
  136. cancel_delayed_work_sync(&sc->hw_pll_work);
  137. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  138. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  139. cancel_work_sync(&sc->mci_work);
  140. #endif
  141. }
  142. static void ath_cancel_work(struct ath_softc *sc)
  143. {
  144. __ath_cancel_work(sc);
  145. cancel_work_sync(&sc->hw_reset_work);
  146. }
  147. static void ath_restart_work(struct ath_softc *sc)
  148. {
  149. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  150. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
  151. AR_SREV_9550(sc->sc_ah))
  152. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  153. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  154. ath_start_rx_poll(sc, 3);
  155. ath_start_ani(sc);
  156. }
  157. static bool ath_prepare_reset(struct ath_softc *sc)
  158. {
  159. struct ath_hw *ah = sc->sc_ah;
  160. bool ret = true;
  161. ieee80211_stop_queues(sc->hw);
  162. sc->hw_busy_count = 0;
  163. ath_stop_ani(sc);
  164. del_timer_sync(&sc->rx_poll_timer);
  165. ath9k_debug_samp_bb_mac(sc);
  166. ath9k_hw_disable_interrupts(ah);
  167. if (!ath_drain_all_txq(sc))
  168. ret = false;
  169. if (!ath_stoprecv(sc))
  170. ret = false;
  171. return ret;
  172. }
  173. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  174. {
  175. struct ath_hw *ah = sc->sc_ah;
  176. struct ath_common *common = ath9k_hw_common(ah);
  177. unsigned long flags;
  178. if (ath_startrecv(sc) != 0) {
  179. ath_err(common, "Unable to restart recv logic\n");
  180. return false;
  181. }
  182. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  183. sc->config.txpowlimit, &sc->curtxpow);
  184. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  185. ath9k_hw_set_interrupts(ah);
  186. ath9k_hw_enable_interrupts(ah);
  187. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  188. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  189. goto work;
  190. ath9k_set_beacon(sc);
  191. if (ah->opmode == NL80211_IFTYPE_STATION &&
  192. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  193. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  194. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  195. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  196. }
  197. work:
  198. ath_restart_work(sc);
  199. }
  200. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  201. ath_ant_comb_update(sc);
  202. ieee80211_wake_queues(sc->hw);
  203. return true;
  204. }
  205. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
  206. {
  207. struct ath_hw *ah = sc->sc_ah;
  208. struct ath_common *common = ath9k_hw_common(ah);
  209. struct ath9k_hw_cal_data *caldata = NULL;
  210. bool fastcc = true;
  211. int r;
  212. __ath_cancel_work(sc);
  213. tasklet_disable(&sc->intr_tq);
  214. spin_lock_bh(&sc->sc_pcu_lock);
  215. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  216. fastcc = false;
  217. caldata = &sc->caldata;
  218. }
  219. if (!hchan) {
  220. fastcc = false;
  221. hchan = ah->curchan;
  222. }
  223. if (!ath_prepare_reset(sc))
  224. fastcc = false;
  225. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  226. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  227. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  228. if (r) {
  229. ath_err(common,
  230. "Unable to reset channel, reset status %d\n", r);
  231. goto out;
  232. }
  233. if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
  234. (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
  235. ath9k_mci_set_txpower(sc, true, false);
  236. if (!ath_complete_reset(sc, true))
  237. r = -EIO;
  238. out:
  239. spin_unlock_bh(&sc->sc_pcu_lock);
  240. tasklet_enable(&sc->intr_tq);
  241. return r;
  242. }
  243. /*
  244. * Set/change channels. If the channel is really being changed, it's done
  245. * by reseting the chip. To accomplish this we must first cleanup any pending
  246. * DMA, then restart stuff.
  247. */
  248. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  249. struct ath9k_channel *hchan)
  250. {
  251. int r;
  252. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  253. return -EIO;
  254. r = ath_reset_internal(sc, hchan);
  255. return r;
  256. }
  257. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  258. struct ieee80211_vif *vif)
  259. {
  260. struct ath_node *an;
  261. u8 density;
  262. an = (struct ath_node *)sta->drv_priv;
  263. an->sc = sc;
  264. an->sta = sta;
  265. an->vif = vif;
  266. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  267. ath_tx_node_init(sc, an);
  268. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  269. sta->ht_cap.ampdu_factor);
  270. density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  271. an->mpdudensity = density;
  272. }
  273. }
  274. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  275. {
  276. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  277. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  278. ath_tx_node_cleanup(sc, an);
  279. }
  280. void ath9k_tasklet(unsigned long data)
  281. {
  282. struct ath_softc *sc = (struct ath_softc *)data;
  283. struct ath_hw *ah = sc->sc_ah;
  284. struct ath_common *common = ath9k_hw_common(ah);
  285. enum ath_reset_type type;
  286. unsigned long flags;
  287. u32 status = sc->intrstatus;
  288. u32 rxmask;
  289. ath9k_ps_wakeup(sc);
  290. spin_lock(&sc->sc_pcu_lock);
  291. if ((status & ATH9K_INT_FATAL) ||
  292. (status & ATH9K_INT_BB_WATCHDOG)) {
  293. if (status & ATH9K_INT_FATAL)
  294. type = RESET_TYPE_FATAL_INT;
  295. else
  296. type = RESET_TYPE_BB_WATCHDOG;
  297. ath9k_queue_reset(sc, type);
  298. goto out;
  299. }
  300. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  301. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  302. /*
  303. * TSF sync does not look correct; remain awake to sync with
  304. * the next Beacon.
  305. */
  306. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  307. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  308. }
  309. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  310. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  311. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  312. ATH9K_INT_RXORN);
  313. else
  314. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  315. if (status & rxmask) {
  316. /* Check for high priority Rx first */
  317. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  318. (status & ATH9K_INT_RXHP))
  319. ath_rx_tasklet(sc, 0, true);
  320. ath_rx_tasklet(sc, 0, false);
  321. }
  322. if (status & ATH9K_INT_TX) {
  323. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  324. ath_tx_edma_tasklet(sc);
  325. else
  326. ath_tx_tasklet(sc);
  327. }
  328. ath9k_btcoex_handle_interrupt(sc, status);
  329. out:
  330. /* re-enable hardware interrupt */
  331. ath9k_hw_enable_interrupts(ah);
  332. spin_unlock(&sc->sc_pcu_lock);
  333. ath9k_ps_restore(sc);
  334. }
  335. irqreturn_t ath_isr(int irq, void *dev)
  336. {
  337. #define SCHED_INTR ( \
  338. ATH9K_INT_FATAL | \
  339. ATH9K_INT_BB_WATCHDOG | \
  340. ATH9K_INT_RXORN | \
  341. ATH9K_INT_RXEOL | \
  342. ATH9K_INT_RX | \
  343. ATH9K_INT_RXLP | \
  344. ATH9K_INT_RXHP | \
  345. ATH9K_INT_TX | \
  346. ATH9K_INT_BMISS | \
  347. ATH9K_INT_CST | \
  348. ATH9K_INT_TSFOOR | \
  349. ATH9K_INT_GENTIMER | \
  350. ATH9K_INT_MCI)
  351. struct ath_softc *sc = dev;
  352. struct ath_hw *ah = sc->sc_ah;
  353. struct ath_common *common = ath9k_hw_common(ah);
  354. enum ath9k_int status;
  355. bool sched = false;
  356. /*
  357. * The hardware is not ready/present, don't
  358. * touch anything. Note this can happen early
  359. * on if the IRQ is shared.
  360. */
  361. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  362. return IRQ_NONE;
  363. /* shared irq, not for us */
  364. if (!ath9k_hw_intrpend(ah))
  365. return IRQ_NONE;
  366. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
  367. ath9k_hw_kill_interrupts(ah);
  368. return IRQ_HANDLED;
  369. }
  370. /*
  371. * Figure out the reason(s) for the interrupt. Note
  372. * that the hal returns a pseudo-ISR that may include
  373. * bits we haven't explicitly enabled so we mask the
  374. * value to insure we only process bits we requested.
  375. */
  376. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  377. status &= ah->imask; /* discard unasked-for bits */
  378. /*
  379. * If there are no status bits set, then this interrupt was not
  380. * for me (should have been caught above).
  381. */
  382. if (!status)
  383. return IRQ_NONE;
  384. /* Cache the status */
  385. sc->intrstatus = status;
  386. if (status & SCHED_INTR)
  387. sched = true;
  388. /*
  389. * If a FATAL or RXORN interrupt is received, we have to reset the
  390. * chip immediately.
  391. */
  392. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  393. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  394. goto chip_reset;
  395. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  396. (status & ATH9K_INT_BB_WATCHDOG)) {
  397. spin_lock(&common->cc_lock);
  398. ath_hw_cycle_counters_update(common);
  399. ar9003_hw_bb_watchdog_dbg_info(ah);
  400. spin_unlock(&common->cc_lock);
  401. goto chip_reset;
  402. }
  403. #ifdef CONFIG_PM_SLEEP
  404. if (status & ATH9K_INT_BMISS) {
  405. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  406. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  407. atomic_inc(&sc->wow_got_bmiss_intr);
  408. atomic_dec(&sc->wow_sleep_proc_intr);
  409. }
  410. }
  411. #endif
  412. if (status & ATH9K_INT_SWBA)
  413. tasklet_schedule(&sc->bcon_tasklet);
  414. if (status & ATH9K_INT_TXURN)
  415. ath9k_hw_updatetxtriglevel(ah, true);
  416. if (status & ATH9K_INT_RXEOL) {
  417. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  418. ath9k_hw_set_interrupts(ah);
  419. }
  420. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  421. if (status & ATH9K_INT_TIM_TIMER) {
  422. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  423. goto chip_reset;
  424. /* Clear RxAbort bit so that we can
  425. * receive frames */
  426. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  427. spin_lock(&sc->sc_pm_lock);
  428. ath9k_hw_setrxabort(sc->sc_ah, 0);
  429. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  430. spin_unlock(&sc->sc_pm_lock);
  431. }
  432. chip_reset:
  433. ath_debug_stat_interrupt(sc, status);
  434. if (sched) {
  435. /* turn off every interrupt */
  436. ath9k_hw_disable_interrupts(ah);
  437. tasklet_schedule(&sc->intr_tq);
  438. }
  439. return IRQ_HANDLED;
  440. #undef SCHED_INTR
  441. }
  442. static int ath_reset(struct ath_softc *sc)
  443. {
  444. int i, r;
  445. ath9k_ps_wakeup(sc);
  446. r = ath_reset_internal(sc, NULL);
  447. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  448. if (!ATH_TXQ_SETUP(sc, i))
  449. continue;
  450. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  451. ath_txq_schedule(sc, &sc->tx.txq[i]);
  452. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  453. }
  454. ath9k_ps_restore(sc);
  455. return r;
  456. }
  457. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  458. {
  459. #ifdef CONFIG_ATH9K_DEBUGFS
  460. RESET_STAT_INC(sc, type);
  461. #endif
  462. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  463. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  464. }
  465. void ath_reset_work(struct work_struct *work)
  466. {
  467. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  468. ath_reset(sc);
  469. }
  470. /**********************/
  471. /* mac80211 callbacks */
  472. /**********************/
  473. static int ath9k_start(struct ieee80211_hw *hw)
  474. {
  475. struct ath_softc *sc = hw->priv;
  476. struct ath_hw *ah = sc->sc_ah;
  477. struct ath_common *common = ath9k_hw_common(ah);
  478. struct ieee80211_channel *curchan = hw->conf.channel;
  479. struct ath9k_channel *init_channel;
  480. int r;
  481. ath_dbg(common, CONFIG,
  482. "Starting driver with initial channel: %d MHz\n",
  483. curchan->center_freq);
  484. ath9k_ps_wakeup(sc);
  485. mutex_lock(&sc->mutex);
  486. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  487. /* Reset SERDES registers */
  488. ath9k_hw_configpcipowersave(ah, false);
  489. /*
  490. * The basic interface to setting the hardware in a good
  491. * state is ``reset''. On return the hardware is known to
  492. * be powered up and with interrupts disabled. This must
  493. * be followed by initialization of the appropriate bits
  494. * and then setup of the interrupt mask.
  495. */
  496. spin_lock_bh(&sc->sc_pcu_lock);
  497. atomic_set(&ah->intr_ref_cnt, -1);
  498. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  499. if (r) {
  500. ath_err(common,
  501. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  502. r, curchan->center_freq);
  503. ah->reset_power_on = false;
  504. }
  505. /* Setup our intr mask. */
  506. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  507. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  508. ATH9K_INT_GLOBAL;
  509. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  510. ah->imask |= ATH9K_INT_RXHP |
  511. ATH9K_INT_RXLP |
  512. ATH9K_INT_BB_WATCHDOG;
  513. else
  514. ah->imask |= ATH9K_INT_RX;
  515. ah->imask |= ATH9K_INT_GTT;
  516. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  517. ah->imask |= ATH9K_INT_CST;
  518. ath_mci_enable(sc);
  519. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  520. sc->sc_ah->is_monitoring = false;
  521. if (!ath_complete_reset(sc, false))
  522. ah->reset_power_on = false;
  523. if (ah->led_pin >= 0) {
  524. ath9k_hw_cfg_output(ah, ah->led_pin,
  525. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  526. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  527. }
  528. /*
  529. * Reset key cache to sane defaults (all entries cleared) instead of
  530. * semi-random values after suspend/resume.
  531. */
  532. ath9k_cmn_init_crypto(sc->sc_ah);
  533. spin_unlock_bh(&sc->sc_pcu_lock);
  534. mutex_unlock(&sc->mutex);
  535. ath9k_ps_restore(sc);
  536. return 0;
  537. }
  538. static void ath9k_tx(struct ieee80211_hw *hw,
  539. struct ieee80211_tx_control *control,
  540. struct sk_buff *skb)
  541. {
  542. struct ath_softc *sc = hw->priv;
  543. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  544. struct ath_tx_control txctl;
  545. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  546. unsigned long flags;
  547. if (sc->ps_enabled) {
  548. /*
  549. * mac80211 does not set PM field for normal data frames, so we
  550. * need to update that based on the current PS mode.
  551. */
  552. if (ieee80211_is_data(hdr->frame_control) &&
  553. !ieee80211_is_nullfunc(hdr->frame_control) &&
  554. !ieee80211_has_pm(hdr->frame_control)) {
  555. ath_dbg(common, PS,
  556. "Add PM=1 for a TX frame while in PS mode\n");
  557. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  558. }
  559. }
  560. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  561. /*
  562. * We are using PS-Poll and mac80211 can request TX while in
  563. * power save mode. Need to wake up hardware for the TX to be
  564. * completed and if needed, also for RX of buffered frames.
  565. */
  566. ath9k_ps_wakeup(sc);
  567. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  568. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  569. ath9k_hw_setrxabort(sc->sc_ah, 0);
  570. if (ieee80211_is_pspoll(hdr->frame_control)) {
  571. ath_dbg(common, PS,
  572. "Sending PS-Poll to pick a buffered frame\n");
  573. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  574. } else {
  575. ath_dbg(common, PS, "Wake up to complete TX\n");
  576. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  577. }
  578. /*
  579. * The actual restore operation will happen only after
  580. * the ps_flags bit is cleared. We are just dropping
  581. * the ps_usecount here.
  582. */
  583. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  584. ath9k_ps_restore(sc);
  585. }
  586. /*
  587. * Cannot tx while the hardware is in full sleep, it first needs a full
  588. * chip reset to recover from that
  589. */
  590. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  591. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  592. goto exit;
  593. }
  594. memset(&txctl, 0, sizeof(struct ath_tx_control));
  595. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  596. txctl.sta = control->sta;
  597. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  598. if (ath_tx_start(hw, skb, &txctl) != 0) {
  599. ath_dbg(common, XMIT, "TX failed\n");
  600. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  601. goto exit;
  602. }
  603. return;
  604. exit:
  605. ieee80211_free_txskb(hw, skb);
  606. }
  607. static void ath9k_stop(struct ieee80211_hw *hw)
  608. {
  609. struct ath_softc *sc = hw->priv;
  610. struct ath_hw *ah = sc->sc_ah;
  611. struct ath_common *common = ath9k_hw_common(ah);
  612. bool prev_idle;
  613. mutex_lock(&sc->mutex);
  614. ath_cancel_work(sc);
  615. del_timer_sync(&sc->rx_poll_timer);
  616. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  617. ath_dbg(common, ANY, "Device not present\n");
  618. mutex_unlock(&sc->mutex);
  619. return;
  620. }
  621. /* Ensure HW is awake when we try to shut it down. */
  622. ath9k_ps_wakeup(sc);
  623. spin_lock_bh(&sc->sc_pcu_lock);
  624. /* prevent tasklets to enable interrupts once we disable them */
  625. ah->imask &= ~ATH9K_INT_GLOBAL;
  626. /* make sure h/w will not generate any interrupt
  627. * before setting the invalid flag. */
  628. ath9k_hw_disable_interrupts(ah);
  629. spin_unlock_bh(&sc->sc_pcu_lock);
  630. /* we can now sync irq and kill any running tasklets, since we already
  631. * disabled interrupts and not holding a spin lock */
  632. synchronize_irq(sc->irq);
  633. tasklet_kill(&sc->intr_tq);
  634. tasklet_kill(&sc->bcon_tasklet);
  635. prev_idle = sc->ps_idle;
  636. sc->ps_idle = true;
  637. spin_lock_bh(&sc->sc_pcu_lock);
  638. if (ah->led_pin >= 0) {
  639. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  640. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  641. }
  642. ath_prepare_reset(sc);
  643. if (sc->rx.frag) {
  644. dev_kfree_skb_any(sc->rx.frag);
  645. sc->rx.frag = NULL;
  646. }
  647. if (!ah->curchan)
  648. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  649. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  650. ath9k_hw_phy_disable(ah);
  651. ath9k_hw_configpcipowersave(ah, true);
  652. spin_unlock_bh(&sc->sc_pcu_lock);
  653. ath9k_ps_restore(sc);
  654. set_bit(SC_OP_INVALID, &sc->sc_flags);
  655. sc->ps_idle = prev_idle;
  656. mutex_unlock(&sc->mutex);
  657. ath_dbg(common, CONFIG, "Driver halt\n");
  658. }
  659. bool ath9k_uses_beacons(int type)
  660. {
  661. switch (type) {
  662. case NL80211_IFTYPE_AP:
  663. case NL80211_IFTYPE_ADHOC:
  664. case NL80211_IFTYPE_MESH_POINT:
  665. return true;
  666. default:
  667. return false;
  668. }
  669. }
  670. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  671. {
  672. struct ath9k_vif_iter_data *iter_data = data;
  673. int i;
  674. if (iter_data->hw_macaddr)
  675. for (i = 0; i < ETH_ALEN; i++)
  676. iter_data->mask[i] &=
  677. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  678. switch (vif->type) {
  679. case NL80211_IFTYPE_AP:
  680. iter_data->naps++;
  681. break;
  682. case NL80211_IFTYPE_STATION:
  683. iter_data->nstations++;
  684. break;
  685. case NL80211_IFTYPE_ADHOC:
  686. iter_data->nadhocs++;
  687. break;
  688. case NL80211_IFTYPE_MESH_POINT:
  689. iter_data->nmeshes++;
  690. break;
  691. case NL80211_IFTYPE_WDS:
  692. iter_data->nwds++;
  693. break;
  694. default:
  695. break;
  696. }
  697. }
  698. static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  699. {
  700. struct ath_softc *sc = data;
  701. struct ath_vif *avp = (void *)vif->drv_priv;
  702. if (vif->type != NL80211_IFTYPE_STATION)
  703. return;
  704. if (avp->primary_sta_vif)
  705. ath9k_set_assoc_state(sc, vif);
  706. }
  707. /* Called with sc->mutex held. */
  708. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  709. struct ieee80211_vif *vif,
  710. struct ath9k_vif_iter_data *iter_data)
  711. {
  712. struct ath_softc *sc = hw->priv;
  713. struct ath_hw *ah = sc->sc_ah;
  714. struct ath_common *common = ath9k_hw_common(ah);
  715. /*
  716. * Use the hardware MAC address as reference, the hardware uses it
  717. * together with the BSSID mask when matching addresses.
  718. */
  719. memset(iter_data, 0, sizeof(*iter_data));
  720. iter_data->hw_macaddr = common->macaddr;
  721. memset(&iter_data->mask, 0xff, ETH_ALEN);
  722. if (vif)
  723. ath9k_vif_iter(iter_data, vif->addr, vif);
  724. /* Get list of all active MAC addresses */
  725. ieee80211_iterate_active_interfaces_atomic(
  726. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  727. ath9k_vif_iter, iter_data);
  728. }
  729. /* Called with sc->mutex held. */
  730. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  731. struct ieee80211_vif *vif)
  732. {
  733. struct ath_softc *sc = hw->priv;
  734. struct ath_hw *ah = sc->sc_ah;
  735. struct ath_common *common = ath9k_hw_common(ah);
  736. struct ath9k_vif_iter_data iter_data;
  737. enum nl80211_iftype old_opmode = ah->opmode;
  738. ath9k_calculate_iter_data(hw, vif, &iter_data);
  739. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  740. ath_hw_setbssidmask(common);
  741. if (iter_data.naps > 0) {
  742. ath9k_hw_set_tsfadjust(ah, true);
  743. ah->opmode = NL80211_IFTYPE_AP;
  744. } else {
  745. ath9k_hw_set_tsfadjust(ah, false);
  746. if (iter_data.nmeshes)
  747. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  748. else if (iter_data.nwds)
  749. ah->opmode = NL80211_IFTYPE_AP;
  750. else if (iter_data.nadhocs)
  751. ah->opmode = NL80211_IFTYPE_ADHOC;
  752. else
  753. ah->opmode = NL80211_IFTYPE_STATION;
  754. }
  755. ath9k_hw_setopmode(ah);
  756. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  757. ah->imask |= ATH9K_INT_TSFOOR;
  758. else
  759. ah->imask &= ~ATH9K_INT_TSFOOR;
  760. ath9k_hw_set_interrupts(ah);
  761. /*
  762. * If we are changing the opmode to STATION,
  763. * a beacon sync needs to be done.
  764. */
  765. if (ah->opmode == NL80211_IFTYPE_STATION &&
  766. old_opmode == NL80211_IFTYPE_AP &&
  767. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  768. ieee80211_iterate_active_interfaces_atomic(
  769. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  770. ath9k_sta_vif_iter, sc);
  771. }
  772. }
  773. static int ath9k_add_interface(struct ieee80211_hw *hw,
  774. struct ieee80211_vif *vif)
  775. {
  776. struct ath_softc *sc = hw->priv;
  777. struct ath_hw *ah = sc->sc_ah;
  778. struct ath_common *common = ath9k_hw_common(ah);
  779. mutex_lock(&sc->mutex);
  780. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  781. sc->nvifs++;
  782. ath9k_ps_wakeup(sc);
  783. ath9k_calculate_summary_state(hw, vif);
  784. ath9k_ps_restore(sc);
  785. if (ath9k_uses_beacons(vif->type))
  786. ath9k_beacon_assign_slot(sc, vif);
  787. mutex_unlock(&sc->mutex);
  788. return 0;
  789. }
  790. static int ath9k_change_interface(struct ieee80211_hw *hw,
  791. struct ieee80211_vif *vif,
  792. enum nl80211_iftype new_type,
  793. bool p2p)
  794. {
  795. struct ath_softc *sc = hw->priv;
  796. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  797. ath_dbg(common, CONFIG, "Change Interface\n");
  798. mutex_lock(&sc->mutex);
  799. if (ath9k_uses_beacons(vif->type))
  800. ath9k_beacon_remove_slot(sc, vif);
  801. vif->type = new_type;
  802. vif->p2p = p2p;
  803. ath9k_ps_wakeup(sc);
  804. ath9k_calculate_summary_state(hw, vif);
  805. ath9k_ps_restore(sc);
  806. if (ath9k_uses_beacons(vif->type))
  807. ath9k_beacon_assign_slot(sc, vif);
  808. mutex_unlock(&sc->mutex);
  809. return 0;
  810. }
  811. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  812. struct ieee80211_vif *vif)
  813. {
  814. struct ath_softc *sc = hw->priv;
  815. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  816. ath_dbg(common, CONFIG, "Detach Interface\n");
  817. mutex_lock(&sc->mutex);
  818. sc->nvifs--;
  819. if (ath9k_uses_beacons(vif->type))
  820. ath9k_beacon_remove_slot(sc, vif);
  821. ath9k_ps_wakeup(sc);
  822. ath9k_calculate_summary_state(hw, NULL);
  823. ath9k_ps_restore(sc);
  824. mutex_unlock(&sc->mutex);
  825. }
  826. static void ath9k_enable_ps(struct ath_softc *sc)
  827. {
  828. struct ath_hw *ah = sc->sc_ah;
  829. struct ath_common *common = ath9k_hw_common(ah);
  830. sc->ps_enabled = true;
  831. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  832. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  833. ah->imask |= ATH9K_INT_TIM_TIMER;
  834. ath9k_hw_set_interrupts(ah);
  835. }
  836. ath9k_hw_setrxabort(ah, 1);
  837. }
  838. ath_dbg(common, PS, "PowerSave enabled\n");
  839. }
  840. static void ath9k_disable_ps(struct ath_softc *sc)
  841. {
  842. struct ath_hw *ah = sc->sc_ah;
  843. struct ath_common *common = ath9k_hw_common(ah);
  844. sc->ps_enabled = false;
  845. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  846. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  847. ath9k_hw_setrxabort(ah, 0);
  848. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  849. PS_WAIT_FOR_CAB |
  850. PS_WAIT_FOR_PSPOLL_DATA |
  851. PS_WAIT_FOR_TX_ACK);
  852. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  853. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  854. ath9k_hw_set_interrupts(ah);
  855. }
  856. }
  857. ath_dbg(common, PS, "PowerSave disabled\n");
  858. }
  859. void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
  860. {
  861. struct ath_softc *sc = hw->priv;
  862. struct ath_hw *ah = sc->sc_ah;
  863. struct ath_common *common = ath9k_hw_common(ah);
  864. u32 rxfilter;
  865. if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
  866. ath_err(common, "spectrum analyzer not implemented on this hardware\n");
  867. return;
  868. }
  869. ath9k_ps_wakeup(sc);
  870. rxfilter = ath9k_hw_getrxfilter(ah);
  871. ath9k_hw_setrxfilter(ah, rxfilter |
  872. ATH9K_RX_FILTER_PHYRADAR |
  873. ATH9K_RX_FILTER_PHYERR);
  874. /* TODO: usually this should not be neccesary, but for some reason
  875. * (or in some mode?) the trigger must be called after the
  876. * configuration, otherwise the register will have its values reset
  877. * (on my ar9220 to value 0x01002310)
  878. */
  879. ath9k_spectral_scan_config(hw, sc->spectral_mode);
  880. ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
  881. ath9k_ps_restore(sc);
  882. }
  883. int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
  884. enum spectral_mode spectral_mode)
  885. {
  886. struct ath_softc *sc = hw->priv;
  887. struct ath_hw *ah = sc->sc_ah;
  888. struct ath_common *common = ath9k_hw_common(ah);
  889. if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
  890. ath_err(common, "spectrum analyzer not implemented on this hardware\n");
  891. return -1;
  892. }
  893. switch (spectral_mode) {
  894. case SPECTRAL_DISABLED:
  895. sc->spec_config.enabled = 0;
  896. break;
  897. case SPECTRAL_BACKGROUND:
  898. /* send endless samples.
  899. * TODO: is this really useful for "background"?
  900. */
  901. sc->spec_config.endless = 1;
  902. sc->spec_config.enabled = 1;
  903. break;
  904. case SPECTRAL_CHANSCAN:
  905. case SPECTRAL_MANUAL:
  906. sc->spec_config.endless = 0;
  907. sc->spec_config.enabled = 1;
  908. break;
  909. default:
  910. return -1;
  911. }
  912. ath9k_ps_wakeup(sc);
  913. ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config);
  914. ath9k_ps_restore(sc);
  915. sc->spectral_mode = spectral_mode;
  916. return 0;
  917. }
  918. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  919. {
  920. struct ath_softc *sc = hw->priv;
  921. struct ath_hw *ah = sc->sc_ah;
  922. struct ath_common *common = ath9k_hw_common(ah);
  923. struct ieee80211_conf *conf = &hw->conf;
  924. bool reset_channel = false;
  925. ath9k_ps_wakeup(sc);
  926. mutex_lock(&sc->mutex);
  927. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  928. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  929. if (sc->ps_idle) {
  930. ath_cancel_work(sc);
  931. ath9k_stop_btcoex(sc);
  932. } else {
  933. ath9k_start_btcoex(sc);
  934. /*
  935. * The chip needs a reset to properly wake up from
  936. * full sleep
  937. */
  938. reset_channel = ah->chip_fullsleep;
  939. }
  940. }
  941. /*
  942. * We just prepare to enable PS. We have to wait until our AP has
  943. * ACK'd our null data frame to disable RX otherwise we'll ignore
  944. * those ACKs and end up retransmitting the same null data frames.
  945. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  946. */
  947. if (changed & IEEE80211_CONF_CHANGE_PS) {
  948. unsigned long flags;
  949. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  950. if (conf->flags & IEEE80211_CONF_PS)
  951. ath9k_enable_ps(sc);
  952. else
  953. ath9k_disable_ps(sc);
  954. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  955. }
  956. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  957. if (conf->flags & IEEE80211_CONF_MONITOR) {
  958. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  959. sc->sc_ah->is_monitoring = true;
  960. } else {
  961. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  962. sc->sc_ah->is_monitoring = false;
  963. }
  964. }
  965. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  966. struct ieee80211_channel *curchan = hw->conf.channel;
  967. int pos = curchan->hw_value;
  968. int old_pos = -1;
  969. unsigned long flags;
  970. if (ah->curchan)
  971. old_pos = ah->curchan - &ah->channels[0];
  972. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  973. curchan->center_freq, conf->channel_type);
  974. /* update survey stats for the old channel before switching */
  975. spin_lock_irqsave(&common->cc_lock, flags);
  976. ath_update_survey_stats(sc);
  977. spin_unlock_irqrestore(&common->cc_lock, flags);
  978. /*
  979. * Preserve the current channel values, before updating
  980. * the same channel
  981. */
  982. if (ah->curchan && (old_pos == pos))
  983. ath9k_hw_getnf(ah, ah->curchan);
  984. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  985. curchan, conf->channel_type);
  986. /*
  987. * If the operating channel changes, change the survey in-use flags
  988. * along with it.
  989. * Reset the survey data for the new channel, unless we're switching
  990. * back to the operating channel from an off-channel operation.
  991. */
  992. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  993. sc->cur_survey != &sc->survey[pos]) {
  994. if (sc->cur_survey)
  995. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  996. sc->cur_survey = &sc->survey[pos];
  997. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  998. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  999. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1000. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1001. }
  1002. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1003. ath_err(common, "Unable to set channel\n");
  1004. mutex_unlock(&sc->mutex);
  1005. ath9k_ps_restore(sc);
  1006. return -EINVAL;
  1007. }
  1008. /*
  1009. * The most recent snapshot of channel->noisefloor for the old
  1010. * channel is only available after the hardware reset. Copy it to
  1011. * the survey stats now.
  1012. */
  1013. if (old_pos >= 0)
  1014. ath_update_survey_nf(sc, old_pos);
  1015. /* perform spectral scan if requested. */
  1016. if (sc->scanning && sc->spectral_mode == SPECTRAL_CHANSCAN)
  1017. ath9k_spectral_scan_trigger(hw);
  1018. }
  1019. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1020. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1021. sc->config.txpowlimit = 2 * conf->power_level;
  1022. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1023. sc->config.txpowlimit, &sc->curtxpow);
  1024. }
  1025. mutex_unlock(&sc->mutex);
  1026. ath9k_ps_restore(sc);
  1027. return 0;
  1028. }
  1029. #define SUPPORTED_FILTERS \
  1030. (FIF_PROMISC_IN_BSS | \
  1031. FIF_ALLMULTI | \
  1032. FIF_CONTROL | \
  1033. FIF_PSPOLL | \
  1034. FIF_OTHER_BSS | \
  1035. FIF_BCN_PRBRESP_PROMISC | \
  1036. FIF_PROBE_REQ | \
  1037. FIF_FCSFAIL)
  1038. /* FIXME: sc->sc_full_reset ? */
  1039. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1040. unsigned int changed_flags,
  1041. unsigned int *total_flags,
  1042. u64 multicast)
  1043. {
  1044. struct ath_softc *sc = hw->priv;
  1045. u32 rfilt;
  1046. changed_flags &= SUPPORTED_FILTERS;
  1047. *total_flags &= SUPPORTED_FILTERS;
  1048. sc->rx.rxfilter = *total_flags;
  1049. ath9k_ps_wakeup(sc);
  1050. rfilt = ath_calcrxfilter(sc);
  1051. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1052. ath9k_ps_restore(sc);
  1053. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1054. rfilt);
  1055. }
  1056. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1057. struct ieee80211_vif *vif,
  1058. struct ieee80211_sta *sta)
  1059. {
  1060. struct ath_softc *sc = hw->priv;
  1061. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1062. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1063. struct ieee80211_key_conf ps_key = { };
  1064. ath_node_attach(sc, sta, vif);
  1065. if (vif->type != NL80211_IFTYPE_AP &&
  1066. vif->type != NL80211_IFTYPE_AP_VLAN)
  1067. return 0;
  1068. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1069. return 0;
  1070. }
  1071. static void ath9k_del_ps_key(struct ath_softc *sc,
  1072. struct ieee80211_vif *vif,
  1073. struct ieee80211_sta *sta)
  1074. {
  1075. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1076. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1077. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1078. if (!an->ps_key)
  1079. return;
  1080. ath_key_delete(common, &ps_key);
  1081. }
  1082. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1083. struct ieee80211_vif *vif,
  1084. struct ieee80211_sta *sta)
  1085. {
  1086. struct ath_softc *sc = hw->priv;
  1087. ath9k_del_ps_key(sc, vif, sta);
  1088. ath_node_detach(sc, sta);
  1089. return 0;
  1090. }
  1091. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1092. struct ieee80211_vif *vif,
  1093. enum sta_notify_cmd cmd,
  1094. struct ieee80211_sta *sta)
  1095. {
  1096. struct ath_softc *sc = hw->priv;
  1097. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1098. if (!sta->ht_cap.ht_supported)
  1099. return;
  1100. switch (cmd) {
  1101. case STA_NOTIFY_SLEEP:
  1102. an->sleeping = true;
  1103. ath_tx_aggr_sleep(sta, sc, an);
  1104. break;
  1105. case STA_NOTIFY_AWAKE:
  1106. an->sleeping = false;
  1107. ath_tx_aggr_wakeup(sc, an);
  1108. break;
  1109. }
  1110. }
  1111. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1112. struct ieee80211_vif *vif, u16 queue,
  1113. const struct ieee80211_tx_queue_params *params)
  1114. {
  1115. struct ath_softc *sc = hw->priv;
  1116. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1117. struct ath_txq *txq;
  1118. struct ath9k_tx_queue_info qi;
  1119. int ret = 0;
  1120. if (queue >= IEEE80211_NUM_ACS)
  1121. return 0;
  1122. txq = sc->tx.txq_map[queue];
  1123. ath9k_ps_wakeup(sc);
  1124. mutex_lock(&sc->mutex);
  1125. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1126. qi.tqi_aifs = params->aifs;
  1127. qi.tqi_cwmin = params->cw_min;
  1128. qi.tqi_cwmax = params->cw_max;
  1129. qi.tqi_burstTime = params->txop * 32;
  1130. ath_dbg(common, CONFIG,
  1131. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1132. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1133. params->cw_max, params->txop);
  1134. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1135. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1136. if (ret)
  1137. ath_err(common, "TXQ Update failed\n");
  1138. mutex_unlock(&sc->mutex);
  1139. ath9k_ps_restore(sc);
  1140. return ret;
  1141. }
  1142. static int ath9k_set_key(struct ieee80211_hw *hw,
  1143. enum set_key_cmd cmd,
  1144. struct ieee80211_vif *vif,
  1145. struct ieee80211_sta *sta,
  1146. struct ieee80211_key_conf *key)
  1147. {
  1148. struct ath_softc *sc = hw->priv;
  1149. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1150. int ret = 0;
  1151. if (ath9k_modparam_nohwcrypt)
  1152. return -ENOSPC;
  1153. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1154. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1155. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1156. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1157. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1158. /*
  1159. * For now, disable hw crypto for the RSN IBSS group keys. This
  1160. * could be optimized in the future to use a modified key cache
  1161. * design to support per-STA RX GTK, but until that gets
  1162. * implemented, use of software crypto for group addressed
  1163. * frames is a acceptable to allow RSN IBSS to be used.
  1164. */
  1165. return -EOPNOTSUPP;
  1166. }
  1167. mutex_lock(&sc->mutex);
  1168. ath9k_ps_wakeup(sc);
  1169. ath_dbg(common, CONFIG, "Set HW Key\n");
  1170. switch (cmd) {
  1171. case SET_KEY:
  1172. if (sta)
  1173. ath9k_del_ps_key(sc, vif, sta);
  1174. ret = ath_key_config(common, vif, sta, key);
  1175. if (ret >= 0) {
  1176. key->hw_key_idx = ret;
  1177. /* push IV and Michael MIC generation to stack */
  1178. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1179. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1180. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1181. if (sc->sc_ah->sw_mgmt_crypto &&
  1182. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1183. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1184. ret = 0;
  1185. }
  1186. break;
  1187. case DISABLE_KEY:
  1188. ath_key_delete(common, key);
  1189. break;
  1190. default:
  1191. ret = -EINVAL;
  1192. }
  1193. ath9k_ps_restore(sc);
  1194. mutex_unlock(&sc->mutex);
  1195. return ret;
  1196. }
  1197. static void ath9k_set_assoc_state(struct ath_softc *sc,
  1198. struct ieee80211_vif *vif)
  1199. {
  1200. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1201. struct ath_vif *avp = (void *)vif->drv_priv;
  1202. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1203. unsigned long flags;
  1204. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1205. avp->primary_sta_vif = true;
  1206. /*
  1207. * Set the AID, BSSID and do beacon-sync only when
  1208. * the HW opmode is STATION.
  1209. *
  1210. * But the primary bit is set above in any case.
  1211. */
  1212. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1213. return;
  1214. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1215. common->curaid = bss_conf->aid;
  1216. ath9k_hw_write_associd(sc->sc_ah);
  1217. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1218. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1219. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1220. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1221. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1222. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1223. ath9k_mci_update_wlan_channels(sc, false);
  1224. ath_dbg(common, CONFIG,
  1225. "Primary Station interface: %pM, BSSID: %pM\n",
  1226. vif->addr, common->curbssid);
  1227. }
  1228. static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1229. {
  1230. struct ath_softc *sc = data;
  1231. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1232. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1233. return;
  1234. if (bss_conf->assoc)
  1235. ath9k_set_assoc_state(sc, vif);
  1236. }
  1237. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1238. struct ieee80211_vif *vif,
  1239. struct ieee80211_bss_conf *bss_conf,
  1240. u32 changed)
  1241. {
  1242. #define CHECK_ANI \
  1243. (BSS_CHANGED_ASSOC | \
  1244. BSS_CHANGED_IBSS | \
  1245. BSS_CHANGED_BEACON_ENABLED)
  1246. struct ath_softc *sc = hw->priv;
  1247. struct ath_hw *ah = sc->sc_ah;
  1248. struct ath_common *common = ath9k_hw_common(ah);
  1249. struct ath_vif *avp = (void *)vif->drv_priv;
  1250. int slottime;
  1251. ath9k_ps_wakeup(sc);
  1252. mutex_lock(&sc->mutex);
  1253. if (changed & BSS_CHANGED_ASSOC) {
  1254. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1255. bss_conf->bssid, bss_conf->assoc);
  1256. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1257. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1258. avp->primary_sta_vif = false;
  1259. if (ah->opmode == NL80211_IFTYPE_STATION)
  1260. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1261. }
  1262. ieee80211_iterate_active_interfaces_atomic(
  1263. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  1264. ath9k_bss_assoc_iter, sc);
  1265. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
  1266. ah->opmode == NL80211_IFTYPE_STATION) {
  1267. memset(common->curbssid, 0, ETH_ALEN);
  1268. common->curaid = 0;
  1269. ath9k_hw_write_associd(sc->sc_ah);
  1270. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1271. ath9k_mci_update_wlan_channels(sc, true);
  1272. }
  1273. }
  1274. if (changed & BSS_CHANGED_IBSS) {
  1275. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1276. common->curaid = bss_conf->aid;
  1277. ath9k_hw_write_associd(sc->sc_ah);
  1278. }
  1279. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1280. (changed & BSS_CHANGED_BEACON_INT)) {
  1281. if (ah->opmode == NL80211_IFTYPE_AP &&
  1282. bss_conf->enable_beacon)
  1283. ath9k_set_tsfadjust(sc, vif);
  1284. if (ath9k_allow_beacon_config(sc, vif))
  1285. ath9k_beacon_config(sc, vif, changed);
  1286. }
  1287. if (changed & BSS_CHANGED_ERP_SLOT) {
  1288. if (bss_conf->use_short_slot)
  1289. slottime = 9;
  1290. else
  1291. slottime = 20;
  1292. if (vif->type == NL80211_IFTYPE_AP) {
  1293. /*
  1294. * Defer update, so that connected stations can adjust
  1295. * their settings at the same time.
  1296. * See beacon.c for more details
  1297. */
  1298. sc->beacon.slottime = slottime;
  1299. sc->beacon.updateslot = UPDATE;
  1300. } else {
  1301. ah->slottime = slottime;
  1302. ath9k_hw_init_global_settings(ah);
  1303. }
  1304. }
  1305. if (changed & CHECK_ANI)
  1306. ath_check_ani(sc);
  1307. mutex_unlock(&sc->mutex);
  1308. ath9k_ps_restore(sc);
  1309. #undef CHECK_ANI
  1310. }
  1311. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1312. {
  1313. struct ath_softc *sc = hw->priv;
  1314. u64 tsf;
  1315. mutex_lock(&sc->mutex);
  1316. ath9k_ps_wakeup(sc);
  1317. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1318. ath9k_ps_restore(sc);
  1319. mutex_unlock(&sc->mutex);
  1320. return tsf;
  1321. }
  1322. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1323. struct ieee80211_vif *vif,
  1324. u64 tsf)
  1325. {
  1326. struct ath_softc *sc = hw->priv;
  1327. mutex_lock(&sc->mutex);
  1328. ath9k_ps_wakeup(sc);
  1329. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1330. ath9k_ps_restore(sc);
  1331. mutex_unlock(&sc->mutex);
  1332. }
  1333. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1334. {
  1335. struct ath_softc *sc = hw->priv;
  1336. mutex_lock(&sc->mutex);
  1337. ath9k_ps_wakeup(sc);
  1338. ath9k_hw_reset_tsf(sc->sc_ah);
  1339. ath9k_ps_restore(sc);
  1340. mutex_unlock(&sc->mutex);
  1341. }
  1342. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1343. struct ieee80211_vif *vif,
  1344. enum ieee80211_ampdu_mlme_action action,
  1345. struct ieee80211_sta *sta,
  1346. u16 tid, u16 *ssn, u8 buf_size)
  1347. {
  1348. struct ath_softc *sc = hw->priv;
  1349. int ret = 0;
  1350. local_bh_disable();
  1351. switch (action) {
  1352. case IEEE80211_AMPDU_RX_START:
  1353. break;
  1354. case IEEE80211_AMPDU_RX_STOP:
  1355. break;
  1356. case IEEE80211_AMPDU_TX_START:
  1357. ath9k_ps_wakeup(sc);
  1358. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1359. if (!ret)
  1360. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1361. ath9k_ps_restore(sc);
  1362. break;
  1363. case IEEE80211_AMPDU_TX_STOP_CONT:
  1364. case IEEE80211_AMPDU_TX_STOP_FLUSH:
  1365. case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
  1366. ath9k_ps_wakeup(sc);
  1367. ath_tx_aggr_stop(sc, sta, tid);
  1368. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1369. ath9k_ps_restore(sc);
  1370. break;
  1371. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1372. ath9k_ps_wakeup(sc);
  1373. ath_tx_aggr_resume(sc, sta, tid);
  1374. ath9k_ps_restore(sc);
  1375. break;
  1376. default:
  1377. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1378. }
  1379. local_bh_enable();
  1380. return ret;
  1381. }
  1382. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1383. struct survey_info *survey)
  1384. {
  1385. struct ath_softc *sc = hw->priv;
  1386. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1387. struct ieee80211_supported_band *sband;
  1388. struct ieee80211_channel *chan;
  1389. unsigned long flags;
  1390. int pos;
  1391. spin_lock_irqsave(&common->cc_lock, flags);
  1392. if (idx == 0)
  1393. ath_update_survey_stats(sc);
  1394. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1395. if (sband && idx >= sband->n_channels) {
  1396. idx -= sband->n_channels;
  1397. sband = NULL;
  1398. }
  1399. if (!sband)
  1400. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1401. if (!sband || idx >= sband->n_channels) {
  1402. spin_unlock_irqrestore(&common->cc_lock, flags);
  1403. return -ENOENT;
  1404. }
  1405. chan = &sband->channels[idx];
  1406. pos = chan->hw_value;
  1407. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1408. survey->channel = chan;
  1409. spin_unlock_irqrestore(&common->cc_lock, flags);
  1410. return 0;
  1411. }
  1412. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1413. {
  1414. struct ath_softc *sc = hw->priv;
  1415. struct ath_hw *ah = sc->sc_ah;
  1416. mutex_lock(&sc->mutex);
  1417. ah->coverage_class = coverage_class;
  1418. ath9k_ps_wakeup(sc);
  1419. ath9k_hw_init_global_settings(ah);
  1420. ath9k_ps_restore(sc);
  1421. mutex_unlock(&sc->mutex);
  1422. }
  1423. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1424. {
  1425. struct ath_softc *sc = hw->priv;
  1426. struct ath_hw *ah = sc->sc_ah;
  1427. struct ath_common *common = ath9k_hw_common(ah);
  1428. int timeout = 200; /* ms */
  1429. int i, j;
  1430. bool drain_txq;
  1431. mutex_lock(&sc->mutex);
  1432. cancel_delayed_work_sync(&sc->tx_complete_work);
  1433. if (ah->ah_flags & AH_UNPLUGGED) {
  1434. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1435. mutex_unlock(&sc->mutex);
  1436. return;
  1437. }
  1438. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1439. ath_dbg(common, ANY, "Device not present\n");
  1440. mutex_unlock(&sc->mutex);
  1441. return;
  1442. }
  1443. for (j = 0; j < timeout; j++) {
  1444. bool npend = false;
  1445. if (j)
  1446. usleep_range(1000, 2000);
  1447. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1448. if (!ATH_TXQ_SETUP(sc, i))
  1449. continue;
  1450. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1451. if (npend)
  1452. break;
  1453. }
  1454. if (!npend)
  1455. break;
  1456. }
  1457. if (drop) {
  1458. ath9k_ps_wakeup(sc);
  1459. spin_lock_bh(&sc->sc_pcu_lock);
  1460. drain_txq = ath_drain_all_txq(sc);
  1461. spin_unlock_bh(&sc->sc_pcu_lock);
  1462. if (!drain_txq)
  1463. ath_reset(sc);
  1464. ath9k_ps_restore(sc);
  1465. ieee80211_wake_queues(hw);
  1466. }
  1467. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1468. mutex_unlock(&sc->mutex);
  1469. }
  1470. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1471. {
  1472. struct ath_softc *sc = hw->priv;
  1473. int i;
  1474. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1475. if (!ATH_TXQ_SETUP(sc, i))
  1476. continue;
  1477. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1478. return true;
  1479. }
  1480. return false;
  1481. }
  1482. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1483. {
  1484. struct ath_softc *sc = hw->priv;
  1485. struct ath_hw *ah = sc->sc_ah;
  1486. struct ieee80211_vif *vif;
  1487. struct ath_vif *avp;
  1488. struct ath_buf *bf;
  1489. struct ath_tx_status ts;
  1490. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1491. int status;
  1492. vif = sc->beacon.bslot[0];
  1493. if (!vif)
  1494. return 0;
  1495. if (!vif->bss_conf.enable_beacon)
  1496. return 0;
  1497. avp = (void *)vif->drv_priv;
  1498. if (!sc->beacon.tx_processed && !edma) {
  1499. tasklet_disable(&sc->bcon_tasklet);
  1500. bf = avp->av_bcbuf;
  1501. if (!bf || !bf->bf_mpdu)
  1502. goto skip;
  1503. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1504. if (status == -EINPROGRESS)
  1505. goto skip;
  1506. sc->beacon.tx_processed = true;
  1507. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1508. skip:
  1509. tasklet_enable(&sc->bcon_tasklet);
  1510. }
  1511. return sc->beacon.tx_last;
  1512. }
  1513. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1514. struct ieee80211_low_level_stats *stats)
  1515. {
  1516. struct ath_softc *sc = hw->priv;
  1517. struct ath_hw *ah = sc->sc_ah;
  1518. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1519. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1520. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1521. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1522. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1523. return 0;
  1524. }
  1525. static u32 fill_chainmask(u32 cap, u32 new)
  1526. {
  1527. u32 filled = 0;
  1528. int i;
  1529. for (i = 0; cap && new; i++, cap >>= 1) {
  1530. if (!(cap & BIT(0)))
  1531. continue;
  1532. if (new & BIT(0))
  1533. filled |= BIT(i);
  1534. new >>= 1;
  1535. }
  1536. return filled;
  1537. }
  1538. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1539. {
  1540. if (AR_SREV_9300_20_OR_LATER(ah))
  1541. return true;
  1542. switch (val & 0x7) {
  1543. case 0x1:
  1544. case 0x3:
  1545. case 0x7:
  1546. return true;
  1547. case 0x2:
  1548. return (ah->caps.rx_chainmask == 1);
  1549. default:
  1550. return false;
  1551. }
  1552. }
  1553. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1554. {
  1555. struct ath_softc *sc = hw->priv;
  1556. struct ath_hw *ah = sc->sc_ah;
  1557. if (ah->caps.rx_chainmask != 1)
  1558. rx_ant |= tx_ant;
  1559. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1560. return -EINVAL;
  1561. sc->ant_rx = rx_ant;
  1562. sc->ant_tx = tx_ant;
  1563. if (ah->caps.rx_chainmask == 1)
  1564. return 0;
  1565. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1566. if (AR_SREV_9100(ah))
  1567. ah->rxchainmask = 0x7;
  1568. else
  1569. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1570. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1571. ath9k_reload_chainmask_settings(sc);
  1572. return 0;
  1573. }
  1574. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1575. {
  1576. struct ath_softc *sc = hw->priv;
  1577. *tx_ant = sc->ant_tx;
  1578. *rx_ant = sc->ant_rx;
  1579. return 0;
  1580. }
  1581. #ifdef CONFIG_PM_SLEEP
  1582. static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1583. struct cfg80211_wowlan *wowlan,
  1584. u32 *wow_triggers)
  1585. {
  1586. if (wowlan->disconnect)
  1587. *wow_triggers |= AH_WOW_LINK_CHANGE |
  1588. AH_WOW_BEACON_MISS;
  1589. if (wowlan->magic_pkt)
  1590. *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1591. if (wowlan->n_patterns)
  1592. *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1593. sc->wow_enabled = *wow_triggers;
  1594. }
  1595. static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1596. {
  1597. struct ath_hw *ah = sc->sc_ah;
  1598. struct ath_common *common = ath9k_hw_common(ah);
  1599. struct ath9k_hw_capabilities *pcaps = &ah->caps;
  1600. int pattern_count = 0;
  1601. int i, byte_cnt;
  1602. u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1603. u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1604. memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1605. memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1606. /*
  1607. * Create Dissassociate / Deauthenticate packet filter
  1608. *
  1609. * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1610. * +--------------+----------+---------+--------+--------+----
  1611. * + Frame Control+ Duration + DA + SA + BSSID +
  1612. * +--------------+----------+---------+--------+--------+----
  1613. *
  1614. * The above is the management frame format for disassociate/
  1615. * deauthenticate pattern, from this we need to match the first byte
  1616. * of 'Frame Control' and DA, SA, and BSSID fields
  1617. * (skipping 2nd byte of FC and Duration feild.
  1618. *
  1619. * Disassociate pattern
  1620. * --------------------
  1621. * Frame control = 00 00 1010
  1622. * DA, SA, BSSID = x:x:x:x:x:x
  1623. * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1624. * | x:x:x:x:x:x -- 22 bytes
  1625. *
  1626. * Deauthenticate pattern
  1627. * ----------------------
  1628. * Frame control = 00 00 1100
  1629. * DA, SA, BSSID = x:x:x:x:x:x
  1630. * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1631. * | x:x:x:x:x:x -- 22 bytes
  1632. */
  1633. /* Create Disassociate Pattern first */
  1634. byte_cnt = 0;
  1635. /* Fill out the mask with all FF's */
  1636. for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1637. dis_deauth_mask[i] = 0xff;
  1638. /* copy the first byte of frame control field */
  1639. dis_deauth_pattern[byte_cnt] = 0xa0;
  1640. byte_cnt++;
  1641. /* skip 2nd byte of frame control and Duration field */
  1642. byte_cnt += 3;
  1643. /*
  1644. * need not match the destination mac address, it can be a broadcast
  1645. * mac address or an unicast to this station
  1646. */
  1647. byte_cnt += 6;
  1648. /* copy the source mac address */
  1649. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1650. byte_cnt += 6;
  1651. /* copy the bssid, its same as the source mac address */
  1652. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1653. /* Create Disassociate pattern mask */
  1654. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
  1655. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
  1656. /*
  1657. * for AR9280, because of hardware limitation, the
  1658. * first 4 bytes have to be matched for all patterns.
  1659. * the mask for disassociation and de-auth pattern
  1660. * matching need to enable the first 4 bytes.
  1661. * also the duration field needs to be filled.
  1662. */
  1663. dis_deauth_mask[0] = 0xf0;
  1664. /*
  1665. * fill in duration field
  1666. FIXME: what is the exact value ?
  1667. */
  1668. dis_deauth_pattern[2] = 0xff;
  1669. dis_deauth_pattern[3] = 0xff;
  1670. } else {
  1671. dis_deauth_mask[0] = 0xfe;
  1672. }
  1673. dis_deauth_mask[1] = 0x03;
  1674. dis_deauth_mask[2] = 0xc0;
  1675. } else {
  1676. dis_deauth_mask[0] = 0xef;
  1677. dis_deauth_mask[1] = 0x3f;
  1678. dis_deauth_mask[2] = 0x00;
  1679. dis_deauth_mask[3] = 0xfc;
  1680. }
  1681. ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1682. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1683. pattern_count, byte_cnt);
  1684. pattern_count++;
  1685. /*
  1686. * for de-authenticate pattern, only the first byte of the frame
  1687. * control field gets changed from 0xA0 to 0xC0
  1688. */
  1689. dis_deauth_pattern[0] = 0xC0;
  1690. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1691. pattern_count, byte_cnt);
  1692. }
  1693. static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1694. struct cfg80211_wowlan *wowlan)
  1695. {
  1696. struct ath_hw *ah = sc->sc_ah;
  1697. struct ath9k_wow_pattern *wow_pattern = NULL;
  1698. struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
  1699. int mask_len;
  1700. s8 i = 0;
  1701. if (!wowlan->n_patterns)
  1702. return;
  1703. /*
  1704. * Add the new user configured patterns
  1705. */
  1706. for (i = 0; i < wowlan->n_patterns; i++) {
  1707. wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1708. if (!wow_pattern)
  1709. return;
  1710. /*
  1711. * TODO: convert the generic user space pattern to
  1712. * appropriate chip specific/802.11 pattern.
  1713. */
  1714. mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1715. memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1716. memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1717. memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1718. patterns[i].pattern_len);
  1719. memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1720. wow_pattern->pattern_len = patterns[i].pattern_len;
  1721. /*
  1722. * just need to take care of deauth and disssoc pattern,
  1723. * make sure we don't overwrite them.
  1724. */
  1725. ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1726. wow_pattern->mask_bytes,
  1727. i + 2,
  1728. wow_pattern->pattern_len);
  1729. kfree(wow_pattern);
  1730. }
  1731. }
  1732. static int ath9k_suspend(struct ieee80211_hw *hw,
  1733. struct cfg80211_wowlan *wowlan)
  1734. {
  1735. struct ath_softc *sc = hw->priv;
  1736. struct ath_hw *ah = sc->sc_ah;
  1737. struct ath_common *common = ath9k_hw_common(ah);
  1738. u32 wow_triggers_enabled = 0;
  1739. int ret = 0;
  1740. mutex_lock(&sc->mutex);
  1741. ath_cancel_work(sc);
  1742. ath_stop_ani(sc);
  1743. del_timer_sync(&sc->rx_poll_timer);
  1744. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1745. ath_dbg(common, ANY, "Device not present\n");
  1746. ret = -EINVAL;
  1747. goto fail_wow;
  1748. }
  1749. if (WARN_ON(!wowlan)) {
  1750. ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1751. ret = -EINVAL;
  1752. goto fail_wow;
  1753. }
  1754. if (!device_can_wakeup(sc->dev)) {
  1755. ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1756. ret = 1;
  1757. goto fail_wow;
  1758. }
  1759. /*
  1760. * none of the sta vifs are associated
  1761. * and we are not currently handling multivif
  1762. * cases, for instance we have to seperately
  1763. * configure 'keep alive frame' for each
  1764. * STA.
  1765. */
  1766. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1767. ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1768. ret = 1;
  1769. goto fail_wow;
  1770. }
  1771. if (sc->nvifs > 1) {
  1772. ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1773. ret = 1;
  1774. goto fail_wow;
  1775. }
  1776. ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1777. ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1778. wow_triggers_enabled);
  1779. ath9k_ps_wakeup(sc);
  1780. ath9k_stop_btcoex(sc);
  1781. /*
  1782. * Enable wake up on recieving disassoc/deauth
  1783. * frame by default.
  1784. */
  1785. ath9k_wow_add_disassoc_deauth_pattern(sc);
  1786. if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1787. ath9k_wow_add_pattern(sc, wowlan);
  1788. spin_lock_bh(&sc->sc_pcu_lock);
  1789. /*
  1790. * To avoid false wake, we enable beacon miss interrupt only
  1791. * when we go to sleep. We save the current interrupt mask
  1792. * so we can restore it after the system wakes up
  1793. */
  1794. sc->wow_intr_before_sleep = ah->imask;
  1795. ah->imask &= ~ATH9K_INT_GLOBAL;
  1796. ath9k_hw_disable_interrupts(ah);
  1797. ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1798. ath9k_hw_set_interrupts(ah);
  1799. ath9k_hw_enable_interrupts(ah);
  1800. spin_unlock_bh(&sc->sc_pcu_lock);
  1801. /*
  1802. * we can now sync irq and kill any running tasklets, since we already
  1803. * disabled interrupts and not holding a spin lock
  1804. */
  1805. synchronize_irq(sc->irq);
  1806. tasklet_kill(&sc->intr_tq);
  1807. ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1808. ath9k_ps_restore(sc);
  1809. ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1810. atomic_inc(&sc->wow_sleep_proc_intr);
  1811. fail_wow:
  1812. mutex_unlock(&sc->mutex);
  1813. return ret;
  1814. }
  1815. static int ath9k_resume(struct ieee80211_hw *hw)
  1816. {
  1817. struct ath_softc *sc = hw->priv;
  1818. struct ath_hw *ah = sc->sc_ah;
  1819. struct ath_common *common = ath9k_hw_common(ah);
  1820. u32 wow_status;
  1821. mutex_lock(&sc->mutex);
  1822. ath9k_ps_wakeup(sc);
  1823. spin_lock_bh(&sc->sc_pcu_lock);
  1824. ath9k_hw_disable_interrupts(ah);
  1825. ah->imask = sc->wow_intr_before_sleep;
  1826. ath9k_hw_set_interrupts(ah);
  1827. ath9k_hw_enable_interrupts(ah);
  1828. spin_unlock_bh(&sc->sc_pcu_lock);
  1829. wow_status = ath9k_hw_wow_wakeup(ah);
  1830. if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1831. /*
  1832. * some devices may not pick beacon miss
  1833. * as the reason they woke up so we add
  1834. * that here for that shortcoming.
  1835. */
  1836. wow_status |= AH_WOW_BEACON_MISS;
  1837. atomic_dec(&sc->wow_got_bmiss_intr);
  1838. ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1839. }
  1840. atomic_dec(&sc->wow_sleep_proc_intr);
  1841. if (wow_status) {
  1842. ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1843. ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1844. }
  1845. ath_restart_work(sc);
  1846. ath9k_start_btcoex(sc);
  1847. ath9k_ps_restore(sc);
  1848. mutex_unlock(&sc->mutex);
  1849. return 0;
  1850. }
  1851. static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1852. {
  1853. struct ath_softc *sc = hw->priv;
  1854. mutex_lock(&sc->mutex);
  1855. device_init_wakeup(sc->dev, 1);
  1856. device_set_wakeup_enable(sc->dev, enabled);
  1857. mutex_unlock(&sc->mutex);
  1858. }
  1859. #endif
  1860. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1861. {
  1862. struct ath_softc *sc = hw->priv;
  1863. sc->scanning = 1;
  1864. }
  1865. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1866. {
  1867. struct ath_softc *sc = hw->priv;
  1868. sc->scanning = 0;
  1869. }
  1870. struct ieee80211_ops ath9k_ops = {
  1871. .tx = ath9k_tx,
  1872. .start = ath9k_start,
  1873. .stop = ath9k_stop,
  1874. .add_interface = ath9k_add_interface,
  1875. .change_interface = ath9k_change_interface,
  1876. .remove_interface = ath9k_remove_interface,
  1877. .config = ath9k_config,
  1878. .configure_filter = ath9k_configure_filter,
  1879. .sta_add = ath9k_sta_add,
  1880. .sta_remove = ath9k_sta_remove,
  1881. .sta_notify = ath9k_sta_notify,
  1882. .conf_tx = ath9k_conf_tx,
  1883. .bss_info_changed = ath9k_bss_info_changed,
  1884. .set_key = ath9k_set_key,
  1885. .get_tsf = ath9k_get_tsf,
  1886. .set_tsf = ath9k_set_tsf,
  1887. .reset_tsf = ath9k_reset_tsf,
  1888. .ampdu_action = ath9k_ampdu_action,
  1889. .get_survey = ath9k_get_survey,
  1890. .rfkill_poll = ath9k_rfkill_poll_state,
  1891. .set_coverage_class = ath9k_set_coverage_class,
  1892. .flush = ath9k_flush,
  1893. .tx_frames_pending = ath9k_tx_frames_pending,
  1894. .tx_last_beacon = ath9k_tx_last_beacon,
  1895. .get_stats = ath9k_get_stats,
  1896. .set_antenna = ath9k_set_antenna,
  1897. .get_antenna = ath9k_get_antenna,
  1898. #ifdef CONFIG_PM_SLEEP
  1899. .suspend = ath9k_suspend,
  1900. .resume = ath9k_resume,
  1901. .set_wakeup = ath9k_set_wakeup,
  1902. #endif
  1903. #ifdef CONFIG_ATH9K_DEBUGFS
  1904. .get_et_sset_count = ath9k_get_et_sset_count,
  1905. .get_et_stats = ath9k_get_et_stats,
  1906. .get_et_strings = ath9k_get_et_strings,
  1907. #endif
  1908. #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS)
  1909. .sta_add_debugfs = ath9k_sta_add_debugfs,
  1910. .sta_remove_debugfs = ath9k_sta_remove_debugfs,
  1911. #endif
  1912. .sw_scan_start = ath9k_sw_scan_start,
  1913. .sw_scan_complete = ath9k_sw_scan_complete,
  1914. };