intel_ringbuffer.h 4.3 KB

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  1. #ifndef _INTEL_RINGBUFFER_H_
  2. #define _INTEL_RINGBUFFER_H_
  3. struct intel_hw_status_page {
  4. void *page_addr;
  5. unsigned int gfx_addr;
  6. struct drm_gem_object *obj;
  7. };
  8. #define I915_READ_TAIL(ring) I915_READ(RING_TAIL(ring->mmio_base))
  9. #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL(ring->mmio_base), val)
  10. #define I915_READ_START(ring) I915_READ(RING_START(ring->mmio_base))
  11. #define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val)
  12. #define I915_READ_HEAD(ring) I915_READ(RING_HEAD(ring->mmio_base))
  13. #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val)
  14. #define I915_READ_CTL(ring) I915_READ(RING_CTL(ring->mmio_base))
  15. #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val)
  16. struct drm_i915_gem_execbuffer2;
  17. struct intel_ring_buffer {
  18. const char *name;
  19. enum intel_ring_id {
  20. RING_RENDER = 0x1,
  21. RING_BSD = 0x2,
  22. RING_BLT = 0x4,
  23. } id;
  24. u32 mmio_base;
  25. unsigned long size;
  26. void *virtual_start;
  27. struct drm_device *dev;
  28. struct drm_gem_object *gem_object;
  29. u32 actual_head;
  30. u32 head;
  31. u32 tail;
  32. int space;
  33. struct intel_hw_status_page status_page;
  34. u32 irq_gem_seqno; /* last seq seem at irq time */
  35. u32 waiting_gem_seqno;
  36. int user_irq_refcount;
  37. void (*user_irq_get)(struct drm_device *dev,
  38. struct intel_ring_buffer *ring);
  39. void (*user_irq_put)(struct drm_device *dev,
  40. struct intel_ring_buffer *ring);
  41. int (*init)(struct drm_device *dev,
  42. struct intel_ring_buffer *ring);
  43. void (*write_tail)(struct drm_device *dev,
  44. struct intel_ring_buffer *ring,
  45. u32 value);
  46. void (*flush)(struct drm_device *dev,
  47. struct intel_ring_buffer *ring,
  48. u32 invalidate_domains,
  49. u32 flush_domains);
  50. u32 (*add_request)(struct drm_device *dev,
  51. struct intel_ring_buffer *ring,
  52. u32 flush_domains);
  53. u32 (*get_seqno)(struct drm_device *dev,
  54. struct intel_ring_buffer *ring);
  55. int (*dispatch_gem_execbuffer)(struct drm_device *dev,
  56. struct intel_ring_buffer *ring,
  57. struct drm_i915_gem_execbuffer2 *exec,
  58. struct drm_clip_rect *cliprects,
  59. uint64_t exec_offset);
  60. void (*cleanup)(struct intel_ring_buffer *ring);
  61. /**
  62. * List of objects currently involved in rendering from the
  63. * ringbuffer.
  64. *
  65. * Includes buffers having the contents of their GPU caches
  66. * flushed, not necessarily primitives. last_rendering_seqno
  67. * represents when the rendering involved will be completed.
  68. *
  69. * A reference is held on the buffer while on this list.
  70. */
  71. struct list_head active_list;
  72. /**
  73. * List of breadcrumbs associated with GPU requests currently
  74. * outstanding.
  75. */
  76. struct list_head request_list;
  77. /**
  78. * List of objects currently pending a GPU write flush.
  79. *
  80. * All elements on this list will belong to either the
  81. * active_list or flushing_list, last_rendering_seqno can
  82. * be used to differentiate between the two elements.
  83. */
  84. struct list_head gpu_write_list;
  85. /**
  86. * Do we have some not yet emitted requests outstanding?
  87. */
  88. bool outstanding_lazy_request;
  89. wait_queue_head_t irq_queue;
  90. drm_local_map_t map;
  91. void *private;
  92. };
  93. static inline u32
  94. intel_read_status_page(struct intel_ring_buffer *ring,
  95. int reg)
  96. {
  97. u32 *regs = ring->status_page.page_addr;
  98. return regs[reg];
  99. }
  100. int intel_init_ring_buffer(struct drm_device *dev,
  101. struct intel_ring_buffer *ring);
  102. void intel_cleanup_ring_buffer(struct drm_device *dev,
  103. struct intel_ring_buffer *ring);
  104. int intel_wait_ring_buffer(struct drm_device *dev,
  105. struct intel_ring_buffer *ring, int n);
  106. void intel_ring_begin(struct drm_device *dev,
  107. struct intel_ring_buffer *ring, int n);
  108. static inline void intel_ring_emit(struct drm_device *dev,
  109. struct intel_ring_buffer *ring,
  110. unsigned int data)
  111. {
  112. unsigned int *virt = ring->virtual_start + ring->tail;
  113. *virt = data;
  114. ring->tail += 4;
  115. }
  116. void intel_ring_advance(struct drm_device *dev,
  117. struct intel_ring_buffer *ring);
  118. u32 intel_ring_get_seqno(struct drm_device *dev,
  119. struct intel_ring_buffer *ring);
  120. int intel_init_render_ring_buffer(struct drm_device *dev);
  121. int intel_init_bsd_ring_buffer(struct drm_device *dev);
  122. int intel_init_blt_ring_buffer(struct drm_device *dev);
  123. u32 intel_ring_get_active_head(struct drm_device *dev,
  124. struct intel_ring_buffer *ring);
  125. void intel_ring_setup_status_page(struct drm_device *dev,
  126. struct intel_ring_buffer *ring);
  127. #endif /* _INTEL_RINGBUFFER_H_ */