iwl-agn.c 121 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/slab.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/sched.h>
  37. #include <linux/skbuff.h>
  38. #include <linux/netdevice.h>
  39. #include <linux/wireless.h>
  40. #include <linux/firmware.h>
  41. #include <linux/etherdevice.h>
  42. #include <linux/if_arp.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #define DRV_NAME "iwlagn"
  46. #include "iwl-eeprom.h"
  47. #include "iwl-dev.h"
  48. #include "iwl-core.h"
  49. #include "iwl-io.h"
  50. #include "iwl-helpers.h"
  51. #include "iwl-sta.h"
  52. #include "iwl-calib.h"
  53. #include "iwl-agn.h"
  54. /******************************************************************************
  55. *
  56. * module boiler plate
  57. *
  58. ******************************************************************************/
  59. /*
  60. * module name, copyright, version, etc.
  61. */
  62. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  63. #ifdef CONFIG_IWLWIFI_DEBUG
  64. #define VD "d"
  65. #else
  66. #define VD
  67. #endif
  68. #define DRV_VERSION IWLWIFI_VERSION VD
  69. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  70. MODULE_VERSION(DRV_VERSION);
  71. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  72. MODULE_LICENSE("GPL");
  73. MODULE_ALIAS("iwl4965");
  74. /**
  75. * iwl_commit_rxon - commit staging_rxon to hardware
  76. *
  77. * The RXON command in staging_rxon is committed to the hardware and
  78. * the active_rxon structure is updated with the new data. This
  79. * function correctly transitions out of the RXON_ASSOC_MSK state if
  80. * a HW tune is required based on the RXON structure changes.
  81. */
  82. int iwl_commit_rxon(struct iwl_priv *priv)
  83. {
  84. /* cast away the const for active_rxon in this function */
  85. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  86. int ret;
  87. bool new_assoc =
  88. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  89. if (!iwl_is_alive(priv))
  90. return -EBUSY;
  91. /* always get timestamp with Rx frame */
  92. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  93. ret = iwl_check_rxon_cmd(priv);
  94. if (ret) {
  95. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  96. return -EINVAL;
  97. }
  98. /*
  99. * receive commit_rxon request
  100. * abort any previous channel switch if still in process
  101. */
  102. if (priv->switch_rxon.switch_in_progress &&
  103. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  104. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  105. le16_to_cpu(priv->switch_rxon.channel));
  106. priv->switch_rxon.switch_in_progress = false;
  107. }
  108. /* If we don't need to send a full RXON, we can use
  109. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  110. * and other flags for the current radio configuration. */
  111. if (!iwl_full_rxon_required(priv)) {
  112. ret = iwl_send_rxon_assoc(priv);
  113. if (ret) {
  114. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  115. return ret;
  116. }
  117. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  118. iwl_print_rx_config_cmd(priv);
  119. return 0;
  120. }
  121. /* If we are currently associated and the new config requires
  122. * an RXON_ASSOC and the new config wants the associated mask enabled,
  123. * we must clear the associated from the active configuration
  124. * before we apply the new config */
  125. if (iwl_is_associated(priv) && new_assoc) {
  126. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  127. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  128. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  129. sizeof(struct iwl_rxon_cmd),
  130. &priv->active_rxon);
  131. /* If the mask clearing failed then we set
  132. * active_rxon back to what it was previously */
  133. if (ret) {
  134. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  135. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  136. return ret;
  137. }
  138. iwl_clear_ucode_stations(priv);
  139. iwl_restore_stations(priv);
  140. ret = iwl_restore_default_wep_keys(priv);
  141. if (ret) {
  142. IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
  143. return ret;
  144. }
  145. }
  146. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  147. "* with%s RXON_FILTER_ASSOC_MSK\n"
  148. "* channel = %d\n"
  149. "* bssid = %pM\n",
  150. (new_assoc ? "" : "out"),
  151. le16_to_cpu(priv->staging_rxon.channel),
  152. priv->staging_rxon.bssid_addr);
  153. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  154. /* Apply the new configuration
  155. * RXON unassoc clears the station table in uCode so restoration of
  156. * stations is needed after it (the RXON command) completes
  157. */
  158. if (!new_assoc) {
  159. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  160. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  161. if (ret) {
  162. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  163. return ret;
  164. }
  165. IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
  166. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  167. iwl_clear_ucode_stations(priv);
  168. iwl_restore_stations(priv);
  169. ret = iwl_restore_default_wep_keys(priv);
  170. if (ret) {
  171. IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
  172. return ret;
  173. }
  174. }
  175. priv->start_calib = 0;
  176. if (new_assoc) {
  177. /*
  178. * allow CTS-to-self if possible for new association.
  179. * this is relevant only for 5000 series and up,
  180. * but will not damage 4965
  181. */
  182. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  183. /* Apply the new configuration
  184. * RXON assoc doesn't clear the station table in uCode,
  185. */
  186. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  187. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  188. if (ret) {
  189. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  190. return ret;
  191. }
  192. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  193. }
  194. iwl_print_rx_config_cmd(priv);
  195. iwl_init_sensitivity(priv);
  196. /* If we issue a new RXON command which required a tune then we must
  197. * send a new TXPOWER command or we won't be able to Tx any frames */
  198. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  199. if (ret) {
  200. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  201. return ret;
  202. }
  203. return 0;
  204. }
  205. void iwl_update_chain_flags(struct iwl_priv *priv)
  206. {
  207. if (priv->cfg->ops->hcmd->set_rxon_chain)
  208. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  209. iwlcore_commit_rxon(priv);
  210. }
  211. static void iwl_clear_free_frames(struct iwl_priv *priv)
  212. {
  213. struct list_head *element;
  214. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  215. priv->frames_count);
  216. while (!list_empty(&priv->free_frames)) {
  217. element = priv->free_frames.next;
  218. list_del(element);
  219. kfree(list_entry(element, struct iwl_frame, list));
  220. priv->frames_count--;
  221. }
  222. if (priv->frames_count) {
  223. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  224. priv->frames_count);
  225. priv->frames_count = 0;
  226. }
  227. }
  228. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  229. {
  230. struct iwl_frame *frame;
  231. struct list_head *element;
  232. if (list_empty(&priv->free_frames)) {
  233. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  234. if (!frame) {
  235. IWL_ERR(priv, "Could not allocate frame!\n");
  236. return NULL;
  237. }
  238. priv->frames_count++;
  239. return frame;
  240. }
  241. element = priv->free_frames.next;
  242. list_del(element);
  243. return list_entry(element, struct iwl_frame, list);
  244. }
  245. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  246. {
  247. memset(frame, 0, sizeof(*frame));
  248. list_add(&frame->list, &priv->free_frames);
  249. }
  250. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  251. struct ieee80211_hdr *hdr,
  252. int left)
  253. {
  254. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  255. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  256. (priv->iw_mode != NL80211_IFTYPE_AP)))
  257. return 0;
  258. if (priv->ibss_beacon->len > left)
  259. return 0;
  260. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  261. return priv->ibss_beacon->len;
  262. }
  263. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  264. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  265. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  266. u8 *beacon, u32 frame_size)
  267. {
  268. u16 tim_idx;
  269. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  270. /*
  271. * The index is relative to frame start but we start looking at the
  272. * variable-length part of the beacon.
  273. */
  274. tim_idx = mgmt->u.beacon.variable - beacon;
  275. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  276. while ((tim_idx < (frame_size - 2)) &&
  277. (beacon[tim_idx] != WLAN_EID_TIM))
  278. tim_idx += beacon[tim_idx+1] + 2;
  279. /* If TIM field was found, set variables */
  280. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  281. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  282. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  283. } else
  284. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  285. }
  286. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  287. struct iwl_frame *frame)
  288. {
  289. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  290. u32 frame_size;
  291. u32 rate_flags;
  292. u32 rate;
  293. /*
  294. * We have to set up the TX command, the TX Beacon command, and the
  295. * beacon contents.
  296. */
  297. /* Initialize memory */
  298. tx_beacon_cmd = &frame->u.beacon;
  299. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  300. /* Set up TX beacon contents */
  301. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  302. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  303. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  304. return 0;
  305. /* Set up TX command fields */
  306. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  307. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  308. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  309. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  310. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  311. /* Set up TX beacon command fields */
  312. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  313. frame_size);
  314. /* Set up packet rate and flags */
  315. rate = iwl_rate_get_lowest_plcp(priv);
  316. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
  317. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  318. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  319. rate_flags |= RATE_MCS_CCK_MSK;
  320. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  321. rate_flags);
  322. return sizeof(*tx_beacon_cmd) + frame_size;
  323. }
  324. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  325. {
  326. struct iwl_frame *frame;
  327. unsigned int frame_size;
  328. int rc;
  329. frame = iwl_get_free_frame(priv);
  330. if (!frame) {
  331. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  332. "command.\n");
  333. return -ENOMEM;
  334. }
  335. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  336. if (!frame_size) {
  337. IWL_ERR(priv, "Error configuring the beacon command\n");
  338. iwl_free_frame(priv, frame);
  339. return -EINVAL;
  340. }
  341. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  342. &frame->u.cmd[0]);
  343. iwl_free_frame(priv, frame);
  344. return rc;
  345. }
  346. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  347. {
  348. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  349. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  350. if (sizeof(dma_addr_t) > sizeof(u32))
  351. addr |=
  352. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  353. return addr;
  354. }
  355. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  356. {
  357. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  358. return le16_to_cpu(tb->hi_n_len) >> 4;
  359. }
  360. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  361. dma_addr_t addr, u16 len)
  362. {
  363. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  364. u16 hi_n_len = len << 4;
  365. put_unaligned_le32(addr, &tb->lo);
  366. if (sizeof(dma_addr_t) > sizeof(u32))
  367. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  368. tb->hi_n_len = cpu_to_le16(hi_n_len);
  369. tfd->num_tbs = idx + 1;
  370. }
  371. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  372. {
  373. return tfd->num_tbs & 0x1f;
  374. }
  375. /**
  376. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  377. * @priv - driver private data
  378. * @txq - tx queue
  379. *
  380. * Does NOT advance any TFD circular buffer read/write indexes
  381. * Does NOT free the TFD itself (which is within circular buffer)
  382. */
  383. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  384. {
  385. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  386. struct iwl_tfd *tfd;
  387. struct pci_dev *dev = priv->pci_dev;
  388. int index = txq->q.read_ptr;
  389. int i;
  390. int num_tbs;
  391. tfd = &tfd_tmp[index];
  392. /* Sanity check on number of chunks */
  393. num_tbs = iwl_tfd_get_num_tbs(tfd);
  394. if (num_tbs >= IWL_NUM_OF_TBS) {
  395. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  396. /* @todo issue fatal error, it is quite serious situation */
  397. return;
  398. }
  399. /* Unmap tx_cmd */
  400. if (num_tbs)
  401. pci_unmap_single(dev,
  402. dma_unmap_addr(&txq->meta[index], mapping),
  403. dma_unmap_len(&txq->meta[index], len),
  404. PCI_DMA_BIDIRECTIONAL);
  405. /* Unmap chunks, if any. */
  406. for (i = 1; i < num_tbs; i++) {
  407. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  408. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  409. if (txq->txb) {
  410. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  411. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  412. }
  413. }
  414. }
  415. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  416. struct iwl_tx_queue *txq,
  417. dma_addr_t addr, u16 len,
  418. u8 reset, u8 pad)
  419. {
  420. struct iwl_queue *q;
  421. struct iwl_tfd *tfd, *tfd_tmp;
  422. u32 num_tbs;
  423. q = &txq->q;
  424. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  425. tfd = &tfd_tmp[q->write_ptr];
  426. if (reset)
  427. memset(tfd, 0, sizeof(*tfd));
  428. num_tbs = iwl_tfd_get_num_tbs(tfd);
  429. /* Each TFD can point to a maximum 20 Tx buffers */
  430. if (num_tbs >= IWL_NUM_OF_TBS) {
  431. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  432. IWL_NUM_OF_TBS);
  433. return -EINVAL;
  434. }
  435. BUG_ON(addr & ~DMA_BIT_MASK(36));
  436. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  437. IWL_ERR(priv, "Unaligned address = %llx\n",
  438. (unsigned long long)addr);
  439. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  440. return 0;
  441. }
  442. /*
  443. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  444. * given Tx queue, and enable the DMA channel used for that queue.
  445. *
  446. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  447. * channels supported in hardware.
  448. */
  449. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  450. struct iwl_tx_queue *txq)
  451. {
  452. int txq_id = txq->q.id;
  453. /* Circular buffer (TFD queue in DRAM) physical base address */
  454. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  455. txq->q.dma_addr >> 8);
  456. return 0;
  457. }
  458. /******************************************************************************
  459. *
  460. * Generic RX handler implementations
  461. *
  462. ******************************************************************************/
  463. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  464. struct iwl_rx_mem_buffer *rxb)
  465. {
  466. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  467. struct iwl_alive_resp *palive;
  468. struct delayed_work *pwork;
  469. palive = &pkt->u.alive_frame;
  470. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  471. "0x%01X 0x%01X\n",
  472. palive->is_valid, palive->ver_type,
  473. palive->ver_subtype);
  474. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  475. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  476. memcpy(&priv->card_alive_init,
  477. &pkt->u.alive_frame,
  478. sizeof(struct iwl_init_alive_resp));
  479. pwork = &priv->init_alive_start;
  480. } else {
  481. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  482. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  483. sizeof(struct iwl_alive_resp));
  484. pwork = &priv->alive_start;
  485. }
  486. /* We delay the ALIVE response by 5ms to
  487. * give the HW RF Kill time to activate... */
  488. if (palive->is_valid == UCODE_VALID_OK)
  489. queue_delayed_work(priv->workqueue, pwork,
  490. msecs_to_jiffies(5));
  491. else
  492. IWL_WARN(priv, "uCode did not respond OK.\n");
  493. }
  494. static void iwl_bg_beacon_update(struct work_struct *work)
  495. {
  496. struct iwl_priv *priv =
  497. container_of(work, struct iwl_priv, beacon_update);
  498. struct sk_buff *beacon;
  499. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  500. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  501. if (!beacon) {
  502. IWL_ERR(priv, "update beacon failed\n");
  503. return;
  504. }
  505. mutex_lock(&priv->mutex);
  506. /* new beacon skb is allocated every time; dispose previous.*/
  507. if (priv->ibss_beacon)
  508. dev_kfree_skb(priv->ibss_beacon);
  509. priv->ibss_beacon = beacon;
  510. mutex_unlock(&priv->mutex);
  511. iwl_send_beacon_cmd(priv);
  512. }
  513. /**
  514. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  515. *
  516. * This callback is provided in order to send a statistics request.
  517. *
  518. * This timer function is continually reset to execute within
  519. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  520. * was received. We need to ensure we receive the statistics in order
  521. * to update the temperature used for calibrating the TXPOWER.
  522. */
  523. static void iwl_bg_statistics_periodic(unsigned long data)
  524. {
  525. struct iwl_priv *priv = (struct iwl_priv *)data;
  526. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  527. return;
  528. /* dont send host command if rf-kill is on */
  529. if (!iwl_is_ready_rf(priv))
  530. return;
  531. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  532. }
  533. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  534. u32 start_idx, u32 num_events,
  535. u32 mode)
  536. {
  537. u32 i;
  538. u32 ptr; /* SRAM byte address of log data */
  539. u32 ev, time, data; /* event log data */
  540. unsigned long reg_flags;
  541. if (mode == 0)
  542. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  543. else
  544. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  545. /* Make sure device is powered up for SRAM reads */
  546. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  547. if (iwl_grab_nic_access(priv)) {
  548. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  549. return;
  550. }
  551. /* Set starting address; reads will auto-increment */
  552. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  553. rmb();
  554. /*
  555. * "time" is actually "data" for mode 0 (no timestamp).
  556. * place event id # at far right for easier visual parsing.
  557. */
  558. for (i = 0; i < num_events; i++) {
  559. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  560. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  561. if (mode == 0) {
  562. trace_iwlwifi_dev_ucode_cont_event(priv,
  563. 0, time, ev);
  564. } else {
  565. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  566. trace_iwlwifi_dev_ucode_cont_event(priv,
  567. time, data, ev);
  568. }
  569. }
  570. /* Allow device to power down */
  571. iwl_release_nic_access(priv);
  572. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  573. }
  574. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  575. {
  576. u32 capacity; /* event log capacity in # entries */
  577. u32 base; /* SRAM byte address of event log header */
  578. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  579. u32 num_wraps; /* # times uCode wrapped to top of log */
  580. u32 next_entry; /* index of next entry to be written by uCode */
  581. if (priv->ucode_type == UCODE_INIT)
  582. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  583. else
  584. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  585. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  586. capacity = iwl_read_targ_mem(priv, base);
  587. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  588. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  589. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  590. } else
  591. return;
  592. if (num_wraps == priv->event_log.num_wraps) {
  593. iwl_print_cont_event_trace(priv,
  594. base, priv->event_log.next_entry,
  595. next_entry - priv->event_log.next_entry,
  596. mode);
  597. priv->event_log.non_wraps_count++;
  598. } else {
  599. if ((num_wraps - priv->event_log.num_wraps) > 1)
  600. priv->event_log.wraps_more_count++;
  601. else
  602. priv->event_log.wraps_once_count++;
  603. trace_iwlwifi_dev_ucode_wrap_event(priv,
  604. num_wraps - priv->event_log.num_wraps,
  605. next_entry, priv->event_log.next_entry);
  606. if (next_entry < priv->event_log.next_entry) {
  607. iwl_print_cont_event_trace(priv, base,
  608. priv->event_log.next_entry,
  609. capacity - priv->event_log.next_entry,
  610. mode);
  611. iwl_print_cont_event_trace(priv, base, 0,
  612. next_entry, mode);
  613. } else {
  614. iwl_print_cont_event_trace(priv, base,
  615. next_entry, capacity - next_entry,
  616. mode);
  617. iwl_print_cont_event_trace(priv, base, 0,
  618. next_entry, mode);
  619. }
  620. }
  621. priv->event_log.num_wraps = num_wraps;
  622. priv->event_log.next_entry = next_entry;
  623. }
  624. /**
  625. * iwl_bg_ucode_trace - Timer callback to log ucode event
  626. *
  627. * The timer is continually set to execute every
  628. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  629. * this function is to perform continuous uCode event logging operation
  630. * if enabled
  631. */
  632. static void iwl_bg_ucode_trace(unsigned long data)
  633. {
  634. struct iwl_priv *priv = (struct iwl_priv *)data;
  635. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  636. return;
  637. if (priv->event_log.ucode_trace) {
  638. iwl_continuous_event_trace(priv);
  639. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  640. mod_timer(&priv->ucode_trace,
  641. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  642. }
  643. }
  644. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  645. struct iwl_rx_mem_buffer *rxb)
  646. {
  647. #ifdef CONFIG_IWLWIFI_DEBUG
  648. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  649. struct iwl4965_beacon_notif *beacon =
  650. (struct iwl4965_beacon_notif *)pkt->u.raw;
  651. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  652. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  653. "tsf %d %d rate %d\n",
  654. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  655. beacon->beacon_notify_hdr.failure_frame,
  656. le32_to_cpu(beacon->ibss_mgr_status),
  657. le32_to_cpu(beacon->high_tsf),
  658. le32_to_cpu(beacon->low_tsf), rate);
  659. #endif
  660. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  661. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  662. queue_work(priv->workqueue, &priv->beacon_update);
  663. }
  664. /* Handle notification from uCode that card's power state is changing
  665. * due to software, hardware, or critical temperature RFKILL */
  666. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  667. struct iwl_rx_mem_buffer *rxb)
  668. {
  669. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  670. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  671. unsigned long status = priv->status;
  672. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  673. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  674. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  675. (flags & CT_CARD_DISABLED) ?
  676. "Reached" : "Not reached");
  677. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  678. CT_CARD_DISABLED)) {
  679. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  680. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  681. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  682. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  683. if (!(flags & RXON_CARD_DISABLED)) {
  684. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  685. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  686. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  687. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  688. }
  689. if (flags & CT_CARD_DISABLED)
  690. iwl_tt_enter_ct_kill(priv);
  691. }
  692. if (!(flags & CT_CARD_DISABLED))
  693. iwl_tt_exit_ct_kill(priv);
  694. if (flags & HW_CARD_DISABLED)
  695. set_bit(STATUS_RF_KILL_HW, &priv->status);
  696. else
  697. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  698. if (!(flags & RXON_CARD_DISABLED))
  699. iwl_scan_cancel(priv);
  700. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  701. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  702. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  703. test_bit(STATUS_RF_KILL_HW, &priv->status));
  704. else
  705. wake_up_interruptible(&priv->wait_command_queue);
  706. }
  707. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  708. {
  709. if (src == IWL_PWR_SRC_VAUX) {
  710. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  711. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  712. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  713. ~APMG_PS_CTRL_MSK_PWR_SRC);
  714. } else {
  715. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  716. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  717. ~APMG_PS_CTRL_MSK_PWR_SRC);
  718. }
  719. return 0;
  720. }
  721. /**
  722. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  723. *
  724. * Setup the RX handlers for each of the reply types sent from the uCode
  725. * to the host.
  726. *
  727. * This function chains into the hardware specific files for them to setup
  728. * any hardware specific handlers as well.
  729. */
  730. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  731. {
  732. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  733. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  734. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  735. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  736. iwl_rx_spectrum_measure_notif;
  737. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  738. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  739. iwl_rx_pm_debug_statistics_notif;
  740. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  741. /*
  742. * The same handler is used for both the REPLY to a discrete
  743. * statistics request from the host as well as for the periodic
  744. * statistics notifications (after received beacons) from the uCode.
  745. */
  746. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  747. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  748. iwl_setup_rx_scan_handlers(priv);
  749. /* status change handler */
  750. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  751. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  752. iwl_rx_missed_beacon_notif;
  753. /* Rx handlers */
  754. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
  755. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
  756. /* block ack */
  757. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
  758. /* Set up hardware specific Rx handlers */
  759. priv->cfg->ops->lib->rx_handler_setup(priv);
  760. }
  761. /**
  762. * iwl_rx_handle - Main entry function for receiving responses from uCode
  763. *
  764. * Uses the priv->rx_handlers callback function array to invoke
  765. * the appropriate handlers, including command responses,
  766. * frame-received notifications, and other notifications.
  767. */
  768. void iwl_rx_handle(struct iwl_priv *priv)
  769. {
  770. struct iwl_rx_mem_buffer *rxb;
  771. struct iwl_rx_packet *pkt;
  772. struct iwl_rx_queue *rxq = &priv->rxq;
  773. u32 r, i;
  774. int reclaim;
  775. unsigned long flags;
  776. u8 fill_rx = 0;
  777. u32 count = 8;
  778. int total_empty;
  779. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  780. * buffer that the driver may process (last buffer filled by ucode). */
  781. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  782. i = rxq->read;
  783. /* Rx interrupt, but nothing sent from uCode */
  784. if (i == r)
  785. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  786. /* calculate total frames need to be restock after handling RX */
  787. total_empty = r - rxq->write_actual;
  788. if (total_empty < 0)
  789. total_empty += RX_QUEUE_SIZE;
  790. if (total_empty > (RX_QUEUE_SIZE / 2))
  791. fill_rx = 1;
  792. while (i != r) {
  793. rxb = rxq->queue[i];
  794. /* If an RXB doesn't have a Rx queue slot associated with it,
  795. * then a bug has been introduced in the queue refilling
  796. * routines -- catch it here */
  797. BUG_ON(rxb == NULL);
  798. rxq->queue[i] = NULL;
  799. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  800. PAGE_SIZE << priv->hw_params.rx_page_order,
  801. PCI_DMA_FROMDEVICE);
  802. pkt = rxb_addr(rxb);
  803. trace_iwlwifi_dev_rx(priv, pkt,
  804. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  805. /* Reclaim a command buffer only if this packet is a response
  806. * to a (driver-originated) command.
  807. * If the packet (e.g. Rx frame) originated from uCode,
  808. * there is no command buffer to reclaim.
  809. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  810. * but apparently a few don't get set; catch them here. */
  811. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  812. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  813. (pkt->hdr.cmd != REPLY_RX) &&
  814. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  815. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  816. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  817. (pkt->hdr.cmd != REPLY_TX);
  818. /* Based on type of command response or notification,
  819. * handle those that need handling via function in
  820. * rx_handlers table. See iwl_setup_rx_handlers() */
  821. if (priv->rx_handlers[pkt->hdr.cmd]) {
  822. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  823. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  824. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  825. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  826. } else {
  827. /* No handling needed */
  828. IWL_DEBUG_RX(priv,
  829. "r %d i %d No handler needed for %s, 0x%02x\n",
  830. r, i, get_cmd_string(pkt->hdr.cmd),
  831. pkt->hdr.cmd);
  832. }
  833. /*
  834. * XXX: After here, we should always check rxb->page
  835. * against NULL before touching it or its virtual
  836. * memory (pkt). Because some rx_handler might have
  837. * already taken or freed the pages.
  838. */
  839. if (reclaim) {
  840. /* Invoke any callbacks, transfer the buffer to caller,
  841. * and fire off the (possibly) blocking iwl_send_cmd()
  842. * as we reclaim the driver command queue */
  843. if (rxb->page)
  844. iwl_tx_cmd_complete(priv, rxb);
  845. else
  846. IWL_WARN(priv, "Claim null rxb?\n");
  847. }
  848. /* Reuse the page if possible. For notification packets and
  849. * SKBs that fail to Rx correctly, add them back into the
  850. * rx_free list for reuse later. */
  851. spin_lock_irqsave(&rxq->lock, flags);
  852. if (rxb->page != NULL) {
  853. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  854. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  855. PCI_DMA_FROMDEVICE);
  856. list_add_tail(&rxb->list, &rxq->rx_free);
  857. rxq->free_count++;
  858. } else
  859. list_add_tail(&rxb->list, &rxq->rx_used);
  860. spin_unlock_irqrestore(&rxq->lock, flags);
  861. i = (i + 1) & RX_QUEUE_MASK;
  862. /* If there are a lot of unused frames,
  863. * restock the Rx queue so ucode wont assert. */
  864. if (fill_rx) {
  865. count++;
  866. if (count >= 8) {
  867. rxq->read = i;
  868. iwlagn_rx_replenish_now(priv);
  869. count = 0;
  870. }
  871. }
  872. }
  873. /* Backtrack one entry */
  874. rxq->read = i;
  875. if (fill_rx)
  876. iwlagn_rx_replenish_now(priv);
  877. else
  878. iwlagn_rx_queue_restock(priv);
  879. }
  880. /* call this function to flush any scheduled tasklet */
  881. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  882. {
  883. /* wait to make sure we flush pending tasklet*/
  884. synchronize_irq(priv->pci_dev->irq);
  885. tasklet_kill(&priv->irq_tasklet);
  886. }
  887. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  888. {
  889. u32 inta, handled = 0;
  890. u32 inta_fh;
  891. unsigned long flags;
  892. u32 i;
  893. #ifdef CONFIG_IWLWIFI_DEBUG
  894. u32 inta_mask;
  895. #endif
  896. spin_lock_irqsave(&priv->lock, flags);
  897. /* Ack/clear/reset pending uCode interrupts.
  898. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  899. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  900. inta = iwl_read32(priv, CSR_INT);
  901. iwl_write32(priv, CSR_INT, inta);
  902. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  903. * Any new interrupts that happen after this, either while we're
  904. * in this tasklet, or later, will show up in next ISR/tasklet. */
  905. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  906. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  907. #ifdef CONFIG_IWLWIFI_DEBUG
  908. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  909. /* just for debug */
  910. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  911. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  912. inta, inta_mask, inta_fh);
  913. }
  914. #endif
  915. spin_unlock_irqrestore(&priv->lock, flags);
  916. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  917. * atomic, make sure that inta covers all the interrupts that
  918. * we've discovered, even if FH interrupt came in just after
  919. * reading CSR_INT. */
  920. if (inta_fh & CSR49_FH_INT_RX_MASK)
  921. inta |= CSR_INT_BIT_FH_RX;
  922. if (inta_fh & CSR49_FH_INT_TX_MASK)
  923. inta |= CSR_INT_BIT_FH_TX;
  924. /* Now service all interrupt bits discovered above. */
  925. if (inta & CSR_INT_BIT_HW_ERR) {
  926. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  927. /* Tell the device to stop sending interrupts */
  928. iwl_disable_interrupts(priv);
  929. priv->isr_stats.hw++;
  930. iwl_irq_handle_error(priv);
  931. handled |= CSR_INT_BIT_HW_ERR;
  932. return;
  933. }
  934. #ifdef CONFIG_IWLWIFI_DEBUG
  935. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  936. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  937. if (inta & CSR_INT_BIT_SCD) {
  938. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  939. "the frame/frames.\n");
  940. priv->isr_stats.sch++;
  941. }
  942. /* Alive notification via Rx interrupt will do the real work */
  943. if (inta & CSR_INT_BIT_ALIVE) {
  944. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  945. priv->isr_stats.alive++;
  946. }
  947. }
  948. #endif
  949. /* Safely ignore these bits for debug checks below */
  950. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  951. /* HW RF KILL switch toggled */
  952. if (inta & CSR_INT_BIT_RF_KILL) {
  953. int hw_rf_kill = 0;
  954. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  955. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  956. hw_rf_kill = 1;
  957. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  958. hw_rf_kill ? "disable radio" : "enable radio");
  959. priv->isr_stats.rfkill++;
  960. /* driver only loads ucode once setting the interface up.
  961. * the driver allows loading the ucode even if the radio
  962. * is killed. Hence update the killswitch state here. The
  963. * rfkill handler will care about restarting if needed.
  964. */
  965. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  966. if (hw_rf_kill)
  967. set_bit(STATUS_RF_KILL_HW, &priv->status);
  968. else
  969. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  970. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  971. }
  972. handled |= CSR_INT_BIT_RF_KILL;
  973. }
  974. /* Chip got too hot and stopped itself */
  975. if (inta & CSR_INT_BIT_CT_KILL) {
  976. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  977. priv->isr_stats.ctkill++;
  978. handled |= CSR_INT_BIT_CT_KILL;
  979. }
  980. /* Error detected by uCode */
  981. if (inta & CSR_INT_BIT_SW_ERR) {
  982. IWL_ERR(priv, "Microcode SW error detected. "
  983. " Restarting 0x%X.\n", inta);
  984. priv->isr_stats.sw++;
  985. priv->isr_stats.sw_err = inta;
  986. iwl_irq_handle_error(priv);
  987. handled |= CSR_INT_BIT_SW_ERR;
  988. }
  989. /*
  990. * uCode wakes up after power-down sleep.
  991. * Tell device about any new tx or host commands enqueued,
  992. * and about any Rx buffers made available while asleep.
  993. */
  994. if (inta & CSR_INT_BIT_WAKEUP) {
  995. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  996. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  997. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  998. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  999. priv->isr_stats.wakeup++;
  1000. handled |= CSR_INT_BIT_WAKEUP;
  1001. }
  1002. /* All uCode command responses, including Tx command responses,
  1003. * Rx "responses" (frame-received notification), and other
  1004. * notifications from uCode come through here*/
  1005. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1006. iwl_rx_handle(priv);
  1007. priv->isr_stats.rx++;
  1008. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1009. }
  1010. /* This "Tx" DMA channel is used only for loading uCode */
  1011. if (inta & CSR_INT_BIT_FH_TX) {
  1012. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1013. priv->isr_stats.tx++;
  1014. handled |= CSR_INT_BIT_FH_TX;
  1015. /* Wake up uCode load routine, now that load is complete */
  1016. priv->ucode_write_complete = 1;
  1017. wake_up_interruptible(&priv->wait_command_queue);
  1018. }
  1019. if (inta & ~handled) {
  1020. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1021. priv->isr_stats.unhandled++;
  1022. }
  1023. if (inta & ~(priv->inta_mask)) {
  1024. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1025. inta & ~priv->inta_mask);
  1026. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1027. }
  1028. /* Re-enable all interrupts */
  1029. /* only Re-enable if diabled by irq */
  1030. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1031. iwl_enable_interrupts(priv);
  1032. #ifdef CONFIG_IWLWIFI_DEBUG
  1033. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1034. inta = iwl_read32(priv, CSR_INT);
  1035. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1036. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1037. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1038. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1039. }
  1040. #endif
  1041. }
  1042. /* tasklet for iwlagn interrupt */
  1043. static void iwl_irq_tasklet(struct iwl_priv *priv)
  1044. {
  1045. u32 inta = 0;
  1046. u32 handled = 0;
  1047. unsigned long flags;
  1048. u32 i;
  1049. #ifdef CONFIG_IWLWIFI_DEBUG
  1050. u32 inta_mask;
  1051. #endif
  1052. spin_lock_irqsave(&priv->lock, flags);
  1053. /* Ack/clear/reset pending uCode interrupts.
  1054. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1055. */
  1056. /* There is a hardware bug in the interrupt mask function that some
  1057. * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
  1058. * they are disabled in the CSR_INT_MASK register. Furthermore the
  1059. * ICT interrupt handling mechanism has another bug that might cause
  1060. * these unmasked interrupts fail to be detected. We workaround the
  1061. * hardware bugs here by ACKing all the possible interrupts so that
  1062. * interrupt coalescing can still be achieved.
  1063. */
  1064. iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
  1065. inta = priv->_agn.inta;
  1066. #ifdef CONFIG_IWLWIFI_DEBUG
  1067. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1068. /* just for debug */
  1069. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1070. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  1071. inta, inta_mask);
  1072. }
  1073. #endif
  1074. spin_unlock_irqrestore(&priv->lock, flags);
  1075. /* saved interrupt in inta variable now we can reset priv->_agn.inta */
  1076. priv->_agn.inta = 0;
  1077. /* Now service all interrupt bits discovered above. */
  1078. if (inta & CSR_INT_BIT_HW_ERR) {
  1079. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1080. /* Tell the device to stop sending interrupts */
  1081. iwl_disable_interrupts(priv);
  1082. priv->isr_stats.hw++;
  1083. iwl_irq_handle_error(priv);
  1084. handled |= CSR_INT_BIT_HW_ERR;
  1085. return;
  1086. }
  1087. #ifdef CONFIG_IWLWIFI_DEBUG
  1088. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1089. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1090. if (inta & CSR_INT_BIT_SCD) {
  1091. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1092. "the frame/frames.\n");
  1093. priv->isr_stats.sch++;
  1094. }
  1095. /* Alive notification via Rx interrupt will do the real work */
  1096. if (inta & CSR_INT_BIT_ALIVE) {
  1097. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1098. priv->isr_stats.alive++;
  1099. }
  1100. }
  1101. #endif
  1102. /* Safely ignore these bits for debug checks below */
  1103. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1104. /* HW RF KILL switch toggled */
  1105. if (inta & CSR_INT_BIT_RF_KILL) {
  1106. int hw_rf_kill = 0;
  1107. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1108. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1109. hw_rf_kill = 1;
  1110. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1111. hw_rf_kill ? "disable radio" : "enable radio");
  1112. priv->isr_stats.rfkill++;
  1113. /* driver only loads ucode once setting the interface up.
  1114. * the driver allows loading the ucode even if the radio
  1115. * is killed. Hence update the killswitch state here. The
  1116. * rfkill handler will care about restarting if needed.
  1117. */
  1118. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1119. if (hw_rf_kill)
  1120. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1121. else
  1122. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1123. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1124. }
  1125. handled |= CSR_INT_BIT_RF_KILL;
  1126. }
  1127. /* Chip got too hot and stopped itself */
  1128. if (inta & CSR_INT_BIT_CT_KILL) {
  1129. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1130. priv->isr_stats.ctkill++;
  1131. handled |= CSR_INT_BIT_CT_KILL;
  1132. }
  1133. /* Error detected by uCode */
  1134. if (inta & CSR_INT_BIT_SW_ERR) {
  1135. IWL_ERR(priv, "Microcode SW error detected. "
  1136. " Restarting 0x%X.\n", inta);
  1137. priv->isr_stats.sw++;
  1138. priv->isr_stats.sw_err = inta;
  1139. iwl_irq_handle_error(priv);
  1140. handled |= CSR_INT_BIT_SW_ERR;
  1141. }
  1142. /* uCode wakes up after power-down sleep */
  1143. if (inta & CSR_INT_BIT_WAKEUP) {
  1144. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1145. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1146. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1147. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1148. priv->isr_stats.wakeup++;
  1149. handled |= CSR_INT_BIT_WAKEUP;
  1150. }
  1151. /* All uCode command responses, including Tx command responses,
  1152. * Rx "responses" (frame-received notification), and other
  1153. * notifications from uCode come through here*/
  1154. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1155. CSR_INT_BIT_RX_PERIODIC)) {
  1156. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1157. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1158. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1159. iwl_write32(priv, CSR_FH_INT_STATUS,
  1160. CSR49_FH_INT_RX_MASK);
  1161. }
  1162. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1163. handled |= CSR_INT_BIT_RX_PERIODIC;
  1164. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1165. }
  1166. /* Sending RX interrupt require many steps to be done in the
  1167. * the device:
  1168. * 1- write interrupt to current index in ICT table.
  1169. * 2- dma RX frame.
  1170. * 3- update RX shared data to indicate last write index.
  1171. * 4- send interrupt.
  1172. * This could lead to RX race, driver could receive RX interrupt
  1173. * but the shared data changes does not reflect this;
  1174. * periodic interrupt will detect any dangling Rx activity.
  1175. */
  1176. /* Disable periodic interrupt; we use it as just a one-shot. */
  1177. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1178. CSR_INT_PERIODIC_DIS);
  1179. iwl_rx_handle(priv);
  1180. /*
  1181. * Enable periodic interrupt in 8 msec only if we received
  1182. * real RX interrupt (instead of just periodic int), to catch
  1183. * any dangling Rx interrupt. If it was just the periodic
  1184. * interrupt, there was no dangling Rx activity, and no need
  1185. * to extend the periodic interrupt; one-shot is enough.
  1186. */
  1187. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1188. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1189. CSR_INT_PERIODIC_ENA);
  1190. priv->isr_stats.rx++;
  1191. }
  1192. /* This "Tx" DMA channel is used only for loading uCode */
  1193. if (inta & CSR_INT_BIT_FH_TX) {
  1194. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1195. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1196. priv->isr_stats.tx++;
  1197. handled |= CSR_INT_BIT_FH_TX;
  1198. /* Wake up uCode load routine, now that load is complete */
  1199. priv->ucode_write_complete = 1;
  1200. wake_up_interruptible(&priv->wait_command_queue);
  1201. }
  1202. if (inta & ~handled) {
  1203. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1204. priv->isr_stats.unhandled++;
  1205. }
  1206. if (inta & ~(priv->inta_mask)) {
  1207. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1208. inta & ~priv->inta_mask);
  1209. }
  1210. /* Re-enable all interrupts */
  1211. /* only Re-enable if diabled by irq */
  1212. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1213. iwl_enable_interrupts(priv);
  1214. }
  1215. /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
  1216. #define ACK_CNT_RATIO (50)
  1217. #define BA_TIMEOUT_CNT (5)
  1218. #define BA_TIMEOUT_MAX (16)
  1219. /**
  1220. * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
  1221. *
  1222. * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
  1223. * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
  1224. * operation state.
  1225. */
  1226. bool iwl_good_ack_health(struct iwl_priv *priv,
  1227. struct iwl_rx_packet *pkt)
  1228. {
  1229. bool rc = true;
  1230. int actual_ack_cnt_delta, expected_ack_cnt_delta;
  1231. int ba_timeout_delta;
  1232. actual_ack_cnt_delta =
  1233. le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
  1234. le32_to_cpu(priv->statistics.tx.actual_ack_cnt);
  1235. expected_ack_cnt_delta =
  1236. le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
  1237. le32_to_cpu(priv->statistics.tx.expected_ack_cnt);
  1238. ba_timeout_delta =
  1239. le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
  1240. le32_to_cpu(priv->statistics.tx.agg.ba_timeout);
  1241. if ((priv->_agn.agg_tids_count > 0) &&
  1242. (expected_ack_cnt_delta > 0) &&
  1243. (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
  1244. < ACK_CNT_RATIO) &&
  1245. (ba_timeout_delta > BA_TIMEOUT_CNT)) {
  1246. IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
  1247. " expected_ack_cnt = %d\n",
  1248. actual_ack_cnt_delta, expected_ack_cnt_delta);
  1249. #ifdef CONFIG_IWLWIFI_DEBUGFS
  1250. /*
  1251. * This is ifdef'ed on DEBUGFS because otherwise the
  1252. * statistics aren't available. If DEBUGFS is set but
  1253. * DEBUG is not, these will just compile out.
  1254. */
  1255. IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
  1256. priv->delta_statistics.tx.rx_detected_cnt);
  1257. IWL_DEBUG_RADIO(priv,
  1258. "ack_or_ba_timeout_collision delta = %d\n",
  1259. priv->delta_statistics.tx.
  1260. ack_or_ba_timeout_collision);
  1261. #endif
  1262. IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
  1263. ba_timeout_delta);
  1264. if (!actual_ack_cnt_delta &&
  1265. (ba_timeout_delta >= BA_TIMEOUT_MAX))
  1266. rc = false;
  1267. }
  1268. return rc;
  1269. }
  1270. /******************************************************************************
  1271. *
  1272. * uCode download functions
  1273. *
  1274. ******************************************************************************/
  1275. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1276. {
  1277. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1278. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1279. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1280. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1281. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1282. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1283. }
  1284. static void iwl_nic_start(struct iwl_priv *priv)
  1285. {
  1286. /* Remove all resets to allow NIC to operate */
  1287. iwl_write32(priv, CSR_RESET, 0);
  1288. }
  1289. struct iwlagn_ucode_capabilities {
  1290. u32 max_probe_length;
  1291. };
  1292. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
  1293. static int iwl_mac_setup_register(struct iwl_priv *priv,
  1294. struct iwlagn_ucode_capabilities *capa);
  1295. static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
  1296. {
  1297. const char *name_pre = priv->cfg->fw_name_pre;
  1298. if (first)
  1299. priv->fw_index = priv->cfg->ucode_api_max;
  1300. else
  1301. priv->fw_index--;
  1302. if (priv->fw_index < priv->cfg->ucode_api_min) {
  1303. IWL_ERR(priv, "no suitable firmware found!\n");
  1304. return -ENOENT;
  1305. }
  1306. sprintf(priv->firmware_name, "%s%d%s",
  1307. name_pre, priv->fw_index, ".ucode");
  1308. IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
  1309. priv->firmware_name);
  1310. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  1311. &priv->pci_dev->dev, GFP_KERNEL, priv,
  1312. iwl_ucode_callback);
  1313. }
  1314. struct iwlagn_firmware_pieces {
  1315. const void *inst, *data, *init, *init_data, *boot;
  1316. size_t inst_size, data_size, init_size, init_data_size, boot_size;
  1317. u32 build;
  1318. u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
  1319. u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
  1320. };
  1321. static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
  1322. const struct firmware *ucode_raw,
  1323. struct iwlagn_firmware_pieces *pieces)
  1324. {
  1325. struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
  1326. u32 api_ver, hdr_size;
  1327. const u8 *src;
  1328. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1329. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1330. switch (api_ver) {
  1331. default:
  1332. /*
  1333. * 4965 doesn't revision the firmware file format
  1334. * along with the API version, it always uses v1
  1335. * file format.
  1336. */
  1337. if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
  1338. CSR_HW_REV_TYPE_4965) {
  1339. hdr_size = 28;
  1340. if (ucode_raw->size < hdr_size) {
  1341. IWL_ERR(priv, "File size too small!\n");
  1342. return -EINVAL;
  1343. }
  1344. pieces->build = le32_to_cpu(ucode->u.v2.build);
  1345. pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
  1346. pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
  1347. pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
  1348. pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
  1349. pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
  1350. src = ucode->u.v2.data;
  1351. break;
  1352. }
  1353. /* fall through for 4965 */
  1354. case 0:
  1355. case 1:
  1356. case 2:
  1357. hdr_size = 24;
  1358. if (ucode_raw->size < hdr_size) {
  1359. IWL_ERR(priv, "File size too small!\n");
  1360. return -EINVAL;
  1361. }
  1362. pieces->build = 0;
  1363. pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
  1364. pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
  1365. pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
  1366. pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
  1367. pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
  1368. src = ucode->u.v1.data;
  1369. break;
  1370. }
  1371. /* Verify size of file vs. image size info in file's header */
  1372. if (ucode_raw->size != hdr_size + pieces->inst_size +
  1373. pieces->data_size + pieces->init_size +
  1374. pieces->init_data_size + pieces->boot_size) {
  1375. IWL_ERR(priv,
  1376. "uCode file size %d does not match expected size\n",
  1377. (int)ucode_raw->size);
  1378. return -EINVAL;
  1379. }
  1380. pieces->inst = src;
  1381. src += pieces->inst_size;
  1382. pieces->data = src;
  1383. src += pieces->data_size;
  1384. pieces->init = src;
  1385. src += pieces->init_size;
  1386. pieces->init_data = src;
  1387. src += pieces->init_data_size;
  1388. pieces->boot = src;
  1389. src += pieces->boot_size;
  1390. return 0;
  1391. }
  1392. static int iwlagn_wanted_ucode_alternative = 1;
  1393. static int iwlagn_load_firmware(struct iwl_priv *priv,
  1394. const struct firmware *ucode_raw,
  1395. struct iwlagn_firmware_pieces *pieces,
  1396. struct iwlagn_ucode_capabilities *capa)
  1397. {
  1398. struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
  1399. struct iwl_ucode_tlv *tlv;
  1400. size_t len = ucode_raw->size;
  1401. const u8 *data;
  1402. int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
  1403. u64 alternatives;
  1404. if (len < sizeof(*ucode))
  1405. return -EINVAL;
  1406. if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC))
  1407. return -EINVAL;
  1408. /*
  1409. * Check which alternatives are present, and "downgrade"
  1410. * when the chosen alternative is not present, warning
  1411. * the user when that happens. Some files may not have
  1412. * any alternatives, so don't warn in that case.
  1413. */
  1414. alternatives = le64_to_cpu(ucode->alternatives);
  1415. tmp = wanted_alternative;
  1416. if (wanted_alternative > 63)
  1417. wanted_alternative = 63;
  1418. while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
  1419. wanted_alternative--;
  1420. if (wanted_alternative && wanted_alternative != tmp)
  1421. IWL_WARN(priv,
  1422. "uCode alternative %d not available, choosing %d\n",
  1423. tmp, wanted_alternative);
  1424. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1425. pieces->build = le32_to_cpu(ucode->build);
  1426. data = ucode->data;
  1427. len -= sizeof(*ucode);
  1428. while (len >= sizeof(*tlv)) {
  1429. u32 tlv_len;
  1430. enum iwl_ucode_tlv_type tlv_type;
  1431. u16 tlv_alt;
  1432. const u8 *tlv_data;
  1433. len -= sizeof(*tlv);
  1434. tlv = (void *)data;
  1435. tlv_len = le32_to_cpu(tlv->length);
  1436. tlv_type = le16_to_cpu(tlv->type);
  1437. tlv_alt = le16_to_cpu(tlv->alternative);
  1438. tlv_data = tlv->data;
  1439. if (len < tlv_len)
  1440. return -EINVAL;
  1441. len -= ALIGN(tlv_len, 4);
  1442. data += sizeof(*tlv) + ALIGN(tlv_len, 4);
  1443. /*
  1444. * Alternative 0 is always valid.
  1445. *
  1446. * Skip alternative TLVs that are not selected.
  1447. */
  1448. if (tlv_alt != 0 && tlv_alt != wanted_alternative)
  1449. continue;
  1450. switch (tlv_type) {
  1451. case IWL_UCODE_TLV_INST:
  1452. pieces->inst = tlv_data;
  1453. pieces->inst_size = tlv_len;
  1454. break;
  1455. case IWL_UCODE_TLV_DATA:
  1456. pieces->data = tlv_data;
  1457. pieces->data_size = tlv_len;
  1458. break;
  1459. case IWL_UCODE_TLV_INIT:
  1460. pieces->init = tlv_data;
  1461. pieces->init_size = tlv_len;
  1462. break;
  1463. case IWL_UCODE_TLV_INIT_DATA:
  1464. pieces->init_data = tlv_data;
  1465. pieces->init_data_size = tlv_len;
  1466. break;
  1467. case IWL_UCODE_TLV_BOOT:
  1468. pieces->boot = tlv_data;
  1469. pieces->boot_size = tlv_len;
  1470. break;
  1471. case IWL_UCODE_TLV_PROBE_MAX_LEN:
  1472. if (tlv_len != 4)
  1473. return -EINVAL;
  1474. capa->max_probe_length =
  1475. le32_to_cpup((__le32 *)tlv_data);
  1476. break;
  1477. case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
  1478. if (tlv_len != 4)
  1479. return -EINVAL;
  1480. pieces->init_evtlog_ptr =
  1481. le32_to_cpup((__le32 *)tlv_data);
  1482. break;
  1483. case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
  1484. if (tlv_len != 4)
  1485. return -EINVAL;
  1486. pieces->init_evtlog_size =
  1487. le32_to_cpup((__le32 *)tlv_data);
  1488. break;
  1489. case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
  1490. if (tlv_len != 4)
  1491. return -EINVAL;
  1492. pieces->init_errlog_ptr =
  1493. le32_to_cpup((__le32 *)tlv_data);
  1494. break;
  1495. case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
  1496. if (tlv_len != 4)
  1497. return -EINVAL;
  1498. pieces->inst_evtlog_ptr =
  1499. le32_to_cpup((__le32 *)tlv_data);
  1500. break;
  1501. case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
  1502. if (tlv_len != 4)
  1503. return -EINVAL;
  1504. pieces->inst_evtlog_size =
  1505. le32_to_cpup((__le32 *)tlv_data);
  1506. break;
  1507. case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
  1508. if (tlv_len != 4)
  1509. return -EINVAL;
  1510. pieces->inst_errlog_ptr =
  1511. le32_to_cpup((__le32 *)tlv_data);
  1512. break;
  1513. default:
  1514. break;
  1515. }
  1516. }
  1517. if (len)
  1518. return -EINVAL;
  1519. return 0;
  1520. }
  1521. /**
  1522. * iwl_ucode_callback - callback when firmware was loaded
  1523. *
  1524. * If loaded successfully, copies the firmware into buffers
  1525. * for the card to fetch (via DMA).
  1526. */
  1527. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
  1528. {
  1529. struct iwl_priv *priv = context;
  1530. struct iwl_ucode_header *ucode;
  1531. int err;
  1532. struct iwlagn_firmware_pieces pieces;
  1533. const unsigned int api_max = priv->cfg->ucode_api_max;
  1534. const unsigned int api_min = priv->cfg->ucode_api_min;
  1535. u32 api_ver;
  1536. char buildstr[25];
  1537. u32 build;
  1538. struct iwlagn_ucode_capabilities ucode_capa = {
  1539. .max_probe_length = 200,
  1540. };
  1541. memset(&pieces, 0, sizeof(pieces));
  1542. if (!ucode_raw) {
  1543. IWL_ERR(priv, "request for firmware file '%s' failed.\n",
  1544. priv->firmware_name);
  1545. goto try_again;
  1546. }
  1547. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1548. priv->firmware_name, ucode_raw->size);
  1549. /* Make sure that we got at least the API version number */
  1550. if (ucode_raw->size < 4) {
  1551. IWL_ERR(priv, "File size way too small!\n");
  1552. goto try_again;
  1553. }
  1554. /* Data from ucode file: header followed by uCode images */
  1555. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1556. if (ucode->ver)
  1557. err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
  1558. else
  1559. err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
  1560. &ucode_capa);
  1561. if (err)
  1562. goto try_again;
  1563. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1564. build = pieces.build;
  1565. /*
  1566. * api_ver should match the api version forming part of the
  1567. * firmware filename ... but we don't check for that and only rely
  1568. * on the API version read from firmware header from here on forward
  1569. */
  1570. if (api_ver < api_min || api_ver > api_max) {
  1571. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1572. "Driver supports v%u, firmware is v%u.\n",
  1573. api_max, api_ver);
  1574. goto try_again;
  1575. }
  1576. if (api_ver != api_max)
  1577. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1578. "got v%u. New firmware can be obtained "
  1579. "from http://www.intellinuxwireless.org.\n",
  1580. api_max, api_ver);
  1581. if (build)
  1582. sprintf(buildstr, " build %u", build);
  1583. else
  1584. buildstr[0] = '\0';
  1585. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
  1586. IWL_UCODE_MAJOR(priv->ucode_ver),
  1587. IWL_UCODE_MINOR(priv->ucode_ver),
  1588. IWL_UCODE_API(priv->ucode_ver),
  1589. IWL_UCODE_SERIAL(priv->ucode_ver),
  1590. buildstr);
  1591. snprintf(priv->hw->wiphy->fw_version,
  1592. sizeof(priv->hw->wiphy->fw_version),
  1593. "%u.%u.%u.%u%s",
  1594. IWL_UCODE_MAJOR(priv->ucode_ver),
  1595. IWL_UCODE_MINOR(priv->ucode_ver),
  1596. IWL_UCODE_API(priv->ucode_ver),
  1597. IWL_UCODE_SERIAL(priv->ucode_ver),
  1598. buildstr);
  1599. /*
  1600. * For any of the failures below (before allocating pci memory)
  1601. * we will try to load a version with a smaller API -- maybe the
  1602. * user just got a corrupted version of the latest API.
  1603. */
  1604. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1605. priv->ucode_ver);
  1606. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
  1607. pieces.inst_size);
  1608. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
  1609. pieces.data_size);
  1610. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
  1611. pieces.init_size);
  1612. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
  1613. pieces.init_data_size);
  1614. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
  1615. pieces.boot_size);
  1616. /* Verify that uCode images will fit in card's SRAM */
  1617. if (pieces.inst_size > priv->hw_params.max_inst_size) {
  1618. IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
  1619. pieces.inst_size);
  1620. goto try_again;
  1621. }
  1622. if (pieces.data_size > priv->hw_params.max_data_size) {
  1623. IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
  1624. pieces.data_size);
  1625. goto try_again;
  1626. }
  1627. if (pieces.init_size > priv->hw_params.max_inst_size) {
  1628. IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
  1629. pieces.init_size);
  1630. goto try_again;
  1631. }
  1632. if (pieces.init_data_size > priv->hw_params.max_data_size) {
  1633. IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
  1634. pieces.init_data_size);
  1635. goto try_again;
  1636. }
  1637. if (pieces.boot_size > priv->hw_params.max_bsm_size) {
  1638. IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
  1639. pieces.boot_size);
  1640. goto try_again;
  1641. }
  1642. /* Allocate ucode buffers for card's bus-master loading ... */
  1643. /* Runtime instructions and 2 copies of data:
  1644. * 1) unmodified from disk
  1645. * 2) backup cache for save/restore during power-downs */
  1646. priv->ucode_code.len = pieces.inst_size;
  1647. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1648. priv->ucode_data.len = pieces.data_size;
  1649. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1650. priv->ucode_data_backup.len = pieces.data_size;
  1651. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1652. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1653. !priv->ucode_data_backup.v_addr)
  1654. goto err_pci_alloc;
  1655. /* Initialization instructions and data */
  1656. if (pieces.init_size && pieces.init_data_size) {
  1657. priv->ucode_init.len = pieces.init_size;
  1658. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1659. priv->ucode_init_data.len = pieces.init_data_size;
  1660. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1661. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1662. goto err_pci_alloc;
  1663. }
  1664. /* Bootstrap (instructions only, no data) */
  1665. if (pieces.boot_size) {
  1666. priv->ucode_boot.len = pieces.boot_size;
  1667. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1668. if (!priv->ucode_boot.v_addr)
  1669. goto err_pci_alloc;
  1670. }
  1671. /* Now that we can no longer fail, copy information */
  1672. /*
  1673. * The (size - 16) / 12 formula is based on the information recorded
  1674. * for each event, which is of mode 1 (including timestamp) for all
  1675. * new microcodes that include this information.
  1676. */
  1677. priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
  1678. if (pieces.init_evtlog_size)
  1679. priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
  1680. else
  1681. priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
  1682. priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
  1683. priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
  1684. if (pieces.inst_evtlog_size)
  1685. priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
  1686. else
  1687. priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
  1688. priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
  1689. /* Copy images into buffers for card's bus-master reads ... */
  1690. /* Runtime instructions (first block of data in file) */
  1691. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
  1692. pieces.inst_size);
  1693. memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
  1694. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1695. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1696. /*
  1697. * Runtime data
  1698. * NOTE: Copy into backup buffer will be done in iwl_up()
  1699. */
  1700. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
  1701. pieces.data_size);
  1702. memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
  1703. memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
  1704. /* Initialization instructions */
  1705. if (pieces.init_size) {
  1706. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1707. pieces.init_size);
  1708. memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
  1709. }
  1710. /* Initialization data */
  1711. if (pieces.init_data_size) {
  1712. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1713. pieces.init_data_size);
  1714. memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
  1715. pieces.init_data_size);
  1716. }
  1717. /* Bootstrap instructions */
  1718. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
  1719. pieces.boot_size);
  1720. memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
  1721. /**************************************************
  1722. * This is still part of probe() in a sense...
  1723. *
  1724. * 9. Setup and register with mac80211 and debugfs
  1725. **************************************************/
  1726. err = iwl_mac_setup_register(priv, &ucode_capa);
  1727. if (err)
  1728. goto out_unbind;
  1729. err = iwl_dbgfs_register(priv, DRV_NAME);
  1730. if (err)
  1731. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  1732. /* We have our copies now, allow OS release its copies */
  1733. release_firmware(ucode_raw);
  1734. complete(&priv->_agn.firmware_loading_complete);
  1735. return;
  1736. try_again:
  1737. /* try next, if any */
  1738. if (iwl_request_firmware(priv, false))
  1739. goto out_unbind;
  1740. release_firmware(ucode_raw);
  1741. return;
  1742. err_pci_alloc:
  1743. IWL_ERR(priv, "failed to allocate pci memory\n");
  1744. iwl_dealloc_ucode_pci(priv);
  1745. out_unbind:
  1746. complete(&priv->_agn.firmware_loading_complete);
  1747. device_release_driver(&priv->pci_dev->dev);
  1748. release_firmware(ucode_raw);
  1749. }
  1750. static const char *desc_lookup_text[] = {
  1751. "OK",
  1752. "FAIL",
  1753. "BAD_PARAM",
  1754. "BAD_CHECKSUM",
  1755. "NMI_INTERRUPT_WDG",
  1756. "SYSASSERT",
  1757. "FATAL_ERROR",
  1758. "BAD_COMMAND",
  1759. "HW_ERROR_TUNE_LOCK",
  1760. "HW_ERROR_TEMPERATURE",
  1761. "ILLEGAL_CHAN_FREQ",
  1762. "VCC_NOT_STABLE",
  1763. "FH_ERROR",
  1764. "NMI_INTERRUPT_HOST",
  1765. "NMI_INTERRUPT_ACTION_PT",
  1766. "NMI_INTERRUPT_UNKNOWN",
  1767. "UCODE_VERSION_MISMATCH",
  1768. "HW_ERROR_ABS_LOCK",
  1769. "HW_ERROR_CAL_LOCK_FAIL",
  1770. "NMI_INTERRUPT_INST_ACTION_PT",
  1771. "NMI_INTERRUPT_DATA_ACTION_PT",
  1772. "NMI_TRM_HW_ER",
  1773. "NMI_INTERRUPT_TRM",
  1774. "NMI_INTERRUPT_BREAK_POINT"
  1775. "DEBUG_0",
  1776. "DEBUG_1",
  1777. "DEBUG_2",
  1778. "DEBUG_3",
  1779. "ADVANCED SYSASSERT"
  1780. };
  1781. static const char *desc_lookup(int i)
  1782. {
  1783. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1784. if (i < 0 || i > max)
  1785. i = max;
  1786. return desc_lookup_text[i];
  1787. }
  1788. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1789. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1790. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1791. {
  1792. u32 data2, line;
  1793. u32 desc, time, count, base, data1;
  1794. u32 blink1, blink2, ilink1, ilink2;
  1795. u32 pc, hcmd;
  1796. if (priv->ucode_type == UCODE_INIT) {
  1797. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1798. if (!base)
  1799. base = priv->_agn.init_errlog_ptr;
  1800. } else {
  1801. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1802. if (!base)
  1803. base = priv->_agn.inst_errlog_ptr;
  1804. }
  1805. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1806. IWL_ERR(priv,
  1807. "Not valid error log pointer 0x%08X for %s uCode\n",
  1808. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1809. return;
  1810. }
  1811. count = iwl_read_targ_mem(priv, base);
  1812. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1813. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1814. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1815. priv->status, count);
  1816. }
  1817. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1818. pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
  1819. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1820. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1821. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1822. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1823. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1824. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1825. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1826. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1827. hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
  1828. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1829. blink1, blink2, ilink1, ilink2);
  1830. IWL_ERR(priv, "Desc Time "
  1831. "data1 data2 line\n");
  1832. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1833. desc_lookup(desc), desc, time, data1, data2, line);
  1834. IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
  1835. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
  1836. pc, blink1, blink2, ilink1, ilink2, hcmd);
  1837. }
  1838. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1839. /**
  1840. * iwl_print_event_log - Dump error event log to syslog
  1841. *
  1842. */
  1843. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1844. u32 num_events, u32 mode,
  1845. int pos, char **buf, size_t bufsz)
  1846. {
  1847. u32 i;
  1848. u32 base; /* SRAM byte address of event log header */
  1849. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1850. u32 ptr; /* SRAM byte address of log data */
  1851. u32 ev, time, data; /* event log data */
  1852. unsigned long reg_flags;
  1853. if (num_events == 0)
  1854. return pos;
  1855. if (priv->ucode_type == UCODE_INIT) {
  1856. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1857. if (!base)
  1858. base = priv->_agn.init_evtlog_ptr;
  1859. } else {
  1860. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1861. if (!base)
  1862. base = priv->_agn.inst_evtlog_ptr;
  1863. }
  1864. if (mode == 0)
  1865. event_size = 2 * sizeof(u32);
  1866. else
  1867. event_size = 3 * sizeof(u32);
  1868. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1869. /* Make sure device is powered up for SRAM reads */
  1870. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1871. iwl_grab_nic_access(priv);
  1872. /* Set starting address; reads will auto-increment */
  1873. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1874. rmb();
  1875. /* "time" is actually "data" for mode 0 (no timestamp).
  1876. * place event id # at far right for easier visual parsing. */
  1877. for (i = 0; i < num_events; i++) {
  1878. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1879. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1880. if (mode == 0) {
  1881. /* data, ev */
  1882. if (bufsz) {
  1883. pos += scnprintf(*buf + pos, bufsz - pos,
  1884. "EVT_LOG:0x%08x:%04u\n",
  1885. time, ev);
  1886. } else {
  1887. trace_iwlwifi_dev_ucode_event(priv, 0,
  1888. time, ev);
  1889. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  1890. time, ev);
  1891. }
  1892. } else {
  1893. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1894. if (bufsz) {
  1895. pos += scnprintf(*buf + pos, bufsz - pos,
  1896. "EVT_LOGT:%010u:0x%08x:%04u\n",
  1897. time, data, ev);
  1898. } else {
  1899. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1900. time, data, ev);
  1901. trace_iwlwifi_dev_ucode_event(priv, time,
  1902. data, ev);
  1903. }
  1904. }
  1905. }
  1906. /* Allow device to power down */
  1907. iwl_release_nic_access(priv);
  1908. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1909. return pos;
  1910. }
  1911. /**
  1912. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1913. */
  1914. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1915. u32 num_wraps, u32 next_entry,
  1916. u32 size, u32 mode,
  1917. int pos, char **buf, size_t bufsz)
  1918. {
  1919. /*
  1920. * display the newest DEFAULT_LOG_ENTRIES entries
  1921. * i.e the entries just before the next ont that uCode would fill.
  1922. */
  1923. if (num_wraps) {
  1924. if (next_entry < size) {
  1925. pos = iwl_print_event_log(priv,
  1926. capacity - (size - next_entry),
  1927. size - next_entry, mode,
  1928. pos, buf, bufsz);
  1929. pos = iwl_print_event_log(priv, 0,
  1930. next_entry, mode,
  1931. pos, buf, bufsz);
  1932. } else
  1933. pos = iwl_print_event_log(priv, next_entry - size,
  1934. size, mode, pos, buf, bufsz);
  1935. } else {
  1936. if (next_entry < size) {
  1937. pos = iwl_print_event_log(priv, 0, next_entry,
  1938. mode, pos, buf, bufsz);
  1939. } else {
  1940. pos = iwl_print_event_log(priv, next_entry - size,
  1941. size, mode, pos, buf, bufsz);
  1942. }
  1943. }
  1944. return pos;
  1945. }
  1946. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1947. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1948. char **buf, bool display)
  1949. {
  1950. u32 base; /* SRAM byte address of event log header */
  1951. u32 capacity; /* event log capacity in # entries */
  1952. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1953. u32 num_wraps; /* # times uCode wrapped to top of log */
  1954. u32 next_entry; /* index of next entry to be written by uCode */
  1955. u32 size; /* # entries that we'll print */
  1956. u32 logsize;
  1957. int pos = 0;
  1958. size_t bufsz = 0;
  1959. if (priv->ucode_type == UCODE_INIT) {
  1960. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1961. logsize = priv->_agn.init_evtlog_size;
  1962. if (!base)
  1963. base = priv->_agn.init_evtlog_ptr;
  1964. } else {
  1965. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1966. logsize = priv->_agn.inst_evtlog_size;
  1967. if (!base)
  1968. base = priv->_agn.inst_evtlog_ptr;
  1969. }
  1970. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1971. IWL_ERR(priv,
  1972. "Invalid event log pointer 0x%08X for %s uCode\n",
  1973. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1974. return -EINVAL;
  1975. }
  1976. /* event log header */
  1977. capacity = iwl_read_targ_mem(priv, base);
  1978. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1979. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1980. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1981. if (capacity > logsize) {
  1982. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1983. capacity, logsize);
  1984. capacity = logsize;
  1985. }
  1986. if (next_entry > logsize) {
  1987. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1988. next_entry, logsize);
  1989. next_entry = logsize;
  1990. }
  1991. size = num_wraps ? capacity : next_entry;
  1992. /* bail out if nothing in log */
  1993. if (size == 0) {
  1994. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1995. return pos;
  1996. }
  1997. #ifdef CONFIG_IWLWIFI_DEBUG
  1998. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1999. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  2000. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  2001. #else
  2002. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  2003. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  2004. #endif
  2005. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  2006. size);
  2007. #ifdef CONFIG_IWLWIFI_DEBUG
  2008. if (display) {
  2009. if (full_log)
  2010. bufsz = capacity * 48;
  2011. else
  2012. bufsz = size * 48;
  2013. *buf = kmalloc(bufsz, GFP_KERNEL);
  2014. if (!*buf)
  2015. return -ENOMEM;
  2016. }
  2017. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  2018. /*
  2019. * if uCode has wrapped back to top of log,
  2020. * start at the oldest entry,
  2021. * i.e the next one that uCode would fill.
  2022. */
  2023. if (num_wraps)
  2024. pos = iwl_print_event_log(priv, next_entry,
  2025. capacity - next_entry, mode,
  2026. pos, buf, bufsz);
  2027. /* (then/else) start at top of log */
  2028. pos = iwl_print_event_log(priv, 0,
  2029. next_entry, mode, pos, buf, bufsz);
  2030. } else
  2031. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  2032. next_entry, size, mode,
  2033. pos, buf, bufsz);
  2034. #else
  2035. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  2036. next_entry, size, mode,
  2037. pos, buf, bufsz);
  2038. #endif
  2039. return pos;
  2040. }
  2041. /**
  2042. * iwl_alive_start - called after REPLY_ALIVE notification received
  2043. * from protocol/runtime uCode (initialization uCode's
  2044. * Alive gets handled by iwl_init_alive_start()).
  2045. */
  2046. static void iwl_alive_start(struct iwl_priv *priv)
  2047. {
  2048. int ret = 0;
  2049. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  2050. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  2051. /* We had an error bringing up the hardware, so take it
  2052. * all the way back down so we can try again */
  2053. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  2054. goto restart;
  2055. }
  2056. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  2057. * This is a paranoid check, because we would not have gotten the
  2058. * "runtime" alive if code weren't properly loaded. */
  2059. if (iwl_verify_ucode(priv)) {
  2060. /* Runtime instruction load was bad;
  2061. * take it all the way back down so we can try again */
  2062. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  2063. goto restart;
  2064. }
  2065. ret = priv->cfg->ops->lib->alive_notify(priv);
  2066. if (ret) {
  2067. IWL_WARN(priv,
  2068. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  2069. goto restart;
  2070. }
  2071. /* After the ALIVE response, we can send host commands to the uCode */
  2072. set_bit(STATUS_ALIVE, &priv->status);
  2073. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  2074. /* Enable timer to monitor the driver queues */
  2075. mod_timer(&priv->monitor_recover,
  2076. jiffies +
  2077. msecs_to_jiffies(priv->cfg->monitor_recover_period));
  2078. }
  2079. if (iwl_is_rfkill(priv))
  2080. return;
  2081. ieee80211_wake_queues(priv->hw);
  2082. priv->active_rate = IWL_RATES_MASK;
  2083. /* Configure Tx antenna selection based on H/W config */
  2084. if (priv->cfg->ops->hcmd->set_tx_ant)
  2085. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  2086. if (iwl_is_associated(priv)) {
  2087. struct iwl_rxon_cmd *active_rxon =
  2088. (struct iwl_rxon_cmd *)&priv->active_rxon;
  2089. /* apply any changes in staging */
  2090. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2091. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2092. } else {
  2093. /* Initialize our rx_config data */
  2094. iwl_connection_init_rx_config(priv, NULL);
  2095. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2096. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2097. }
  2098. /* Configure Bluetooth device coexistence support */
  2099. priv->cfg->ops->hcmd->send_bt_config(priv);
  2100. iwl_reset_run_time_calib(priv);
  2101. /* Configure the adapter for unassociated operation */
  2102. iwlcore_commit_rxon(priv);
  2103. /* At this point, the NIC is initialized and operational */
  2104. iwl_rf_kill_ct_config(priv);
  2105. iwl_leds_init(priv);
  2106. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  2107. set_bit(STATUS_READY, &priv->status);
  2108. wake_up_interruptible(&priv->wait_command_queue);
  2109. iwl_power_update_mode(priv, true);
  2110. IWL_DEBUG_INFO(priv, "Updated power mode\n");
  2111. return;
  2112. restart:
  2113. queue_work(priv->workqueue, &priv->restart);
  2114. }
  2115. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  2116. static void __iwl_down(struct iwl_priv *priv)
  2117. {
  2118. unsigned long flags;
  2119. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  2120. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  2121. if (!exit_pending)
  2122. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2123. iwl_clear_ucode_stations(priv);
  2124. iwl_dealloc_bcast_station(priv);
  2125. iwl_clear_driver_stations(priv);
  2126. /* Unblock any waiting calls */
  2127. wake_up_interruptible_all(&priv->wait_command_queue);
  2128. /* Wipe out the EXIT_PENDING status bit if we are not actually
  2129. * exiting the module */
  2130. if (!exit_pending)
  2131. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2132. /* stop and reset the on-board processor */
  2133. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2134. /* tell the device to stop sending interrupts */
  2135. spin_lock_irqsave(&priv->lock, flags);
  2136. iwl_disable_interrupts(priv);
  2137. spin_unlock_irqrestore(&priv->lock, flags);
  2138. iwl_synchronize_irq(priv);
  2139. if (priv->mac80211_registered)
  2140. ieee80211_stop_queues(priv->hw);
  2141. /* If we have not previously called iwl_init() then
  2142. * clear all bits but the RF Kill bit and return */
  2143. if (!iwl_is_init(priv)) {
  2144. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2145. STATUS_RF_KILL_HW |
  2146. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2147. STATUS_GEO_CONFIGURED |
  2148. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2149. STATUS_EXIT_PENDING;
  2150. goto exit;
  2151. }
  2152. /* ...otherwise clear out all the status bits but the RF Kill
  2153. * bit and continue taking the NIC down. */
  2154. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2155. STATUS_RF_KILL_HW |
  2156. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2157. STATUS_GEO_CONFIGURED |
  2158. test_bit(STATUS_FW_ERROR, &priv->status) <<
  2159. STATUS_FW_ERROR |
  2160. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2161. STATUS_EXIT_PENDING;
  2162. /* device going down, Stop using ICT table */
  2163. iwl_disable_ict(priv);
  2164. iwlagn_txq_ctx_stop(priv);
  2165. iwlagn_rxq_stop(priv);
  2166. /* Power-down device's busmaster DMA clocks */
  2167. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  2168. udelay(5);
  2169. /* Make sure (redundant) we've released our request to stay awake */
  2170. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2171. /* Stop the device, and put it in low power state */
  2172. priv->cfg->ops->lib->apm_ops.stop(priv);
  2173. exit:
  2174. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  2175. if (priv->ibss_beacon)
  2176. dev_kfree_skb(priv->ibss_beacon);
  2177. priv->ibss_beacon = NULL;
  2178. /* clear out any free frames */
  2179. iwl_clear_free_frames(priv);
  2180. }
  2181. static void iwl_down(struct iwl_priv *priv)
  2182. {
  2183. mutex_lock(&priv->mutex);
  2184. __iwl_down(priv);
  2185. mutex_unlock(&priv->mutex);
  2186. iwl_cancel_deferred_work(priv);
  2187. }
  2188. #define HW_READY_TIMEOUT (50)
  2189. static int iwl_set_hw_ready(struct iwl_priv *priv)
  2190. {
  2191. int ret = 0;
  2192. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  2193. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  2194. /* See if we got it */
  2195. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  2196. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2197. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2198. HW_READY_TIMEOUT);
  2199. if (ret != -ETIMEDOUT)
  2200. priv->hw_ready = true;
  2201. else
  2202. priv->hw_ready = false;
  2203. IWL_DEBUG_INFO(priv, "hardware %s\n",
  2204. (priv->hw_ready == 1) ? "ready" : "not ready");
  2205. return ret;
  2206. }
  2207. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  2208. {
  2209. int ret = 0;
  2210. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
  2211. ret = iwl_set_hw_ready(priv);
  2212. if (priv->hw_ready)
  2213. return ret;
  2214. /* If HW is not ready, prepare the conditions to check again */
  2215. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  2216. CSR_HW_IF_CONFIG_REG_PREPARE);
  2217. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  2218. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  2219. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  2220. /* HW should be ready by now, check again. */
  2221. if (ret != -ETIMEDOUT)
  2222. iwl_set_hw_ready(priv);
  2223. return ret;
  2224. }
  2225. #define MAX_HW_RESTARTS 5
  2226. static int __iwl_up(struct iwl_priv *priv)
  2227. {
  2228. int i;
  2229. int ret;
  2230. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2231. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  2232. return -EIO;
  2233. }
  2234. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  2235. IWL_ERR(priv, "ucode not available for device bringup\n");
  2236. return -EIO;
  2237. }
  2238. ret = iwl_alloc_bcast_station(priv, true);
  2239. if (ret)
  2240. return ret;
  2241. iwl_prepare_card_hw(priv);
  2242. if (!priv->hw_ready) {
  2243. IWL_WARN(priv, "Exit HW not ready\n");
  2244. return -EIO;
  2245. }
  2246. /* If platform's RF_KILL switch is NOT set to KILL */
  2247. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2248. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2249. else
  2250. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2251. if (iwl_is_rfkill(priv)) {
  2252. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  2253. iwl_enable_interrupts(priv);
  2254. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  2255. return 0;
  2256. }
  2257. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2258. ret = iwlagn_hw_nic_init(priv);
  2259. if (ret) {
  2260. IWL_ERR(priv, "Unable to init nic\n");
  2261. return ret;
  2262. }
  2263. /* make sure rfkill handshake bits are cleared */
  2264. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2265. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  2266. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2267. /* clear (again), then enable host interrupts */
  2268. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2269. iwl_enable_interrupts(priv);
  2270. /* really make sure rfkill handshake bits are cleared */
  2271. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2272. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2273. /* Copy original ucode data image from disk into backup cache.
  2274. * This will be used to initialize the on-board processor's
  2275. * data SRAM for a clean start when the runtime program first loads. */
  2276. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  2277. priv->ucode_data.len);
  2278. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2279. /* load bootstrap state machine,
  2280. * load bootstrap program into processor's memory,
  2281. * prepare to load the "initialize" uCode */
  2282. ret = priv->cfg->ops->lib->load_ucode(priv);
  2283. if (ret) {
  2284. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  2285. ret);
  2286. continue;
  2287. }
  2288. /* start card; "initialize" will load runtime ucode */
  2289. iwl_nic_start(priv);
  2290. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2291. return 0;
  2292. }
  2293. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2294. __iwl_down(priv);
  2295. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2296. /* tried to restart and config the device for as long as our
  2297. * patience could withstand */
  2298. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2299. return -EIO;
  2300. }
  2301. /*****************************************************************************
  2302. *
  2303. * Workqueue callbacks
  2304. *
  2305. *****************************************************************************/
  2306. static void iwl_bg_init_alive_start(struct work_struct *data)
  2307. {
  2308. struct iwl_priv *priv =
  2309. container_of(data, struct iwl_priv, init_alive_start.work);
  2310. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2311. return;
  2312. mutex_lock(&priv->mutex);
  2313. priv->cfg->ops->lib->init_alive_start(priv);
  2314. mutex_unlock(&priv->mutex);
  2315. }
  2316. static void iwl_bg_alive_start(struct work_struct *data)
  2317. {
  2318. struct iwl_priv *priv =
  2319. container_of(data, struct iwl_priv, alive_start.work);
  2320. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2321. return;
  2322. /* enable dram interrupt */
  2323. iwl_reset_ict(priv);
  2324. mutex_lock(&priv->mutex);
  2325. iwl_alive_start(priv);
  2326. mutex_unlock(&priv->mutex);
  2327. }
  2328. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  2329. {
  2330. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2331. run_time_calib_work);
  2332. mutex_lock(&priv->mutex);
  2333. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2334. test_bit(STATUS_SCANNING, &priv->status)) {
  2335. mutex_unlock(&priv->mutex);
  2336. return;
  2337. }
  2338. if (priv->start_calib) {
  2339. iwl_chain_noise_calibration(priv, &priv->statistics);
  2340. iwl_sensitivity_calibration(priv, &priv->statistics);
  2341. }
  2342. mutex_unlock(&priv->mutex);
  2343. }
  2344. static void iwl_bg_restart(struct work_struct *data)
  2345. {
  2346. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2347. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2348. return;
  2349. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2350. mutex_lock(&priv->mutex);
  2351. priv->vif = NULL;
  2352. priv->is_open = 0;
  2353. mutex_unlock(&priv->mutex);
  2354. iwl_down(priv);
  2355. ieee80211_restart_hw(priv->hw);
  2356. } else {
  2357. iwl_down(priv);
  2358. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2359. return;
  2360. mutex_lock(&priv->mutex);
  2361. __iwl_up(priv);
  2362. mutex_unlock(&priv->mutex);
  2363. }
  2364. }
  2365. static void iwl_bg_rx_replenish(struct work_struct *data)
  2366. {
  2367. struct iwl_priv *priv =
  2368. container_of(data, struct iwl_priv, rx_replenish);
  2369. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2370. return;
  2371. mutex_lock(&priv->mutex);
  2372. iwlagn_rx_replenish(priv);
  2373. mutex_unlock(&priv->mutex);
  2374. }
  2375. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  2376. void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2377. {
  2378. struct ieee80211_conf *conf = NULL;
  2379. int ret = 0;
  2380. if (!vif || !priv->is_open)
  2381. return;
  2382. if (vif->type == NL80211_IFTYPE_AP) {
  2383. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2384. return;
  2385. }
  2386. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2387. return;
  2388. iwl_scan_cancel_timeout(priv, 200);
  2389. conf = ieee80211_get_hw_conf(priv->hw);
  2390. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2391. iwlcore_commit_rxon(priv);
  2392. iwl_setup_rxon_timing(priv, vif);
  2393. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2394. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2395. if (ret)
  2396. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2397. "Attempting to continue.\n");
  2398. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2399. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2400. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2401. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2402. priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid);
  2403. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2404. vif->bss_conf.aid, vif->bss_conf.beacon_int);
  2405. if (vif->bss_conf.use_short_preamble)
  2406. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2407. else
  2408. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2409. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2410. if (vif->bss_conf.use_short_slot)
  2411. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2412. else
  2413. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2414. }
  2415. iwlcore_commit_rxon(priv);
  2416. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2417. vif->bss_conf.aid, priv->active_rxon.bssid_addr);
  2418. switch (vif->type) {
  2419. case NL80211_IFTYPE_STATION:
  2420. break;
  2421. case NL80211_IFTYPE_ADHOC:
  2422. iwl_send_beacon_cmd(priv);
  2423. break;
  2424. default:
  2425. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2426. __func__, vif->type);
  2427. break;
  2428. }
  2429. /* the chain noise calibration will enabled PM upon completion
  2430. * If chain noise has already been run, then we need to enable
  2431. * power management here */
  2432. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  2433. iwl_power_update_mode(priv, false);
  2434. /* Enable Rx differential gain and sensitivity calibrations */
  2435. iwl_chain_noise_reset(priv);
  2436. priv->start_calib = 1;
  2437. }
  2438. /*****************************************************************************
  2439. *
  2440. * mac80211 entry point functions
  2441. *
  2442. *****************************************************************************/
  2443. #define UCODE_READY_TIMEOUT (4 * HZ)
  2444. /*
  2445. * Not a mac80211 entry point function, but it fits in with all the
  2446. * other mac80211 functions grouped here.
  2447. */
  2448. static int iwl_mac_setup_register(struct iwl_priv *priv,
  2449. struct iwlagn_ucode_capabilities *capa)
  2450. {
  2451. int ret;
  2452. struct ieee80211_hw *hw = priv->hw;
  2453. hw->rate_control_algorithm = "iwl-agn-rs";
  2454. /* Tell mac80211 our characteristics */
  2455. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2456. IEEE80211_HW_AMPDU_AGGREGATION |
  2457. IEEE80211_HW_SPECTRUM_MGMT;
  2458. if (!priv->cfg->broken_powersave)
  2459. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2460. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2461. if (priv->cfg->sku & IWL_SKU_N)
  2462. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2463. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2464. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2465. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  2466. hw->wiphy->interface_modes =
  2467. BIT(NL80211_IFTYPE_STATION) |
  2468. BIT(NL80211_IFTYPE_ADHOC);
  2469. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  2470. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2471. /*
  2472. * For now, disable PS by default because it affects
  2473. * RX performance significantly.
  2474. */
  2475. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2476. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2477. /* we create the 802.11 header and a zero-length SSID element */
  2478. hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
  2479. /* Default value; 4 EDCA QOS priorities */
  2480. hw->queues = 4;
  2481. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2482. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2483. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2484. &priv->bands[IEEE80211_BAND_2GHZ];
  2485. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2486. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2487. &priv->bands[IEEE80211_BAND_5GHZ];
  2488. ret = ieee80211_register_hw(priv->hw);
  2489. if (ret) {
  2490. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2491. return ret;
  2492. }
  2493. priv->mac80211_registered = 1;
  2494. return 0;
  2495. }
  2496. static int iwl_mac_start(struct ieee80211_hw *hw)
  2497. {
  2498. struct iwl_priv *priv = hw->priv;
  2499. int ret;
  2500. IWL_DEBUG_MAC80211(priv, "enter\n");
  2501. /* we should be verifying the device is ready to be opened */
  2502. mutex_lock(&priv->mutex);
  2503. ret = __iwl_up(priv);
  2504. mutex_unlock(&priv->mutex);
  2505. if (ret)
  2506. return ret;
  2507. if (iwl_is_rfkill(priv))
  2508. goto out;
  2509. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2510. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2511. * mac80211 will not be run successfully. */
  2512. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2513. test_bit(STATUS_READY, &priv->status),
  2514. UCODE_READY_TIMEOUT);
  2515. if (!ret) {
  2516. if (!test_bit(STATUS_READY, &priv->status)) {
  2517. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2518. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2519. return -ETIMEDOUT;
  2520. }
  2521. }
  2522. iwl_led_start(priv);
  2523. out:
  2524. priv->is_open = 1;
  2525. IWL_DEBUG_MAC80211(priv, "leave\n");
  2526. return 0;
  2527. }
  2528. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2529. {
  2530. struct iwl_priv *priv = hw->priv;
  2531. IWL_DEBUG_MAC80211(priv, "enter\n");
  2532. if (!priv->is_open)
  2533. return;
  2534. priv->is_open = 0;
  2535. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2536. /* stop mac, cancel any scan request and clear
  2537. * RXON_FILTER_ASSOC_MSK BIT
  2538. */
  2539. mutex_lock(&priv->mutex);
  2540. iwl_scan_cancel_timeout(priv, 100);
  2541. mutex_unlock(&priv->mutex);
  2542. }
  2543. iwl_down(priv);
  2544. flush_workqueue(priv->workqueue);
  2545. /* enable interrupts again in order to receive rfkill changes */
  2546. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2547. iwl_enable_interrupts(priv);
  2548. IWL_DEBUG_MAC80211(priv, "leave\n");
  2549. }
  2550. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2551. {
  2552. struct iwl_priv *priv = hw->priv;
  2553. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2554. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2555. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2556. if (iwlagn_tx_skb(priv, skb))
  2557. dev_kfree_skb_any(skb);
  2558. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2559. return NETDEV_TX_OK;
  2560. }
  2561. void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2562. {
  2563. int ret = 0;
  2564. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2565. return;
  2566. /* The following should be done only at AP bring up */
  2567. if (!iwl_is_associated(priv)) {
  2568. /* RXON - unassoc (to set timing command) */
  2569. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2570. iwlcore_commit_rxon(priv);
  2571. /* RXON Timing */
  2572. iwl_setup_rxon_timing(priv, vif);
  2573. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2574. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2575. if (ret)
  2576. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2577. "Attempting to continue.\n");
  2578. /* AP has all antennas */
  2579. priv->chain_noise_data.active_chains =
  2580. priv->hw_params.valid_rx_ant;
  2581. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2582. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2583. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2584. priv->staging_rxon.assoc_id = 0;
  2585. if (vif->bss_conf.use_short_preamble)
  2586. priv->staging_rxon.flags |=
  2587. RXON_FLG_SHORT_PREAMBLE_MSK;
  2588. else
  2589. priv->staging_rxon.flags &=
  2590. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2591. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2592. if (vif->bss_conf.use_short_slot)
  2593. priv->staging_rxon.flags |=
  2594. RXON_FLG_SHORT_SLOT_MSK;
  2595. else
  2596. priv->staging_rxon.flags &=
  2597. ~RXON_FLG_SHORT_SLOT_MSK;
  2598. }
  2599. /* restore RXON assoc */
  2600. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2601. iwlcore_commit_rxon(priv);
  2602. }
  2603. iwl_send_beacon_cmd(priv);
  2604. /* FIXME - we need to add code here to detect a totally new
  2605. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2606. * clear sta table, add BCAST sta... */
  2607. }
  2608. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2609. struct ieee80211_vif *vif,
  2610. struct ieee80211_key_conf *keyconf,
  2611. struct ieee80211_sta *sta,
  2612. u32 iv32, u16 *phase1key)
  2613. {
  2614. struct iwl_priv *priv = hw->priv;
  2615. IWL_DEBUG_MAC80211(priv, "enter\n");
  2616. iwl_update_tkip_key(priv, keyconf, sta,
  2617. iv32, phase1key);
  2618. IWL_DEBUG_MAC80211(priv, "leave\n");
  2619. }
  2620. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2621. struct ieee80211_vif *vif,
  2622. struct ieee80211_sta *sta,
  2623. struct ieee80211_key_conf *key)
  2624. {
  2625. struct iwl_priv *priv = hw->priv;
  2626. int ret;
  2627. u8 sta_id;
  2628. bool is_default_wep_key = false;
  2629. IWL_DEBUG_MAC80211(priv, "enter\n");
  2630. if (priv->cfg->mod_params->sw_crypto) {
  2631. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2632. return -EOPNOTSUPP;
  2633. }
  2634. sta_id = iwl_sta_id_or_broadcast(priv, sta);
  2635. if (sta_id == IWL_INVALID_STATION)
  2636. return -EINVAL;
  2637. mutex_lock(&priv->mutex);
  2638. iwl_scan_cancel_timeout(priv, 100);
  2639. /*
  2640. * If we are getting WEP group key and we didn't receive any key mapping
  2641. * so far, we are in legacy wep mode (group key only), otherwise we are
  2642. * in 1X mode.
  2643. * In legacy wep mode, we use another host command to the uCode.
  2644. */
  2645. if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
  2646. if (cmd == SET_KEY)
  2647. is_default_wep_key = !priv->key_mapping_key;
  2648. else
  2649. is_default_wep_key =
  2650. (key->hw_key_idx == HW_KEY_DEFAULT);
  2651. }
  2652. switch (cmd) {
  2653. case SET_KEY:
  2654. if (is_default_wep_key)
  2655. ret = iwl_set_default_wep_key(priv, key);
  2656. else
  2657. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2658. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2659. break;
  2660. case DISABLE_KEY:
  2661. if (is_default_wep_key)
  2662. ret = iwl_remove_default_wep_key(priv, key);
  2663. else
  2664. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2665. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2666. break;
  2667. default:
  2668. ret = -EINVAL;
  2669. }
  2670. mutex_unlock(&priv->mutex);
  2671. IWL_DEBUG_MAC80211(priv, "leave\n");
  2672. return ret;
  2673. }
  2674. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2675. struct ieee80211_vif *vif,
  2676. enum ieee80211_ampdu_mlme_action action,
  2677. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2678. {
  2679. struct iwl_priv *priv = hw->priv;
  2680. int ret;
  2681. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2682. sta->addr, tid);
  2683. if (!(priv->cfg->sku & IWL_SKU_N))
  2684. return -EACCES;
  2685. switch (action) {
  2686. case IEEE80211_AMPDU_RX_START:
  2687. IWL_DEBUG_HT(priv, "start Rx\n");
  2688. return iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
  2689. case IEEE80211_AMPDU_RX_STOP:
  2690. IWL_DEBUG_HT(priv, "stop Rx\n");
  2691. ret = iwl_sta_rx_agg_stop(priv, sta, tid);
  2692. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2693. return 0;
  2694. else
  2695. return ret;
  2696. case IEEE80211_AMPDU_TX_START:
  2697. IWL_DEBUG_HT(priv, "start Tx\n");
  2698. ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
  2699. if (ret == 0) {
  2700. priv->_agn.agg_tids_count++;
  2701. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2702. priv->_agn.agg_tids_count);
  2703. }
  2704. return ret;
  2705. case IEEE80211_AMPDU_TX_STOP:
  2706. IWL_DEBUG_HT(priv, "stop Tx\n");
  2707. ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
  2708. if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
  2709. priv->_agn.agg_tids_count--;
  2710. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2711. priv->_agn.agg_tids_count);
  2712. }
  2713. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2714. return 0;
  2715. else
  2716. return ret;
  2717. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2718. /* do nothing */
  2719. return -EOPNOTSUPP;
  2720. default:
  2721. IWL_DEBUG_HT(priv, "unknown\n");
  2722. return -EINVAL;
  2723. break;
  2724. }
  2725. return 0;
  2726. }
  2727. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2728. struct ieee80211_vif *vif,
  2729. enum sta_notify_cmd cmd,
  2730. struct ieee80211_sta *sta)
  2731. {
  2732. struct iwl_priv *priv = hw->priv;
  2733. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2734. int sta_id;
  2735. switch (cmd) {
  2736. case STA_NOTIFY_SLEEP:
  2737. WARN_ON(!sta_priv->client);
  2738. sta_priv->asleep = true;
  2739. if (atomic_read(&sta_priv->pending_frames) > 0)
  2740. ieee80211_sta_block_awake(hw, sta, true);
  2741. break;
  2742. case STA_NOTIFY_AWAKE:
  2743. WARN_ON(!sta_priv->client);
  2744. if (!sta_priv->asleep)
  2745. break;
  2746. sta_priv->asleep = false;
  2747. sta_id = iwl_sta_id(sta);
  2748. if (sta_id != IWL_INVALID_STATION)
  2749. iwl_sta_modify_ps_wake(priv, sta_id);
  2750. break;
  2751. default:
  2752. break;
  2753. }
  2754. }
  2755. static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
  2756. struct ieee80211_vif *vif,
  2757. struct ieee80211_sta *sta)
  2758. {
  2759. struct iwl_priv *priv = hw->priv;
  2760. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2761. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2762. int ret;
  2763. u8 sta_id;
  2764. sta_priv->common.sta_id = IWL_INVALID_STATION;
  2765. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2766. sta->addr);
  2767. atomic_set(&sta_priv->pending_frames, 0);
  2768. if (vif->type == NL80211_IFTYPE_AP)
  2769. sta_priv->client = true;
  2770. ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
  2771. &sta_id);
  2772. if (ret) {
  2773. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2774. sta->addr, ret);
  2775. /* Should we return success if return code is EEXIST ? */
  2776. return ret;
  2777. }
  2778. sta_priv->common.sta_id = sta_id;
  2779. /* Initialize rate scaling */
  2780. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2781. sta->addr);
  2782. iwl_rs_rate_init(priv, sta, sta_id);
  2783. return 0;
  2784. }
  2785. /*****************************************************************************
  2786. *
  2787. * sysfs attributes
  2788. *
  2789. *****************************************************************************/
  2790. #ifdef CONFIG_IWLWIFI_DEBUG
  2791. /*
  2792. * The following adds a new attribute to the sysfs representation
  2793. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2794. * used for controlling the debug level.
  2795. *
  2796. * See the level definitions in iwl for details.
  2797. *
  2798. * The debug_level being managed using sysfs below is a per device debug
  2799. * level that is used instead of the global debug level if it (the per
  2800. * device debug level) is set.
  2801. */
  2802. static ssize_t show_debug_level(struct device *d,
  2803. struct device_attribute *attr, char *buf)
  2804. {
  2805. struct iwl_priv *priv = dev_get_drvdata(d);
  2806. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2807. }
  2808. static ssize_t store_debug_level(struct device *d,
  2809. struct device_attribute *attr,
  2810. const char *buf, size_t count)
  2811. {
  2812. struct iwl_priv *priv = dev_get_drvdata(d);
  2813. unsigned long val;
  2814. int ret;
  2815. ret = strict_strtoul(buf, 0, &val);
  2816. if (ret)
  2817. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2818. else {
  2819. priv->debug_level = val;
  2820. if (iwl_alloc_traffic_mem(priv))
  2821. IWL_ERR(priv,
  2822. "Not enough memory to generate traffic log\n");
  2823. }
  2824. return strnlen(buf, count);
  2825. }
  2826. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2827. show_debug_level, store_debug_level);
  2828. #endif /* CONFIG_IWLWIFI_DEBUG */
  2829. static ssize_t show_temperature(struct device *d,
  2830. struct device_attribute *attr, char *buf)
  2831. {
  2832. struct iwl_priv *priv = dev_get_drvdata(d);
  2833. if (!iwl_is_alive(priv))
  2834. return -EAGAIN;
  2835. return sprintf(buf, "%d\n", priv->temperature);
  2836. }
  2837. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2838. static ssize_t show_tx_power(struct device *d,
  2839. struct device_attribute *attr, char *buf)
  2840. {
  2841. struct iwl_priv *priv = dev_get_drvdata(d);
  2842. if (!iwl_is_ready_rf(priv))
  2843. return sprintf(buf, "off\n");
  2844. else
  2845. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2846. }
  2847. static ssize_t store_tx_power(struct device *d,
  2848. struct device_attribute *attr,
  2849. const char *buf, size_t count)
  2850. {
  2851. struct iwl_priv *priv = dev_get_drvdata(d);
  2852. unsigned long val;
  2853. int ret;
  2854. ret = strict_strtoul(buf, 10, &val);
  2855. if (ret)
  2856. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2857. else {
  2858. ret = iwl_set_tx_power(priv, val, false);
  2859. if (ret)
  2860. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2861. ret);
  2862. else
  2863. ret = count;
  2864. }
  2865. return ret;
  2866. }
  2867. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2868. static ssize_t show_rts_ht_protection(struct device *d,
  2869. struct device_attribute *attr, char *buf)
  2870. {
  2871. struct iwl_priv *priv = dev_get_drvdata(d);
  2872. return sprintf(buf, "%s\n",
  2873. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2874. }
  2875. static ssize_t store_rts_ht_protection(struct device *d,
  2876. struct device_attribute *attr,
  2877. const char *buf, size_t count)
  2878. {
  2879. struct iwl_priv *priv = dev_get_drvdata(d);
  2880. unsigned long val;
  2881. int ret;
  2882. ret = strict_strtoul(buf, 10, &val);
  2883. if (ret)
  2884. IWL_INFO(priv, "Input is not in decimal form.\n");
  2885. else {
  2886. if (!iwl_is_associated(priv))
  2887. priv->cfg->use_rts_for_ht = val ? true : false;
  2888. else
  2889. IWL_ERR(priv, "Sta associated with AP - "
  2890. "Change protection mechanism is not allowed\n");
  2891. ret = count;
  2892. }
  2893. return ret;
  2894. }
  2895. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2896. show_rts_ht_protection, store_rts_ht_protection);
  2897. /*****************************************************************************
  2898. *
  2899. * driver setup and teardown
  2900. *
  2901. *****************************************************************************/
  2902. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2903. {
  2904. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2905. init_waitqueue_head(&priv->wait_command_queue);
  2906. INIT_WORK(&priv->restart, iwl_bg_restart);
  2907. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2908. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2909. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2910. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2911. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2912. iwl_setup_scan_deferred_work(priv);
  2913. if (priv->cfg->ops->lib->setup_deferred_work)
  2914. priv->cfg->ops->lib->setup_deferred_work(priv);
  2915. init_timer(&priv->statistics_periodic);
  2916. priv->statistics_periodic.data = (unsigned long)priv;
  2917. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2918. init_timer(&priv->ucode_trace);
  2919. priv->ucode_trace.data = (unsigned long)priv;
  2920. priv->ucode_trace.function = iwl_bg_ucode_trace;
  2921. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  2922. init_timer(&priv->monitor_recover);
  2923. priv->monitor_recover.data = (unsigned long)priv;
  2924. priv->monitor_recover.function =
  2925. priv->cfg->ops->lib->recover_from_tx_stall;
  2926. }
  2927. if (!priv->cfg->use_isr_legacy)
  2928. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2929. iwl_irq_tasklet, (unsigned long)priv);
  2930. else
  2931. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2932. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2933. }
  2934. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2935. {
  2936. if (priv->cfg->ops->lib->cancel_deferred_work)
  2937. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2938. cancel_delayed_work_sync(&priv->init_alive_start);
  2939. cancel_delayed_work(&priv->scan_check);
  2940. cancel_work_sync(&priv->start_internal_scan);
  2941. cancel_delayed_work(&priv->alive_start);
  2942. cancel_work_sync(&priv->beacon_update);
  2943. del_timer_sync(&priv->statistics_periodic);
  2944. del_timer_sync(&priv->ucode_trace);
  2945. if (priv->cfg->ops->lib->recover_from_tx_stall)
  2946. del_timer_sync(&priv->monitor_recover);
  2947. }
  2948. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2949. struct ieee80211_rate *rates)
  2950. {
  2951. int i;
  2952. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2953. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2954. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2955. rates[i].hw_value_short = i;
  2956. rates[i].flags = 0;
  2957. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2958. /*
  2959. * If CCK != 1M then set short preamble rate flag.
  2960. */
  2961. rates[i].flags |=
  2962. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2963. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2964. }
  2965. }
  2966. }
  2967. static int iwl_init_drv(struct iwl_priv *priv)
  2968. {
  2969. int ret;
  2970. priv->ibss_beacon = NULL;
  2971. spin_lock_init(&priv->sta_lock);
  2972. spin_lock_init(&priv->hcmd_lock);
  2973. INIT_LIST_HEAD(&priv->free_frames);
  2974. mutex_init(&priv->mutex);
  2975. mutex_init(&priv->sync_cmd_mutex);
  2976. priv->ieee_channels = NULL;
  2977. priv->ieee_rates = NULL;
  2978. priv->band = IEEE80211_BAND_2GHZ;
  2979. priv->iw_mode = NL80211_IFTYPE_STATION;
  2980. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  2981. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  2982. priv->_agn.agg_tids_count = 0;
  2983. /* initialize force reset */
  2984. priv->force_reset[IWL_RF_RESET].reset_duration =
  2985. IWL_DELAY_NEXT_FORCE_RF_RESET;
  2986. priv->force_reset[IWL_FW_RESET].reset_duration =
  2987. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  2988. /* Choose which receivers/antennas to use */
  2989. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2990. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2991. iwl_init_scan_params(priv);
  2992. /* Set the tx_power_user_lmt to the lowest power level
  2993. * this value will get overwritten by channel max power avg
  2994. * from eeprom */
  2995. priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
  2996. ret = iwl_init_channel_map(priv);
  2997. if (ret) {
  2998. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2999. goto err;
  3000. }
  3001. ret = iwlcore_init_geos(priv);
  3002. if (ret) {
  3003. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  3004. goto err_free_channel_map;
  3005. }
  3006. iwl_init_hw_rates(priv, priv->ieee_rates);
  3007. return 0;
  3008. err_free_channel_map:
  3009. iwl_free_channel_map(priv);
  3010. err:
  3011. return ret;
  3012. }
  3013. static void iwl_uninit_drv(struct iwl_priv *priv)
  3014. {
  3015. iwl_calib_free_results(priv);
  3016. iwlcore_free_geos(priv);
  3017. iwl_free_channel_map(priv);
  3018. kfree(priv->scan_cmd);
  3019. }
  3020. static struct attribute *iwl_sysfs_entries[] = {
  3021. &dev_attr_temperature.attr,
  3022. &dev_attr_tx_power.attr,
  3023. &dev_attr_rts_ht_protection.attr,
  3024. #ifdef CONFIG_IWLWIFI_DEBUG
  3025. &dev_attr_debug_level.attr,
  3026. #endif
  3027. NULL
  3028. };
  3029. static struct attribute_group iwl_attribute_group = {
  3030. .name = NULL, /* put in device directory */
  3031. .attrs = iwl_sysfs_entries,
  3032. };
  3033. static struct ieee80211_ops iwl_hw_ops = {
  3034. .tx = iwl_mac_tx,
  3035. .start = iwl_mac_start,
  3036. .stop = iwl_mac_stop,
  3037. .add_interface = iwl_mac_add_interface,
  3038. .remove_interface = iwl_mac_remove_interface,
  3039. .config = iwl_mac_config,
  3040. .configure_filter = iwl_configure_filter,
  3041. .set_key = iwl_mac_set_key,
  3042. .update_tkip_key = iwl_mac_update_tkip_key,
  3043. .conf_tx = iwl_mac_conf_tx,
  3044. .reset_tsf = iwl_mac_reset_tsf,
  3045. .bss_info_changed = iwl_bss_info_changed,
  3046. .ampdu_action = iwl_mac_ampdu_action,
  3047. .hw_scan = iwl_mac_hw_scan,
  3048. .sta_notify = iwl_mac_sta_notify,
  3049. .sta_add = iwlagn_mac_sta_add,
  3050. .sta_remove = iwl_mac_sta_remove,
  3051. };
  3052. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  3053. {
  3054. int err = 0;
  3055. struct iwl_priv *priv;
  3056. struct ieee80211_hw *hw;
  3057. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  3058. unsigned long flags;
  3059. u16 pci_cmd;
  3060. /************************
  3061. * 1. Allocating HW data
  3062. ************************/
  3063. /* Disabling hardware scan means that mac80211 will perform scans
  3064. * "the hard way", rather than using device's scan. */
  3065. if (cfg->mod_params->disable_hw_scan) {
  3066. if (iwl_debug_level & IWL_DL_INFO)
  3067. dev_printk(KERN_DEBUG, &(pdev->dev),
  3068. "Disabling hw_scan\n");
  3069. iwl_hw_ops.hw_scan = NULL;
  3070. }
  3071. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  3072. if (!hw) {
  3073. err = -ENOMEM;
  3074. goto out;
  3075. }
  3076. priv = hw->priv;
  3077. /* At this point both hw and priv are allocated. */
  3078. SET_IEEE80211_DEV(hw, &pdev->dev);
  3079. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  3080. priv->cfg = cfg;
  3081. priv->pci_dev = pdev;
  3082. priv->inta_mask = CSR_INI_SET_MASK;
  3083. #ifdef CONFIG_IWLWIFI_DEBUG
  3084. atomic_set(&priv->restrict_refcnt, 0);
  3085. #endif
  3086. if (iwl_alloc_traffic_mem(priv))
  3087. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  3088. /**************************
  3089. * 2. Initializing PCI bus
  3090. **************************/
  3091. if (pci_enable_device(pdev)) {
  3092. err = -ENODEV;
  3093. goto out_ieee80211_free_hw;
  3094. }
  3095. pci_set_master(pdev);
  3096. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  3097. if (!err)
  3098. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  3099. if (err) {
  3100. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3101. if (!err)
  3102. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3103. /* both attempts failed: */
  3104. if (err) {
  3105. IWL_WARN(priv, "No suitable DMA available.\n");
  3106. goto out_pci_disable_device;
  3107. }
  3108. }
  3109. err = pci_request_regions(pdev, DRV_NAME);
  3110. if (err)
  3111. goto out_pci_disable_device;
  3112. pci_set_drvdata(pdev, priv);
  3113. /***********************
  3114. * 3. Read REV register
  3115. ***********************/
  3116. priv->hw_base = pci_iomap(pdev, 0, 0);
  3117. if (!priv->hw_base) {
  3118. err = -ENODEV;
  3119. goto out_pci_release_regions;
  3120. }
  3121. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  3122. (unsigned long long) pci_resource_len(pdev, 0));
  3123. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  3124. /* these spin locks will be used in apm_ops.init and EEPROM access
  3125. * we should init now
  3126. */
  3127. spin_lock_init(&priv->reg_lock);
  3128. spin_lock_init(&priv->lock);
  3129. /*
  3130. * stop and reset the on-board processor just in case it is in a
  3131. * strange state ... like being left stranded by a primary kernel
  3132. * and this is now the kdump kernel trying to start up
  3133. */
  3134. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3135. iwl_hw_detect(priv);
  3136. IWL_INFO(priv, "Detected %s, REV=0x%X\n",
  3137. priv->cfg->name, priv->hw_rev);
  3138. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3139. * PCI Tx retries from interfering with C3 CPU state */
  3140. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  3141. iwl_prepare_card_hw(priv);
  3142. if (!priv->hw_ready) {
  3143. IWL_WARN(priv, "Failed, HW not ready\n");
  3144. goto out_iounmap;
  3145. }
  3146. /*****************
  3147. * 4. Read EEPROM
  3148. *****************/
  3149. /* Read the EEPROM */
  3150. err = iwl_eeprom_init(priv);
  3151. if (err) {
  3152. IWL_ERR(priv, "Unable to init EEPROM\n");
  3153. goto out_iounmap;
  3154. }
  3155. err = iwl_eeprom_check_version(priv);
  3156. if (err)
  3157. goto out_free_eeprom;
  3158. /* extract MAC Address */
  3159. iwl_eeprom_get_mac(priv, priv->mac_addr);
  3160. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  3161. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  3162. /************************
  3163. * 5. Setup HW constants
  3164. ************************/
  3165. if (iwl_set_hw_params(priv)) {
  3166. IWL_ERR(priv, "failed to set hw parameters\n");
  3167. goto out_free_eeprom;
  3168. }
  3169. /*******************
  3170. * 6. Setup priv
  3171. *******************/
  3172. err = iwl_init_drv(priv);
  3173. if (err)
  3174. goto out_free_eeprom;
  3175. /* At this point both hw and priv are initialized. */
  3176. /********************
  3177. * 7. Setup services
  3178. ********************/
  3179. spin_lock_irqsave(&priv->lock, flags);
  3180. iwl_disable_interrupts(priv);
  3181. spin_unlock_irqrestore(&priv->lock, flags);
  3182. pci_enable_msi(priv->pci_dev);
  3183. iwl_alloc_isr_ict(priv);
  3184. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  3185. IRQF_SHARED, DRV_NAME, priv);
  3186. if (err) {
  3187. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3188. goto out_disable_msi;
  3189. }
  3190. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  3191. if (err) {
  3192. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  3193. goto out_free_irq;
  3194. }
  3195. iwl_setup_deferred_work(priv);
  3196. iwl_setup_rx_handlers(priv);
  3197. /*********************************************
  3198. * 8. Enable interrupts and read RFKILL state
  3199. *********************************************/
  3200. /* enable interrupts if needed: hw bug w/a */
  3201. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  3202. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3203. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3204. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  3205. }
  3206. iwl_enable_interrupts(priv);
  3207. /* If platform's RF_KILL switch is NOT set to KILL */
  3208. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3209. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3210. else
  3211. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3212. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  3213. test_bit(STATUS_RF_KILL_HW, &priv->status));
  3214. iwl_power_initialize(priv);
  3215. iwl_tt_initialize(priv);
  3216. init_completion(&priv->_agn.firmware_loading_complete);
  3217. err = iwl_request_firmware(priv, true);
  3218. if (err)
  3219. goto out_remove_sysfs;
  3220. return 0;
  3221. out_remove_sysfs:
  3222. destroy_workqueue(priv->workqueue);
  3223. priv->workqueue = NULL;
  3224. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3225. out_free_irq:
  3226. free_irq(priv->pci_dev->irq, priv);
  3227. iwl_free_isr_ict(priv);
  3228. out_disable_msi:
  3229. pci_disable_msi(priv->pci_dev);
  3230. iwl_uninit_drv(priv);
  3231. out_free_eeprom:
  3232. iwl_eeprom_free(priv);
  3233. out_iounmap:
  3234. pci_iounmap(pdev, priv->hw_base);
  3235. out_pci_release_regions:
  3236. pci_set_drvdata(pdev, NULL);
  3237. pci_release_regions(pdev);
  3238. out_pci_disable_device:
  3239. pci_disable_device(pdev);
  3240. out_ieee80211_free_hw:
  3241. iwl_free_traffic_mem(priv);
  3242. ieee80211_free_hw(priv->hw);
  3243. out:
  3244. return err;
  3245. }
  3246. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  3247. {
  3248. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3249. unsigned long flags;
  3250. if (!priv)
  3251. return;
  3252. wait_for_completion(&priv->_agn.firmware_loading_complete);
  3253. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3254. iwl_dbgfs_unregister(priv);
  3255. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3256. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3257. * to be called and iwl_down since we are removing the device
  3258. * we need to set STATUS_EXIT_PENDING bit.
  3259. */
  3260. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3261. if (priv->mac80211_registered) {
  3262. ieee80211_unregister_hw(priv->hw);
  3263. priv->mac80211_registered = 0;
  3264. } else {
  3265. iwl_down(priv);
  3266. }
  3267. /*
  3268. * Make sure device is reset to low power before unloading driver.
  3269. * This may be redundant with iwl_down(), but there are paths to
  3270. * run iwl_down() without calling apm_ops.stop(), and there are
  3271. * paths to avoid running iwl_down() at all before leaving driver.
  3272. * This (inexpensive) call *makes sure* device is reset.
  3273. */
  3274. priv->cfg->ops->lib->apm_ops.stop(priv);
  3275. iwl_tt_exit(priv);
  3276. /* make sure we flush any pending irq or
  3277. * tasklet for the driver
  3278. */
  3279. spin_lock_irqsave(&priv->lock, flags);
  3280. iwl_disable_interrupts(priv);
  3281. spin_unlock_irqrestore(&priv->lock, flags);
  3282. iwl_synchronize_irq(priv);
  3283. iwl_dealloc_ucode_pci(priv);
  3284. if (priv->rxq.bd)
  3285. iwlagn_rx_queue_free(priv, &priv->rxq);
  3286. iwlagn_hw_txq_ctx_free(priv);
  3287. iwl_eeprom_free(priv);
  3288. /*netif_stop_queue(dev); */
  3289. flush_workqueue(priv->workqueue);
  3290. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3291. * priv->workqueue... so we can't take down the workqueue
  3292. * until now... */
  3293. destroy_workqueue(priv->workqueue);
  3294. priv->workqueue = NULL;
  3295. iwl_free_traffic_mem(priv);
  3296. free_irq(priv->pci_dev->irq, priv);
  3297. pci_disable_msi(priv->pci_dev);
  3298. pci_iounmap(pdev, priv->hw_base);
  3299. pci_release_regions(pdev);
  3300. pci_disable_device(pdev);
  3301. pci_set_drvdata(pdev, NULL);
  3302. iwl_uninit_drv(priv);
  3303. iwl_free_isr_ict(priv);
  3304. if (priv->ibss_beacon)
  3305. dev_kfree_skb(priv->ibss_beacon);
  3306. ieee80211_free_hw(priv->hw);
  3307. }
  3308. /*****************************************************************************
  3309. *
  3310. * driver and module entry point
  3311. *
  3312. *****************************************************************************/
  3313. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3314. static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
  3315. #ifdef CONFIG_IWL4965
  3316. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  3317. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  3318. #endif /* CONFIG_IWL4965 */
  3319. #ifdef CONFIG_IWL5000
  3320. /* 5100 Series WiFi */
  3321. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3322. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3323. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3324. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3325. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3326. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3327. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3328. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3329. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3330. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3331. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3332. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3333. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3334. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3335. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3336. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3337. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3338. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3339. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3340. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3341. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3342. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3343. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3344. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3345. /* 5300 Series WiFi */
  3346. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3347. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3348. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3349. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3350. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3351. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3352. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3353. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3354. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3355. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3356. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3357. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3358. /* 5350 Series WiFi/WiMax */
  3359. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3360. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3361. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3362. /* 5150 Series Wifi/WiMax */
  3363. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3364. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3365. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3366. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3367. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3368. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3369. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3370. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3371. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3372. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3373. /* 6x00 Series */
  3374. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3375. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3376. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3377. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3378. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3379. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3380. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3381. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3382. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3383. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3384. /* 6x00 Series Gen2a */
  3385. {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
  3386. {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
  3387. {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
  3388. {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
  3389. {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
  3390. {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
  3391. {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
  3392. {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
  3393. {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
  3394. {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
  3395. {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
  3396. {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
  3397. {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
  3398. {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
  3399. /* 6x00 Series Gen2b */
  3400. {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
  3401. {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
  3402. {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
  3403. {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
  3404. {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
  3405. {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
  3406. {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
  3407. {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
  3408. {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
  3409. {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
  3410. {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
  3411. {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
  3412. {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
  3413. {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
  3414. {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
  3415. {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
  3416. {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
  3417. {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
  3418. {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
  3419. {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
  3420. {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
  3421. {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
  3422. {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
  3423. {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
  3424. {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
  3425. {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
  3426. {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
  3427. {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
  3428. /* 6x50 WiFi/WiMax Series */
  3429. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3430. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3431. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3432. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3433. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3434. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3435. /* 1000 Series WiFi */
  3436. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3437. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3438. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3439. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3440. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3441. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3442. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3443. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3444. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3445. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3446. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3447. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3448. #endif /* CONFIG_IWL5000 */
  3449. {0}
  3450. };
  3451. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3452. static struct pci_driver iwl_driver = {
  3453. .name = DRV_NAME,
  3454. .id_table = iwl_hw_card_ids,
  3455. .probe = iwl_pci_probe,
  3456. .remove = __devexit_p(iwl_pci_remove),
  3457. #ifdef CONFIG_PM
  3458. .suspend = iwl_pci_suspend,
  3459. .resume = iwl_pci_resume,
  3460. #endif
  3461. };
  3462. static int __init iwl_init(void)
  3463. {
  3464. int ret;
  3465. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3466. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  3467. ret = iwlagn_rate_control_register();
  3468. if (ret) {
  3469. printk(KERN_ERR DRV_NAME
  3470. "Unable to register rate control algorithm: %d\n", ret);
  3471. return ret;
  3472. }
  3473. ret = pci_register_driver(&iwl_driver);
  3474. if (ret) {
  3475. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  3476. goto error_register;
  3477. }
  3478. return ret;
  3479. error_register:
  3480. iwlagn_rate_control_unregister();
  3481. return ret;
  3482. }
  3483. static void __exit iwl_exit(void)
  3484. {
  3485. pci_unregister_driver(&iwl_driver);
  3486. iwlagn_rate_control_unregister();
  3487. }
  3488. module_exit(iwl_exit);
  3489. module_init(iwl_init);
  3490. #ifdef CONFIG_IWLWIFI_DEBUG
  3491. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3492. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3493. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3494. MODULE_PARM_DESC(debug, "debug output mask");
  3495. #endif
  3496. module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
  3497. MODULE_PARM_DESC(swcrypto50,
  3498. "using crypto in software (default 0 [hardware]) (deprecated)");
  3499. module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
  3500. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
  3501. module_param_named(queues_num50,
  3502. iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3503. MODULE_PARM_DESC(queues_num50,
  3504. "number of hw queues in 50xx series (deprecated)");
  3505. module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3506. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3507. module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3508. MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
  3509. module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3510. MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
  3511. module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
  3512. int, S_IRUGO);
  3513. MODULE_PARM_DESC(amsdu_size_8K50,
  3514. "enable 8K amsdu size in 50XX series (deprecated)");
  3515. module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
  3516. int, S_IRUGO);
  3517. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3518. module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3519. MODULE_PARM_DESC(fw_restart50,
  3520. "restart firmware in case of error (deprecated)");
  3521. module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3522. MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
  3523. module_param_named(
  3524. disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
  3525. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  3526. module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
  3527. S_IRUGO);
  3528. MODULE_PARM_DESC(ucode_alternative,
  3529. "specify ucode alternative to use from ucode file");