main.c 53 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include "ath9k.h"
  18. #include "btcoex.h"
  19. static void ath_cache_conf_rate(struct ath_softc *sc,
  20. struct ieee80211_conf *conf)
  21. {
  22. switch (conf->channel->band) {
  23. case IEEE80211_BAND_2GHZ:
  24. if (conf_is_ht20(conf))
  25. sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
  26. else if (conf_is_ht40_minus(conf))
  27. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
  28. else if (conf_is_ht40_plus(conf))
  29. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
  30. else
  31. sc->cur_rate_mode = ATH9K_MODE_11G;
  32. break;
  33. case IEEE80211_BAND_5GHZ:
  34. if (conf_is_ht20(conf))
  35. sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
  36. else if (conf_is_ht40_minus(conf))
  37. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
  38. else if (conf_is_ht40_plus(conf))
  39. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
  40. else
  41. sc->cur_rate_mode = ATH9K_MODE_11A;
  42. break;
  43. default:
  44. BUG_ON(1);
  45. break;
  46. }
  47. }
  48. static void ath_update_txpow(struct ath_softc *sc)
  49. {
  50. struct ath_hw *ah = sc->sc_ah;
  51. u32 txpow;
  52. if (sc->curtxpow != sc->config.txpowlimit) {
  53. ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
  54. /* read back in case value is clamped */
  55. ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
  56. sc->curtxpow = txpow;
  57. }
  58. }
  59. static u8 parse_mpdudensity(u8 mpdudensity)
  60. {
  61. /*
  62. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  63. * 0 for no restriction
  64. * 1 for 1/4 us
  65. * 2 for 1/2 us
  66. * 3 for 1 us
  67. * 4 for 2 us
  68. * 5 for 4 us
  69. * 6 for 8 us
  70. * 7 for 16 us
  71. */
  72. switch (mpdudensity) {
  73. case 0:
  74. return 0;
  75. case 1:
  76. case 2:
  77. case 3:
  78. /* Our lower layer calculations limit our precision to
  79. 1 microsecond */
  80. return 1;
  81. case 4:
  82. return 2;
  83. case 5:
  84. return 4;
  85. case 6:
  86. return 8;
  87. case 7:
  88. return 16;
  89. default:
  90. return 0;
  91. }
  92. }
  93. static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
  94. struct ieee80211_hw *hw)
  95. {
  96. struct ieee80211_channel *curchan = hw->conf.channel;
  97. struct ath9k_channel *channel;
  98. u8 chan_idx;
  99. chan_idx = curchan->hw_value;
  100. channel = &sc->sc_ah->channels[chan_idx];
  101. ath9k_update_ichannel(sc, hw, channel);
  102. return channel;
  103. }
  104. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  105. {
  106. unsigned long flags;
  107. bool ret;
  108. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  109. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  110. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  111. return ret;
  112. }
  113. void ath9k_ps_wakeup(struct ath_softc *sc)
  114. {
  115. unsigned long flags;
  116. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  117. if (++sc->ps_usecount != 1)
  118. goto unlock;
  119. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  120. unlock:
  121. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  122. }
  123. void ath9k_ps_restore(struct ath_softc *sc)
  124. {
  125. unsigned long flags;
  126. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  127. if (--sc->ps_usecount != 0)
  128. goto unlock;
  129. if (sc->ps_idle)
  130. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  131. else if (sc->ps_enabled &&
  132. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  133. PS_WAIT_FOR_CAB |
  134. PS_WAIT_FOR_PSPOLL_DATA |
  135. PS_WAIT_FOR_TX_ACK)))
  136. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
  137. unlock:
  138. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  139. }
  140. /*
  141. * Set/change channels. If the channel is really being changed, it's done
  142. * by reseting the chip. To accomplish this we must first cleanup any pending
  143. * DMA, then restart stuff.
  144. */
  145. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  146. struct ath9k_channel *hchan)
  147. {
  148. struct ath_hw *ah = sc->sc_ah;
  149. struct ath_common *common = ath9k_hw_common(ah);
  150. struct ieee80211_conf *conf = &common->hw->conf;
  151. bool fastcc = true, stopped;
  152. struct ieee80211_channel *channel = hw->conf.channel;
  153. int r;
  154. if (sc->sc_flags & SC_OP_INVALID)
  155. return -EIO;
  156. ath9k_ps_wakeup(sc);
  157. /*
  158. * This is only performed if the channel settings have
  159. * actually changed.
  160. *
  161. * To switch channels clear any pending DMA operations;
  162. * wait long enough for the RX fifo to drain, reset the
  163. * hardware at the new frequency, and then re-enable
  164. * the relevant bits of the h/w.
  165. */
  166. ath9k_hw_set_interrupts(ah, 0);
  167. ath_drain_all_txq(sc, false);
  168. stopped = ath_stoprecv(sc);
  169. /* XXX: do not flush receive queue here. We don't want
  170. * to flush data frames already in queue because of
  171. * changing channel. */
  172. if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
  173. fastcc = false;
  174. ath_print(common, ATH_DBG_CONFIG,
  175. "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
  176. sc->sc_ah->curchan->channel,
  177. channel->center_freq, conf_is_ht40(conf));
  178. spin_lock_bh(&sc->sc_resetlock);
  179. r = ath9k_hw_reset(ah, hchan, fastcc);
  180. if (r) {
  181. ath_print(common, ATH_DBG_FATAL,
  182. "Unable to reset channel (%u MHz), "
  183. "reset status %d\n",
  184. channel->center_freq, r);
  185. spin_unlock_bh(&sc->sc_resetlock);
  186. goto ps_restore;
  187. }
  188. spin_unlock_bh(&sc->sc_resetlock);
  189. sc->sc_flags &= ~SC_OP_FULL_RESET;
  190. if (ath_startrecv(sc) != 0) {
  191. ath_print(common, ATH_DBG_FATAL,
  192. "Unable to restart recv logic\n");
  193. r = -EIO;
  194. goto ps_restore;
  195. }
  196. ath_cache_conf_rate(sc, &hw->conf);
  197. ath_update_txpow(sc);
  198. ath9k_hw_set_interrupts(ah, ah->imask);
  199. ps_restore:
  200. ath9k_ps_restore(sc);
  201. return r;
  202. }
  203. /*
  204. * This routine performs the periodic noise floor calibration function
  205. * that is used to adjust and optimize the chip performance. This
  206. * takes environmental changes (location, temperature) into account.
  207. * When the task is complete, it reschedules itself depending on the
  208. * appropriate interval that was calculated.
  209. */
  210. void ath_ani_calibrate(unsigned long data)
  211. {
  212. struct ath_softc *sc = (struct ath_softc *)data;
  213. struct ath_hw *ah = sc->sc_ah;
  214. struct ath_common *common = ath9k_hw_common(ah);
  215. bool longcal = false;
  216. bool shortcal = false;
  217. bool aniflag = false;
  218. unsigned int timestamp = jiffies_to_msecs(jiffies);
  219. u32 cal_interval, short_cal_interval;
  220. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  221. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  222. /* Only calibrate if awake */
  223. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  224. goto set_timer;
  225. ath9k_ps_wakeup(sc);
  226. /* Long calibration runs independently of short calibration. */
  227. if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
  228. longcal = true;
  229. ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  230. common->ani.longcal_timer = timestamp;
  231. }
  232. /* Short calibration applies only while caldone is false */
  233. if (!common->ani.caldone) {
  234. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  235. shortcal = true;
  236. ath_print(common, ATH_DBG_ANI,
  237. "shortcal @%lu\n", jiffies);
  238. common->ani.shortcal_timer = timestamp;
  239. common->ani.resetcal_timer = timestamp;
  240. }
  241. } else {
  242. if ((timestamp - common->ani.resetcal_timer) >=
  243. ATH_RESTART_CALINTERVAL) {
  244. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  245. if (common->ani.caldone)
  246. common->ani.resetcal_timer = timestamp;
  247. }
  248. }
  249. /* Verify whether we must check ANI */
  250. if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
  251. aniflag = true;
  252. common->ani.checkani_timer = timestamp;
  253. }
  254. /* Skip all processing if there's nothing to do. */
  255. if (longcal || shortcal || aniflag) {
  256. /* Call ANI routine if necessary */
  257. if (aniflag)
  258. ath9k_hw_ani_monitor(ah, ah->curchan);
  259. /* Perform calibration if necessary */
  260. if (longcal || shortcal) {
  261. common->ani.caldone =
  262. ath9k_hw_calibrate(ah,
  263. ah->curchan,
  264. common->rx_chainmask,
  265. longcal);
  266. if (longcal)
  267. common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
  268. ah->curchan);
  269. ath_print(common, ATH_DBG_ANI,
  270. " calibrate chan %u/%x nf: %d\n",
  271. ah->curchan->channel,
  272. ah->curchan->channelFlags,
  273. common->ani.noise_floor);
  274. }
  275. }
  276. ath9k_ps_restore(sc);
  277. set_timer:
  278. /*
  279. * Set timer interval based on previous results.
  280. * The interval must be the shortest necessary to satisfy ANI,
  281. * short calibration and long calibration.
  282. */
  283. cal_interval = ATH_LONG_CALINTERVAL;
  284. if (sc->sc_ah->config.enable_ani)
  285. cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
  286. if (!common->ani.caldone)
  287. cal_interval = min(cal_interval, (u32)short_cal_interval);
  288. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  289. }
  290. static void ath_start_ani(struct ath_common *common)
  291. {
  292. unsigned long timestamp = jiffies_to_msecs(jiffies);
  293. common->ani.longcal_timer = timestamp;
  294. common->ani.shortcal_timer = timestamp;
  295. common->ani.checkani_timer = timestamp;
  296. mod_timer(&common->ani.timer,
  297. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  298. }
  299. /*
  300. * Update tx/rx chainmask. For legacy association,
  301. * hard code chainmask to 1x1, for 11n association, use
  302. * the chainmask configuration, for bt coexistence, use
  303. * the chainmask configuration even in legacy mode.
  304. */
  305. void ath_update_chainmask(struct ath_softc *sc, int is_ht)
  306. {
  307. struct ath_hw *ah = sc->sc_ah;
  308. struct ath_common *common = ath9k_hw_common(ah);
  309. if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
  310. (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
  311. common->tx_chainmask = ah->caps.tx_chainmask;
  312. common->rx_chainmask = ah->caps.rx_chainmask;
  313. } else {
  314. common->tx_chainmask = 1;
  315. common->rx_chainmask = 1;
  316. }
  317. ath_print(common, ATH_DBG_CONFIG,
  318. "tx chmask: %d, rx chmask: %d\n",
  319. common->tx_chainmask,
  320. common->rx_chainmask);
  321. }
  322. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  323. {
  324. struct ath_node *an;
  325. an = (struct ath_node *)sta->drv_priv;
  326. if (sc->sc_flags & SC_OP_TXAGGR) {
  327. ath_tx_node_init(sc, an);
  328. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  329. sta->ht_cap.ampdu_factor);
  330. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  331. an->last_rssi = ATH_RSSI_DUMMY_MARKER;
  332. }
  333. }
  334. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  335. {
  336. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  337. if (sc->sc_flags & SC_OP_TXAGGR)
  338. ath_tx_node_cleanup(sc, an);
  339. }
  340. void ath9k_tasklet(unsigned long data)
  341. {
  342. struct ath_softc *sc = (struct ath_softc *)data;
  343. struct ath_hw *ah = sc->sc_ah;
  344. struct ath_common *common = ath9k_hw_common(ah);
  345. u32 status = sc->intrstatus;
  346. u32 rxmask;
  347. ath9k_ps_wakeup(sc);
  348. if (status & ATH9K_INT_FATAL) {
  349. ath_reset(sc, false);
  350. ath9k_ps_restore(sc);
  351. return;
  352. }
  353. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  354. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  355. ATH9K_INT_RXORN);
  356. else
  357. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  358. if (status & rxmask) {
  359. spin_lock_bh(&sc->rx.rxflushlock);
  360. /* Check for high priority Rx first */
  361. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  362. (status & ATH9K_INT_RXHP))
  363. ath_rx_tasklet(sc, 0, true);
  364. ath_rx_tasklet(sc, 0, false);
  365. spin_unlock_bh(&sc->rx.rxflushlock);
  366. }
  367. if (status & ATH9K_INT_TX) {
  368. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  369. ath_tx_edma_tasklet(sc);
  370. else
  371. ath_tx_tasklet(sc);
  372. }
  373. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  374. /*
  375. * TSF sync does not look correct; remain awake to sync with
  376. * the next Beacon.
  377. */
  378. ath_print(common, ATH_DBG_PS,
  379. "TSFOOR - Sync with next Beacon\n");
  380. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  381. }
  382. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  383. if (status & ATH9K_INT_GENTIMER)
  384. ath_gen_timer_isr(sc->sc_ah);
  385. /* re-enable hardware interrupt */
  386. ath9k_hw_set_interrupts(ah, ah->imask);
  387. ath9k_ps_restore(sc);
  388. }
  389. irqreturn_t ath_isr(int irq, void *dev)
  390. {
  391. #define SCHED_INTR ( \
  392. ATH9K_INT_FATAL | \
  393. ATH9K_INT_RXORN | \
  394. ATH9K_INT_RXEOL | \
  395. ATH9K_INT_RX | \
  396. ATH9K_INT_RXLP | \
  397. ATH9K_INT_RXHP | \
  398. ATH9K_INT_TX | \
  399. ATH9K_INT_BMISS | \
  400. ATH9K_INT_CST | \
  401. ATH9K_INT_TSFOOR | \
  402. ATH9K_INT_GENTIMER)
  403. struct ath_softc *sc = dev;
  404. struct ath_hw *ah = sc->sc_ah;
  405. enum ath9k_int status;
  406. bool sched = false;
  407. /*
  408. * The hardware is not ready/present, don't
  409. * touch anything. Note this can happen early
  410. * on if the IRQ is shared.
  411. */
  412. if (sc->sc_flags & SC_OP_INVALID)
  413. return IRQ_NONE;
  414. /* shared irq, not for us */
  415. if (!ath9k_hw_intrpend(ah))
  416. return IRQ_NONE;
  417. /*
  418. * Figure out the reason(s) for the interrupt. Note
  419. * that the hal returns a pseudo-ISR that may include
  420. * bits we haven't explicitly enabled so we mask the
  421. * value to insure we only process bits we requested.
  422. */
  423. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  424. status &= ah->imask; /* discard unasked-for bits */
  425. /*
  426. * If there are no status bits set, then this interrupt was not
  427. * for me (should have been caught above).
  428. */
  429. if (!status)
  430. return IRQ_NONE;
  431. /* Cache the status */
  432. sc->intrstatus = status;
  433. if (status & SCHED_INTR)
  434. sched = true;
  435. /*
  436. * If a FATAL or RXORN interrupt is received, we have to reset the
  437. * chip immediately.
  438. */
  439. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  440. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  441. goto chip_reset;
  442. if (status & ATH9K_INT_SWBA)
  443. tasklet_schedule(&sc->bcon_tasklet);
  444. if (status & ATH9K_INT_TXURN)
  445. ath9k_hw_updatetxtriglevel(ah, true);
  446. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  447. if (status & ATH9K_INT_RXEOL) {
  448. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  449. ath9k_hw_set_interrupts(ah, ah->imask);
  450. }
  451. }
  452. if (status & ATH9K_INT_MIB) {
  453. /*
  454. * Disable interrupts until we service the MIB
  455. * interrupt; otherwise it will continue to
  456. * fire.
  457. */
  458. ath9k_hw_set_interrupts(ah, 0);
  459. /*
  460. * Let the hal handle the event. We assume
  461. * it will clear whatever condition caused
  462. * the interrupt.
  463. */
  464. ath9k_hw_procmibevent(ah);
  465. ath9k_hw_set_interrupts(ah, ah->imask);
  466. }
  467. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  468. if (status & ATH9K_INT_TIM_TIMER) {
  469. /* Clear RxAbort bit so that we can
  470. * receive frames */
  471. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  472. ath9k_hw_setrxabort(sc->sc_ah, 0);
  473. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  474. }
  475. chip_reset:
  476. ath_debug_stat_interrupt(sc, status);
  477. if (sched) {
  478. /* turn off every interrupt except SWBA */
  479. ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
  480. tasklet_schedule(&sc->intr_tq);
  481. }
  482. return IRQ_HANDLED;
  483. #undef SCHED_INTR
  484. }
  485. static u32 ath_get_extchanmode(struct ath_softc *sc,
  486. struct ieee80211_channel *chan,
  487. enum nl80211_channel_type channel_type)
  488. {
  489. u32 chanmode = 0;
  490. switch (chan->band) {
  491. case IEEE80211_BAND_2GHZ:
  492. switch(channel_type) {
  493. case NL80211_CHAN_NO_HT:
  494. case NL80211_CHAN_HT20:
  495. chanmode = CHANNEL_G_HT20;
  496. break;
  497. case NL80211_CHAN_HT40PLUS:
  498. chanmode = CHANNEL_G_HT40PLUS;
  499. break;
  500. case NL80211_CHAN_HT40MINUS:
  501. chanmode = CHANNEL_G_HT40MINUS;
  502. break;
  503. }
  504. break;
  505. case IEEE80211_BAND_5GHZ:
  506. switch(channel_type) {
  507. case NL80211_CHAN_NO_HT:
  508. case NL80211_CHAN_HT20:
  509. chanmode = CHANNEL_A_HT20;
  510. break;
  511. case NL80211_CHAN_HT40PLUS:
  512. chanmode = CHANNEL_A_HT40PLUS;
  513. break;
  514. case NL80211_CHAN_HT40MINUS:
  515. chanmode = CHANNEL_A_HT40MINUS;
  516. break;
  517. }
  518. break;
  519. default:
  520. break;
  521. }
  522. return chanmode;
  523. }
  524. static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
  525. struct ath9k_keyval *hk, const u8 *addr,
  526. bool authenticator)
  527. {
  528. struct ath_hw *ah = common->ah;
  529. const u8 *key_rxmic;
  530. const u8 *key_txmic;
  531. key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
  532. key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
  533. if (addr == NULL) {
  534. /*
  535. * Group key installation - only two key cache entries are used
  536. * regardless of splitmic capability since group key is only
  537. * used either for TX or RX.
  538. */
  539. if (authenticator) {
  540. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  541. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
  542. } else {
  543. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  544. memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
  545. }
  546. return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
  547. }
  548. if (!common->splitmic) {
  549. /* TX and RX keys share the same key cache entry. */
  550. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  551. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
  552. return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
  553. }
  554. /* Separate key cache entries for TX and RX */
  555. /* TX key goes at first index, RX key at +32. */
  556. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  557. if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
  558. /* TX MIC entry failed. No need to proceed further */
  559. ath_print(common, ATH_DBG_FATAL,
  560. "Setting TX MIC Key Failed\n");
  561. return 0;
  562. }
  563. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  564. /* XXX delete tx key on failure? */
  565. return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
  566. }
  567. static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
  568. {
  569. int i;
  570. for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
  571. if (test_bit(i, common->keymap) ||
  572. test_bit(i + 64, common->keymap))
  573. continue; /* At least one part of TKIP key allocated */
  574. if (common->splitmic &&
  575. (test_bit(i + 32, common->keymap) ||
  576. test_bit(i + 64 + 32, common->keymap)))
  577. continue; /* At least one part of TKIP key allocated */
  578. /* Found a free slot for a TKIP key */
  579. return i;
  580. }
  581. return -1;
  582. }
  583. static int ath_reserve_key_cache_slot(struct ath_common *common)
  584. {
  585. int i;
  586. /* First, try to find slots that would not be available for TKIP. */
  587. if (common->splitmic) {
  588. for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
  589. if (!test_bit(i, common->keymap) &&
  590. (test_bit(i + 32, common->keymap) ||
  591. test_bit(i + 64, common->keymap) ||
  592. test_bit(i + 64 + 32, common->keymap)))
  593. return i;
  594. if (!test_bit(i + 32, common->keymap) &&
  595. (test_bit(i, common->keymap) ||
  596. test_bit(i + 64, common->keymap) ||
  597. test_bit(i + 64 + 32, common->keymap)))
  598. return i + 32;
  599. if (!test_bit(i + 64, common->keymap) &&
  600. (test_bit(i , common->keymap) ||
  601. test_bit(i + 32, common->keymap) ||
  602. test_bit(i + 64 + 32, common->keymap)))
  603. return i + 64;
  604. if (!test_bit(i + 64 + 32, common->keymap) &&
  605. (test_bit(i, common->keymap) ||
  606. test_bit(i + 32, common->keymap) ||
  607. test_bit(i + 64, common->keymap)))
  608. return i + 64 + 32;
  609. }
  610. } else {
  611. for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
  612. if (!test_bit(i, common->keymap) &&
  613. test_bit(i + 64, common->keymap))
  614. return i;
  615. if (test_bit(i, common->keymap) &&
  616. !test_bit(i + 64, common->keymap))
  617. return i + 64;
  618. }
  619. }
  620. /* No partially used TKIP slots, pick any available slot */
  621. for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
  622. /* Do not allow slots that could be needed for TKIP group keys
  623. * to be used. This limitation could be removed if we know that
  624. * TKIP will not be used. */
  625. if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
  626. continue;
  627. if (common->splitmic) {
  628. if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
  629. continue;
  630. if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
  631. continue;
  632. }
  633. if (!test_bit(i, common->keymap))
  634. return i; /* Found a free slot for a key */
  635. }
  636. /* No free slot found */
  637. return -1;
  638. }
  639. static int ath_key_config(struct ath_common *common,
  640. struct ieee80211_vif *vif,
  641. struct ieee80211_sta *sta,
  642. struct ieee80211_key_conf *key)
  643. {
  644. struct ath_hw *ah = common->ah;
  645. struct ath9k_keyval hk;
  646. const u8 *mac = NULL;
  647. u8 gmac[ETH_ALEN];
  648. int ret = 0;
  649. int idx;
  650. memset(&hk, 0, sizeof(hk));
  651. switch (key->alg) {
  652. case ALG_WEP:
  653. hk.kv_type = ATH9K_CIPHER_WEP;
  654. break;
  655. case ALG_TKIP:
  656. hk.kv_type = ATH9K_CIPHER_TKIP;
  657. break;
  658. case ALG_CCMP:
  659. hk.kv_type = ATH9K_CIPHER_AES_CCM;
  660. break;
  661. default:
  662. return -EOPNOTSUPP;
  663. }
  664. hk.kv_len = key->keylen;
  665. memcpy(hk.kv_val, key->key, key->keylen);
  666. if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  667. if (key->ap_addr) {
  668. /*
  669. * Group keys on hardware that supports multicast frame
  670. * key search use a mac that is the sender's address with
  671. * the high bit set instead of the app-specified address.
  672. */
  673. memcpy(gmac, key->ap_addr, ETH_ALEN);
  674. gmac[0] |= 0x80;
  675. mac = gmac;
  676. if (key->alg == ALG_TKIP)
  677. idx = ath_reserve_key_cache_slot_tkip(common);
  678. else
  679. idx = ath_reserve_key_cache_slot(common);
  680. if (idx < 0)
  681. mac = NULL; /* no free key cache entries */
  682. }
  683. if (!mac) {
  684. /* For now, use the default keys for broadcast keys. This may
  685. * need to change with virtual interfaces. */
  686. idx = key->keyidx;
  687. }
  688. } else if (key->keyidx) {
  689. if (WARN_ON(!sta))
  690. return -EOPNOTSUPP;
  691. mac = sta->addr;
  692. if (vif->type != NL80211_IFTYPE_AP) {
  693. /* Only keyidx 0 should be used with unicast key, but
  694. * allow this for client mode for now. */
  695. idx = key->keyidx;
  696. } else
  697. return -EIO;
  698. } else {
  699. if (WARN_ON(!sta))
  700. return -EOPNOTSUPP;
  701. mac = sta->addr;
  702. if (key->alg == ALG_TKIP)
  703. idx = ath_reserve_key_cache_slot_tkip(common);
  704. else
  705. idx = ath_reserve_key_cache_slot(common);
  706. if (idx < 0)
  707. return -ENOSPC; /* no free key cache entries */
  708. }
  709. if (key->alg == ALG_TKIP)
  710. ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
  711. vif->type == NL80211_IFTYPE_AP);
  712. else
  713. ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
  714. if (!ret)
  715. return -EIO;
  716. set_bit(idx, common->keymap);
  717. if (key->alg == ALG_TKIP) {
  718. set_bit(idx + 64, common->keymap);
  719. if (common->splitmic) {
  720. set_bit(idx + 32, common->keymap);
  721. set_bit(idx + 64 + 32, common->keymap);
  722. }
  723. }
  724. return idx;
  725. }
  726. static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
  727. {
  728. struct ath_hw *ah = common->ah;
  729. ath9k_hw_keyreset(ah, key->hw_key_idx);
  730. if (key->hw_key_idx < IEEE80211_WEP_NKID)
  731. return;
  732. clear_bit(key->hw_key_idx, common->keymap);
  733. if (key->alg != ALG_TKIP)
  734. return;
  735. clear_bit(key->hw_key_idx + 64, common->keymap);
  736. if (common->splitmic) {
  737. ath9k_hw_keyreset(ah, key->hw_key_idx + 32);
  738. clear_bit(key->hw_key_idx + 32, common->keymap);
  739. clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
  740. }
  741. }
  742. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  743. struct ieee80211_vif *vif,
  744. struct ieee80211_bss_conf *bss_conf)
  745. {
  746. struct ath_hw *ah = sc->sc_ah;
  747. struct ath_common *common = ath9k_hw_common(ah);
  748. if (bss_conf->assoc) {
  749. ath_print(common, ATH_DBG_CONFIG,
  750. "Bss Info ASSOC %d, bssid: %pM\n",
  751. bss_conf->aid, common->curbssid);
  752. /* New association, store aid */
  753. common->curaid = bss_conf->aid;
  754. ath9k_hw_write_associd(ah);
  755. /*
  756. * Request a re-configuration of Beacon related timers
  757. * on the receipt of the first Beacon frame (i.e.,
  758. * after time sync with the AP).
  759. */
  760. sc->ps_flags |= PS_BEACON_SYNC;
  761. /* Configure the beacon */
  762. ath_beacon_config(sc, vif);
  763. /* Reset rssi stats */
  764. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  765. ath_start_ani(common);
  766. } else {
  767. ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
  768. common->curaid = 0;
  769. /* Stop ANI */
  770. del_timer_sync(&common->ani.timer);
  771. }
  772. }
  773. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  774. {
  775. struct ath_hw *ah = sc->sc_ah;
  776. struct ath_common *common = ath9k_hw_common(ah);
  777. struct ieee80211_channel *channel = hw->conf.channel;
  778. int r;
  779. ath9k_ps_wakeup(sc);
  780. ath9k_hw_configpcipowersave(ah, 0, 0);
  781. if (!ah->curchan)
  782. ah->curchan = ath_get_curchannel(sc, sc->hw);
  783. spin_lock_bh(&sc->sc_resetlock);
  784. r = ath9k_hw_reset(ah, ah->curchan, false);
  785. if (r) {
  786. ath_print(common, ATH_DBG_FATAL,
  787. "Unable to reset channel (%u MHz), "
  788. "reset status %d\n",
  789. channel->center_freq, r);
  790. }
  791. spin_unlock_bh(&sc->sc_resetlock);
  792. ath_update_txpow(sc);
  793. if (ath_startrecv(sc) != 0) {
  794. ath_print(common, ATH_DBG_FATAL,
  795. "Unable to restart recv logic\n");
  796. return;
  797. }
  798. if (sc->sc_flags & SC_OP_BEACONS)
  799. ath_beacon_config(sc, NULL); /* restart beacons */
  800. /* Re-Enable interrupts */
  801. ath9k_hw_set_interrupts(ah, ah->imask);
  802. /* Enable LED */
  803. ath9k_hw_cfg_output(ah, ah->led_pin,
  804. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  805. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  806. ieee80211_wake_queues(hw);
  807. ath9k_ps_restore(sc);
  808. }
  809. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  810. {
  811. struct ath_hw *ah = sc->sc_ah;
  812. struct ieee80211_channel *channel = hw->conf.channel;
  813. int r;
  814. ath9k_ps_wakeup(sc);
  815. ieee80211_stop_queues(hw);
  816. /* Disable LED */
  817. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  818. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  819. /* Disable interrupts */
  820. ath9k_hw_set_interrupts(ah, 0);
  821. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  822. ath_stoprecv(sc); /* turn off frame recv */
  823. ath_flushrecv(sc); /* flush recv queue */
  824. if (!ah->curchan)
  825. ah->curchan = ath_get_curchannel(sc, hw);
  826. spin_lock_bh(&sc->sc_resetlock);
  827. r = ath9k_hw_reset(ah, ah->curchan, false);
  828. if (r) {
  829. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  830. "Unable to reset channel (%u MHz), "
  831. "reset status %d\n",
  832. channel->center_freq, r);
  833. }
  834. spin_unlock_bh(&sc->sc_resetlock);
  835. ath9k_hw_phy_disable(ah);
  836. ath9k_hw_configpcipowersave(ah, 1, 1);
  837. ath9k_ps_restore(sc);
  838. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  839. }
  840. int ath_reset(struct ath_softc *sc, bool retry_tx)
  841. {
  842. struct ath_hw *ah = sc->sc_ah;
  843. struct ath_common *common = ath9k_hw_common(ah);
  844. struct ieee80211_hw *hw = sc->hw;
  845. int r;
  846. /* Stop ANI */
  847. del_timer_sync(&common->ani.timer);
  848. ieee80211_stop_queues(hw);
  849. ath9k_hw_set_interrupts(ah, 0);
  850. ath_drain_all_txq(sc, retry_tx);
  851. ath_stoprecv(sc);
  852. ath_flushrecv(sc);
  853. spin_lock_bh(&sc->sc_resetlock);
  854. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
  855. if (r)
  856. ath_print(common, ATH_DBG_FATAL,
  857. "Unable to reset hardware; reset status %d\n", r);
  858. spin_unlock_bh(&sc->sc_resetlock);
  859. if (ath_startrecv(sc) != 0)
  860. ath_print(common, ATH_DBG_FATAL,
  861. "Unable to start recv logic\n");
  862. /*
  863. * We may be doing a reset in response to a request
  864. * that changes the channel so update any state that
  865. * might change as a result.
  866. */
  867. ath_cache_conf_rate(sc, &hw->conf);
  868. ath_update_txpow(sc);
  869. if (sc->sc_flags & SC_OP_BEACONS)
  870. ath_beacon_config(sc, NULL); /* restart beacons */
  871. ath9k_hw_set_interrupts(ah, ah->imask);
  872. if (retry_tx) {
  873. int i;
  874. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  875. if (ATH_TXQ_SETUP(sc, i)) {
  876. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  877. ath_txq_schedule(sc, &sc->tx.txq[i]);
  878. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  879. }
  880. }
  881. }
  882. ieee80211_wake_queues(hw);
  883. /* Start ANI */
  884. ath_start_ani(common);
  885. return r;
  886. }
  887. int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
  888. {
  889. int qnum;
  890. switch (queue) {
  891. case 0:
  892. qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
  893. break;
  894. case 1:
  895. qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
  896. break;
  897. case 2:
  898. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
  899. break;
  900. case 3:
  901. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
  902. break;
  903. default:
  904. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
  905. break;
  906. }
  907. return qnum;
  908. }
  909. int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
  910. {
  911. int qnum;
  912. switch (queue) {
  913. case ATH9K_WME_AC_VO:
  914. qnum = 0;
  915. break;
  916. case ATH9K_WME_AC_VI:
  917. qnum = 1;
  918. break;
  919. case ATH9K_WME_AC_BE:
  920. qnum = 2;
  921. break;
  922. case ATH9K_WME_AC_BK:
  923. qnum = 3;
  924. break;
  925. default:
  926. qnum = -1;
  927. break;
  928. }
  929. return qnum;
  930. }
  931. /* XXX: Remove me once we don't depend on ath9k_channel for all
  932. * this redundant data */
  933. void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
  934. struct ath9k_channel *ichan)
  935. {
  936. struct ieee80211_channel *chan = hw->conf.channel;
  937. struct ieee80211_conf *conf = &hw->conf;
  938. ichan->channel = chan->center_freq;
  939. ichan->chan = chan;
  940. if (chan->band == IEEE80211_BAND_2GHZ) {
  941. ichan->chanmode = CHANNEL_G;
  942. ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
  943. } else {
  944. ichan->chanmode = CHANNEL_A;
  945. ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
  946. }
  947. if (conf_is_ht(conf))
  948. ichan->chanmode = ath_get_extchanmode(sc, chan,
  949. conf->channel_type);
  950. }
  951. /**********************/
  952. /* mac80211 callbacks */
  953. /**********************/
  954. static int ath9k_start(struct ieee80211_hw *hw)
  955. {
  956. struct ath_wiphy *aphy = hw->priv;
  957. struct ath_softc *sc = aphy->sc;
  958. struct ath_hw *ah = sc->sc_ah;
  959. struct ath_common *common = ath9k_hw_common(ah);
  960. struct ieee80211_channel *curchan = hw->conf.channel;
  961. struct ath9k_channel *init_channel;
  962. int r;
  963. ath_print(common, ATH_DBG_CONFIG,
  964. "Starting driver with initial channel: %d MHz\n",
  965. curchan->center_freq);
  966. mutex_lock(&sc->mutex);
  967. if (ath9k_wiphy_started(sc)) {
  968. if (sc->chan_idx == curchan->hw_value) {
  969. /*
  970. * Already on the operational channel, the new wiphy
  971. * can be marked active.
  972. */
  973. aphy->state = ATH_WIPHY_ACTIVE;
  974. ieee80211_wake_queues(hw);
  975. } else {
  976. /*
  977. * Another wiphy is on another channel, start the new
  978. * wiphy in paused state.
  979. */
  980. aphy->state = ATH_WIPHY_PAUSED;
  981. ieee80211_stop_queues(hw);
  982. }
  983. mutex_unlock(&sc->mutex);
  984. return 0;
  985. }
  986. aphy->state = ATH_WIPHY_ACTIVE;
  987. /* setup initial channel */
  988. sc->chan_idx = curchan->hw_value;
  989. init_channel = ath_get_curchannel(sc, hw);
  990. /* Reset SERDES registers */
  991. ath9k_hw_configpcipowersave(ah, 0, 0);
  992. /*
  993. * The basic interface to setting the hardware in a good
  994. * state is ``reset''. On return the hardware is known to
  995. * be powered up and with interrupts disabled. This must
  996. * be followed by initialization of the appropriate bits
  997. * and then setup of the interrupt mask.
  998. */
  999. spin_lock_bh(&sc->sc_resetlock);
  1000. r = ath9k_hw_reset(ah, init_channel, false);
  1001. if (r) {
  1002. ath_print(common, ATH_DBG_FATAL,
  1003. "Unable to reset hardware; reset status %d "
  1004. "(freq %u MHz)\n", r,
  1005. curchan->center_freq);
  1006. spin_unlock_bh(&sc->sc_resetlock);
  1007. goto mutex_unlock;
  1008. }
  1009. spin_unlock_bh(&sc->sc_resetlock);
  1010. /*
  1011. * This is needed only to setup initial state
  1012. * but it's best done after a reset.
  1013. */
  1014. ath_update_txpow(sc);
  1015. /*
  1016. * Setup the hardware after reset:
  1017. * The receive engine is set going.
  1018. * Frame transmit is handled entirely
  1019. * in the frame output path; there's nothing to do
  1020. * here except setup the interrupt mask.
  1021. */
  1022. if (ath_startrecv(sc) != 0) {
  1023. ath_print(common, ATH_DBG_FATAL,
  1024. "Unable to start recv logic\n");
  1025. r = -EIO;
  1026. goto mutex_unlock;
  1027. }
  1028. /* Setup our intr mask. */
  1029. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  1030. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  1031. ATH9K_INT_GLOBAL;
  1032. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  1033. ah->imask |= ATH9K_INT_RXHP | ATH9K_INT_RXLP;
  1034. else
  1035. ah->imask |= ATH9K_INT_RX;
  1036. if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
  1037. ah->imask |= ATH9K_INT_GTT;
  1038. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  1039. ah->imask |= ATH9K_INT_CST;
  1040. ath_cache_conf_rate(sc, &hw->conf);
  1041. sc->sc_flags &= ~SC_OP_INVALID;
  1042. /* Disable BMISS interrupt when we're not associated */
  1043. ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  1044. ath9k_hw_set_interrupts(ah, ah->imask);
  1045. ieee80211_wake_queues(hw);
  1046. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  1047. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  1048. !ah->btcoex_hw.enabled) {
  1049. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  1050. AR_STOMP_LOW_WLAN_WGHT);
  1051. ath9k_hw_btcoex_enable(ah);
  1052. if (common->bus_ops->bt_coex_prep)
  1053. common->bus_ops->bt_coex_prep(common);
  1054. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1055. ath9k_btcoex_timer_resume(sc);
  1056. }
  1057. mutex_unlock:
  1058. mutex_unlock(&sc->mutex);
  1059. return r;
  1060. }
  1061. static int ath9k_tx(struct ieee80211_hw *hw,
  1062. struct sk_buff *skb)
  1063. {
  1064. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1065. struct ath_wiphy *aphy = hw->priv;
  1066. struct ath_softc *sc = aphy->sc;
  1067. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1068. struct ath_tx_control txctl;
  1069. int padpos, padsize;
  1070. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  1071. if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
  1072. ath_print(common, ATH_DBG_XMIT,
  1073. "ath9k: %s: TX in unexpected wiphy state "
  1074. "%d\n", wiphy_name(hw->wiphy), aphy->state);
  1075. goto exit;
  1076. }
  1077. if (sc->ps_enabled) {
  1078. /*
  1079. * mac80211 does not set PM field for normal data frames, so we
  1080. * need to update that based on the current PS mode.
  1081. */
  1082. if (ieee80211_is_data(hdr->frame_control) &&
  1083. !ieee80211_is_nullfunc(hdr->frame_control) &&
  1084. !ieee80211_has_pm(hdr->frame_control)) {
  1085. ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
  1086. "while in PS mode\n");
  1087. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  1088. }
  1089. }
  1090. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  1091. /*
  1092. * We are using PS-Poll and mac80211 can request TX while in
  1093. * power save mode. Need to wake up hardware for the TX to be
  1094. * completed and if needed, also for RX of buffered frames.
  1095. */
  1096. ath9k_ps_wakeup(sc);
  1097. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1098. if (ieee80211_is_pspoll(hdr->frame_control)) {
  1099. ath_print(common, ATH_DBG_PS,
  1100. "Sending PS-Poll to pick a buffered frame\n");
  1101. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  1102. } else {
  1103. ath_print(common, ATH_DBG_PS,
  1104. "Wake up to complete TX\n");
  1105. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  1106. }
  1107. /*
  1108. * The actual restore operation will happen only after
  1109. * the sc_flags bit is cleared. We are just dropping
  1110. * the ps_usecount here.
  1111. */
  1112. ath9k_ps_restore(sc);
  1113. }
  1114. memset(&txctl, 0, sizeof(struct ath_tx_control));
  1115. /*
  1116. * As a temporary workaround, assign seq# here; this will likely need
  1117. * to be cleaned up to work better with Beacon transmission and virtual
  1118. * BSSes.
  1119. */
  1120. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1121. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  1122. sc->tx.seq_no += 0x10;
  1123. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1124. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1125. }
  1126. /* Add the padding after the header if this is not already done */
  1127. padpos = ath9k_cmn_padpos(hdr->frame_control);
  1128. padsize = padpos & 3;
  1129. if (padsize && skb->len>padpos) {
  1130. if (skb_headroom(skb) < padsize)
  1131. return -1;
  1132. skb_push(skb, padsize);
  1133. memmove(skb->data, skb->data + padsize, padpos);
  1134. }
  1135. /* Check if a tx queue is available */
  1136. txctl.txq = ath_test_get_txq(sc, skb);
  1137. if (!txctl.txq)
  1138. goto exit;
  1139. ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  1140. if (ath_tx_start(hw, skb, &txctl) != 0) {
  1141. ath_print(common, ATH_DBG_XMIT, "TX failed\n");
  1142. goto exit;
  1143. }
  1144. return 0;
  1145. exit:
  1146. dev_kfree_skb_any(skb);
  1147. return 0;
  1148. }
  1149. static void ath9k_stop(struct ieee80211_hw *hw)
  1150. {
  1151. struct ath_wiphy *aphy = hw->priv;
  1152. struct ath_softc *sc = aphy->sc;
  1153. struct ath_hw *ah = sc->sc_ah;
  1154. struct ath_common *common = ath9k_hw_common(ah);
  1155. mutex_lock(&sc->mutex);
  1156. aphy->state = ATH_WIPHY_INACTIVE;
  1157. cancel_delayed_work_sync(&sc->ath_led_blink_work);
  1158. cancel_delayed_work_sync(&sc->tx_complete_work);
  1159. if (!sc->num_sec_wiphy) {
  1160. cancel_delayed_work_sync(&sc->wiphy_work);
  1161. cancel_work_sync(&sc->chan_work);
  1162. }
  1163. if (sc->sc_flags & SC_OP_INVALID) {
  1164. ath_print(common, ATH_DBG_ANY, "Device not present\n");
  1165. mutex_unlock(&sc->mutex);
  1166. return;
  1167. }
  1168. if (ath9k_wiphy_started(sc)) {
  1169. mutex_unlock(&sc->mutex);
  1170. return; /* another wiphy still in use */
  1171. }
  1172. /* Ensure HW is awake when we try to shut it down. */
  1173. ath9k_ps_wakeup(sc);
  1174. if (ah->btcoex_hw.enabled) {
  1175. ath9k_hw_btcoex_disable(ah);
  1176. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1177. ath9k_btcoex_timer_pause(sc);
  1178. }
  1179. /* make sure h/w will not generate any interrupt
  1180. * before setting the invalid flag. */
  1181. ath9k_hw_set_interrupts(ah, 0);
  1182. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1183. ath_drain_all_txq(sc, false);
  1184. ath_stoprecv(sc);
  1185. ath9k_hw_phy_disable(ah);
  1186. } else
  1187. sc->rx.rxlink = NULL;
  1188. /* disable HAL and put h/w to sleep */
  1189. ath9k_hw_disable(ah);
  1190. ath9k_hw_configpcipowersave(ah, 1, 1);
  1191. ath9k_ps_restore(sc);
  1192. /* Finally, put the chip in FULL SLEEP mode */
  1193. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  1194. sc->sc_flags |= SC_OP_INVALID;
  1195. mutex_unlock(&sc->mutex);
  1196. ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
  1197. }
  1198. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1199. struct ieee80211_vif *vif)
  1200. {
  1201. struct ath_wiphy *aphy = hw->priv;
  1202. struct ath_softc *sc = aphy->sc;
  1203. struct ath_hw *ah = sc->sc_ah;
  1204. struct ath_common *common = ath9k_hw_common(ah);
  1205. struct ath_vif *avp = (void *)vif->drv_priv;
  1206. enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
  1207. int ret = 0;
  1208. mutex_lock(&sc->mutex);
  1209. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
  1210. sc->nvifs > 0) {
  1211. ret = -ENOBUFS;
  1212. goto out;
  1213. }
  1214. switch (vif->type) {
  1215. case NL80211_IFTYPE_STATION:
  1216. ic_opmode = NL80211_IFTYPE_STATION;
  1217. break;
  1218. case NL80211_IFTYPE_ADHOC:
  1219. case NL80211_IFTYPE_AP:
  1220. case NL80211_IFTYPE_MESH_POINT:
  1221. if (sc->nbcnvifs >= ATH_BCBUF) {
  1222. ret = -ENOBUFS;
  1223. goto out;
  1224. }
  1225. ic_opmode = vif->type;
  1226. break;
  1227. default:
  1228. ath_print(common, ATH_DBG_FATAL,
  1229. "Interface type %d not yet supported\n", vif->type);
  1230. ret = -EOPNOTSUPP;
  1231. goto out;
  1232. }
  1233. ath_print(common, ATH_DBG_CONFIG,
  1234. "Attach a VIF of type: %d\n", ic_opmode);
  1235. /* Set the VIF opmode */
  1236. avp->av_opmode = ic_opmode;
  1237. avp->av_bslot = -1;
  1238. sc->nvifs++;
  1239. if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
  1240. ath9k_set_bssid_mask(hw);
  1241. if (sc->nvifs > 1)
  1242. goto out; /* skip global settings for secondary vif */
  1243. if (ic_opmode == NL80211_IFTYPE_AP) {
  1244. ath9k_hw_set_tsfadjust(ah, 1);
  1245. sc->sc_flags |= SC_OP_TSF_RESET;
  1246. }
  1247. /* Set the device opmode */
  1248. ah->opmode = ic_opmode;
  1249. /*
  1250. * Enable MIB interrupts when there are hardware phy counters.
  1251. * Note we only do this (at the moment) for station mode.
  1252. */
  1253. if ((vif->type == NL80211_IFTYPE_STATION) ||
  1254. (vif->type == NL80211_IFTYPE_ADHOC) ||
  1255. (vif->type == NL80211_IFTYPE_MESH_POINT)) {
  1256. if (ah->config.enable_ani)
  1257. ah->imask |= ATH9K_INT_MIB;
  1258. ah->imask |= ATH9K_INT_TSFOOR;
  1259. }
  1260. ath9k_hw_set_interrupts(ah, ah->imask);
  1261. if (vif->type == NL80211_IFTYPE_AP ||
  1262. vif->type == NL80211_IFTYPE_ADHOC ||
  1263. vif->type == NL80211_IFTYPE_MONITOR)
  1264. ath_start_ani(common);
  1265. out:
  1266. mutex_unlock(&sc->mutex);
  1267. return ret;
  1268. }
  1269. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1270. struct ieee80211_vif *vif)
  1271. {
  1272. struct ath_wiphy *aphy = hw->priv;
  1273. struct ath_softc *sc = aphy->sc;
  1274. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1275. struct ath_vif *avp = (void *)vif->drv_priv;
  1276. int i;
  1277. ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1278. mutex_lock(&sc->mutex);
  1279. /* Stop ANI */
  1280. del_timer_sync(&common->ani.timer);
  1281. /* Reclaim beacon resources */
  1282. if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
  1283. (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1284. (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
  1285. ath9k_ps_wakeup(sc);
  1286. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1287. ath9k_ps_restore(sc);
  1288. }
  1289. ath_beacon_return(sc, avp);
  1290. sc->sc_flags &= ~SC_OP_BEACONS;
  1291. for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
  1292. if (sc->beacon.bslot[i] == vif) {
  1293. printk(KERN_DEBUG "%s: vif had allocated beacon "
  1294. "slot\n", __func__);
  1295. sc->beacon.bslot[i] = NULL;
  1296. sc->beacon.bslot_aphy[i] = NULL;
  1297. }
  1298. }
  1299. sc->nvifs--;
  1300. mutex_unlock(&sc->mutex);
  1301. }
  1302. void ath9k_enable_ps(struct ath_softc *sc)
  1303. {
  1304. struct ath_hw *ah = sc->sc_ah;
  1305. sc->ps_enabled = true;
  1306. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1307. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1308. ah->imask |= ATH9K_INT_TIM_TIMER;
  1309. ath9k_hw_set_interrupts(ah, ah->imask);
  1310. }
  1311. }
  1312. ath9k_hw_setrxabort(ah, 1);
  1313. }
  1314. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1315. {
  1316. struct ath_wiphy *aphy = hw->priv;
  1317. struct ath_softc *sc = aphy->sc;
  1318. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1319. struct ieee80211_conf *conf = &hw->conf;
  1320. struct ath_hw *ah = sc->sc_ah;
  1321. bool disable_radio;
  1322. mutex_lock(&sc->mutex);
  1323. /*
  1324. * Leave this as the first check because we need to turn on the
  1325. * radio if it was disabled before prior to processing the rest
  1326. * of the changes. Likewise we must only disable the radio towards
  1327. * the end.
  1328. */
  1329. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1330. bool enable_radio;
  1331. bool all_wiphys_idle;
  1332. bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1333. spin_lock_bh(&sc->wiphy_lock);
  1334. all_wiphys_idle = ath9k_all_wiphys_idle(sc);
  1335. ath9k_set_wiphy_idle(aphy, idle);
  1336. enable_radio = (!idle && all_wiphys_idle);
  1337. /*
  1338. * After we unlock here its possible another wiphy
  1339. * can be re-renabled so to account for that we will
  1340. * only disable the radio toward the end of this routine
  1341. * if by then all wiphys are still idle.
  1342. */
  1343. spin_unlock_bh(&sc->wiphy_lock);
  1344. if (enable_radio) {
  1345. sc->ps_idle = false;
  1346. ath_radio_enable(sc, hw);
  1347. ath_print(common, ATH_DBG_CONFIG,
  1348. "not-idle: enabling radio\n");
  1349. }
  1350. }
  1351. /*
  1352. * We just prepare to enable PS. We have to wait until our AP has
  1353. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1354. * those ACKs and end up retransmitting the same null data frames.
  1355. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1356. */
  1357. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1358. if (conf->flags & IEEE80211_CONF_PS) {
  1359. sc->ps_flags |= PS_ENABLED;
  1360. /*
  1361. * At this point we know hardware has received an ACK
  1362. * of a previously sent null data frame.
  1363. */
  1364. if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
  1365. sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
  1366. ath9k_enable_ps(sc);
  1367. }
  1368. } else {
  1369. sc->ps_enabled = false;
  1370. sc->ps_flags &= ~(PS_ENABLED |
  1371. PS_NULLFUNC_COMPLETED);
  1372. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  1373. if (!(ah->caps.hw_caps &
  1374. ATH9K_HW_CAP_AUTOSLEEP)) {
  1375. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1376. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1377. PS_WAIT_FOR_CAB |
  1378. PS_WAIT_FOR_PSPOLL_DATA |
  1379. PS_WAIT_FOR_TX_ACK);
  1380. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1381. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1382. ath9k_hw_set_interrupts(sc->sc_ah,
  1383. ah->imask);
  1384. }
  1385. }
  1386. }
  1387. }
  1388. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1389. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1390. ath_print(common, ATH_DBG_CONFIG,
  1391. "HW opmode set to Monitor mode\n");
  1392. sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
  1393. }
  1394. }
  1395. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1396. struct ieee80211_channel *curchan = hw->conf.channel;
  1397. int pos = curchan->hw_value;
  1398. aphy->chan_idx = pos;
  1399. aphy->chan_is_ht = conf_is_ht(conf);
  1400. if (aphy->state == ATH_WIPHY_SCAN ||
  1401. aphy->state == ATH_WIPHY_ACTIVE)
  1402. ath9k_wiphy_pause_all_forced(sc, aphy);
  1403. else {
  1404. /*
  1405. * Do not change operational channel based on a paused
  1406. * wiphy changes.
  1407. */
  1408. goto skip_chan_change;
  1409. }
  1410. ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
  1411. curchan->center_freq);
  1412. /* XXX: remove me eventualy */
  1413. ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
  1414. ath_update_chainmask(sc, conf_is_ht(conf));
  1415. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1416. ath_print(common, ATH_DBG_FATAL,
  1417. "Unable to set channel\n");
  1418. mutex_unlock(&sc->mutex);
  1419. return -EINVAL;
  1420. }
  1421. }
  1422. skip_chan_change:
  1423. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1424. sc->config.txpowlimit = 2 * conf->power_level;
  1425. ath_update_txpow(sc);
  1426. }
  1427. spin_lock_bh(&sc->wiphy_lock);
  1428. disable_radio = ath9k_all_wiphys_idle(sc);
  1429. spin_unlock_bh(&sc->wiphy_lock);
  1430. if (disable_radio) {
  1431. ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1432. sc->ps_idle = true;
  1433. ath_radio_disable(sc, hw);
  1434. }
  1435. mutex_unlock(&sc->mutex);
  1436. return 0;
  1437. }
  1438. #define SUPPORTED_FILTERS \
  1439. (FIF_PROMISC_IN_BSS | \
  1440. FIF_ALLMULTI | \
  1441. FIF_CONTROL | \
  1442. FIF_PSPOLL | \
  1443. FIF_OTHER_BSS | \
  1444. FIF_BCN_PRBRESP_PROMISC | \
  1445. FIF_FCSFAIL)
  1446. /* FIXME: sc->sc_full_reset ? */
  1447. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1448. unsigned int changed_flags,
  1449. unsigned int *total_flags,
  1450. u64 multicast)
  1451. {
  1452. struct ath_wiphy *aphy = hw->priv;
  1453. struct ath_softc *sc = aphy->sc;
  1454. u32 rfilt;
  1455. changed_flags &= SUPPORTED_FILTERS;
  1456. *total_flags &= SUPPORTED_FILTERS;
  1457. sc->rx.rxfilter = *total_flags;
  1458. ath9k_ps_wakeup(sc);
  1459. rfilt = ath_calcrxfilter(sc);
  1460. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1461. ath9k_ps_restore(sc);
  1462. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1463. "Set HW RX filter: 0x%x\n", rfilt);
  1464. }
  1465. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1466. struct ieee80211_vif *vif,
  1467. struct ieee80211_sta *sta)
  1468. {
  1469. struct ath_wiphy *aphy = hw->priv;
  1470. struct ath_softc *sc = aphy->sc;
  1471. ath_node_attach(sc, sta);
  1472. return 0;
  1473. }
  1474. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1475. struct ieee80211_vif *vif,
  1476. struct ieee80211_sta *sta)
  1477. {
  1478. struct ath_wiphy *aphy = hw->priv;
  1479. struct ath_softc *sc = aphy->sc;
  1480. ath_node_detach(sc, sta);
  1481. return 0;
  1482. }
  1483. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1484. const struct ieee80211_tx_queue_params *params)
  1485. {
  1486. struct ath_wiphy *aphy = hw->priv;
  1487. struct ath_softc *sc = aphy->sc;
  1488. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1489. struct ath9k_tx_queue_info qi;
  1490. int ret = 0, qnum;
  1491. if (queue >= WME_NUM_AC)
  1492. return 0;
  1493. mutex_lock(&sc->mutex);
  1494. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1495. qi.tqi_aifs = params->aifs;
  1496. qi.tqi_cwmin = params->cw_min;
  1497. qi.tqi_cwmax = params->cw_max;
  1498. qi.tqi_burstTime = params->txop;
  1499. qnum = ath_get_hal_qnum(queue, sc);
  1500. ath_print(common, ATH_DBG_CONFIG,
  1501. "Configure tx [queue/halq] [%d/%d], "
  1502. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1503. queue, qnum, params->aifs, params->cw_min,
  1504. params->cw_max, params->txop);
  1505. ret = ath_txq_update(sc, qnum, &qi);
  1506. if (ret)
  1507. ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
  1508. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1509. if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret)
  1510. ath_beaconq_config(sc);
  1511. mutex_unlock(&sc->mutex);
  1512. return ret;
  1513. }
  1514. static int ath9k_set_key(struct ieee80211_hw *hw,
  1515. enum set_key_cmd cmd,
  1516. struct ieee80211_vif *vif,
  1517. struct ieee80211_sta *sta,
  1518. struct ieee80211_key_conf *key)
  1519. {
  1520. struct ath_wiphy *aphy = hw->priv;
  1521. struct ath_softc *sc = aphy->sc;
  1522. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1523. int ret = 0;
  1524. if (modparam_nohwcrypt)
  1525. return -ENOSPC;
  1526. mutex_lock(&sc->mutex);
  1527. ath9k_ps_wakeup(sc);
  1528. ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1529. switch (cmd) {
  1530. case SET_KEY:
  1531. ret = ath_key_config(common, vif, sta, key);
  1532. if (ret >= 0) {
  1533. key->hw_key_idx = ret;
  1534. /* push IV and Michael MIC generation to stack */
  1535. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1536. if (key->alg == ALG_TKIP)
  1537. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1538. if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
  1539. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1540. ret = 0;
  1541. }
  1542. break;
  1543. case DISABLE_KEY:
  1544. ath_key_delete(common, key);
  1545. break;
  1546. default:
  1547. ret = -EINVAL;
  1548. }
  1549. ath9k_ps_restore(sc);
  1550. mutex_unlock(&sc->mutex);
  1551. return ret;
  1552. }
  1553. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1554. struct ieee80211_vif *vif,
  1555. struct ieee80211_bss_conf *bss_conf,
  1556. u32 changed)
  1557. {
  1558. struct ath_wiphy *aphy = hw->priv;
  1559. struct ath_softc *sc = aphy->sc;
  1560. struct ath_hw *ah = sc->sc_ah;
  1561. struct ath_common *common = ath9k_hw_common(ah);
  1562. struct ath_vif *avp = (void *)vif->drv_priv;
  1563. int slottime;
  1564. int error;
  1565. mutex_lock(&sc->mutex);
  1566. if (changed & BSS_CHANGED_BSSID) {
  1567. /* Set BSSID */
  1568. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1569. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1570. common->curaid = 0;
  1571. ath9k_hw_write_associd(ah);
  1572. /* Set aggregation protection mode parameters */
  1573. sc->config.ath_aggr_prot = 0;
  1574. /* Only legacy IBSS for now */
  1575. if (vif->type == NL80211_IFTYPE_ADHOC)
  1576. ath_update_chainmask(sc, 0);
  1577. ath_print(common, ATH_DBG_CONFIG,
  1578. "BSSID: %pM aid: 0x%x\n",
  1579. common->curbssid, common->curaid);
  1580. /* need to reconfigure the beacon */
  1581. sc->sc_flags &= ~SC_OP_BEACONS ;
  1582. }
  1583. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1584. if ((changed & BSS_CHANGED_BEACON) ||
  1585. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1586. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1587. error = ath_beacon_alloc(aphy, vif);
  1588. if (!error)
  1589. ath_beacon_config(sc, vif);
  1590. }
  1591. if (changed & BSS_CHANGED_ERP_SLOT) {
  1592. if (bss_conf->use_short_slot)
  1593. slottime = 9;
  1594. else
  1595. slottime = 20;
  1596. if (vif->type == NL80211_IFTYPE_AP) {
  1597. /*
  1598. * Defer update, so that connected stations can adjust
  1599. * their settings at the same time.
  1600. * See beacon.c for more details
  1601. */
  1602. sc->beacon.slottime = slottime;
  1603. sc->beacon.updateslot = UPDATE;
  1604. } else {
  1605. ah->slottime = slottime;
  1606. ath9k_hw_init_global_settings(ah);
  1607. }
  1608. }
  1609. /* Disable transmission of beacons */
  1610. if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
  1611. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1612. if (changed & BSS_CHANGED_BEACON_INT) {
  1613. sc->beacon_interval = bss_conf->beacon_int;
  1614. /*
  1615. * In case of AP mode, the HW TSF has to be reset
  1616. * when the beacon interval changes.
  1617. */
  1618. if (vif->type == NL80211_IFTYPE_AP) {
  1619. sc->sc_flags |= SC_OP_TSF_RESET;
  1620. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1621. error = ath_beacon_alloc(aphy, vif);
  1622. if (!error)
  1623. ath_beacon_config(sc, vif);
  1624. } else {
  1625. ath_beacon_config(sc, vif);
  1626. }
  1627. }
  1628. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1629. ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1630. bss_conf->use_short_preamble);
  1631. if (bss_conf->use_short_preamble)
  1632. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1633. else
  1634. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1635. }
  1636. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1637. ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1638. bss_conf->use_cts_prot);
  1639. if (bss_conf->use_cts_prot &&
  1640. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1641. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1642. else
  1643. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1644. }
  1645. if (changed & BSS_CHANGED_ASSOC) {
  1646. ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
  1647. bss_conf->assoc);
  1648. ath9k_bss_assoc_info(sc, vif, bss_conf);
  1649. }
  1650. mutex_unlock(&sc->mutex);
  1651. }
  1652. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1653. {
  1654. u64 tsf;
  1655. struct ath_wiphy *aphy = hw->priv;
  1656. struct ath_softc *sc = aphy->sc;
  1657. mutex_lock(&sc->mutex);
  1658. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1659. mutex_unlock(&sc->mutex);
  1660. return tsf;
  1661. }
  1662. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  1663. {
  1664. struct ath_wiphy *aphy = hw->priv;
  1665. struct ath_softc *sc = aphy->sc;
  1666. mutex_lock(&sc->mutex);
  1667. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1668. mutex_unlock(&sc->mutex);
  1669. }
  1670. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1671. {
  1672. struct ath_wiphy *aphy = hw->priv;
  1673. struct ath_softc *sc = aphy->sc;
  1674. mutex_lock(&sc->mutex);
  1675. ath9k_ps_wakeup(sc);
  1676. ath9k_hw_reset_tsf(sc->sc_ah);
  1677. ath9k_ps_restore(sc);
  1678. mutex_unlock(&sc->mutex);
  1679. }
  1680. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1681. struct ieee80211_vif *vif,
  1682. enum ieee80211_ampdu_mlme_action action,
  1683. struct ieee80211_sta *sta,
  1684. u16 tid, u16 *ssn)
  1685. {
  1686. struct ath_wiphy *aphy = hw->priv;
  1687. struct ath_softc *sc = aphy->sc;
  1688. int ret = 0;
  1689. switch (action) {
  1690. case IEEE80211_AMPDU_RX_START:
  1691. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1692. ret = -ENOTSUPP;
  1693. break;
  1694. case IEEE80211_AMPDU_RX_STOP:
  1695. break;
  1696. case IEEE80211_AMPDU_TX_START:
  1697. ath9k_ps_wakeup(sc);
  1698. ath_tx_aggr_start(sc, sta, tid, ssn);
  1699. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1700. ath9k_ps_restore(sc);
  1701. break;
  1702. case IEEE80211_AMPDU_TX_STOP:
  1703. ath9k_ps_wakeup(sc);
  1704. ath_tx_aggr_stop(sc, sta, tid);
  1705. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1706. ath9k_ps_restore(sc);
  1707. break;
  1708. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1709. ath9k_ps_wakeup(sc);
  1710. ath_tx_aggr_resume(sc, sta, tid);
  1711. ath9k_ps_restore(sc);
  1712. break;
  1713. default:
  1714. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  1715. "Unknown AMPDU action\n");
  1716. }
  1717. return ret;
  1718. }
  1719. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1720. {
  1721. struct ath_wiphy *aphy = hw->priv;
  1722. struct ath_softc *sc = aphy->sc;
  1723. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1724. mutex_lock(&sc->mutex);
  1725. if (ath9k_wiphy_scanning(sc)) {
  1726. printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
  1727. "same time\n");
  1728. /*
  1729. * Do not allow the concurrent scanning state for now. This
  1730. * could be improved with scanning control moved into ath9k.
  1731. */
  1732. mutex_unlock(&sc->mutex);
  1733. return;
  1734. }
  1735. aphy->state = ATH_WIPHY_SCAN;
  1736. ath9k_wiphy_pause_all_forced(sc, aphy);
  1737. sc->sc_flags |= SC_OP_SCANNING;
  1738. del_timer_sync(&common->ani.timer);
  1739. cancel_delayed_work_sync(&sc->tx_complete_work);
  1740. mutex_unlock(&sc->mutex);
  1741. }
  1742. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1743. {
  1744. struct ath_wiphy *aphy = hw->priv;
  1745. struct ath_softc *sc = aphy->sc;
  1746. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1747. mutex_lock(&sc->mutex);
  1748. aphy->state = ATH_WIPHY_ACTIVE;
  1749. sc->sc_flags &= ~SC_OP_SCANNING;
  1750. sc->sc_flags |= SC_OP_FULL_RESET;
  1751. ath_start_ani(common);
  1752. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  1753. ath_beacon_config(sc, NULL);
  1754. mutex_unlock(&sc->mutex);
  1755. }
  1756. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1757. {
  1758. struct ath_wiphy *aphy = hw->priv;
  1759. struct ath_softc *sc = aphy->sc;
  1760. struct ath_hw *ah = sc->sc_ah;
  1761. mutex_lock(&sc->mutex);
  1762. ah->coverage_class = coverage_class;
  1763. ath9k_hw_init_global_settings(ah);
  1764. mutex_unlock(&sc->mutex);
  1765. }
  1766. struct ieee80211_ops ath9k_ops = {
  1767. .tx = ath9k_tx,
  1768. .start = ath9k_start,
  1769. .stop = ath9k_stop,
  1770. .add_interface = ath9k_add_interface,
  1771. .remove_interface = ath9k_remove_interface,
  1772. .config = ath9k_config,
  1773. .configure_filter = ath9k_configure_filter,
  1774. .sta_add = ath9k_sta_add,
  1775. .sta_remove = ath9k_sta_remove,
  1776. .conf_tx = ath9k_conf_tx,
  1777. .bss_info_changed = ath9k_bss_info_changed,
  1778. .set_key = ath9k_set_key,
  1779. .get_tsf = ath9k_get_tsf,
  1780. .set_tsf = ath9k_set_tsf,
  1781. .reset_tsf = ath9k_reset_tsf,
  1782. .ampdu_action = ath9k_ampdu_action,
  1783. .sw_scan_start = ath9k_sw_scan_start,
  1784. .sw_scan_complete = ath9k_sw_scan_complete,
  1785. .rfkill_poll = ath9k_rfkill_poll_state,
  1786. .set_coverage_class = ath9k_set_coverage_class,
  1787. };