ssb.h 17 KB

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  1. #ifndef LINUX_SSB_H_
  2. #define LINUX_SSB_H_
  3. #include <linux/device.h>
  4. #include <linux/list.h>
  5. #include <linux/types.h>
  6. #include <linux/spinlock.h>
  7. #include <linux/pci.h>
  8. #include <linux/mod_devicetable.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/ssb/ssb_regs.h>
  11. struct pcmcia_device;
  12. struct ssb_bus;
  13. struct ssb_driver;
  14. struct ssb_sprom_core_pwr_info {
  15. u8 itssi_2g, itssi_5g;
  16. u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
  17. u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
  18. };
  19. struct ssb_sprom {
  20. u8 revision;
  21. u8 il0mac[6]; /* MAC address for 802.11b/g */
  22. u8 et0mac[6]; /* MAC address for Ethernet */
  23. u8 et1mac[6]; /* MAC address for 802.11a */
  24. u8 et0phyaddr; /* MII address for enet0 */
  25. u8 et1phyaddr; /* MII address for enet1 */
  26. u8 et0mdcport; /* MDIO for enet0 */
  27. u8 et1mdcport; /* MDIO for enet1 */
  28. u16 board_rev; /* Board revision number from SPROM. */
  29. u8 country_code; /* Country Code */
  30. char alpha2[2]; /* Country Code as two chars like EU or US */
  31. u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
  32. u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
  33. u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
  34. u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
  35. u16 pa0b0;
  36. u16 pa0b1;
  37. u16 pa0b2;
  38. u16 pa1b0;
  39. u16 pa1b1;
  40. u16 pa1b2;
  41. u16 pa1lob0;
  42. u16 pa1lob1;
  43. u16 pa1lob2;
  44. u16 pa1hib0;
  45. u16 pa1hib1;
  46. u16 pa1hib2;
  47. u8 gpio0; /* GPIO pin 0 */
  48. u8 gpio1; /* GPIO pin 1 */
  49. u8 gpio2; /* GPIO pin 2 */
  50. u8 gpio3; /* GPIO pin 3 */
  51. u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
  52. u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
  53. u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
  54. u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
  55. u8 itssi_a; /* Idle TSSI Target for A-PHY */
  56. u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
  57. u8 tri2g; /* 2.4GHz TX isolation */
  58. u8 tri5gl; /* 5.2GHz TX isolation */
  59. u8 tri5g; /* 5.3GHz TX isolation */
  60. u8 tri5gh; /* 5.8GHz TX isolation */
  61. u8 txpid2g[4]; /* 2GHz TX power index */
  62. u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
  63. u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
  64. u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
  65. s8 rxpo2g; /* 2GHz RX power offset */
  66. s8 rxpo5g; /* 5GHz RX power offset */
  67. u8 rssisav2g; /* 2GHz RSSI params */
  68. u8 rssismc2g;
  69. u8 rssismf2g;
  70. u8 bxa2g; /* 2GHz BX arch */
  71. u8 rssisav5g; /* 5GHz RSSI params */
  72. u8 rssismc5g;
  73. u8 rssismf5g;
  74. u8 bxa5g; /* 5GHz BX arch */
  75. u16 cck2gpo; /* CCK power offset */
  76. u32 ofdm2gpo; /* 2.4GHz OFDM power offset */
  77. u32 ofdm5glpo; /* 5.2GHz OFDM power offset */
  78. u32 ofdm5gpo; /* 5.3GHz OFDM power offset */
  79. u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */
  80. u16 boardflags_lo; /* Board flags (bits 0-15) */
  81. u16 boardflags_hi; /* Board flags (bits 16-31) */
  82. u16 boardflags2_lo; /* Board flags (bits 32-47) */
  83. u16 boardflags2_hi; /* Board flags (bits 48-63) */
  84. /* TODO store board flags in a single u64 */
  85. struct ssb_sprom_core_pwr_info core_pwr_info[4];
  86. /* Antenna gain values for up to 4 antennas
  87. * on each band. Values in dBm/4 (Q5.2). Negative gain means the
  88. * loss in the connectors is bigger than the gain. */
  89. struct {
  90. s8 a0, a1, a2, a3;
  91. } antenna_gain;
  92. struct {
  93. struct {
  94. u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
  95. } ghz2;
  96. struct {
  97. u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
  98. } ghz5;
  99. } fem;
  100. /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
  101. };
  102. /* Information about the PCB the circuitry is soldered on. */
  103. struct ssb_boardinfo {
  104. u16 vendor;
  105. u16 type;
  106. u8 rev;
  107. };
  108. struct ssb_device;
  109. /* Lowlevel read/write operations on the device MMIO.
  110. * Internal, don't use that outside of ssb. */
  111. struct ssb_bus_ops {
  112. u8 (*read8)(struct ssb_device *dev, u16 offset);
  113. u16 (*read16)(struct ssb_device *dev, u16 offset);
  114. u32 (*read32)(struct ssb_device *dev, u16 offset);
  115. void (*write8)(struct ssb_device *dev, u16 offset, u8 value);
  116. void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
  117. void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
  118. #ifdef CONFIG_SSB_BLOCKIO
  119. void (*block_read)(struct ssb_device *dev, void *buffer,
  120. size_t count, u16 offset, u8 reg_width);
  121. void (*block_write)(struct ssb_device *dev, const void *buffer,
  122. size_t count, u16 offset, u8 reg_width);
  123. #endif
  124. };
  125. /* Core-ID values. */
  126. #define SSB_DEV_CHIPCOMMON 0x800
  127. #define SSB_DEV_ILINE20 0x801
  128. #define SSB_DEV_SDRAM 0x803
  129. #define SSB_DEV_PCI 0x804
  130. #define SSB_DEV_MIPS 0x805
  131. #define SSB_DEV_ETHERNET 0x806
  132. #define SSB_DEV_V90 0x807
  133. #define SSB_DEV_USB11_HOSTDEV 0x808
  134. #define SSB_DEV_ADSL 0x809
  135. #define SSB_DEV_ILINE100 0x80A
  136. #define SSB_DEV_IPSEC 0x80B
  137. #define SSB_DEV_PCMCIA 0x80D
  138. #define SSB_DEV_INTERNAL_MEM 0x80E
  139. #define SSB_DEV_MEMC_SDRAM 0x80F
  140. #define SSB_DEV_EXTIF 0x811
  141. #define SSB_DEV_80211 0x812
  142. #define SSB_DEV_MIPS_3302 0x816
  143. #define SSB_DEV_USB11_HOST 0x817
  144. #define SSB_DEV_USB11_DEV 0x818
  145. #define SSB_DEV_USB20_HOST 0x819
  146. #define SSB_DEV_USB20_DEV 0x81A
  147. #define SSB_DEV_SDIO_HOST 0x81B
  148. #define SSB_DEV_ROBOSWITCH 0x81C
  149. #define SSB_DEV_PARA_ATA 0x81D
  150. #define SSB_DEV_SATA_XORDMA 0x81E
  151. #define SSB_DEV_ETHERNET_GBIT 0x81F
  152. #define SSB_DEV_PCIE 0x820
  153. #define SSB_DEV_MIMO_PHY 0x821
  154. #define SSB_DEV_SRAM_CTRLR 0x822
  155. #define SSB_DEV_MINI_MACPHY 0x823
  156. #define SSB_DEV_ARM_1176 0x824
  157. #define SSB_DEV_ARM_7TDMI 0x825
  158. /* Vendor-ID values */
  159. #define SSB_VENDOR_BROADCOM 0x4243
  160. /* Some kernel subsystems poke with dev->drvdata, so we must use the
  161. * following ugly workaround to get from struct device to struct ssb_device */
  162. struct __ssb_dev_wrapper {
  163. struct device dev;
  164. struct ssb_device *sdev;
  165. };
  166. struct ssb_device {
  167. /* Having a copy of the ops pointer in each dev struct
  168. * is an optimization. */
  169. const struct ssb_bus_ops *ops;
  170. struct device *dev, *dma_dev;
  171. struct ssb_bus *bus;
  172. struct ssb_device_id id;
  173. u8 core_index;
  174. unsigned int irq;
  175. /* Internal-only stuff follows. */
  176. void *drvdata; /* Per-device data */
  177. void *devtypedata; /* Per-devicetype (eg 802.11) data */
  178. };
  179. /* Go from struct device to struct ssb_device. */
  180. static inline
  181. struct ssb_device * dev_to_ssb_dev(struct device *dev)
  182. {
  183. struct __ssb_dev_wrapper *wrap;
  184. wrap = container_of(dev, struct __ssb_dev_wrapper, dev);
  185. return wrap->sdev;
  186. }
  187. /* Device specific user data */
  188. static inline
  189. void ssb_set_drvdata(struct ssb_device *dev, void *data)
  190. {
  191. dev->drvdata = data;
  192. }
  193. static inline
  194. void * ssb_get_drvdata(struct ssb_device *dev)
  195. {
  196. return dev->drvdata;
  197. }
  198. /* Devicetype specific user data. This is per device-type (not per device) */
  199. void ssb_set_devtypedata(struct ssb_device *dev, void *data);
  200. static inline
  201. void * ssb_get_devtypedata(struct ssb_device *dev)
  202. {
  203. return dev->devtypedata;
  204. }
  205. struct ssb_driver {
  206. const char *name;
  207. const struct ssb_device_id *id_table;
  208. int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id);
  209. void (*remove)(struct ssb_device *dev);
  210. int (*suspend)(struct ssb_device *dev, pm_message_t state);
  211. int (*resume)(struct ssb_device *dev);
  212. void (*shutdown)(struct ssb_device *dev);
  213. struct device_driver drv;
  214. };
  215. #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
  216. extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
  217. #define ssb_driver_register(drv) \
  218. __ssb_driver_register(drv, THIS_MODULE)
  219. extern void ssb_driver_unregister(struct ssb_driver *drv);
  220. enum ssb_bustype {
  221. SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */
  222. SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */
  223. SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */
  224. SSB_BUSTYPE_SDIO, /* SSB is connected to SDIO bus */
  225. };
  226. /* board_vendor */
  227. #define SSB_BOARDVENDOR_BCM 0x14E4 /* Broadcom */
  228. #define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */
  229. #define SSB_BOARDVENDOR_HP 0x0E11 /* HP */
  230. /* board_type */
  231. #define SSB_BOARD_BCM94306MP 0x0418
  232. #define SSB_BOARD_BCM4309G 0x0421
  233. #define SSB_BOARD_BCM4306CB 0x0417
  234. #define SSB_BOARD_BCM4309MP 0x040C
  235. #define SSB_BOARD_MP4318 0x044A
  236. #define SSB_BOARD_BU4306 0x0416
  237. #define SSB_BOARD_BU4309 0x040A
  238. /* chip_package */
  239. #define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */
  240. #define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */
  241. #define SSB_CHIPPACK_BCM4712L 0 /* Large 340pin 4712 */
  242. #include <linux/ssb/ssb_driver_chipcommon.h>
  243. #include <linux/ssb/ssb_driver_mips.h>
  244. #include <linux/ssb/ssb_driver_extif.h>
  245. #include <linux/ssb/ssb_driver_pci.h>
  246. struct ssb_bus {
  247. /* The MMIO area. */
  248. void __iomem *mmio;
  249. const struct ssb_bus_ops *ops;
  250. /* The core currently mapped into the MMIO window.
  251. * Not valid on all host-buses. So don't use outside of SSB. */
  252. struct ssb_device *mapped_device;
  253. union {
  254. /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
  255. u8 mapped_pcmcia_seg;
  256. /* Current SSB base address window for SDIO. */
  257. u32 sdio_sbaddr;
  258. };
  259. /* Lock for core and segment switching.
  260. * On PCMCIA-host busses this is used to protect the whole MMIO access. */
  261. spinlock_t bar_lock;
  262. /* The host-bus this backplane is running on. */
  263. enum ssb_bustype bustype;
  264. /* Pointers to the host-bus. Check bustype before using any of these pointers. */
  265. union {
  266. /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
  267. struct pci_dev *host_pci;
  268. /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
  269. struct pcmcia_device *host_pcmcia;
  270. /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
  271. struct sdio_func *host_sdio;
  272. };
  273. /* See enum ssb_quirks */
  274. unsigned int quirks;
  275. #ifdef CONFIG_SSB_SPROM
  276. /* Mutex to protect the SPROM writing. */
  277. struct mutex sprom_mutex;
  278. #endif
  279. /* ID information about the Chip. */
  280. u16 chip_id;
  281. u8 chip_rev;
  282. u16 sprom_offset;
  283. u16 sprom_size; /* number of words in sprom */
  284. u8 chip_package;
  285. /* List of devices (cores) on the backplane. */
  286. struct ssb_device devices[SSB_MAX_NR_CORES];
  287. u8 nr_devices;
  288. /* Software ID number for this bus. */
  289. unsigned int busnumber;
  290. /* The ChipCommon device (if available). */
  291. struct ssb_chipcommon chipco;
  292. /* The PCI-core device (if available). */
  293. struct ssb_pcicore pcicore;
  294. /* The MIPS-core device (if available). */
  295. struct ssb_mipscore mipscore;
  296. /* The EXTif-core device (if available). */
  297. struct ssb_extif extif;
  298. /* The following structure elements are not available in early
  299. * SSB initialization. Though, they are available for regular
  300. * registered drivers at any stage. So be careful when
  301. * using them in the ssb core code. */
  302. /* ID information about the PCB. */
  303. struct ssb_boardinfo boardinfo;
  304. /* Contents of the SPROM. */
  305. struct ssb_sprom sprom;
  306. /* If the board has a cardbus slot, this is set to true. */
  307. bool has_cardbus_slot;
  308. #ifdef CONFIG_SSB_EMBEDDED
  309. /* Lock for GPIO register access. */
  310. spinlock_t gpio_lock;
  311. #endif /* EMBEDDED */
  312. /* Internal-only stuff follows. Do not touch. */
  313. struct list_head list;
  314. #ifdef CONFIG_SSB_DEBUG
  315. /* Is the bus already powered up? */
  316. bool powered_up;
  317. int power_warn_count;
  318. #endif /* DEBUG */
  319. };
  320. enum ssb_quirks {
  321. /* SDIO connected card requires performing a read after writing a 32-bit value */
  322. SSB_QUIRK_SDIO_READ_AFTER_WRITE32 = (1 << 0),
  323. };
  324. /* The initialization-invariants. */
  325. struct ssb_init_invariants {
  326. /* Versioning information about the PCB. */
  327. struct ssb_boardinfo boardinfo;
  328. /* The SPROM information. That's either stored in an
  329. * EEPROM or NVRAM on the board. */
  330. struct ssb_sprom sprom;
  331. /* If the board has a cardbus slot, this is set to true. */
  332. bool has_cardbus_slot;
  333. };
  334. /* Type of function to fetch the invariants. */
  335. typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
  336. struct ssb_init_invariants *iv);
  337. /* Register a SSB system bus. get_invariants() is called after the
  338. * basic system devices are initialized.
  339. * The invariants are usually fetched from some NVRAM.
  340. * Put the invariants into the struct pointed to by iv. */
  341. extern int ssb_bus_ssbbus_register(struct ssb_bus *bus,
  342. unsigned long baseaddr,
  343. ssb_invariants_func_t get_invariants);
  344. #ifdef CONFIG_SSB_PCIHOST
  345. extern int ssb_bus_pcibus_register(struct ssb_bus *bus,
  346. struct pci_dev *host_pci);
  347. #endif /* CONFIG_SSB_PCIHOST */
  348. #ifdef CONFIG_SSB_PCMCIAHOST
  349. extern int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
  350. struct pcmcia_device *pcmcia_dev,
  351. unsigned long baseaddr);
  352. #endif /* CONFIG_SSB_PCMCIAHOST */
  353. #ifdef CONFIG_SSB_SDIOHOST
  354. extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
  355. struct sdio_func *sdio_func,
  356. unsigned int quirks);
  357. #endif /* CONFIG_SSB_SDIOHOST */
  358. extern void ssb_bus_unregister(struct ssb_bus *bus);
  359. /* Does the device have an SPROM? */
  360. extern bool ssb_is_sprom_available(struct ssb_bus *bus);
  361. /* Set a fallback SPROM.
  362. * See kdoc at the function definition for complete documentation. */
  363. extern int ssb_arch_register_fallback_sprom(
  364. int (*sprom_callback)(struct ssb_bus *bus,
  365. struct ssb_sprom *out));
  366. /* Suspend a SSB bus.
  367. * Call this from the parent bus suspend routine. */
  368. extern int ssb_bus_suspend(struct ssb_bus *bus);
  369. /* Resume a SSB bus.
  370. * Call this from the parent bus resume routine. */
  371. extern int ssb_bus_resume(struct ssb_bus *bus);
  372. extern u32 ssb_clockspeed(struct ssb_bus *bus);
  373. /* Is the device enabled in hardware? */
  374. int ssb_device_is_enabled(struct ssb_device *dev);
  375. /* Enable a device and pass device-specific SSB_TMSLOW flags.
  376. * If no device-specific flags are available, use 0. */
  377. void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags);
  378. /* Disable a device in hardware and pass SSB_TMSLOW flags (if any). */
  379. void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags);
  380. /* Device MMIO register read/write functions. */
  381. static inline u8 ssb_read8(struct ssb_device *dev, u16 offset)
  382. {
  383. return dev->ops->read8(dev, offset);
  384. }
  385. static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
  386. {
  387. return dev->ops->read16(dev, offset);
  388. }
  389. static inline u32 ssb_read32(struct ssb_device *dev, u16 offset)
  390. {
  391. return dev->ops->read32(dev, offset);
  392. }
  393. static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
  394. {
  395. dev->ops->write8(dev, offset, value);
  396. }
  397. static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
  398. {
  399. dev->ops->write16(dev, offset, value);
  400. }
  401. static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
  402. {
  403. dev->ops->write32(dev, offset, value);
  404. }
  405. #ifdef CONFIG_SSB_BLOCKIO
  406. static inline void ssb_block_read(struct ssb_device *dev, void *buffer,
  407. size_t count, u16 offset, u8 reg_width)
  408. {
  409. dev->ops->block_read(dev, buffer, count, offset, reg_width);
  410. }
  411. static inline void ssb_block_write(struct ssb_device *dev, const void *buffer,
  412. size_t count, u16 offset, u8 reg_width)
  413. {
  414. dev->ops->block_write(dev, buffer, count, offset, reg_width);
  415. }
  416. #endif /* CONFIG_SSB_BLOCKIO */
  417. /* The SSB DMA API. Use this API for any DMA operation on the device.
  418. * This API basically is a wrapper that calls the correct DMA API for
  419. * the host device type the SSB device is attached to. */
  420. /* Translation (routing) bits that need to be ORed to DMA
  421. * addresses before they are given to a device. */
  422. extern u32 ssb_dma_translation(struct ssb_device *dev);
  423. #define SSB_DMA_TRANSLATION_MASK 0xC0000000
  424. #define SSB_DMA_TRANSLATION_SHIFT 30
  425. static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev)
  426. {
  427. #ifdef CONFIG_SSB_DEBUG
  428. printk(KERN_ERR "SSB: BUG! Calling DMA API for "
  429. "unsupported bustype %d\n", dev->bus->bustype);
  430. #endif /* DEBUG */
  431. }
  432. #ifdef CONFIG_SSB_PCIHOST
  433. /* PCI-host wrapper driver */
  434. extern int ssb_pcihost_register(struct pci_driver *driver);
  435. static inline void ssb_pcihost_unregister(struct pci_driver *driver)
  436. {
  437. pci_unregister_driver(driver);
  438. }
  439. static inline
  440. void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
  441. {
  442. if (sdev->bus->bustype == SSB_BUSTYPE_PCI)
  443. pci_set_power_state(sdev->bus->host_pci, state);
  444. }
  445. #else
  446. static inline void ssb_pcihost_unregister(struct pci_driver *driver)
  447. {
  448. }
  449. static inline
  450. void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
  451. {
  452. }
  453. #endif /* CONFIG_SSB_PCIHOST */
  454. /* If a driver is shutdown or suspended, call this to signal
  455. * that the bus may be completely powered down. SSB will decide,
  456. * if it's really time to power down the bus, based on if there
  457. * are other devices that want to run. */
  458. extern int ssb_bus_may_powerdown(struct ssb_bus *bus);
  459. /* Before initializing and enabling a device, call this to power-up the bus.
  460. * If you want to allow use of dynamic-power-control, pass the flag.
  461. * Otherwise static always-on powercontrol will be used. */
  462. extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
  463. extern void ssb_commit_settings(struct ssb_bus *bus);
  464. /* Various helper functions */
  465. extern u32 ssb_admatch_base(u32 adm);
  466. extern u32 ssb_admatch_size(u32 adm);
  467. /* PCI device mapping and fixup routines.
  468. * Called from the architecture pcibios init code.
  469. * These are only available on SSB_EMBEDDED configurations. */
  470. #ifdef CONFIG_SSB_EMBEDDED
  471. int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
  472. int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
  473. #endif /* CONFIG_SSB_EMBEDDED */
  474. #endif /* LINUX_SSB_H_ */