w5300.c 18 KB

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  1. /*
  2. * Ethernet driver for the WIZnet W5300 chip.
  3. *
  4. * Copyright (C) 2008-2009 WIZnet Co.,Ltd.
  5. * Copyright (C) 2011 Taehun Kim <kth3321 <at> gmail.com>
  6. * Copyright (C) 2012 Mike Sinkovsky <msink@permonline.ru>
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/kconfig.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/platform_data/wiznet.h>
  17. #include <linux/ethtool.h>
  18. #include <linux/skbuff.h>
  19. #include <linux/types.h>
  20. #include <linux/errno.h>
  21. #include <linux/delay.h>
  22. #include <linux/slab.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/io.h>
  25. #include <linux/ioport.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/gpio.h>
  28. #define DRV_NAME "w5300"
  29. #define DRV_VERSION "2012-04-04"
  30. MODULE_DESCRIPTION("WIZnet W5300 Ethernet driver v"DRV_VERSION);
  31. MODULE_AUTHOR("Mike Sinkovsky <msink@permonline.ru>");
  32. MODULE_ALIAS("platform:"DRV_NAME);
  33. MODULE_LICENSE("GPL");
  34. /*
  35. * Registers
  36. */
  37. #define W5300_MR 0x0000 /* Mode Register */
  38. #define MR_DBW (1 << 15) /* Data bus width */
  39. #define MR_MPF (1 << 14) /* Mac layer pause frame */
  40. #define MR_WDF(n) (((n)&7)<<11) /* Write data fetch time */
  41. #define MR_RDH (1 << 10) /* Read data hold time */
  42. #define MR_FS (1 << 8) /* FIFO swap */
  43. #define MR_RST (1 << 7) /* S/W reset */
  44. #define MR_PB (1 << 4) /* Ping block */
  45. #define MR_DBS (1 << 2) /* Data bus swap */
  46. #define MR_IND (1 << 0) /* Indirect mode */
  47. #define W5300_IR 0x0002 /* Interrupt Register */
  48. #define W5300_IMR 0x0004 /* Interrupt Mask Register */
  49. #define IR_S0 0x0001 /* S0 interrupt */
  50. #define W5300_SHARL 0x0008 /* Source MAC address (0123) */
  51. #define W5300_SHARH 0x000c /* Source MAC address (45) */
  52. #define W5300_TMSRL 0x0020 /* Transmit Memory Size (0123) */
  53. #define W5300_TMSRH 0x0024 /* Transmit Memory Size (4567) */
  54. #define W5300_RMSRL 0x0028 /* Receive Memory Size (0123) */
  55. #define W5300_RMSRH 0x002c /* Receive Memory Size (4567) */
  56. #define W5300_MTYPE 0x0030 /* Memory Type */
  57. #define W5300_IDR 0x00fe /* Chip ID register */
  58. #define IDR_W5300 0x5300 /* =0x5300 for WIZnet W5300 */
  59. #define W5300_S0_MR 0x0200 /* S0 Mode Register */
  60. #define S0_MR_CLOSED 0x0000 /* Close mode */
  61. #define S0_MR_MACRAW 0x0004 /* MAC RAW mode (promiscous) */
  62. #define S0_MR_MACRAW_MF 0x0044 /* MAC RAW mode (filtered) */
  63. #define W5300_S0_CR 0x0202 /* S0 Command Register */
  64. #define S0_CR_OPEN 0x0001 /* OPEN command */
  65. #define S0_CR_CLOSE 0x0010 /* CLOSE command */
  66. #define S0_CR_SEND 0x0020 /* SEND command */
  67. #define S0_CR_RECV 0x0040 /* RECV command */
  68. #define W5300_S0_IMR 0x0204 /* S0 Interrupt Mask Register */
  69. #define W5300_S0_IR 0x0206 /* S0 Interrupt Register */
  70. #define S0_IR_RECV 0x0004 /* Receive interrupt */
  71. #define S0_IR_SENDOK 0x0010 /* Send OK interrupt */
  72. #define W5300_S0_SSR 0x0208 /* S0 Socket Status Register */
  73. #define W5300_S0_TX_WRSR 0x0220 /* S0 TX Write Size Register */
  74. #define W5300_S0_TX_FSR 0x0224 /* S0 TX Free Size Register */
  75. #define W5300_S0_RX_RSR 0x0228 /* S0 Received data Size */
  76. #define W5300_S0_TX_FIFO 0x022e /* S0 Transmit FIFO */
  77. #define W5300_S0_RX_FIFO 0x0230 /* S0 Receive FIFO */
  78. #define W5300_REGS_LEN 0x0400
  79. /*
  80. * Device driver private data structure
  81. */
  82. struct w5300_priv {
  83. void __iomem *base;
  84. spinlock_t reg_lock;
  85. bool indirect;
  86. u16 (*read) (struct w5300_priv *priv, u16 addr);
  87. void (*write)(struct w5300_priv *priv, u16 addr, u16 data);
  88. int irq;
  89. int link_irq;
  90. int link_gpio;
  91. struct napi_struct napi;
  92. struct net_device *ndev;
  93. bool promisc;
  94. u32 msg_enable;
  95. };
  96. /************************************************************************
  97. *
  98. * Lowlevel I/O functions
  99. *
  100. ***********************************************************************/
  101. /*
  102. * In direct address mode host system can directly access W5300 registers
  103. * after mapping to Memory-Mapped I/O space.
  104. *
  105. * 0x400 bytes are required for memory space.
  106. */
  107. static inline u16 w5300_read_direct(struct w5300_priv *priv, u16 addr)
  108. {
  109. return ioread16(priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
  110. }
  111. static inline void w5300_write_direct(struct w5300_priv *priv,
  112. u16 addr, u16 data)
  113. {
  114. iowrite16(data, priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
  115. }
  116. /*
  117. * In indirect address mode host system indirectly accesses registers by
  118. * using Indirect Mode Address Register (IDM_AR) and Indirect Mode Data
  119. * Register (IDM_DR), which are directly mapped to Memory-Mapped I/O space.
  120. * Mode Register (MR) is directly accessible.
  121. *
  122. * Only 0x06 bytes are required for memory space.
  123. */
  124. #define W5300_IDM_AR 0x0002 /* Indirect Mode Address */
  125. #define W5300_IDM_DR 0x0004 /* Indirect Mode Data */
  126. static u16 w5300_read_indirect(struct w5300_priv *priv, u16 addr)
  127. {
  128. unsigned long flags;
  129. u16 data;
  130. spin_lock_irqsave(&priv->reg_lock, flags);
  131. w5300_write_direct(priv, W5300_IDM_AR, addr);
  132. mmiowb();
  133. data = w5300_read_direct(priv, W5300_IDM_DR);
  134. spin_unlock_irqrestore(&priv->reg_lock, flags);
  135. return data;
  136. }
  137. static void w5300_write_indirect(struct w5300_priv *priv, u16 addr, u16 data)
  138. {
  139. unsigned long flags;
  140. spin_lock_irqsave(&priv->reg_lock, flags);
  141. w5300_write_direct(priv, W5300_IDM_AR, addr);
  142. mmiowb();
  143. w5300_write_direct(priv, W5300_IDM_DR, data);
  144. mmiowb();
  145. spin_unlock_irqrestore(&priv->reg_lock, flags);
  146. }
  147. #if defined(CONFIG_WIZNET_BUS_DIRECT)
  148. #define w5300_read w5300_read_direct
  149. #define w5300_write w5300_write_direct
  150. #elif defined(CONFIG_WIZNET_BUS_INDIRECT)
  151. #define w5300_read w5300_read_indirect
  152. #define w5300_write w5300_write_indirect
  153. #else /* CONFIG_WIZNET_BUS_ANY */
  154. #define w5300_read priv->read
  155. #define w5300_write priv->write
  156. #endif
  157. static u32 w5300_read32(struct w5300_priv *priv, u16 addr)
  158. {
  159. u32 data;
  160. data = w5300_read(priv, addr) << 16;
  161. data |= w5300_read(priv, addr + 2);
  162. return data;
  163. }
  164. static void w5300_write32(struct w5300_priv *priv, u16 addr, u32 data)
  165. {
  166. w5300_write(priv, addr, data >> 16);
  167. w5300_write(priv, addr + 2, data);
  168. }
  169. static int w5300_command(struct w5300_priv *priv, u16 cmd)
  170. {
  171. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  172. w5300_write(priv, W5300_S0_CR, cmd);
  173. mmiowb();
  174. while (w5300_read(priv, W5300_S0_CR) != 0) {
  175. if (time_after(jiffies, timeout))
  176. return -EIO;
  177. cpu_relax();
  178. }
  179. return 0;
  180. }
  181. static void w5300_read_frame(struct w5300_priv *priv, u8 *buf, int len)
  182. {
  183. u16 fifo;
  184. int i;
  185. for (i = 0; i < len; i += 2) {
  186. fifo = w5300_read(priv, W5300_S0_RX_FIFO);
  187. *buf++ = fifo >> 8;
  188. *buf++ = fifo;
  189. }
  190. fifo = w5300_read(priv, W5300_S0_RX_FIFO);
  191. fifo = w5300_read(priv, W5300_S0_RX_FIFO);
  192. }
  193. static void w5300_write_frame(struct w5300_priv *priv, u8 *buf, int len)
  194. {
  195. u16 fifo;
  196. int i;
  197. for (i = 0; i < len; i += 2) {
  198. fifo = *buf++ << 8;
  199. fifo |= *buf++;
  200. w5300_write(priv, W5300_S0_TX_FIFO, fifo);
  201. }
  202. w5300_write32(priv, W5300_S0_TX_WRSR, len);
  203. }
  204. static void w5300_write_macaddr(struct w5300_priv *priv)
  205. {
  206. struct net_device *ndev = priv->ndev;
  207. w5300_write32(priv, W5300_SHARL,
  208. ndev->dev_addr[0] << 24 |
  209. ndev->dev_addr[1] << 16 |
  210. ndev->dev_addr[2] << 8 |
  211. ndev->dev_addr[3]);
  212. w5300_write(priv, W5300_SHARH,
  213. ndev->dev_addr[4] << 8 |
  214. ndev->dev_addr[5]);
  215. mmiowb();
  216. }
  217. static void w5300_hw_reset(struct w5300_priv *priv)
  218. {
  219. w5300_write_direct(priv, W5300_MR, MR_RST);
  220. mmiowb();
  221. mdelay(5);
  222. w5300_write_direct(priv, W5300_MR, priv->indirect ?
  223. MR_WDF(7) | MR_PB | MR_IND :
  224. MR_WDF(7) | MR_PB);
  225. mmiowb();
  226. w5300_write(priv, W5300_IMR, 0);
  227. w5300_write_macaddr(priv);
  228. /* Configure 128K of internal memory
  229. * as 64K RX fifo and 64K TX fifo
  230. */
  231. w5300_write32(priv, W5300_RMSRL, 64 << 24);
  232. w5300_write32(priv, W5300_RMSRH, 0);
  233. w5300_write32(priv, W5300_TMSRL, 64 << 24);
  234. w5300_write32(priv, W5300_TMSRH, 0);
  235. w5300_write(priv, W5300_MTYPE, 0x00ff);
  236. mmiowb();
  237. }
  238. static void w5300_hw_start(struct w5300_priv *priv)
  239. {
  240. w5300_write(priv, W5300_S0_MR, priv->promisc ?
  241. S0_MR_MACRAW : S0_MR_MACRAW_MF);
  242. mmiowb();
  243. w5300_command(priv, S0_CR_OPEN);
  244. w5300_write(priv, W5300_S0_IMR, IS_ENABLED(CONFIG_WIZNET_TX_FLOW) ?
  245. S0_IR_RECV | S0_IR_SENDOK :
  246. S0_IR_RECV);
  247. w5300_write(priv, W5300_IMR, IR_S0);
  248. mmiowb();
  249. }
  250. static void w5300_hw_close(struct w5300_priv *priv)
  251. {
  252. w5300_write(priv, W5300_IMR, 0);
  253. mmiowb();
  254. w5300_command(priv, S0_CR_CLOSE);
  255. }
  256. /***********************************************************************
  257. *
  258. * Device driver functions / callbacks
  259. *
  260. ***********************************************************************/
  261. static void w5300_get_drvinfo(struct net_device *ndev,
  262. struct ethtool_drvinfo *info)
  263. {
  264. strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
  265. strlcpy(info->version, DRV_VERSION, sizeof(info->version));
  266. strlcpy(info->bus_info, dev_name(ndev->dev.parent),
  267. sizeof(info->bus_info));
  268. }
  269. static u32 w5300_get_link(struct net_device *ndev)
  270. {
  271. struct w5300_priv *priv = netdev_priv(ndev);
  272. if (gpio_is_valid(priv->link_gpio))
  273. return !!gpio_get_value(priv->link_gpio);
  274. return 1;
  275. }
  276. static u32 w5300_get_msglevel(struct net_device *ndev)
  277. {
  278. struct w5300_priv *priv = netdev_priv(ndev);
  279. return priv->msg_enable;
  280. }
  281. static void w5300_set_msglevel(struct net_device *ndev, u32 value)
  282. {
  283. struct w5300_priv *priv = netdev_priv(ndev);
  284. priv->msg_enable = value;
  285. }
  286. static int w5300_get_regs_len(struct net_device *ndev)
  287. {
  288. return W5300_REGS_LEN;
  289. }
  290. static void w5300_get_regs(struct net_device *ndev,
  291. struct ethtool_regs *regs, void *_buf)
  292. {
  293. struct w5300_priv *priv = netdev_priv(ndev);
  294. u8 *buf = _buf;
  295. u16 addr;
  296. u16 data;
  297. regs->version = 1;
  298. for (addr = 0; addr < W5300_REGS_LEN; addr += 2) {
  299. switch (addr & 0x23f) {
  300. case W5300_S0_TX_FIFO: /* cannot read TX_FIFO */
  301. case W5300_S0_RX_FIFO: /* cannot read RX_FIFO */
  302. data = 0xffff;
  303. break;
  304. default:
  305. data = w5300_read(priv, addr);
  306. break;
  307. }
  308. *buf++ = data >> 8;
  309. *buf++ = data;
  310. }
  311. }
  312. static void w5300_tx_timeout(struct net_device *ndev)
  313. {
  314. struct w5300_priv *priv = netdev_priv(ndev);
  315. netif_stop_queue(ndev);
  316. w5300_hw_reset(priv);
  317. w5300_hw_start(priv);
  318. ndev->stats.tx_errors++;
  319. ndev->trans_start = jiffies;
  320. netif_wake_queue(ndev);
  321. }
  322. static int w5300_start_tx(struct sk_buff *skb, struct net_device *ndev)
  323. {
  324. struct w5300_priv *priv = netdev_priv(ndev);
  325. if (IS_ENABLED(CONFIG_WIZNET_TX_FLOW))
  326. netif_stop_queue(ndev);
  327. w5300_write_frame(priv, skb->data, skb->len);
  328. mmiowb();
  329. ndev->stats.tx_packets++;
  330. ndev->stats.tx_bytes += skb->len;
  331. dev_kfree_skb(skb);
  332. netif_dbg(priv, tx_queued, ndev, "tx queued\n");
  333. w5300_command(priv, S0_CR_SEND);
  334. return NETDEV_TX_OK;
  335. }
  336. static int w5300_napi_poll(struct napi_struct *napi, int budget)
  337. {
  338. struct w5300_priv *priv = container_of(napi, struct w5300_priv, napi);
  339. struct net_device *ndev = priv->ndev;
  340. struct sk_buff *skb;
  341. int rx_count;
  342. u16 rx_len;
  343. for (rx_count = 0; rx_count < budget; rx_count++) {
  344. u32 rx_fifo_len = w5300_read32(priv, W5300_S0_RX_RSR);
  345. if (rx_fifo_len == 0)
  346. break;
  347. rx_len = w5300_read(priv, W5300_S0_RX_FIFO);
  348. skb = netdev_alloc_skb_ip_align(ndev, roundup(rx_len, 2));
  349. if (unlikely(!skb)) {
  350. u32 i;
  351. for (i = 0; i < rx_fifo_len; i += 2)
  352. w5300_read(priv, W5300_S0_RX_FIFO);
  353. ndev->stats.rx_dropped++;
  354. return -ENOMEM;
  355. }
  356. skb_put(skb, rx_len);
  357. w5300_read_frame(priv, skb->data, rx_len);
  358. skb->protocol = eth_type_trans(skb, ndev);
  359. netif_receive_skb(skb);
  360. ndev->stats.rx_packets++;
  361. ndev->stats.rx_bytes += rx_len;
  362. }
  363. if (rx_count < budget) {
  364. w5300_write(priv, W5300_IMR, IR_S0);
  365. mmiowb();
  366. napi_complete(napi);
  367. }
  368. return rx_count;
  369. }
  370. static irqreturn_t w5300_interrupt(int irq, void *ndev_instance)
  371. {
  372. struct net_device *ndev = ndev_instance;
  373. struct w5300_priv *priv = netdev_priv(ndev);
  374. int ir = w5300_read(priv, W5300_S0_IR);
  375. if (!ir)
  376. return IRQ_NONE;
  377. w5300_write(priv, W5300_S0_IR, ir);
  378. mmiowb();
  379. if (IS_ENABLED(CONFIG_WIZNET_TX_FLOW) && (ir & S0_IR_SENDOK)) {
  380. netif_dbg(priv, tx_done, ndev, "tx done\n");
  381. netif_wake_queue(ndev);
  382. }
  383. if (ir & S0_IR_RECV) {
  384. if (napi_schedule_prep(&priv->napi)) {
  385. w5300_write(priv, W5300_IMR, 0);
  386. mmiowb();
  387. __napi_schedule(&priv->napi);
  388. }
  389. }
  390. return IRQ_HANDLED;
  391. }
  392. static irqreturn_t w5300_detect_link(int irq, void *ndev_instance)
  393. {
  394. struct net_device *ndev = ndev_instance;
  395. struct w5300_priv *priv = netdev_priv(ndev);
  396. if (netif_running(ndev)) {
  397. if (gpio_get_value(priv->link_gpio) != 0) {
  398. netif_info(priv, link, ndev, "link is up\n");
  399. netif_carrier_on(ndev);
  400. } else {
  401. netif_info(priv, link, ndev, "link is down\n");
  402. netif_carrier_off(ndev);
  403. }
  404. }
  405. return IRQ_HANDLED;
  406. }
  407. static void w5300_set_rx_mode(struct net_device *ndev)
  408. {
  409. struct w5300_priv *priv = netdev_priv(ndev);
  410. bool set_promisc = (ndev->flags & IFF_PROMISC) != 0;
  411. if (priv->promisc != set_promisc) {
  412. priv->promisc = set_promisc;
  413. w5300_hw_start(priv);
  414. }
  415. }
  416. static int w5300_set_macaddr(struct net_device *ndev, void *addr)
  417. {
  418. struct w5300_priv *priv = netdev_priv(ndev);
  419. struct sockaddr *sock_addr = addr;
  420. if (!is_valid_ether_addr(sock_addr->sa_data))
  421. return -EADDRNOTAVAIL;
  422. memcpy(ndev->dev_addr, sock_addr->sa_data, ETH_ALEN);
  423. ndev->addr_assign_type &= ~NET_ADDR_RANDOM;
  424. w5300_write_macaddr(priv);
  425. return 0;
  426. }
  427. static int w5300_open(struct net_device *ndev)
  428. {
  429. struct w5300_priv *priv = netdev_priv(ndev);
  430. netif_info(priv, ifup, ndev, "enabling\n");
  431. if (!is_valid_ether_addr(ndev->dev_addr))
  432. return -EINVAL;
  433. w5300_hw_start(priv);
  434. napi_enable(&priv->napi);
  435. netif_start_queue(ndev);
  436. if (!gpio_is_valid(priv->link_gpio) ||
  437. gpio_get_value(priv->link_gpio) != 0)
  438. netif_carrier_on(ndev);
  439. return 0;
  440. }
  441. static int w5300_stop(struct net_device *ndev)
  442. {
  443. struct w5300_priv *priv = netdev_priv(ndev);
  444. netif_info(priv, ifdown, ndev, "shutting down\n");
  445. w5300_hw_close(priv);
  446. netif_carrier_off(ndev);
  447. netif_stop_queue(ndev);
  448. napi_disable(&priv->napi);
  449. return 0;
  450. }
  451. static const struct ethtool_ops w5300_ethtool_ops = {
  452. .get_drvinfo = w5300_get_drvinfo,
  453. .get_msglevel = w5300_get_msglevel,
  454. .set_msglevel = w5300_set_msglevel,
  455. .get_link = w5300_get_link,
  456. .get_regs_len = w5300_get_regs_len,
  457. .get_regs = w5300_get_regs,
  458. };
  459. static const struct net_device_ops w5300_netdev_ops = {
  460. .ndo_open = w5300_open,
  461. .ndo_stop = w5300_stop,
  462. .ndo_start_xmit = w5300_start_tx,
  463. .ndo_tx_timeout = w5300_tx_timeout,
  464. .ndo_set_rx_mode = w5300_set_rx_mode,
  465. .ndo_set_mac_address = w5300_set_macaddr,
  466. .ndo_validate_addr = eth_validate_addr,
  467. .ndo_change_mtu = eth_change_mtu,
  468. };
  469. static int __devinit w5300_hw_probe(struct platform_device *pdev)
  470. {
  471. struct wiznet_platform_data *data = pdev->dev.platform_data;
  472. struct net_device *ndev = platform_get_drvdata(pdev);
  473. struct w5300_priv *priv = netdev_priv(ndev);
  474. const char *name = netdev_name(ndev);
  475. struct resource *mem;
  476. int mem_size;
  477. int irq;
  478. int ret;
  479. if (data && is_valid_ether_addr(data->mac_addr)) {
  480. memcpy(ndev->dev_addr, data->mac_addr, ETH_ALEN);
  481. } else {
  482. random_ether_addr(ndev->dev_addr);
  483. ndev->addr_assign_type |= NET_ADDR_RANDOM;
  484. }
  485. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  486. if (!mem)
  487. return -ENXIO;
  488. mem_size = resource_size(mem);
  489. if (!devm_request_mem_region(&pdev->dev, mem->start, mem_size, name))
  490. return -EBUSY;
  491. priv->base = devm_ioremap(&pdev->dev, mem->start, mem_size);
  492. if (!priv->base)
  493. return -EBUSY;
  494. spin_lock_init(&priv->reg_lock);
  495. priv->indirect = mem_size < W5300_BUS_DIRECT_SIZE;
  496. if (priv->indirect) {
  497. priv->read = w5300_read_indirect;
  498. priv->write = w5300_write_indirect;
  499. } else {
  500. priv->read = w5300_read_direct;
  501. priv->write = w5300_write_direct;
  502. }
  503. w5300_hw_reset(priv);
  504. if (w5300_read(priv, W5300_IDR) != IDR_W5300)
  505. return -ENODEV;
  506. irq = platform_get_irq(pdev, 0);
  507. if (irq < 0)
  508. return irq;
  509. ret = request_irq(irq, w5300_interrupt,
  510. IRQ_TYPE_LEVEL_LOW, name, ndev);
  511. if (ret < 0)
  512. return ret;
  513. priv->irq = irq;
  514. priv->link_gpio = data->link_gpio;
  515. if (gpio_is_valid(priv->link_gpio)) {
  516. char *link_name = devm_kzalloc(&pdev->dev, 16, GFP_KERNEL);
  517. if (!link_name)
  518. return -ENOMEM;
  519. snprintf(link_name, 16, "%s-link", name);
  520. priv->link_irq = gpio_to_irq(priv->link_gpio);
  521. if (request_any_context_irq(priv->link_irq, w5300_detect_link,
  522. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
  523. link_name, priv->ndev) < 0)
  524. priv->link_gpio = -EINVAL;
  525. }
  526. netdev_info(ndev, "at 0x%llx irq %d\n", (u64)mem->start, irq);
  527. return 0;
  528. }
  529. static int __devinit w5300_probe(struct platform_device *pdev)
  530. {
  531. struct w5300_priv *priv;
  532. struct net_device *ndev;
  533. int err;
  534. ndev = alloc_etherdev(sizeof(*priv));
  535. if (!ndev)
  536. return -ENOMEM;
  537. SET_NETDEV_DEV(ndev, &pdev->dev);
  538. platform_set_drvdata(pdev, ndev);
  539. priv = netdev_priv(ndev);
  540. priv->ndev = ndev;
  541. ether_setup(ndev);
  542. ndev->netdev_ops = &w5300_netdev_ops;
  543. ndev->ethtool_ops = &w5300_ethtool_ops;
  544. ndev->watchdog_timeo = HZ;
  545. netif_napi_add(ndev, &priv->napi, w5300_napi_poll, 16);
  546. /* This chip doesn't support VLAN packets with normal MTU,
  547. * so disable VLAN for this device.
  548. */
  549. ndev->features |= NETIF_F_VLAN_CHALLENGED;
  550. err = register_netdev(ndev);
  551. if (err < 0)
  552. goto err_register;
  553. err = w5300_hw_probe(pdev);
  554. if (err < 0)
  555. goto err_hw_probe;
  556. return 0;
  557. err_hw_probe:
  558. unregister_netdev(ndev);
  559. err_register:
  560. free_netdev(ndev);
  561. platform_set_drvdata(pdev, NULL);
  562. return err;
  563. }
  564. static int __devexit w5300_remove(struct platform_device *pdev)
  565. {
  566. struct net_device *ndev = platform_get_drvdata(pdev);
  567. struct w5300_priv *priv = netdev_priv(ndev);
  568. w5300_hw_reset(priv);
  569. free_irq(priv->irq, ndev);
  570. if (gpio_is_valid(priv->link_gpio))
  571. free_irq(priv->link_irq, ndev);
  572. unregister_netdev(ndev);
  573. free_netdev(ndev);
  574. platform_set_drvdata(pdev, NULL);
  575. return 0;
  576. }
  577. #ifdef CONFIG_PM
  578. static int w5300_suspend(struct device *dev)
  579. {
  580. struct platform_device *pdev = to_platform_device(dev);
  581. struct net_device *ndev = platform_get_drvdata(pdev);
  582. struct w5300_priv *priv = netdev_priv(ndev);
  583. if (netif_running(ndev)) {
  584. netif_carrier_off(ndev);
  585. netif_device_detach(ndev);
  586. w5300_hw_close(priv);
  587. }
  588. return 0;
  589. }
  590. static int w5300_resume(struct device *dev)
  591. {
  592. struct platform_device *pdev = to_platform_device(dev);
  593. struct net_device *ndev = platform_get_drvdata(pdev);
  594. struct w5300_priv *priv = netdev_priv(ndev);
  595. if (!netif_running(ndev)) {
  596. w5300_hw_reset(priv);
  597. w5300_hw_start(priv);
  598. netif_device_attach(ndev);
  599. if (!gpio_is_valid(priv->link_gpio) ||
  600. gpio_get_value(priv->link_gpio) != 0)
  601. netif_carrier_on(ndev);
  602. }
  603. return 0;
  604. }
  605. #endif /* CONFIG_PM */
  606. static SIMPLE_DEV_PM_OPS(w5300_pm_ops, w5300_suspend, w5300_resume);
  607. static struct platform_driver w5300_driver = {
  608. .driver = {
  609. .name = DRV_NAME,
  610. .owner = THIS_MODULE,
  611. .pm = &w5300_pm_ops,
  612. },
  613. .probe = w5300_probe,
  614. .remove = __devexit_p(w5300_remove),
  615. };
  616. module_platform_driver(w5300_driver);