mISDNipac.c 42 KB

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  1. /*
  2. * isac.c ISAC specific routines
  3. *
  4. * Author Karsten Keil <keil@isdn4linux.de>
  5. *
  6. * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. *
  21. */
  22. #include <linux/irqreturn.h>
  23. #include <linux/slab.h>
  24. #include <linux/module.h>
  25. #include <linux/mISDNhw.h>
  26. #include "ipac.h"
  27. #define DBUSY_TIMER_VALUE 80
  28. #define ARCOFI_USE 1
  29. #define ISAC_REV "2.0"
  30. MODULE_AUTHOR("Karsten Keil");
  31. MODULE_VERSION(ISAC_REV);
  32. MODULE_LICENSE("GPL v2");
  33. #define ReadISAC(is, o) (is->read_reg(is->dch.hw, o + is->off))
  34. #define WriteISAC(is, o, v) (is->write_reg(is->dch.hw, o + is->off, v))
  35. #define ReadHSCX(h, o) (h->ip->read_reg(h->ip->hw, h->off + o))
  36. #define WriteHSCX(h, o, v) (h->ip->write_reg(h->ip->hw, h->off + o, v))
  37. #define ReadIPAC(ip, o) (ip->read_reg(ip->hw, o))
  38. #define WriteIPAC(ip, o, v) (ip->write_reg(ip->hw, o, v))
  39. static inline void
  40. ph_command(struct isac_hw *isac, u8 command)
  41. {
  42. pr_debug("%s: ph_command %x\n", isac->name, command);
  43. if (isac->type & IPAC_TYPE_ISACX)
  44. WriteISAC(isac, ISACX_CIX0, (command << 4) | 0xE);
  45. else
  46. WriteISAC(isac, ISAC_CIX0, (command << 2) | 3);
  47. }
  48. static void
  49. isac_ph_state_change(struct isac_hw *isac)
  50. {
  51. switch (isac->state) {
  52. case (ISAC_IND_RS):
  53. case (ISAC_IND_EI):
  54. ph_command(isac, ISAC_CMD_DUI);
  55. }
  56. schedule_event(&isac->dch, FLG_PHCHANGE);
  57. }
  58. static void
  59. isac_ph_state_bh(struct dchannel *dch)
  60. {
  61. struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
  62. switch (isac->state) {
  63. case ISAC_IND_RS:
  64. case ISAC_IND_EI:
  65. dch->state = 0;
  66. l1_event(dch->l1, HW_RESET_IND);
  67. break;
  68. case ISAC_IND_DID:
  69. dch->state = 3;
  70. l1_event(dch->l1, HW_DEACT_CNF);
  71. break;
  72. case ISAC_IND_DR:
  73. dch->state = 3;
  74. l1_event(dch->l1, HW_DEACT_IND);
  75. break;
  76. case ISAC_IND_PU:
  77. dch->state = 4;
  78. l1_event(dch->l1, HW_POWERUP_IND);
  79. break;
  80. case ISAC_IND_RSY:
  81. if (dch->state <= 5) {
  82. dch->state = 5;
  83. l1_event(dch->l1, ANYSIGNAL);
  84. } else {
  85. dch->state = 8;
  86. l1_event(dch->l1, LOSTFRAMING);
  87. }
  88. break;
  89. case ISAC_IND_ARD:
  90. dch->state = 6;
  91. l1_event(dch->l1, INFO2);
  92. break;
  93. case ISAC_IND_AI8:
  94. dch->state = 7;
  95. l1_event(dch->l1, INFO4_P8);
  96. break;
  97. case ISAC_IND_AI10:
  98. dch->state = 7;
  99. l1_event(dch->l1, INFO4_P10);
  100. break;
  101. }
  102. pr_debug("%s: TE newstate %x\n", isac->name, dch->state);
  103. }
  104. void
  105. isac_empty_fifo(struct isac_hw *isac, int count)
  106. {
  107. u8 *ptr;
  108. pr_debug("%s: %s %d\n", isac->name, __func__, count);
  109. if (!isac->dch.rx_skb) {
  110. isac->dch.rx_skb = mI_alloc_skb(isac->dch.maxlen, GFP_ATOMIC);
  111. if (!isac->dch.rx_skb) {
  112. pr_info("%s: D receive out of memory\n", isac->name);
  113. WriteISAC(isac, ISAC_CMDR, 0x80);
  114. return;
  115. }
  116. }
  117. if ((isac->dch.rx_skb->len + count) >= isac->dch.maxlen) {
  118. pr_debug("%s: %s overrun %d\n", isac->name, __func__,
  119. isac->dch.rx_skb->len + count);
  120. WriteISAC(isac, ISAC_CMDR, 0x80);
  121. return;
  122. }
  123. ptr = skb_put(isac->dch.rx_skb, count);
  124. isac->read_fifo(isac->dch.hw, isac->off, ptr, count);
  125. WriteISAC(isac, ISAC_CMDR, 0x80);
  126. if (isac->dch.debug & DEBUG_HW_DFIFO) {
  127. char pfx[MISDN_MAX_IDLEN + 16];
  128. snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-recv %s %d ",
  129. isac->name, count);
  130. print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count);
  131. }
  132. }
  133. static void
  134. isac_fill_fifo(struct isac_hw *isac)
  135. {
  136. int count, more;
  137. u8 *ptr;
  138. if (!isac->dch.tx_skb)
  139. return;
  140. count = isac->dch.tx_skb->len - isac->dch.tx_idx;
  141. if (count <= 0)
  142. return;
  143. more = 0;
  144. if (count > 32) {
  145. more = !0;
  146. count = 32;
  147. }
  148. pr_debug("%s: %s %d\n", isac->name, __func__, count);
  149. ptr = isac->dch.tx_skb->data + isac->dch.tx_idx;
  150. isac->dch.tx_idx += count;
  151. isac->write_fifo(isac->dch.hw, isac->off, ptr, count);
  152. WriteISAC(isac, ISAC_CMDR, more ? 0x8 : 0xa);
  153. if (test_and_set_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) {
  154. pr_debug("%s: %s dbusytimer running\n", isac->name, __func__);
  155. del_timer(&isac->dch.timer);
  156. }
  157. init_timer(&isac->dch.timer);
  158. isac->dch.timer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
  159. add_timer(&isac->dch.timer);
  160. if (isac->dch.debug & DEBUG_HW_DFIFO) {
  161. char pfx[MISDN_MAX_IDLEN + 16];
  162. snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-send %s %d ",
  163. isac->name, count);
  164. print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count);
  165. }
  166. }
  167. static void
  168. isac_rme_irq(struct isac_hw *isac)
  169. {
  170. u8 val, count;
  171. val = ReadISAC(isac, ISAC_RSTA);
  172. if ((val & 0x70) != 0x20) {
  173. if (val & 0x40) {
  174. pr_debug("%s: ISAC RDO\n", isac->name);
  175. #ifdef ERROR_STATISTIC
  176. isac->dch.err_rx++;
  177. #endif
  178. }
  179. if (!(val & 0x20)) {
  180. pr_debug("%s: ISAC CRC error\n", isac->name);
  181. #ifdef ERROR_STATISTIC
  182. isac->dch.err_crc++;
  183. #endif
  184. }
  185. WriteISAC(isac, ISAC_CMDR, 0x80);
  186. if (isac->dch.rx_skb)
  187. dev_kfree_skb(isac->dch.rx_skb);
  188. isac->dch.rx_skb = NULL;
  189. } else {
  190. count = ReadISAC(isac, ISAC_RBCL) & 0x1f;
  191. if (count == 0)
  192. count = 32;
  193. isac_empty_fifo(isac, count);
  194. recv_Dchannel(&isac->dch);
  195. }
  196. }
  197. static void
  198. isac_xpr_irq(struct isac_hw *isac)
  199. {
  200. if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags))
  201. del_timer(&isac->dch.timer);
  202. if (isac->dch.tx_skb && isac->dch.tx_idx < isac->dch.tx_skb->len) {
  203. isac_fill_fifo(isac);
  204. } else {
  205. if (isac->dch.tx_skb)
  206. dev_kfree_skb(isac->dch.tx_skb);
  207. if (get_next_dframe(&isac->dch))
  208. isac_fill_fifo(isac);
  209. }
  210. }
  211. static void
  212. isac_retransmit(struct isac_hw *isac)
  213. {
  214. if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags))
  215. del_timer(&isac->dch.timer);
  216. if (test_bit(FLG_TX_BUSY, &isac->dch.Flags)) {
  217. /* Restart frame */
  218. isac->dch.tx_idx = 0;
  219. isac_fill_fifo(isac);
  220. } else if (isac->dch.tx_skb) { /* should not happen */
  221. pr_info("%s: tx_skb exist but not busy\n", isac->name);
  222. test_and_set_bit(FLG_TX_BUSY, &isac->dch.Flags);
  223. isac->dch.tx_idx = 0;
  224. isac_fill_fifo(isac);
  225. } else {
  226. pr_info("%s: ISAC XDU no TX_BUSY\n", isac->name);
  227. if (get_next_dframe(&isac->dch))
  228. isac_fill_fifo(isac);
  229. }
  230. }
  231. static void
  232. isac_mos_irq(struct isac_hw *isac)
  233. {
  234. u8 val;
  235. int ret;
  236. val = ReadISAC(isac, ISAC_MOSR);
  237. pr_debug("%s: ISAC MOSR %02x\n", isac->name, val);
  238. #if ARCOFI_USE
  239. if (val & 0x08) {
  240. if (!isac->mon_rx) {
  241. isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
  242. if (!isac->mon_rx) {
  243. pr_info("%s: ISAC MON RX out of memory!\n",
  244. isac->name);
  245. isac->mocr &= 0xf0;
  246. isac->mocr |= 0x0a;
  247. WriteISAC(isac, ISAC_MOCR, isac->mocr);
  248. goto afterMONR0;
  249. } else
  250. isac->mon_rxp = 0;
  251. }
  252. if (isac->mon_rxp >= MAX_MON_FRAME) {
  253. isac->mocr &= 0xf0;
  254. isac->mocr |= 0x0a;
  255. WriteISAC(isac, ISAC_MOCR, isac->mocr);
  256. isac->mon_rxp = 0;
  257. pr_debug("%s: ISAC MON RX overflow!\n", isac->name);
  258. goto afterMONR0;
  259. }
  260. isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR0);
  261. pr_debug("%s: ISAC MOR0 %02x\n", isac->name,
  262. isac->mon_rx[isac->mon_rxp - 1]);
  263. if (isac->mon_rxp == 1) {
  264. isac->mocr |= 0x04;
  265. WriteISAC(isac, ISAC_MOCR, isac->mocr);
  266. }
  267. }
  268. afterMONR0:
  269. if (val & 0x80) {
  270. if (!isac->mon_rx) {
  271. isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
  272. if (!isac->mon_rx) {
  273. pr_info("%s: ISAC MON RX out of memory!\n",
  274. isac->name);
  275. isac->mocr &= 0x0f;
  276. isac->mocr |= 0xa0;
  277. WriteISAC(isac, ISAC_MOCR, isac->mocr);
  278. goto afterMONR1;
  279. } else
  280. isac->mon_rxp = 0;
  281. }
  282. if (isac->mon_rxp >= MAX_MON_FRAME) {
  283. isac->mocr &= 0x0f;
  284. isac->mocr |= 0xa0;
  285. WriteISAC(isac, ISAC_MOCR, isac->mocr);
  286. isac->mon_rxp = 0;
  287. pr_debug("%s: ISAC MON RX overflow!\n", isac->name);
  288. goto afterMONR1;
  289. }
  290. isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR1);
  291. pr_debug("%s: ISAC MOR1 %02x\n", isac->name,
  292. isac->mon_rx[isac->mon_rxp - 1]);
  293. isac->mocr |= 0x40;
  294. WriteISAC(isac, ISAC_MOCR, isac->mocr);
  295. }
  296. afterMONR1:
  297. if (val & 0x04) {
  298. isac->mocr &= 0xf0;
  299. WriteISAC(isac, ISAC_MOCR, isac->mocr);
  300. isac->mocr |= 0x0a;
  301. WriteISAC(isac, ISAC_MOCR, isac->mocr);
  302. if (isac->monitor) {
  303. ret = isac->monitor(isac->dch.hw, MONITOR_RX_0,
  304. isac->mon_rx, isac->mon_rxp);
  305. if (ret)
  306. kfree(isac->mon_rx);
  307. } else {
  308. pr_info("%s: MONITOR 0 received %d but no user\n",
  309. isac->name, isac->mon_rxp);
  310. kfree(isac->mon_rx);
  311. }
  312. isac->mon_rx = NULL;
  313. isac->mon_rxp = 0;
  314. }
  315. if (val & 0x40) {
  316. isac->mocr &= 0x0f;
  317. WriteISAC(isac, ISAC_MOCR, isac->mocr);
  318. isac->mocr |= 0xa0;
  319. WriteISAC(isac, ISAC_MOCR, isac->mocr);
  320. if (isac->monitor) {
  321. ret = isac->monitor(isac->dch.hw, MONITOR_RX_1,
  322. isac->mon_rx, isac->mon_rxp);
  323. if (ret)
  324. kfree(isac->mon_rx);
  325. } else {
  326. pr_info("%s: MONITOR 1 received %d but no user\n",
  327. isac->name, isac->mon_rxp);
  328. kfree(isac->mon_rx);
  329. }
  330. isac->mon_rx = NULL;
  331. isac->mon_rxp = 0;
  332. }
  333. if (val & 0x02) {
  334. if ((!isac->mon_tx) || (isac->mon_txc &&
  335. (isac->mon_txp >= isac->mon_txc) && !(val & 0x08))) {
  336. isac->mocr &= 0xf0;
  337. WriteISAC(isac, ISAC_MOCR, isac->mocr);
  338. isac->mocr |= 0x0a;
  339. WriteISAC(isac, ISAC_MOCR, isac->mocr);
  340. if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
  341. if (isac->monitor)
  342. ret = isac->monitor(isac->dch.hw,
  343. MONITOR_TX_0, NULL, 0);
  344. }
  345. kfree(isac->mon_tx);
  346. isac->mon_tx = NULL;
  347. isac->mon_txc = 0;
  348. isac->mon_txp = 0;
  349. goto AfterMOX0;
  350. }
  351. if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
  352. if (isac->monitor)
  353. ret = isac->monitor(isac->dch.hw,
  354. MONITOR_TX_0, NULL, 0);
  355. kfree(isac->mon_tx);
  356. isac->mon_tx = NULL;
  357. isac->mon_txc = 0;
  358. isac->mon_txp = 0;
  359. goto AfterMOX0;
  360. }
  361. WriteISAC(isac, ISAC_MOX0, isac->mon_tx[isac->mon_txp++]);
  362. pr_debug("%s: ISAC %02x -> MOX0\n", isac->name,
  363. isac->mon_tx[isac->mon_txp - 1]);
  364. }
  365. AfterMOX0:
  366. if (val & 0x20) {
  367. if ((!isac->mon_tx) || (isac->mon_txc &&
  368. (isac->mon_txp >= isac->mon_txc) && !(val & 0x80))) {
  369. isac->mocr &= 0x0f;
  370. WriteISAC(isac, ISAC_MOCR, isac->mocr);
  371. isac->mocr |= 0xa0;
  372. WriteISAC(isac, ISAC_MOCR, isac->mocr);
  373. if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
  374. if (isac->monitor)
  375. ret = isac->monitor(isac->dch.hw,
  376. MONITOR_TX_1, NULL, 0);
  377. }
  378. kfree(isac->mon_tx);
  379. isac->mon_tx = NULL;
  380. isac->mon_txc = 0;
  381. isac->mon_txp = 0;
  382. goto AfterMOX1;
  383. }
  384. if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
  385. if (isac->monitor)
  386. ret = isac->monitor(isac->dch.hw,
  387. MONITOR_TX_1, NULL, 0);
  388. kfree(isac->mon_tx);
  389. isac->mon_tx = NULL;
  390. isac->mon_txc = 0;
  391. isac->mon_txp = 0;
  392. goto AfterMOX1;
  393. }
  394. WriteISAC(isac, ISAC_MOX1, isac->mon_tx[isac->mon_txp++]);
  395. pr_debug("%s: ISAC %02x -> MOX1\n", isac->name,
  396. isac->mon_tx[isac->mon_txp - 1]);
  397. }
  398. AfterMOX1:
  399. val = 0; /* dummy to avoid warning */
  400. #endif
  401. }
  402. static void
  403. isac_cisq_irq(struct isac_hw *isac) {
  404. u8 val;
  405. val = ReadISAC(isac, ISAC_CIR0);
  406. pr_debug("%s: ISAC CIR0 %02X\n", isac->name, val);
  407. if (val & 2) {
  408. pr_debug("%s: ph_state change %x->%x\n", isac->name,
  409. isac->state, (val >> 2) & 0xf);
  410. isac->state = (val >> 2) & 0xf;
  411. isac_ph_state_change(isac);
  412. }
  413. if (val & 1) {
  414. val = ReadISAC(isac, ISAC_CIR1);
  415. pr_debug("%s: ISAC CIR1 %02X\n", isac->name, val);
  416. }
  417. }
  418. static void
  419. isacsx_cic_irq(struct isac_hw *isac)
  420. {
  421. u8 val;
  422. val = ReadISAC(isac, ISACX_CIR0);
  423. pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val);
  424. if (val & ISACX_CIR0_CIC0) {
  425. pr_debug("%s: ph_state change %x->%x\n", isac->name,
  426. isac->state, val >> 4);
  427. isac->state = val >> 4;
  428. isac_ph_state_change(isac);
  429. }
  430. }
  431. static void
  432. isacsx_rme_irq(struct isac_hw *isac)
  433. {
  434. int count;
  435. u8 val;
  436. val = ReadISAC(isac, ISACX_RSTAD);
  437. if ((val & (ISACX_RSTAD_VFR |
  438. ISACX_RSTAD_RDO |
  439. ISACX_RSTAD_CRC |
  440. ISACX_RSTAD_RAB))
  441. != (ISACX_RSTAD_VFR | ISACX_RSTAD_CRC)) {
  442. pr_debug("%s: RSTAD %#x, dropped\n", isac->name, val);
  443. #ifdef ERROR_STATISTIC
  444. if (val & ISACX_RSTAD_CRC)
  445. isac->dch.err_rx++;
  446. else
  447. isac->dch.err_crc++;
  448. #endif
  449. WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC);
  450. if (isac->dch.rx_skb)
  451. dev_kfree_skb(isac->dch.rx_skb);
  452. isac->dch.rx_skb = NULL;
  453. } else {
  454. count = ReadISAC(isac, ISACX_RBCLD) & 0x1f;
  455. if (count == 0)
  456. count = 32;
  457. isac_empty_fifo(isac, count);
  458. if (isac->dch.rx_skb) {
  459. skb_trim(isac->dch.rx_skb, isac->dch.rx_skb->len - 1);
  460. pr_debug("%s: dchannel received %d\n", isac->name,
  461. isac->dch.rx_skb->len);
  462. recv_Dchannel(&isac->dch);
  463. }
  464. }
  465. }
  466. irqreturn_t
  467. mISDNisac_irq(struct isac_hw *isac, u8 val)
  468. {
  469. if (unlikely(!val))
  470. return IRQ_NONE;
  471. pr_debug("%s: ISAC interrupt %02x\n", isac->name, val);
  472. if (isac->type & IPAC_TYPE_ISACX) {
  473. if (val & ISACX__CIC)
  474. isacsx_cic_irq(isac);
  475. if (val & ISACX__ICD) {
  476. val = ReadISAC(isac, ISACX_ISTAD);
  477. pr_debug("%s: ISTAD %02x\n", isac->name, val);
  478. if (val & ISACX_D_XDU) {
  479. pr_debug("%s: ISAC XDU\n", isac->name);
  480. #ifdef ERROR_STATISTIC
  481. isac->dch.err_tx++;
  482. #endif
  483. isac_retransmit(isac);
  484. }
  485. if (val & ISACX_D_XMR) {
  486. pr_debug("%s: ISAC XMR\n", isac->name);
  487. #ifdef ERROR_STATISTIC
  488. isac->dch.err_tx++;
  489. #endif
  490. isac_retransmit(isac);
  491. }
  492. if (val & ISACX_D_XPR)
  493. isac_xpr_irq(isac);
  494. if (val & ISACX_D_RFO) {
  495. pr_debug("%s: ISAC RFO\n", isac->name);
  496. WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC);
  497. }
  498. if (val & ISACX_D_RME)
  499. isacsx_rme_irq(isac);
  500. if (val & ISACX_D_RPF)
  501. isac_empty_fifo(isac, 0x20);
  502. }
  503. } else {
  504. if (val & 0x80) /* RME */
  505. isac_rme_irq(isac);
  506. if (val & 0x40) /* RPF */
  507. isac_empty_fifo(isac, 32);
  508. if (val & 0x10) /* XPR */
  509. isac_xpr_irq(isac);
  510. if (val & 0x04) /* CISQ */
  511. isac_cisq_irq(isac);
  512. if (val & 0x20) /* RSC - never */
  513. pr_debug("%s: ISAC RSC interrupt\n", isac->name);
  514. if (val & 0x02) /* SIN - never */
  515. pr_debug("%s: ISAC SIN interrupt\n", isac->name);
  516. if (val & 0x01) { /* EXI */
  517. val = ReadISAC(isac, ISAC_EXIR);
  518. pr_debug("%s: ISAC EXIR %02x\n", isac->name, val);
  519. if (val & 0x80) /* XMR */
  520. pr_debug("%s: ISAC XMR\n", isac->name);
  521. if (val & 0x40) { /* XDU */
  522. pr_debug("%s: ISAC XDU\n", isac->name);
  523. #ifdef ERROR_STATISTIC
  524. isac->dch.err_tx++;
  525. #endif
  526. isac_retransmit(isac);
  527. }
  528. if (val & 0x04) /* MOS */
  529. isac_mos_irq(isac);
  530. }
  531. }
  532. return IRQ_HANDLED;
  533. }
  534. EXPORT_SYMBOL(mISDNisac_irq);
  535. static int
  536. isac_l1hw(struct mISDNchannel *ch, struct sk_buff *skb)
  537. {
  538. struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
  539. struct dchannel *dch = container_of(dev, struct dchannel, dev);
  540. struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
  541. int ret = -EINVAL;
  542. struct mISDNhead *hh = mISDN_HEAD_P(skb);
  543. u32 id;
  544. u_long flags;
  545. switch (hh->prim) {
  546. case PH_DATA_REQ:
  547. spin_lock_irqsave(isac->hwlock, flags);
  548. ret = dchannel_senddata(dch, skb);
  549. if (ret > 0) { /* direct TX */
  550. id = hh->id; /* skb can be freed */
  551. isac_fill_fifo(isac);
  552. ret = 0;
  553. spin_unlock_irqrestore(isac->hwlock, flags);
  554. queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
  555. } else
  556. spin_unlock_irqrestore(isac->hwlock, flags);
  557. return ret;
  558. case PH_ACTIVATE_REQ:
  559. ret = l1_event(dch->l1, hh->prim);
  560. break;
  561. case PH_DEACTIVATE_REQ:
  562. test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
  563. ret = l1_event(dch->l1, hh->prim);
  564. break;
  565. }
  566. if (!ret)
  567. dev_kfree_skb(skb);
  568. return ret;
  569. }
  570. static int
  571. isac_ctrl(struct isac_hw *isac, u32 cmd, unsigned long para)
  572. {
  573. u8 tl = 0;
  574. unsigned long flags;
  575. int ret = 0;
  576. switch (cmd) {
  577. case HW_TESTLOOP:
  578. spin_lock_irqsave(isac->hwlock, flags);
  579. if (!(isac->type & IPAC_TYPE_ISACX)) {
  580. /* TODO: implement for IPAC_TYPE_ISACX */
  581. if (para & 1) /* B1 */
  582. tl |= 0x0c;
  583. else if (para & 2) /* B2 */
  584. tl |= 0x3;
  585. /* we only support IOM2 mode */
  586. WriteISAC(isac, ISAC_SPCR, tl);
  587. if (tl)
  588. WriteISAC(isac, ISAC_ADF1, 0x8);
  589. else
  590. WriteISAC(isac, ISAC_ADF1, 0x0);
  591. }
  592. spin_unlock_irqrestore(isac->hwlock, flags);
  593. break;
  594. case HW_TIMER3_VALUE:
  595. ret = l1_event(isac->dch.l1, HW_TIMER3_VALUE | (para & 0xff));
  596. break;
  597. default:
  598. pr_debug("%s: %s unknown command %x %lx\n", isac->name,
  599. __func__, cmd, para);
  600. ret = -1;
  601. }
  602. return ret;
  603. }
  604. static int
  605. isac_l1cmd(struct dchannel *dch, u32 cmd)
  606. {
  607. struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
  608. u_long flags;
  609. pr_debug("%s: cmd(%x) state(%02x)\n", isac->name, cmd, isac->state);
  610. switch (cmd) {
  611. case INFO3_P8:
  612. spin_lock_irqsave(isac->hwlock, flags);
  613. ph_command(isac, ISAC_CMD_AR8);
  614. spin_unlock_irqrestore(isac->hwlock, flags);
  615. break;
  616. case INFO3_P10:
  617. spin_lock_irqsave(isac->hwlock, flags);
  618. ph_command(isac, ISAC_CMD_AR10);
  619. spin_unlock_irqrestore(isac->hwlock, flags);
  620. break;
  621. case HW_RESET_REQ:
  622. spin_lock_irqsave(isac->hwlock, flags);
  623. if ((isac->state == ISAC_IND_EI) ||
  624. (isac->state == ISAC_IND_DR) ||
  625. (isac->state == ISAC_IND_RS))
  626. ph_command(isac, ISAC_CMD_TIM);
  627. else
  628. ph_command(isac, ISAC_CMD_RS);
  629. spin_unlock_irqrestore(isac->hwlock, flags);
  630. break;
  631. case HW_DEACT_REQ:
  632. skb_queue_purge(&dch->squeue);
  633. if (dch->tx_skb) {
  634. dev_kfree_skb(dch->tx_skb);
  635. dch->tx_skb = NULL;
  636. }
  637. dch->tx_idx = 0;
  638. if (dch->rx_skb) {
  639. dev_kfree_skb(dch->rx_skb);
  640. dch->rx_skb = NULL;
  641. }
  642. test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
  643. if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
  644. del_timer(&dch->timer);
  645. break;
  646. case HW_POWERUP_REQ:
  647. spin_lock_irqsave(isac->hwlock, flags);
  648. ph_command(isac, ISAC_CMD_TIM);
  649. spin_unlock_irqrestore(isac->hwlock, flags);
  650. break;
  651. case PH_ACTIVATE_IND:
  652. test_and_set_bit(FLG_ACTIVE, &dch->Flags);
  653. _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
  654. GFP_ATOMIC);
  655. break;
  656. case PH_DEACTIVATE_IND:
  657. test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
  658. _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
  659. GFP_ATOMIC);
  660. break;
  661. default:
  662. pr_debug("%s: %s unknown command %x\n", isac->name,
  663. __func__, cmd);
  664. return -1;
  665. }
  666. return 0;
  667. }
  668. static void
  669. isac_release(struct isac_hw *isac)
  670. {
  671. if (isac->type & IPAC_TYPE_ISACX)
  672. WriteISAC(isac, ISACX_MASK, 0xff);
  673. else
  674. WriteISAC(isac, ISAC_MASK, 0xff);
  675. if (isac->dch.timer.function != NULL) {
  676. del_timer(&isac->dch.timer);
  677. isac->dch.timer.function = NULL;
  678. }
  679. kfree(isac->mon_rx);
  680. isac->mon_rx = NULL;
  681. kfree(isac->mon_tx);
  682. isac->mon_tx = NULL;
  683. if (isac->dch.l1)
  684. l1_event(isac->dch.l1, CLOSE_CHANNEL);
  685. mISDN_freedchannel(&isac->dch);
  686. }
  687. static void
  688. dbusy_timer_handler(struct isac_hw *isac)
  689. {
  690. int rbch, star;
  691. u_long flags;
  692. if (test_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) {
  693. spin_lock_irqsave(isac->hwlock, flags);
  694. rbch = ReadISAC(isac, ISAC_RBCH);
  695. star = ReadISAC(isac, ISAC_STAR);
  696. pr_debug("%s: D-Channel Busy RBCH %02x STAR %02x\n",
  697. isac->name, rbch, star);
  698. if (rbch & ISAC_RBCH_XAC) /* D-Channel Busy */
  699. test_and_set_bit(FLG_L1_BUSY, &isac->dch.Flags);
  700. else {
  701. /* discard frame; reset transceiver */
  702. test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags);
  703. if (isac->dch.tx_idx)
  704. isac->dch.tx_idx = 0;
  705. else
  706. pr_info("%s: ISAC D-Channel Busy no tx_idx\n",
  707. isac->name);
  708. /* Transmitter reset */
  709. WriteISAC(isac, ISAC_CMDR, 0x01);
  710. }
  711. spin_unlock_irqrestore(isac->hwlock, flags);
  712. }
  713. }
  714. static int
  715. open_dchannel(struct isac_hw *isac, struct channel_req *rq)
  716. {
  717. pr_debug("%s: %s dev(%d) open from %p\n", isac->name, __func__,
  718. isac->dch.dev.id, __builtin_return_address(1));
  719. if (rq->protocol != ISDN_P_TE_S0)
  720. return -EINVAL;
  721. if (rq->adr.channel == 1)
  722. /* E-Channel not supported */
  723. return -EINVAL;
  724. rq->ch = &isac->dch.dev.D;
  725. rq->ch->protocol = rq->protocol;
  726. if (isac->dch.state == 7)
  727. _queue_data(rq->ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
  728. 0, NULL, GFP_KERNEL);
  729. return 0;
  730. }
  731. static const char *ISACVer[] =
  732. {"2086/2186 V1.1", "2085 B1", "2085 B2",
  733. "2085 V2.3"};
  734. static int
  735. isac_init(struct isac_hw *isac)
  736. {
  737. u8 val;
  738. int err = 0;
  739. if (!isac->dch.l1) {
  740. err = create_l1(&isac->dch, isac_l1cmd);
  741. if (err)
  742. return err;
  743. }
  744. isac->mon_tx = NULL;
  745. isac->mon_rx = NULL;
  746. isac->dch.timer.function = (void *) dbusy_timer_handler;
  747. isac->dch.timer.data = (long)isac;
  748. init_timer(&isac->dch.timer);
  749. isac->mocr = 0xaa;
  750. if (isac->type & IPAC_TYPE_ISACX) {
  751. /* Disable all IRQ */
  752. WriteISAC(isac, ISACX_MASK, 0xff);
  753. val = ReadISAC(isac, ISACX_STARD);
  754. pr_debug("%s: ISACX STARD %x\n", isac->name, val);
  755. val = ReadISAC(isac, ISACX_ISTAD);
  756. pr_debug("%s: ISACX ISTAD %x\n", isac->name, val);
  757. val = ReadISAC(isac, ISACX_ISTA);
  758. pr_debug("%s: ISACX ISTA %x\n", isac->name, val);
  759. /* clear LDD */
  760. WriteISAC(isac, ISACX_TR_CONF0, 0x00);
  761. /* enable transmitter */
  762. WriteISAC(isac, ISACX_TR_CONF2, 0x00);
  763. /* transparent mode 0, RAC, stop/go */
  764. WriteISAC(isac, ISACX_MODED, 0xc9);
  765. /* all HDLC IRQ unmasked */
  766. val = ReadISAC(isac, ISACX_ID);
  767. if (isac->dch.debug & DEBUG_HW)
  768. pr_notice("%s: ISACX Design ID %x\n",
  769. isac->name, val & 0x3f);
  770. val = ReadISAC(isac, ISACX_CIR0);
  771. pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val);
  772. isac->state = val >> 4;
  773. isac_ph_state_change(isac);
  774. ph_command(isac, ISAC_CMD_RS);
  775. WriteISAC(isac, ISACX_MASK, IPACX__ON);
  776. WriteISAC(isac, ISACX_MASKD, 0x00);
  777. } else { /* old isac */
  778. WriteISAC(isac, ISAC_MASK, 0xff);
  779. val = ReadISAC(isac, ISAC_STAR);
  780. pr_debug("%s: ISAC STAR %x\n", isac->name, val);
  781. val = ReadISAC(isac, ISAC_MODE);
  782. pr_debug("%s: ISAC MODE %x\n", isac->name, val);
  783. val = ReadISAC(isac, ISAC_ADF2);
  784. pr_debug("%s: ISAC ADF2 %x\n", isac->name, val);
  785. val = ReadISAC(isac, ISAC_ISTA);
  786. pr_debug("%s: ISAC ISTA %x\n", isac->name, val);
  787. if (val & 0x01) {
  788. val = ReadISAC(isac, ISAC_EXIR);
  789. pr_debug("%s: ISAC EXIR %x\n", isac->name, val);
  790. }
  791. val = ReadISAC(isac, ISAC_RBCH);
  792. if (isac->dch.debug & DEBUG_HW)
  793. pr_notice("%s: ISAC version (%x): %s\n", isac->name,
  794. val, ISACVer[(val >> 5) & 3]);
  795. isac->type |= ((val >> 5) & 3);
  796. if (!isac->adf2)
  797. isac->adf2 = 0x80;
  798. if (!(isac->adf2 & 0x80)) { /* only IOM 2 Mode */
  799. pr_info("%s: only support IOM2 mode but adf2=%02x\n",
  800. isac->name, isac->adf2);
  801. isac_release(isac);
  802. return -EINVAL;
  803. }
  804. WriteISAC(isac, ISAC_ADF2, isac->adf2);
  805. WriteISAC(isac, ISAC_SQXR, 0x2f);
  806. WriteISAC(isac, ISAC_SPCR, 0x00);
  807. WriteISAC(isac, ISAC_STCR, 0x70);
  808. WriteISAC(isac, ISAC_MODE, 0xc9);
  809. WriteISAC(isac, ISAC_TIMR, 0x00);
  810. WriteISAC(isac, ISAC_ADF1, 0x00);
  811. val = ReadISAC(isac, ISAC_CIR0);
  812. pr_debug("%s: ISAC CIR0 %x\n", isac->name, val);
  813. isac->state = (val >> 2) & 0xf;
  814. isac_ph_state_change(isac);
  815. ph_command(isac, ISAC_CMD_RS);
  816. WriteISAC(isac, ISAC_MASK, 0);
  817. }
  818. return err;
  819. }
  820. int
  821. mISDNisac_init(struct isac_hw *isac, void *hw)
  822. {
  823. mISDN_initdchannel(&isac->dch, MAX_DFRAME_LEN_L1, isac_ph_state_bh);
  824. isac->dch.hw = hw;
  825. isac->dch.dev.D.send = isac_l1hw;
  826. isac->init = isac_init;
  827. isac->release = isac_release;
  828. isac->ctrl = isac_ctrl;
  829. isac->open = open_dchannel;
  830. isac->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0);
  831. isac->dch.dev.nrbchan = 2;
  832. return 0;
  833. }
  834. EXPORT_SYMBOL(mISDNisac_init);
  835. static void
  836. waitforCEC(struct hscx_hw *hx)
  837. {
  838. u8 starb, to = 50;
  839. while (to) {
  840. starb = ReadHSCX(hx, IPAC_STARB);
  841. if (!(starb & 0x04))
  842. break;
  843. udelay(1);
  844. to--;
  845. }
  846. if (to < 50)
  847. pr_debug("%s: B%1d CEC %d us\n", hx->ip->name, hx->bch.nr,
  848. 50 - to);
  849. if (!to)
  850. pr_info("%s: B%1d CEC timeout\n", hx->ip->name, hx->bch.nr);
  851. }
  852. static void
  853. waitforXFW(struct hscx_hw *hx)
  854. {
  855. u8 starb, to = 50;
  856. while (to) {
  857. starb = ReadHSCX(hx, IPAC_STARB);
  858. if ((starb & 0x44) == 0x40)
  859. break;
  860. udelay(1);
  861. to--;
  862. }
  863. if (to < 50)
  864. pr_debug("%s: B%1d XFW %d us\n", hx->ip->name, hx->bch.nr,
  865. 50 - to);
  866. if (!to)
  867. pr_info("%s: B%1d XFW timeout\n", hx->ip->name, hx->bch.nr);
  868. }
  869. static void
  870. hscx_cmdr(struct hscx_hw *hx, u8 cmd)
  871. {
  872. if (hx->ip->type & IPAC_TYPE_IPACX)
  873. WriteHSCX(hx, IPACX_CMDRB, cmd);
  874. else {
  875. waitforCEC(hx);
  876. WriteHSCX(hx, IPAC_CMDRB, cmd);
  877. }
  878. }
  879. static void
  880. hscx_empty_fifo(struct hscx_hw *hscx, u8 count)
  881. {
  882. u8 *p;
  883. int maxlen;
  884. pr_debug("%s: B%1d %d\n", hscx->ip->name, hscx->bch.nr, count);
  885. maxlen = bchannel_get_rxbuf(&hscx->bch, count);
  886. if (maxlen < 0) {
  887. hscx_cmdr(hscx, 0x80); /* RMC */
  888. if (hscx->bch.rx_skb)
  889. skb_trim(hscx->bch.rx_skb, 0);
  890. pr_warning("%s.B%d: No bufferspace for %d bytes\n",
  891. hscx->ip->name, hscx->bch.nr, count);
  892. return;
  893. }
  894. p = skb_put(hscx->bch.rx_skb, count);
  895. if (hscx->ip->type & IPAC_TYPE_IPACX)
  896. hscx->ip->read_fifo(hscx->ip->hw,
  897. hscx->off + IPACX_RFIFOB, p, count);
  898. else
  899. hscx->ip->read_fifo(hscx->ip->hw,
  900. hscx->off, p, count);
  901. hscx_cmdr(hscx, 0x80); /* RMC */
  902. if (hscx->bch.debug & DEBUG_HW_BFIFO) {
  903. snprintf(hscx->log, 64, "B%1d-recv %s %d ",
  904. hscx->bch.nr, hscx->ip->name, count);
  905. print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count);
  906. }
  907. }
  908. static void
  909. hscx_fill_fifo(struct hscx_hw *hscx)
  910. {
  911. int count, more;
  912. u8 *p;
  913. if (!hscx->bch.tx_skb)
  914. return;
  915. count = hscx->bch.tx_skb->len - hscx->bch.tx_idx;
  916. if (count <= 0)
  917. return;
  918. p = hscx->bch.tx_skb->data + hscx->bch.tx_idx;
  919. more = test_bit(FLG_TRANSPARENT, &hscx->bch.Flags) ? 1 : 0;
  920. if (count > hscx->fifo_size) {
  921. count = hscx->fifo_size;
  922. more = 1;
  923. }
  924. pr_debug("%s: B%1d %d/%d/%d\n", hscx->ip->name, hscx->bch.nr, count,
  925. hscx->bch.tx_idx, hscx->bch.tx_skb->len);
  926. hscx->bch.tx_idx += count;
  927. if (hscx->ip->type & IPAC_TYPE_IPACX)
  928. hscx->ip->write_fifo(hscx->ip->hw,
  929. hscx->off + IPACX_XFIFOB, p, count);
  930. else {
  931. waitforXFW(hscx);
  932. hscx->ip->write_fifo(hscx->ip->hw,
  933. hscx->off, p, count);
  934. }
  935. hscx_cmdr(hscx, more ? 0x08 : 0x0a);
  936. if (hscx->bch.debug & DEBUG_HW_BFIFO) {
  937. snprintf(hscx->log, 64, "B%1d-send %s %d ",
  938. hscx->bch.nr, hscx->ip->name, count);
  939. print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count);
  940. }
  941. }
  942. static void
  943. hscx_xpr(struct hscx_hw *hx)
  944. {
  945. if (hx->bch.tx_skb && hx->bch.tx_idx < hx->bch.tx_skb->len) {
  946. hscx_fill_fifo(hx);
  947. } else {
  948. if (hx->bch.tx_skb)
  949. dev_kfree_skb(hx->bch.tx_skb);
  950. if (get_next_bframe(&hx->bch))
  951. hscx_fill_fifo(hx);
  952. }
  953. }
  954. static void
  955. ipac_rme(struct hscx_hw *hx)
  956. {
  957. int count;
  958. u8 rstab;
  959. if (hx->ip->type & IPAC_TYPE_IPACX)
  960. rstab = ReadHSCX(hx, IPACX_RSTAB);
  961. else
  962. rstab = ReadHSCX(hx, IPAC_RSTAB);
  963. pr_debug("%s: B%1d RSTAB %02x\n", hx->ip->name, hx->bch.nr, rstab);
  964. if ((rstab & 0xf0) != 0xa0) {
  965. /* !(VFR && !RDO && CRC && !RAB) */
  966. if (!(rstab & 0x80)) {
  967. if (hx->bch.debug & DEBUG_HW_BCHANNEL)
  968. pr_notice("%s: B%1d invalid frame\n",
  969. hx->ip->name, hx->bch.nr);
  970. }
  971. if (rstab & 0x40) {
  972. if (hx->bch.debug & DEBUG_HW_BCHANNEL)
  973. pr_notice("%s: B%1d RDO proto=%x\n",
  974. hx->ip->name, hx->bch.nr,
  975. hx->bch.state);
  976. }
  977. if (!(rstab & 0x20)) {
  978. if (hx->bch.debug & DEBUG_HW_BCHANNEL)
  979. pr_notice("%s: B%1d CRC error\n",
  980. hx->ip->name, hx->bch.nr);
  981. }
  982. hscx_cmdr(hx, 0x80); /* Do RMC */
  983. return;
  984. }
  985. if (hx->ip->type & IPAC_TYPE_IPACX)
  986. count = ReadHSCX(hx, IPACX_RBCLB);
  987. else
  988. count = ReadHSCX(hx, IPAC_RBCLB);
  989. count &= (hx->fifo_size - 1);
  990. if (count == 0)
  991. count = hx->fifo_size;
  992. hscx_empty_fifo(hx, count);
  993. if (!hx->bch.rx_skb)
  994. return;
  995. if (hx->bch.rx_skb->len < 2) {
  996. pr_debug("%s: B%1d frame to short %d\n",
  997. hx->ip->name, hx->bch.nr, hx->bch.rx_skb->len);
  998. skb_trim(hx->bch.rx_skb, 0);
  999. } else {
  1000. skb_trim(hx->bch.rx_skb, hx->bch.rx_skb->len - 1);
  1001. recv_Bchannel(&hx->bch, 0, false);
  1002. }
  1003. }
  1004. static void
  1005. ipac_irq(struct hscx_hw *hx, u8 ista)
  1006. {
  1007. u8 istab, m, exirb = 0;
  1008. if (hx->ip->type & IPAC_TYPE_IPACX)
  1009. istab = ReadHSCX(hx, IPACX_ISTAB);
  1010. else if (hx->ip->type & IPAC_TYPE_IPAC) {
  1011. istab = ReadHSCX(hx, IPAC_ISTAB);
  1012. m = (hx->bch.nr & 1) ? IPAC__EXA : IPAC__EXB;
  1013. if (m & ista) {
  1014. exirb = ReadHSCX(hx, IPAC_EXIRB);
  1015. pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
  1016. hx->bch.nr, exirb);
  1017. }
  1018. } else if (hx->bch.nr & 2) { /* HSCX B */
  1019. if (ista & (HSCX__EXA | HSCX__ICA))
  1020. ipac_irq(&hx->ip->hscx[0], ista);
  1021. if (ista & HSCX__EXB) {
  1022. exirb = ReadHSCX(hx, IPAC_EXIRB);
  1023. pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
  1024. hx->bch.nr, exirb);
  1025. }
  1026. istab = ista & 0xF8;
  1027. } else { /* HSCX A */
  1028. istab = ReadHSCX(hx, IPAC_ISTAB);
  1029. if (ista & HSCX__EXA) {
  1030. exirb = ReadHSCX(hx, IPAC_EXIRB);
  1031. pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
  1032. hx->bch.nr, exirb);
  1033. }
  1034. istab = istab & 0xF8;
  1035. }
  1036. if (exirb & IPAC_B_XDU)
  1037. istab |= IPACX_B_XDU;
  1038. if (exirb & IPAC_B_RFO)
  1039. istab |= IPACX_B_RFO;
  1040. pr_debug("%s: B%1d ISTAB %02x\n", hx->ip->name, hx->bch.nr, istab);
  1041. if (!test_bit(FLG_ACTIVE, &hx->bch.Flags))
  1042. return;
  1043. if (istab & IPACX_B_RME)
  1044. ipac_rme(hx);
  1045. if (istab & IPACX_B_RPF) {
  1046. hscx_empty_fifo(hx, hx->fifo_size);
  1047. if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags))
  1048. recv_Bchannel(&hx->bch, 0, false);
  1049. }
  1050. if (istab & IPACX_B_RFO) {
  1051. pr_debug("%s: B%1d RFO error\n", hx->ip->name, hx->bch.nr);
  1052. hscx_cmdr(hx, 0x40); /* RRES */
  1053. }
  1054. if (istab & IPACX_B_XPR)
  1055. hscx_xpr(hx);
  1056. if (istab & IPACX_B_XDU) {
  1057. if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags)) {
  1058. hscx_fill_fifo(hx);
  1059. return;
  1060. }
  1061. pr_debug("%s: B%1d XDU error at len %d\n", hx->ip->name,
  1062. hx->bch.nr, hx->bch.tx_idx);
  1063. hx->bch.tx_idx = 0;
  1064. hscx_cmdr(hx, 0x01); /* XRES */
  1065. }
  1066. }
  1067. irqreturn_t
  1068. mISDNipac_irq(struct ipac_hw *ipac, int maxloop)
  1069. {
  1070. int cnt = maxloop + 1;
  1071. u8 ista, istad;
  1072. struct isac_hw *isac = &ipac->isac;
  1073. if (ipac->type & IPAC_TYPE_IPACX) {
  1074. ista = ReadIPAC(ipac, ISACX_ISTA);
  1075. while (ista && cnt--) {
  1076. pr_debug("%s: ISTA %02x\n", ipac->name, ista);
  1077. if (ista & IPACX__ICA)
  1078. ipac_irq(&ipac->hscx[0], ista);
  1079. if (ista & IPACX__ICB)
  1080. ipac_irq(&ipac->hscx[1], ista);
  1081. if (ista & (ISACX__ICD | ISACX__CIC))
  1082. mISDNisac_irq(&ipac->isac, ista);
  1083. ista = ReadIPAC(ipac, ISACX_ISTA);
  1084. }
  1085. } else if (ipac->type & IPAC_TYPE_IPAC) {
  1086. ista = ReadIPAC(ipac, IPAC_ISTA);
  1087. while (ista && cnt--) {
  1088. pr_debug("%s: ISTA %02x\n", ipac->name, ista);
  1089. if (ista & (IPAC__ICD | IPAC__EXD)) {
  1090. istad = ReadISAC(isac, ISAC_ISTA);
  1091. pr_debug("%s: ISTAD %02x\n", ipac->name, istad);
  1092. if (istad & IPAC_D_TIN2)
  1093. pr_debug("%s TIN2 irq\n", ipac->name);
  1094. if (ista & IPAC__EXD)
  1095. istad |= 1; /* ISAC EXI */
  1096. mISDNisac_irq(isac, istad);
  1097. }
  1098. if (ista & (IPAC__ICA | IPAC__EXA))
  1099. ipac_irq(&ipac->hscx[0], ista);
  1100. if (ista & (IPAC__ICB | IPAC__EXB))
  1101. ipac_irq(&ipac->hscx[1], ista);
  1102. ista = ReadIPAC(ipac, IPAC_ISTA);
  1103. }
  1104. } else if (ipac->type & IPAC_TYPE_HSCX) {
  1105. while (cnt) {
  1106. ista = ReadIPAC(ipac, IPAC_ISTAB + ipac->hscx[1].off);
  1107. pr_debug("%s: B2 ISTA %02x\n", ipac->name, ista);
  1108. if (ista)
  1109. ipac_irq(&ipac->hscx[1], ista);
  1110. istad = ReadISAC(isac, ISAC_ISTA);
  1111. pr_debug("%s: ISTAD %02x\n", ipac->name, istad);
  1112. if (istad)
  1113. mISDNisac_irq(isac, istad);
  1114. if (0 == (ista | istad))
  1115. break;
  1116. cnt--;
  1117. }
  1118. }
  1119. if (cnt > maxloop) /* only for ISAC/HSCX without PCI IRQ test */
  1120. return IRQ_NONE;
  1121. if (cnt < maxloop)
  1122. pr_debug("%s: %d irqloops cpu%d\n", ipac->name,
  1123. maxloop - cnt, smp_processor_id());
  1124. if (maxloop && !cnt)
  1125. pr_notice("%s: %d IRQ LOOP cpu%d\n", ipac->name,
  1126. maxloop, smp_processor_id());
  1127. return IRQ_HANDLED;
  1128. }
  1129. EXPORT_SYMBOL(mISDNipac_irq);
  1130. static int
  1131. hscx_mode(struct hscx_hw *hscx, u32 bprotocol)
  1132. {
  1133. pr_debug("%s: HSCX %c protocol %x-->%x ch %d\n", hscx->ip->name,
  1134. '@' + hscx->bch.nr, hscx->bch.state, bprotocol, hscx->bch.nr);
  1135. if (hscx->ip->type & IPAC_TYPE_IPACX) {
  1136. if (hscx->bch.nr & 1) { /* B1 and ICA */
  1137. WriteIPAC(hscx->ip, ISACX_BCHA_TSDP_BC1, 0x80);
  1138. WriteIPAC(hscx->ip, ISACX_BCHA_CR, 0x88);
  1139. } else { /* B2 and ICB */
  1140. WriteIPAC(hscx->ip, ISACX_BCHB_TSDP_BC1, 0x81);
  1141. WriteIPAC(hscx->ip, ISACX_BCHB_CR, 0x88);
  1142. }
  1143. switch (bprotocol) {
  1144. case ISDN_P_NONE: /* init */
  1145. WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* rec off */
  1146. WriteHSCX(hscx, IPACX_EXMB, 0x30); /* std adj. */
  1147. WriteHSCX(hscx, IPACX_MASKB, 0xFF); /* ints off */
  1148. hscx_cmdr(hscx, 0x41);
  1149. test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
  1150. test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
  1151. break;
  1152. case ISDN_P_B_RAW:
  1153. WriteHSCX(hscx, IPACX_MODEB, 0x88); /* ex trans */
  1154. WriteHSCX(hscx, IPACX_EXMB, 0x00); /* trans */
  1155. hscx_cmdr(hscx, 0x41);
  1156. WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON);
  1157. test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
  1158. break;
  1159. case ISDN_P_B_HDLC:
  1160. WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* trans */
  1161. WriteHSCX(hscx, IPACX_EXMB, 0x00); /* hdlc,crc */
  1162. hscx_cmdr(hscx, 0x41);
  1163. WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON);
  1164. test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
  1165. break;
  1166. default:
  1167. pr_info("%s: protocol not known %x\n", hscx->ip->name,
  1168. bprotocol);
  1169. return -ENOPROTOOPT;
  1170. }
  1171. } else if (hscx->ip->type & IPAC_TYPE_IPAC) { /* IPAC */
  1172. WriteHSCX(hscx, IPAC_CCR1, 0x82);
  1173. WriteHSCX(hscx, IPAC_CCR2, 0x30);
  1174. WriteHSCX(hscx, IPAC_XCCR, 0x07);
  1175. WriteHSCX(hscx, IPAC_RCCR, 0x07);
  1176. WriteHSCX(hscx, IPAC_TSAX, hscx->slot);
  1177. WriteHSCX(hscx, IPAC_TSAR, hscx->slot);
  1178. switch (bprotocol) {
  1179. case ISDN_P_NONE:
  1180. WriteHSCX(hscx, IPAC_TSAX, 0x1F);
  1181. WriteHSCX(hscx, IPAC_TSAR, 0x1F);
  1182. WriteHSCX(hscx, IPAC_MODEB, 0x84);
  1183. WriteHSCX(hscx, IPAC_CCR1, 0x82);
  1184. WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */
  1185. test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
  1186. test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
  1187. break;
  1188. case ISDN_P_B_RAW:
  1189. WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */
  1190. WriteHSCX(hscx, IPAC_CCR1, 0x82);
  1191. hscx_cmdr(hscx, 0x41);
  1192. WriteHSCX(hscx, IPAC_MASKB, 0);
  1193. test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
  1194. break;
  1195. case ISDN_P_B_HDLC:
  1196. WriteHSCX(hscx, IPAC_MODEB, 0x8c);
  1197. WriteHSCX(hscx, IPAC_CCR1, 0x8a);
  1198. hscx_cmdr(hscx, 0x41);
  1199. WriteHSCX(hscx, IPAC_MASKB, 0);
  1200. test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
  1201. break;
  1202. default:
  1203. pr_info("%s: protocol not known %x\n", hscx->ip->name,
  1204. bprotocol);
  1205. return -ENOPROTOOPT;
  1206. }
  1207. } else if (hscx->ip->type & IPAC_TYPE_HSCX) { /* HSCX */
  1208. WriteHSCX(hscx, IPAC_CCR1, 0x85);
  1209. WriteHSCX(hscx, IPAC_CCR2, 0x30);
  1210. WriteHSCX(hscx, IPAC_XCCR, 0x07);
  1211. WriteHSCX(hscx, IPAC_RCCR, 0x07);
  1212. WriteHSCX(hscx, IPAC_TSAX, hscx->slot);
  1213. WriteHSCX(hscx, IPAC_TSAR, hscx->slot);
  1214. switch (bprotocol) {
  1215. case ISDN_P_NONE:
  1216. WriteHSCX(hscx, IPAC_TSAX, 0x1F);
  1217. WriteHSCX(hscx, IPAC_TSAR, 0x1F);
  1218. WriteHSCX(hscx, IPAC_MODEB, 0x84);
  1219. WriteHSCX(hscx, IPAC_CCR1, 0x85);
  1220. WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */
  1221. test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
  1222. test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
  1223. break;
  1224. case ISDN_P_B_RAW:
  1225. WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */
  1226. WriteHSCX(hscx, IPAC_CCR1, 0x85);
  1227. hscx_cmdr(hscx, 0x41);
  1228. WriteHSCX(hscx, IPAC_MASKB, 0);
  1229. test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
  1230. break;
  1231. case ISDN_P_B_HDLC:
  1232. WriteHSCX(hscx, IPAC_MODEB, 0x8c);
  1233. WriteHSCX(hscx, IPAC_CCR1, 0x8d);
  1234. hscx_cmdr(hscx, 0x41);
  1235. WriteHSCX(hscx, IPAC_MASKB, 0);
  1236. test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
  1237. break;
  1238. default:
  1239. pr_info("%s: protocol not known %x\n", hscx->ip->name,
  1240. bprotocol);
  1241. return -ENOPROTOOPT;
  1242. }
  1243. } else
  1244. return -EINVAL;
  1245. hscx->bch.state = bprotocol;
  1246. return 0;
  1247. }
  1248. static int
  1249. hscx_l2l1(struct mISDNchannel *ch, struct sk_buff *skb)
  1250. {
  1251. struct bchannel *bch = container_of(ch, struct bchannel, ch);
  1252. struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch);
  1253. int ret = -EINVAL;
  1254. struct mISDNhead *hh = mISDN_HEAD_P(skb);
  1255. unsigned long flags;
  1256. switch (hh->prim) {
  1257. case PH_DATA_REQ:
  1258. spin_lock_irqsave(hx->ip->hwlock, flags);
  1259. ret = bchannel_senddata(bch, skb);
  1260. if (ret > 0) { /* direct TX */
  1261. ret = 0;
  1262. hscx_fill_fifo(hx);
  1263. }
  1264. spin_unlock_irqrestore(hx->ip->hwlock, flags);
  1265. return ret;
  1266. case PH_ACTIVATE_REQ:
  1267. spin_lock_irqsave(hx->ip->hwlock, flags);
  1268. if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
  1269. ret = hscx_mode(hx, ch->protocol);
  1270. else
  1271. ret = 0;
  1272. spin_unlock_irqrestore(hx->ip->hwlock, flags);
  1273. if (!ret)
  1274. _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
  1275. NULL, GFP_KERNEL);
  1276. break;
  1277. case PH_DEACTIVATE_REQ:
  1278. spin_lock_irqsave(hx->ip->hwlock, flags);
  1279. mISDN_clear_bchannel(bch);
  1280. hscx_mode(hx, ISDN_P_NONE);
  1281. spin_unlock_irqrestore(hx->ip->hwlock, flags);
  1282. _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
  1283. NULL, GFP_KERNEL);
  1284. ret = 0;
  1285. break;
  1286. default:
  1287. pr_info("%s: %s unknown prim(%x,%x)\n",
  1288. hx->ip->name, __func__, hh->prim, hh->id);
  1289. ret = -EINVAL;
  1290. }
  1291. if (!ret)
  1292. dev_kfree_skb(skb);
  1293. return ret;
  1294. }
  1295. static int
  1296. channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
  1297. {
  1298. return mISDN_ctrl_bchannel(bch, cq);
  1299. }
  1300. static int
  1301. hscx_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
  1302. {
  1303. struct bchannel *bch = container_of(ch, struct bchannel, ch);
  1304. struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch);
  1305. int ret = -EINVAL;
  1306. u_long flags;
  1307. pr_debug("%s: %s cmd:%x %p\n", hx->ip->name, __func__, cmd, arg);
  1308. switch (cmd) {
  1309. case CLOSE_CHANNEL:
  1310. test_and_clear_bit(FLG_OPEN, &bch->Flags);
  1311. spin_lock_irqsave(hx->ip->hwlock, flags);
  1312. mISDN_freebchannel(bch);
  1313. hscx_mode(hx, ISDN_P_NONE);
  1314. spin_unlock_irqrestore(hx->ip->hwlock, flags);
  1315. ch->protocol = ISDN_P_NONE;
  1316. ch->peer = NULL;
  1317. module_put(hx->ip->owner);
  1318. ret = 0;
  1319. break;
  1320. case CONTROL_CHANNEL:
  1321. ret = channel_bctrl(bch, arg);
  1322. break;
  1323. default:
  1324. pr_info("%s: %s unknown prim(%x)\n",
  1325. hx->ip->name, __func__, cmd);
  1326. }
  1327. return ret;
  1328. }
  1329. static void
  1330. free_ipac(struct ipac_hw *ipac)
  1331. {
  1332. isac_release(&ipac->isac);
  1333. }
  1334. static const char *HSCXVer[] =
  1335. {"A1", "?1", "A2", "?3", "A3", "V2.1", "?6", "?7",
  1336. "?8", "?9", "?10", "?11", "?12", "?13", "?14", "???"};
  1337. static void
  1338. hscx_init(struct hscx_hw *hx)
  1339. {
  1340. u8 val;
  1341. WriteHSCX(hx, IPAC_RAH2, 0xFF);
  1342. WriteHSCX(hx, IPAC_XBCH, 0x00);
  1343. WriteHSCX(hx, IPAC_RLCR, 0x00);
  1344. if (hx->ip->type & IPAC_TYPE_HSCX) {
  1345. WriteHSCX(hx, IPAC_CCR1, 0x85);
  1346. val = ReadHSCX(hx, HSCX_VSTR);
  1347. pr_debug("%s: HSCX VSTR %02x\n", hx->ip->name, val);
  1348. if (hx->bch.debug & DEBUG_HW)
  1349. pr_notice("%s: HSCX version %s\n", hx->ip->name,
  1350. HSCXVer[val & 0x0f]);
  1351. } else
  1352. WriteHSCX(hx, IPAC_CCR1, 0x82);
  1353. WriteHSCX(hx, IPAC_CCR2, 0x30);
  1354. WriteHSCX(hx, IPAC_XCCR, 0x07);
  1355. WriteHSCX(hx, IPAC_RCCR, 0x07);
  1356. }
  1357. static int
  1358. ipac_init(struct ipac_hw *ipac)
  1359. {
  1360. u8 val;
  1361. if (ipac->type & IPAC_TYPE_HSCX) {
  1362. hscx_init(&ipac->hscx[0]);
  1363. hscx_init(&ipac->hscx[1]);
  1364. val = ReadIPAC(ipac, IPAC_ID);
  1365. } else if (ipac->type & IPAC_TYPE_IPAC) {
  1366. hscx_init(&ipac->hscx[0]);
  1367. hscx_init(&ipac->hscx[1]);
  1368. WriteIPAC(ipac, IPAC_MASK, IPAC__ON);
  1369. val = ReadIPAC(ipac, IPAC_CONF);
  1370. /* conf is default 0, but can be overwritten by card setup */
  1371. pr_debug("%s: IPAC CONF %02x/%02x\n", ipac->name,
  1372. val, ipac->conf);
  1373. WriteIPAC(ipac, IPAC_CONF, ipac->conf);
  1374. val = ReadIPAC(ipac, IPAC_ID);
  1375. if (ipac->hscx[0].bch.debug & DEBUG_HW)
  1376. pr_notice("%s: IPAC Design ID %02x\n", ipac->name, val);
  1377. }
  1378. /* nothing special for IPACX to do here */
  1379. return isac_init(&ipac->isac);
  1380. }
  1381. static int
  1382. open_bchannel(struct ipac_hw *ipac, struct channel_req *rq)
  1383. {
  1384. struct bchannel *bch;
  1385. if (rq->adr.channel == 0 || rq->adr.channel > 2)
  1386. return -EINVAL;
  1387. if (rq->protocol == ISDN_P_NONE)
  1388. return -EINVAL;
  1389. bch = &ipac->hscx[rq->adr.channel - 1].bch;
  1390. if (test_and_set_bit(FLG_OPEN, &bch->Flags))
  1391. return -EBUSY; /* b-channel can be only open once */
  1392. test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
  1393. bch->ch.protocol = rq->protocol;
  1394. rq->ch = &bch->ch;
  1395. return 0;
  1396. }
  1397. static int
  1398. channel_ctrl(struct ipac_hw *ipac, struct mISDN_ctrl_req *cq)
  1399. {
  1400. int ret = 0;
  1401. switch (cq->op) {
  1402. case MISDN_CTRL_GETOP:
  1403. cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_L1_TIMER3;
  1404. break;
  1405. case MISDN_CTRL_LOOP:
  1406. /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
  1407. if (cq->channel < 0 || cq->channel > 3) {
  1408. ret = -EINVAL;
  1409. break;
  1410. }
  1411. ret = ipac->ctrl(ipac, HW_TESTLOOP, cq->channel);
  1412. break;
  1413. case MISDN_CTRL_L1_TIMER3:
  1414. ret = ipac->isac.ctrl(&ipac->isac, HW_TIMER3_VALUE, cq->p1);
  1415. break;
  1416. default:
  1417. pr_info("%s: unknown CTRL OP %x\n", ipac->name, cq->op);
  1418. ret = -EINVAL;
  1419. break;
  1420. }
  1421. return ret;
  1422. }
  1423. static int
  1424. ipac_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
  1425. {
  1426. struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
  1427. struct dchannel *dch = container_of(dev, struct dchannel, dev);
  1428. struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
  1429. struct ipac_hw *ipac = container_of(isac, struct ipac_hw, isac);
  1430. struct channel_req *rq;
  1431. int err = 0;
  1432. pr_debug("%s: DCTRL: %x %p\n", ipac->name, cmd, arg);
  1433. switch (cmd) {
  1434. case OPEN_CHANNEL:
  1435. rq = arg;
  1436. if (rq->protocol == ISDN_P_TE_S0)
  1437. err = open_dchannel(isac, rq);
  1438. else
  1439. err = open_bchannel(ipac, rq);
  1440. if (err)
  1441. break;
  1442. if (!try_module_get(ipac->owner))
  1443. pr_info("%s: cannot get module\n", ipac->name);
  1444. break;
  1445. case CLOSE_CHANNEL:
  1446. pr_debug("%s: dev(%d) close from %p\n", ipac->name,
  1447. dch->dev.id, __builtin_return_address(0));
  1448. module_put(ipac->owner);
  1449. break;
  1450. case CONTROL_CHANNEL:
  1451. err = channel_ctrl(ipac, arg);
  1452. break;
  1453. default:
  1454. pr_debug("%s: unknown DCTRL command %x\n", ipac->name, cmd);
  1455. return -EINVAL;
  1456. }
  1457. return err;
  1458. }
  1459. u32
  1460. mISDNipac_init(struct ipac_hw *ipac, void *hw)
  1461. {
  1462. u32 ret;
  1463. u8 i;
  1464. ipac->hw = hw;
  1465. if (ipac->isac.dch.debug & DEBUG_HW)
  1466. pr_notice("%s: ipac type %x\n", ipac->name, ipac->type);
  1467. if (ipac->type & IPAC_TYPE_HSCX) {
  1468. ipac->isac.type = IPAC_TYPE_ISAC;
  1469. ipac->hscx[0].off = 0;
  1470. ipac->hscx[1].off = 0x40;
  1471. ipac->hscx[0].fifo_size = 32;
  1472. ipac->hscx[1].fifo_size = 32;
  1473. } else if (ipac->type & IPAC_TYPE_IPAC) {
  1474. ipac->isac.type = IPAC_TYPE_IPAC | IPAC_TYPE_ISAC;
  1475. ipac->hscx[0].off = 0;
  1476. ipac->hscx[1].off = 0x40;
  1477. ipac->hscx[0].fifo_size = 64;
  1478. ipac->hscx[1].fifo_size = 64;
  1479. } else if (ipac->type & IPAC_TYPE_IPACX) {
  1480. ipac->isac.type = IPAC_TYPE_IPACX | IPAC_TYPE_ISACX;
  1481. ipac->hscx[0].off = IPACX_OFF_ICA;
  1482. ipac->hscx[1].off = IPACX_OFF_ICB;
  1483. ipac->hscx[0].fifo_size = 64;
  1484. ipac->hscx[1].fifo_size = 64;
  1485. } else
  1486. return 0;
  1487. mISDNisac_init(&ipac->isac, hw);
  1488. ipac->isac.dch.dev.D.ctrl = ipac_dctrl;
  1489. for (i = 0; i < 2; i++) {
  1490. ipac->hscx[i].bch.nr = i + 1;
  1491. set_channelmap(i + 1, ipac->isac.dch.dev.channelmap);
  1492. list_add(&ipac->hscx[i].bch.ch.list,
  1493. &ipac->isac.dch.dev.bchannels);
  1494. mISDN_initbchannel(&ipac->hscx[i].bch, MAX_DATA_MEM,
  1495. ipac->hscx[i].fifo_size);
  1496. ipac->hscx[i].bch.ch.nr = i + 1;
  1497. ipac->hscx[i].bch.ch.send = &hscx_l2l1;
  1498. ipac->hscx[i].bch.ch.ctrl = hscx_bctrl;
  1499. ipac->hscx[i].bch.hw = hw;
  1500. ipac->hscx[i].ip = ipac;
  1501. /* default values for IOM time slots
  1502. * can be overwriten by card */
  1503. ipac->hscx[i].slot = (i == 0) ? 0x2f : 0x03;
  1504. }
  1505. ipac->init = ipac_init;
  1506. ipac->release = free_ipac;
  1507. ret = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
  1508. (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
  1509. return ret;
  1510. }
  1511. EXPORT_SYMBOL(mISDNipac_init);
  1512. static int __init
  1513. isac_mod_init(void)
  1514. {
  1515. pr_notice("mISDNipac module version %s\n", ISAC_REV);
  1516. return 0;
  1517. }
  1518. static void __exit
  1519. isac_mod_cleanup(void)
  1520. {
  1521. pr_notice("mISDNipac module unloaded\n");
  1522. }
  1523. module_init(isac_mod_init);
  1524. module_exit(isac_mod_cleanup);