psb_device.c 10.0 KB

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  1. /**************************************************************************
  2. * Copyright (c) 2011, Intel Corporation.
  3. * All Rights Reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. *
  18. **************************************************************************/
  19. #include <linux/backlight.h>
  20. #include <drm/drmP.h>
  21. #include <drm/drm.h>
  22. #include "gma_drm.h"
  23. #include "psb_drv.h"
  24. #include "psb_reg.h"
  25. #include "psb_intel_reg.h"
  26. #include "intel_bios.h"
  27. static int psb_output_init(struct drm_device *dev)
  28. {
  29. struct drm_psb_private *dev_priv = dev->dev_private;
  30. psb_intel_lvds_init(dev, &dev_priv->mode_dev);
  31. psb_intel_sdvo_init(dev, SDVOB);
  32. return 0;
  33. }
  34. #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  35. /*
  36. * Poulsbo Backlight Interfaces
  37. */
  38. #define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
  39. #define BLC_PWM_FREQ_CALC_CONSTANT 32
  40. #define MHz 1000000
  41. #define PSB_BLC_PWM_PRECISION_FACTOR 10
  42. #define PSB_BLC_MAX_PWM_REG_FREQ 0xFFFE
  43. #define PSB_BLC_MIN_PWM_REG_FREQ 0x2
  44. #define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
  45. #define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
  46. static int psb_brightness;
  47. static struct backlight_device *psb_backlight_device;
  48. static int psb_get_brightness(struct backlight_device *bd)
  49. {
  50. /* return locally cached var instead of HW read (due to DPST etc.) */
  51. /* FIXME: ideally return actual value in case firmware fiddled with
  52. it */
  53. return psb_brightness;
  54. }
  55. static int psb_backlight_setup(struct drm_device *dev)
  56. {
  57. struct drm_psb_private *dev_priv = dev->dev_private;
  58. unsigned long core_clock;
  59. /* u32 bl_max_freq; */
  60. /* unsigned long value; */
  61. u16 bl_max_freq;
  62. uint32_t value;
  63. uint32_t blc_pwm_precision_factor;
  64. /* get bl_max_freq and pol from dev_priv*/
  65. if (!dev_priv->lvds_bl) {
  66. dev_err(dev->dev, "Has no valid LVDS backlight info\n");
  67. return -ENOENT;
  68. }
  69. bl_max_freq = dev_priv->lvds_bl->freq;
  70. blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
  71. core_clock = dev_priv->core_freq;
  72. value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
  73. value *= blc_pwm_precision_factor;
  74. value /= bl_max_freq;
  75. value /= blc_pwm_precision_factor;
  76. if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
  77. value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
  78. return -ERANGE;
  79. else {
  80. value &= PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR;
  81. REG_WRITE(BLC_PWM_CTL,
  82. (value << PSB_BACKLIGHT_PWM_CTL_SHIFT) | (value));
  83. }
  84. return 0;
  85. }
  86. static int psb_set_brightness(struct backlight_device *bd)
  87. {
  88. struct drm_device *dev = bl_get_data(psb_backlight_device);
  89. int level = bd->props.brightness;
  90. /* Percentage 1-100% being valid */
  91. if (level < 1)
  92. level = 1;
  93. psb_intel_lvds_set_brightness(dev, level);
  94. psb_brightness = level;
  95. return 0;
  96. }
  97. static const struct backlight_ops psb_ops = {
  98. .get_brightness = psb_get_brightness,
  99. .update_status = psb_set_brightness,
  100. };
  101. static int psb_backlight_init(struct drm_device *dev)
  102. {
  103. struct drm_psb_private *dev_priv = dev->dev_private;
  104. int ret;
  105. struct backlight_properties props;
  106. memset(&props, 0, sizeof(struct backlight_properties));
  107. props.max_brightness = 100;
  108. props.type = BACKLIGHT_PLATFORM;
  109. psb_backlight_device = backlight_device_register("psb-bl",
  110. NULL, (void *)dev, &psb_ops, &props);
  111. if (IS_ERR(psb_backlight_device))
  112. return PTR_ERR(psb_backlight_device);
  113. ret = psb_backlight_setup(dev);
  114. if (ret < 0) {
  115. backlight_device_unregister(psb_backlight_device);
  116. psb_backlight_device = NULL;
  117. return ret;
  118. }
  119. psb_backlight_device->props.brightness = 100;
  120. psb_backlight_device->props.max_brightness = 100;
  121. backlight_update_status(psb_backlight_device);
  122. dev_priv->backlight_device = psb_backlight_device;
  123. return 0;
  124. }
  125. #endif
  126. /*
  127. * Provide the Poulsbo specific chip logic and low level methods
  128. * for power management
  129. */
  130. static void psb_init_pm(struct drm_device *dev)
  131. {
  132. struct drm_psb_private *dev_priv = dev->dev_private;
  133. u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL);
  134. gating &= ~3; /* Disable 2D clock gating */
  135. gating |= 1;
  136. PSB_WSGX32(gating, PSB_CR_CLKGATECTL);
  137. PSB_RSGX32(PSB_CR_CLKGATECTL);
  138. }
  139. /**
  140. * psb_save_display_registers - save registers lost on suspend
  141. * @dev: our DRM device
  142. *
  143. * Save the state we need in order to be able to restore the interface
  144. * upon resume from suspend
  145. */
  146. static int psb_save_display_registers(struct drm_device *dev)
  147. {
  148. struct drm_psb_private *dev_priv = dev->dev_private;
  149. struct drm_crtc *crtc;
  150. struct drm_connector *connector;
  151. struct psb_state *regs = &dev_priv->regs.psb;
  152. /* Display arbitration control + watermarks */
  153. regs->saveDSPARB = PSB_RVDC32(DSPARB);
  154. regs->saveDSPFW1 = PSB_RVDC32(DSPFW1);
  155. regs->saveDSPFW2 = PSB_RVDC32(DSPFW2);
  156. regs->saveDSPFW3 = PSB_RVDC32(DSPFW3);
  157. regs->saveDSPFW4 = PSB_RVDC32(DSPFW4);
  158. regs->saveDSPFW5 = PSB_RVDC32(DSPFW5);
  159. regs->saveDSPFW6 = PSB_RVDC32(DSPFW6);
  160. regs->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
  161. /* Save crtc and output state */
  162. mutex_lock(&dev->mode_config.mutex);
  163. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  164. if (drm_helper_crtc_in_use(crtc))
  165. crtc->funcs->save(crtc);
  166. }
  167. list_for_each_entry(connector, &dev->mode_config.connector_list, head)
  168. connector->funcs->save(connector);
  169. mutex_unlock(&dev->mode_config.mutex);
  170. return 0;
  171. }
  172. /**
  173. * psb_restore_display_registers - restore lost register state
  174. * @dev: our DRM device
  175. *
  176. * Restore register state that was lost during suspend and resume.
  177. */
  178. static int psb_restore_display_registers(struct drm_device *dev)
  179. {
  180. struct drm_psb_private *dev_priv = dev->dev_private;
  181. struct drm_crtc *crtc;
  182. struct drm_connector *connector;
  183. struct psb_state *regs = &dev_priv->regs.psb;
  184. /* Display arbitration + watermarks */
  185. PSB_WVDC32(regs->saveDSPARB, DSPARB);
  186. PSB_WVDC32(regs->saveDSPFW1, DSPFW1);
  187. PSB_WVDC32(regs->saveDSPFW2, DSPFW2);
  188. PSB_WVDC32(regs->saveDSPFW3, DSPFW3);
  189. PSB_WVDC32(regs->saveDSPFW4, DSPFW4);
  190. PSB_WVDC32(regs->saveDSPFW5, DSPFW5);
  191. PSB_WVDC32(regs->saveDSPFW6, DSPFW6);
  192. PSB_WVDC32(regs->saveCHICKENBIT, DSPCHICKENBIT);
  193. /*make sure VGA plane is off. it initializes to on after reset!*/
  194. PSB_WVDC32(0x80000000, VGACNTRL);
  195. mutex_lock(&dev->mode_config.mutex);
  196. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
  197. if (drm_helper_crtc_in_use(crtc))
  198. crtc->funcs->restore(crtc);
  199. list_for_each_entry(connector, &dev->mode_config.connector_list, head)
  200. connector->funcs->restore(connector);
  201. mutex_unlock(&dev->mode_config.mutex);
  202. return 0;
  203. }
  204. static int psb_power_down(struct drm_device *dev)
  205. {
  206. return 0;
  207. }
  208. static int psb_power_up(struct drm_device *dev)
  209. {
  210. return 0;
  211. }
  212. static void psb_get_core_freq(struct drm_device *dev)
  213. {
  214. uint32_t clock;
  215. struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
  216. struct drm_psb_private *dev_priv = dev->dev_private;
  217. /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
  218. /*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
  219. pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
  220. pci_read_config_dword(pci_root, 0xD4, &clock);
  221. pci_dev_put(pci_root);
  222. switch (clock & 0x07) {
  223. case 0:
  224. dev_priv->core_freq = 100;
  225. break;
  226. case 1:
  227. dev_priv->core_freq = 133;
  228. break;
  229. case 2:
  230. dev_priv->core_freq = 150;
  231. break;
  232. case 3:
  233. dev_priv->core_freq = 178;
  234. break;
  235. case 4:
  236. dev_priv->core_freq = 200;
  237. break;
  238. case 5:
  239. case 6:
  240. case 7:
  241. dev_priv->core_freq = 266;
  242. default:
  243. dev_priv->core_freq = 0;
  244. }
  245. }
  246. /* Poulsbo */
  247. static const struct psb_offset psb_regmap[2] = {
  248. {
  249. .fp0 = FPA0,
  250. .fp1 = FPA1,
  251. .cntr = DSPACNTR,
  252. .conf = PIPEACONF,
  253. .src = PIPEASRC,
  254. .dpll = DPLL_A,
  255. .htotal = HTOTAL_A,
  256. .hblank = HBLANK_A,
  257. .hsync = HSYNC_A,
  258. .vtotal = VTOTAL_A,
  259. .vblank = VBLANK_A,
  260. .vsync = VSYNC_A,
  261. .stride = DSPASTRIDE,
  262. .size = DSPASIZE,
  263. .pos = DSPAPOS,
  264. .base = DSPABASE,
  265. .surf = DSPASURF,
  266. .addr = DSPABASE,
  267. .status = PIPEASTAT,
  268. .linoff = DSPALINOFF,
  269. .tileoff = DSPATILEOFF,
  270. .palette = PALETTE_A,
  271. },
  272. {
  273. .fp0 = FPB0,
  274. .fp1 = FPB1,
  275. .cntr = DSPBCNTR,
  276. .conf = PIPEBCONF,
  277. .src = PIPEBSRC,
  278. .dpll = DPLL_B,
  279. .htotal = HTOTAL_B,
  280. .hblank = HBLANK_B,
  281. .hsync = HSYNC_B,
  282. .vtotal = VTOTAL_B,
  283. .vblank = VBLANK_B,
  284. .vsync = VSYNC_B,
  285. .stride = DSPBSTRIDE,
  286. .size = DSPBSIZE,
  287. .pos = DSPBPOS,
  288. .base = DSPBBASE,
  289. .surf = DSPBSURF,
  290. .addr = DSPBBASE,
  291. .status = PIPEBSTAT,
  292. .linoff = DSPBLINOFF,
  293. .tileoff = DSPBTILEOFF,
  294. .palette = PALETTE_B,
  295. }
  296. };
  297. static int psb_chip_setup(struct drm_device *dev)
  298. {
  299. struct drm_psb_private *dev_priv = dev->dev_private;
  300. dev_priv->regmap = psb_regmap;
  301. psb_get_core_freq(dev);
  302. gma_intel_setup_gmbus(dev);
  303. psb_intel_opregion_init(dev);
  304. psb_intel_init_bios(dev);
  305. return 0;
  306. }
  307. /* Not exactly an erratum more an irritation */
  308. static void psb_chip_errata(struct drm_device *dev)
  309. {
  310. struct drm_psb_private *dev_priv = dev->dev_private;
  311. psb_lid_timer_init(dev_priv);
  312. }
  313. static void psb_chip_teardown(struct drm_device *dev)
  314. {
  315. struct drm_psb_private *dev_priv = dev->dev_private;
  316. psb_lid_timer_takedown(dev_priv);
  317. gma_intel_teardown_gmbus(dev);
  318. }
  319. const struct psb_ops psb_chip_ops = {
  320. .name = "Poulsbo",
  321. .accel_2d = 1,
  322. .pipes = 2,
  323. .crtcs = 2,
  324. .hdmi_mask = (1 << 0),
  325. .lvds_mask = (1 << 1),
  326. .sgx_offset = PSB_SGX_OFFSET,
  327. .chip_setup = psb_chip_setup,
  328. .chip_teardown = psb_chip_teardown,
  329. .errata = psb_chip_errata,
  330. .crtc_helper = &psb_intel_helper_funcs,
  331. .crtc_funcs = &psb_intel_crtc_funcs,
  332. .output_init = psb_output_init,
  333. #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  334. .backlight_init = psb_backlight_init,
  335. #endif
  336. .init_pm = psb_init_pm,
  337. .save_regs = psb_save_display_registers,
  338. .restore_regs = psb_restore_display_registers,
  339. .power_down = psb_power_down,
  340. .power_up = psb_power_up,
  341. };