musb_dsps.c 19 KB

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  1. /*
  2. * Texas Instruments DSPS platforms "glue layer"
  3. *
  4. * Copyright (C) 2012, by Texas Instruments
  5. *
  6. * Based on the am35x "glue layer" code.
  7. *
  8. * This file is part of the Inventra Controller Driver for Linux.
  9. *
  10. * The Inventra Controller Driver for Linux is free software; you
  11. * can redistribute it and/or modify it under the terms of the GNU
  12. * General Public License version 2 as published by the Free Software
  13. * Foundation.
  14. *
  15. * The Inventra Controller Driver for Linux is distributed in
  16. * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  17. * without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  19. * License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with The Inventra Controller Driver for Linux ; if not,
  23. * write to the Free Software Foundation, Inc., 59 Temple Place,
  24. * Suite 330, Boston, MA 02111-1307 USA
  25. *
  26. * musb_dsps.c will be a common file for all the TI DSPS platforms
  27. * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
  28. * For now only ti81x is using this and in future davinci.c, am35x.c
  29. * da8xx.c would be merged to this file after testing.
  30. */
  31. #include <linux/init.h>
  32. #include <linux/io.h>
  33. #include <linux/err.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/pm_runtime.h>
  37. #include <linux/module.h>
  38. #include <linux/of.h>
  39. #include <linux/of_device.h>
  40. #include <linux/of_address.h>
  41. #include <plat/usb.h>
  42. #include "musb_core.h"
  43. /**
  44. * avoid using musb_readx()/musb_writex() as glue layer should not be
  45. * dependent on musb core layer symbols.
  46. */
  47. static inline u8 dsps_readb(const void __iomem *addr, unsigned offset)
  48. { return __raw_readb(addr + offset); }
  49. static inline u32 dsps_readl(const void __iomem *addr, unsigned offset)
  50. { return __raw_readl(addr + offset); }
  51. static inline void dsps_writeb(void __iomem *addr, unsigned offset, u8 data)
  52. { __raw_writeb(data, addr + offset); }
  53. static inline void dsps_writel(void __iomem *addr, unsigned offset, u32 data)
  54. { __raw_writel(data, addr + offset); }
  55. /**
  56. * DSPS musb wrapper register offset.
  57. * FIXME: This should be expanded to have all the wrapper registers from TI DSPS
  58. * musb ips.
  59. */
  60. struct dsps_musb_wrapper {
  61. u16 revision;
  62. u16 control;
  63. u16 status;
  64. u16 eoi;
  65. u16 epintr_set;
  66. u16 epintr_clear;
  67. u16 epintr_status;
  68. u16 coreintr_set;
  69. u16 coreintr_clear;
  70. u16 coreintr_status;
  71. u16 phy_utmi;
  72. u16 mode;
  73. /* bit positions for control */
  74. unsigned reset:5;
  75. /* bit positions for interrupt */
  76. unsigned usb_shift:5;
  77. u32 usb_mask;
  78. u32 usb_bitmap;
  79. unsigned drvvbus:5;
  80. unsigned txep_shift:5;
  81. u32 txep_mask;
  82. u32 txep_bitmap;
  83. unsigned rxep_shift:5;
  84. u32 rxep_mask;
  85. u32 rxep_bitmap;
  86. /* bit positions for phy_utmi */
  87. unsigned otg_disable:5;
  88. /* bit positions for mode */
  89. unsigned iddig:5;
  90. /* miscellaneous stuff */
  91. u32 musb_core_offset;
  92. u8 poll_seconds;
  93. };
  94. /**
  95. * DSPS glue structure.
  96. */
  97. struct dsps_glue {
  98. struct device *dev;
  99. struct platform_device *musb; /* child musb pdev */
  100. const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */
  101. struct timer_list timer; /* otg_workaround timer */
  102. };
  103. /**
  104. * dsps_musb_enable - enable interrupts
  105. */
  106. static void dsps_musb_enable(struct musb *musb)
  107. {
  108. struct device *dev = musb->controller;
  109. struct platform_device *pdev = to_platform_device(dev->parent);
  110. struct dsps_glue *glue = platform_get_drvdata(pdev);
  111. const struct dsps_musb_wrapper *wrp = glue->wrp;
  112. void __iomem *reg_base = musb->ctrl_base;
  113. u32 epmask, coremask;
  114. /* Workaround: setup IRQs through both register sets. */
  115. epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) |
  116. ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift);
  117. coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);
  118. dsps_writel(reg_base, wrp->epintr_set, epmask);
  119. dsps_writel(reg_base, wrp->coreintr_set, coremask);
  120. /* Force the DRVVBUS IRQ so we can start polling for ID change. */
  121. dsps_writel(reg_base, wrp->coreintr_set,
  122. (1 << wrp->drvvbus) << wrp->usb_shift);
  123. }
  124. /**
  125. * dsps_musb_disable - disable HDRC and flush interrupts
  126. */
  127. static void dsps_musb_disable(struct musb *musb)
  128. {
  129. struct device *dev = musb->controller;
  130. struct platform_device *pdev = to_platform_device(dev->parent);
  131. struct dsps_glue *glue = platform_get_drvdata(pdev);
  132. const struct dsps_musb_wrapper *wrp = glue->wrp;
  133. void __iomem *reg_base = musb->ctrl_base;
  134. dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
  135. dsps_writel(reg_base, wrp->epintr_clear,
  136. wrp->txep_bitmap | wrp->rxep_bitmap);
  137. dsps_writeb(musb->mregs, MUSB_DEVCTL, 0);
  138. dsps_writel(reg_base, wrp->eoi, 0);
  139. }
  140. static void otg_timer(unsigned long _musb)
  141. {
  142. struct musb *musb = (void *)_musb;
  143. void __iomem *mregs = musb->mregs;
  144. struct device *dev = musb->controller;
  145. struct platform_device *pdev = to_platform_device(dev->parent);
  146. struct dsps_glue *glue = platform_get_drvdata(pdev);
  147. const struct dsps_musb_wrapper *wrp = glue->wrp;
  148. u8 devctl;
  149. unsigned long flags;
  150. /*
  151. * We poll because DSPS IP's won't expose several OTG-critical
  152. * status change events (from the transceiver) otherwise.
  153. */
  154. devctl = dsps_readb(mregs, MUSB_DEVCTL);
  155. dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
  156. otg_state_string(musb->xceiv->state));
  157. spin_lock_irqsave(&musb->lock, flags);
  158. switch (musb->xceiv->state) {
  159. case OTG_STATE_A_WAIT_BCON:
  160. devctl &= ~MUSB_DEVCTL_SESSION;
  161. dsps_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  162. devctl = dsps_readb(musb->mregs, MUSB_DEVCTL);
  163. if (devctl & MUSB_DEVCTL_BDEVICE) {
  164. musb->xceiv->state = OTG_STATE_B_IDLE;
  165. MUSB_DEV_MODE(musb);
  166. } else {
  167. musb->xceiv->state = OTG_STATE_A_IDLE;
  168. MUSB_HST_MODE(musb);
  169. }
  170. break;
  171. case OTG_STATE_A_WAIT_VFALL:
  172. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  173. dsps_writel(musb->ctrl_base, wrp->coreintr_set,
  174. MUSB_INTR_VBUSERROR << wrp->usb_shift);
  175. break;
  176. case OTG_STATE_B_IDLE:
  177. devctl = dsps_readb(mregs, MUSB_DEVCTL);
  178. if (devctl & MUSB_DEVCTL_BDEVICE)
  179. mod_timer(&glue->timer,
  180. jiffies + wrp->poll_seconds * HZ);
  181. else
  182. musb->xceiv->state = OTG_STATE_A_IDLE;
  183. break;
  184. default:
  185. break;
  186. }
  187. spin_unlock_irqrestore(&musb->lock, flags);
  188. }
  189. static void dsps_musb_try_idle(struct musb *musb, unsigned long timeout)
  190. {
  191. struct device *dev = musb->controller;
  192. struct platform_device *pdev = to_platform_device(dev->parent);
  193. struct dsps_glue *glue = platform_get_drvdata(pdev);
  194. static unsigned long last_timer;
  195. if (timeout == 0)
  196. timeout = jiffies + msecs_to_jiffies(3);
  197. /* Never idle if active, or when VBUS timeout is not set as host */
  198. if (musb->is_active || (musb->a_wait_bcon == 0 &&
  199. musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
  200. dev_dbg(musb->controller, "%s active, deleting timer\n",
  201. otg_state_string(musb->xceiv->state));
  202. del_timer(&glue->timer);
  203. last_timer = jiffies;
  204. return;
  205. }
  206. if (time_after(last_timer, timeout) && timer_pending(&glue->timer)) {
  207. dev_dbg(musb->controller,
  208. "Longer idle timer already pending, ignoring...\n");
  209. return;
  210. }
  211. last_timer = timeout;
  212. dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
  213. otg_state_string(musb->xceiv->state),
  214. jiffies_to_msecs(timeout - jiffies));
  215. mod_timer(&glue->timer, timeout);
  216. }
  217. static irqreturn_t dsps_interrupt(int irq, void *hci)
  218. {
  219. struct musb *musb = hci;
  220. void __iomem *reg_base = musb->ctrl_base;
  221. struct device *dev = musb->controller;
  222. struct platform_device *pdev = to_platform_device(dev->parent);
  223. struct dsps_glue *glue = platform_get_drvdata(pdev);
  224. const struct dsps_musb_wrapper *wrp = glue->wrp;
  225. unsigned long flags;
  226. irqreturn_t ret = IRQ_NONE;
  227. u32 epintr, usbintr;
  228. spin_lock_irqsave(&musb->lock, flags);
  229. /* Get endpoint interrupts */
  230. epintr = dsps_readl(reg_base, wrp->epintr_status);
  231. musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;
  232. musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;
  233. if (epintr)
  234. dsps_writel(reg_base, wrp->epintr_status, epintr);
  235. /* Get usb core interrupts */
  236. usbintr = dsps_readl(reg_base, wrp->coreintr_status);
  237. if (!usbintr && !epintr)
  238. goto eoi;
  239. musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift;
  240. if (usbintr)
  241. dsps_writel(reg_base, wrp->coreintr_status, usbintr);
  242. dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",
  243. usbintr, epintr);
  244. /*
  245. * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
  246. * DSPS IP's missing ID change IRQ. We need an ID change IRQ to
  247. * switch appropriately between halves of the OTG state machine.
  248. * Managing DEVCTL.SESSION per Mentor docs requires that we know its
  249. * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
  250. * Also, DRVVBUS pulses for SRP (but not at 5V) ...
  251. */
  252. if (usbintr & MUSB_INTR_BABBLE)
  253. pr_info("CAUTION: musb: Babble Interrupt Occured\n");
  254. if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {
  255. int drvvbus = dsps_readl(reg_base, wrp->status);
  256. void __iomem *mregs = musb->mregs;
  257. u8 devctl = dsps_readb(mregs, MUSB_DEVCTL);
  258. int err;
  259. err = musb->int_usb & MUSB_INTR_VBUSERROR;
  260. if (err) {
  261. /*
  262. * The Mentor core doesn't debounce VBUS as needed
  263. * to cope with device connect current spikes. This
  264. * means it's not uncommon for bus-powered devices
  265. * to get VBUS errors during enumeration.
  266. *
  267. * This is a workaround, but newer RTL from Mentor
  268. * seems to allow a better one: "re"-starting sessions
  269. * without waiting for VBUS to stop registering in
  270. * devctl.
  271. */
  272. musb->int_usb &= ~MUSB_INTR_VBUSERROR;
  273. musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
  274. mod_timer(&glue->timer,
  275. jiffies + wrp->poll_seconds * HZ);
  276. WARNING("VBUS error workaround (delay coming)\n");
  277. } else if (drvvbus) {
  278. musb->is_active = 1;
  279. MUSB_HST_MODE(musb);
  280. musb->xceiv->otg->default_a = 1;
  281. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  282. del_timer(&glue->timer);
  283. } else {
  284. musb->is_active = 0;
  285. MUSB_DEV_MODE(musb);
  286. musb->xceiv->otg->default_a = 0;
  287. musb->xceiv->state = OTG_STATE_B_IDLE;
  288. }
  289. /* NOTE: this must complete power-on within 100 ms. */
  290. dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
  291. drvvbus ? "on" : "off",
  292. otg_state_string(musb->xceiv->state),
  293. err ? " ERROR" : "",
  294. devctl);
  295. ret = IRQ_HANDLED;
  296. }
  297. if (musb->int_tx || musb->int_rx || musb->int_usb)
  298. ret |= musb_interrupt(musb);
  299. eoi:
  300. /* EOI needs to be written for the IRQ to be re-asserted. */
  301. if (ret == IRQ_HANDLED || epintr || usbintr)
  302. dsps_writel(reg_base, wrp->eoi, 1);
  303. /* Poll for ID change */
  304. if (musb->xceiv->state == OTG_STATE_B_IDLE)
  305. mod_timer(&glue->timer, jiffies + wrp->poll_seconds * HZ);
  306. spin_unlock_irqrestore(&musb->lock, flags);
  307. return ret;
  308. }
  309. static int dsps_musb_init(struct musb *musb)
  310. {
  311. struct device *dev = musb->controller;
  312. struct musb_hdrc_platform_data *plat = dev->platform_data;
  313. struct platform_device *pdev = to_platform_device(dev->parent);
  314. struct dsps_glue *glue = platform_get_drvdata(pdev);
  315. const struct dsps_musb_wrapper *wrp = glue->wrp;
  316. struct omap_musb_board_data *data = plat->board_data;
  317. void __iomem *reg_base = musb->ctrl_base;
  318. u32 rev, val;
  319. int status;
  320. /* mentor core register starts at offset of 0x400 from musb base */
  321. musb->mregs += wrp->musb_core_offset;
  322. /* NOP driver needs change if supporting dual instance */
  323. usb_nop_xceiv_register();
  324. musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
  325. if (IS_ERR_OR_NULL(musb->xceiv))
  326. return -ENODEV;
  327. /* Returns zero if e.g. not clocked */
  328. rev = dsps_readl(reg_base, wrp->revision);
  329. if (!rev) {
  330. status = -ENODEV;
  331. goto err0;
  332. }
  333. setup_timer(&glue->timer, otg_timer, (unsigned long) musb);
  334. /* Reset the musb */
  335. dsps_writel(reg_base, wrp->control, (1 << wrp->reset));
  336. /* Start the on-chip PHY and its PLL. */
  337. if (data->set_phy_power)
  338. data->set_phy_power(1);
  339. musb->isr = dsps_interrupt;
  340. /* reset the otgdisable bit, needed for host mode to work */
  341. val = dsps_readl(reg_base, wrp->phy_utmi);
  342. val &= ~(1 << wrp->otg_disable);
  343. dsps_writel(musb->ctrl_base, wrp->phy_utmi, val);
  344. /* clear level interrupt */
  345. dsps_writel(reg_base, wrp->eoi, 0);
  346. return 0;
  347. err0:
  348. usb_put_phy(musb->xceiv);
  349. usb_nop_xceiv_unregister();
  350. return status;
  351. }
  352. static int dsps_musb_exit(struct musb *musb)
  353. {
  354. struct device *dev = musb->controller;
  355. struct musb_hdrc_platform_data *plat = dev->platform_data;
  356. struct omap_musb_board_data *data = plat->board_data;
  357. struct platform_device *pdev = to_platform_device(dev->parent);
  358. struct dsps_glue *glue = platform_get_drvdata(pdev);
  359. del_timer_sync(&glue->timer);
  360. /* Shutdown the on-chip PHY and its PLL. */
  361. if (data->set_phy_power)
  362. data->set_phy_power(0);
  363. /* NOP driver needs change if supporting dual instance */
  364. usb_put_phy(musb->xceiv);
  365. usb_nop_xceiv_unregister();
  366. return 0;
  367. }
  368. static struct musb_platform_ops dsps_ops = {
  369. .init = dsps_musb_init,
  370. .exit = dsps_musb_exit,
  371. .enable = dsps_musb_enable,
  372. .disable = dsps_musb_disable,
  373. .try_idle = dsps_musb_try_idle,
  374. };
  375. static u64 musb_dmamask = DMA_BIT_MASK(32);
  376. static int __devinit dsps_create_musb_pdev(struct dsps_glue *glue, u8 id)
  377. {
  378. struct device *dev = glue->dev;
  379. struct platform_device *pdev = to_platform_device(dev);
  380. struct musb_hdrc_platform_data *pdata = dev->platform_data;
  381. struct platform_device *musb;
  382. struct resource *res;
  383. struct resource resources[2];
  384. char res_name[10];
  385. int ret;
  386. /* get memory resource */
  387. sprintf(res_name, "musb%d", id);
  388. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name);
  389. if (!res) {
  390. dev_err(dev, "%s get mem resource failed\n", res_name);
  391. ret = -ENODEV;
  392. goto err0;
  393. }
  394. res->parent = NULL;
  395. resources[0] = *res;
  396. /* get irq resource */
  397. sprintf(res_name, "musb%d-irq", id);
  398. res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res_name);
  399. if (!res) {
  400. dev_err(dev, "%s get irq resource failed\n", res_name);
  401. ret = -ENODEV;
  402. goto err0;
  403. }
  404. strcpy((u8 *)res->name, "mc");
  405. res->parent = NULL;
  406. resources[1] = *res;
  407. /* allocate the child platform device */
  408. musb = platform_device_alloc("musb-hdrc", -1);
  409. if (!musb) {
  410. dev_err(dev, "failed to allocate musb device\n");
  411. ret = -ENOMEM;
  412. goto err0;
  413. }
  414. musb->dev.parent = dev;
  415. musb->dev.dma_mask = &musb_dmamask;
  416. musb->dev.coherent_dma_mask = musb_dmamask;
  417. glue->musb = musb;
  418. pdata->platform_ops = &dsps_ops;
  419. ret = platform_device_add_resources(musb, resources, 2);
  420. if (ret) {
  421. dev_err(dev, "failed to add resources\n");
  422. goto err1;
  423. }
  424. ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
  425. if (ret) {
  426. dev_err(dev, "failed to add platform_data\n");
  427. goto err1;
  428. }
  429. ret = platform_device_add(musb);
  430. if (ret) {
  431. dev_err(dev, "failed to register musb device\n");
  432. goto err1;
  433. }
  434. return 0;
  435. err1:
  436. platform_device_put(musb);
  437. err0:
  438. return ret;
  439. }
  440. static void __devexit dsps_delete_musb_pdev(struct dsps_glue *glue)
  441. {
  442. platform_device_del(glue->musb);
  443. platform_device_put(glue->musb);
  444. }
  445. static int __devinit dsps_probe(struct platform_device *pdev)
  446. {
  447. const struct platform_device_id *id = platform_get_device_id(pdev);
  448. const struct dsps_musb_wrapper *wrp =
  449. (struct dsps_musb_wrapper *)id->driver_data;
  450. struct dsps_glue *glue;
  451. struct resource *iomem;
  452. int ret;
  453. /* allocate glue */
  454. glue = kzalloc(sizeof(*glue), GFP_KERNEL);
  455. if (!glue) {
  456. dev_err(&pdev->dev, "unable to allocate glue memory\n");
  457. ret = -ENOMEM;
  458. goto err0;
  459. }
  460. /* get memory resource */
  461. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  462. if (!iomem) {
  463. dev_err(&pdev->dev, "failed to get usbss mem resourse\n");
  464. ret = -ENODEV;
  465. goto err1;
  466. }
  467. glue->dev = &pdev->dev;
  468. glue->wrp = kmemdup(wrp, sizeof(*wrp), GFP_KERNEL);
  469. if (!glue->wrp) {
  470. dev_err(&pdev->dev, "failed to duplicate wrapper struct memory\n");
  471. ret = -ENOMEM;
  472. goto err1;
  473. }
  474. platform_set_drvdata(pdev, glue);
  475. /* create the child platform device for first instances of musb */
  476. ret = dsps_create_musb_pdev(glue, 0);
  477. if (ret != 0) {
  478. dev_err(&pdev->dev, "failed to create child pdev\n");
  479. goto err2;
  480. }
  481. /* enable the usbss clocks */
  482. pm_runtime_enable(&pdev->dev);
  483. ret = pm_runtime_get_sync(&pdev->dev);
  484. if (ret < 0) {
  485. dev_err(&pdev->dev, "pm_runtime_get_sync FAILED");
  486. goto err3;
  487. }
  488. return 0;
  489. err3:
  490. pm_runtime_disable(&pdev->dev);
  491. err2:
  492. kfree(glue->wrp);
  493. err1:
  494. kfree(glue);
  495. err0:
  496. return ret;
  497. }
  498. static int __devexit dsps_remove(struct platform_device *pdev)
  499. {
  500. struct dsps_glue *glue = platform_get_drvdata(pdev);
  501. /* delete the child platform device */
  502. dsps_delete_musb_pdev(glue);
  503. /* disable usbss clocks */
  504. pm_runtime_put(&pdev->dev);
  505. pm_runtime_disable(&pdev->dev);
  506. kfree(glue->wrp);
  507. kfree(glue);
  508. return 0;
  509. }
  510. #ifdef CONFIG_PM_SLEEP
  511. static int dsps_suspend(struct device *dev)
  512. {
  513. struct musb_hdrc_platform_data *plat = dev->platform_data;
  514. struct omap_musb_board_data *data = plat->board_data;
  515. /* Shutdown the on-chip PHY and its PLL. */
  516. if (data->set_phy_power)
  517. data->set_phy_power(0);
  518. return 0;
  519. }
  520. static int dsps_resume(struct device *dev)
  521. {
  522. struct musb_hdrc_platform_data *plat = dev->platform_data;
  523. struct omap_musb_board_data *data = plat->board_data;
  524. /* Start the on-chip PHY and its PLL. */
  525. if (data->set_phy_power)
  526. data->set_phy_power(1);
  527. return 0;
  528. }
  529. #endif
  530. static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume);
  531. static const struct dsps_musb_wrapper ti81xx_driver_data __devinitconst = {
  532. .revision = 0x00,
  533. .control = 0x14,
  534. .status = 0x18,
  535. .eoi = 0x24,
  536. .epintr_set = 0x38,
  537. .epintr_clear = 0x40,
  538. .epintr_status = 0x30,
  539. .coreintr_set = 0x3c,
  540. .coreintr_clear = 0x44,
  541. .coreintr_status = 0x34,
  542. .phy_utmi = 0xe0,
  543. .mode = 0xe8,
  544. .reset = 0,
  545. .otg_disable = 21,
  546. .iddig = 8,
  547. .usb_shift = 0,
  548. .usb_mask = 0x1ff,
  549. .usb_bitmap = (0x1ff << 0),
  550. .drvvbus = 8,
  551. .txep_shift = 0,
  552. .txep_mask = 0xffff,
  553. .txep_bitmap = (0xffff << 0),
  554. .rxep_shift = 16,
  555. .rxep_mask = 0xfffe,
  556. .rxep_bitmap = (0xfffe << 16),
  557. .musb_core_offset = 0x400,
  558. .poll_seconds = 2,
  559. };
  560. static const struct platform_device_id musb_dsps_id_table[] __devinitconst = {
  561. {
  562. .name = "musb-ti81xx",
  563. .driver_data = (kernel_ulong_t) &ti81xx_driver_data,
  564. },
  565. { }, /* Terminating Entry */
  566. };
  567. MODULE_DEVICE_TABLE(platform, musb_dsps_id_table);
  568. static const struct of_device_id musb_dsps_of_match[] __devinitconst = {
  569. { .compatible = "musb-ti81xx", },
  570. { .compatible = "ti,ti81xx-musb", },
  571. { .compatible = "ti,am335x-musb", },
  572. { },
  573. };
  574. MODULE_DEVICE_TABLE(of, musb_dsps_of_match);
  575. static struct platform_driver dsps_usbss_driver = {
  576. .probe = dsps_probe,
  577. .remove = __devexit_p(dsps_remove),
  578. .driver = {
  579. .name = "musb-dsps",
  580. .pm = &dsps_pm_ops,
  581. .of_match_table = musb_dsps_of_match,
  582. },
  583. .id_table = musb_dsps_id_table,
  584. };
  585. MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer");
  586. MODULE_AUTHOR("Ravi B <ravibabu@ti.com>");
  587. MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
  588. MODULE_LICENSE("GPL v2");
  589. static int __init dsps_init(void)
  590. {
  591. return platform_driver_register(&dsps_usbss_driver);
  592. }
  593. subsys_initcall(dsps_init);
  594. static void __exit dsps_exit(void)
  595. {
  596. platform_driver_unregister(&dsps_usbss_driver);
  597. }
  598. module_exit(dsps_exit);