mpc5200_dma.c 14 KB

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  1. /*
  2. * Freescale MPC5200 PSC DMA
  3. * ALSA SoC Platform driver
  4. *
  5. * Copyright (C) 2008 Secret Lab Technologies Ltd.
  6. * Copyright (C) 2009 Jon Smirl, Digispeaker
  7. */
  8. #include <linux/module.h>
  9. #include <linux/of_device.h>
  10. #include <sound/soc.h>
  11. #include <sysdev/bestcomm/bestcomm.h>
  12. #include <sysdev/bestcomm/gen_bd.h>
  13. #include <asm/mpc52xx_psc.h>
  14. #include "mpc5200_dma.h"
  15. /*
  16. * Interrupt handlers
  17. */
  18. static irqreturn_t psc_dma_status_irq(int irq, void *_psc_dma)
  19. {
  20. struct psc_dma *psc_dma = _psc_dma;
  21. struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
  22. u16 isr;
  23. isr = in_be16(&regs->mpc52xx_psc_isr);
  24. /* Playback underrun error */
  25. if (psc_dma->playback.active && (isr & MPC52xx_PSC_IMR_TXEMP))
  26. psc_dma->stats.underrun_count++;
  27. /* Capture overrun error */
  28. if (psc_dma->capture.active && (isr & MPC52xx_PSC_IMR_ORERR))
  29. psc_dma->stats.overrun_count++;
  30. out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
  31. return IRQ_HANDLED;
  32. }
  33. /**
  34. * psc_dma_bcom_enqueue_next_buffer - Enqueue another audio buffer
  35. * @s: pointer to stream private data structure
  36. *
  37. * Enqueues another audio period buffer into the bestcomm queue.
  38. *
  39. * Note: The routine must only be called when there is space available in
  40. * the queue. Otherwise the enqueue will fail and the audio ring buffer
  41. * will get out of sync
  42. */
  43. static void psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream *s)
  44. {
  45. struct bcom_bd *bd;
  46. /* Prepare and enqueue the next buffer descriptor */
  47. bd = bcom_prepare_next_buffer(s->bcom_task);
  48. bd->status = s->period_bytes;
  49. bd->data[0] = s->runtime->dma_addr + (s->period_next * s->period_bytes);
  50. bcom_submit_next_buffer(s->bcom_task, NULL);
  51. /* Update for next period */
  52. s->period_next = (s->period_next + 1) % s->runtime->periods;
  53. }
  54. /* Bestcomm DMA irq handler */
  55. static irqreturn_t psc_dma_bcom_irq(int irq, void *_psc_dma_stream)
  56. {
  57. struct psc_dma_stream *s = _psc_dma_stream;
  58. spin_lock(&s->psc_dma->lock);
  59. /* For each finished period, dequeue the completed period buffer
  60. * and enqueue a new one in it's place. */
  61. while (bcom_buffer_done(s->bcom_task)) {
  62. bcom_retrieve_buffer(s->bcom_task, NULL, NULL);
  63. s->period_current = (s->period_current+1) % s->runtime->periods;
  64. s->period_count++;
  65. psc_dma_bcom_enqueue_next_buffer(s);
  66. }
  67. spin_unlock(&s->psc_dma->lock);
  68. /* If the stream is active, then also inform the PCM middle layer
  69. * of the period finished event. */
  70. if (s->active)
  71. snd_pcm_period_elapsed(s->stream);
  72. return IRQ_HANDLED;
  73. }
  74. static int psc_dma_hw_free(struct snd_pcm_substream *substream)
  75. {
  76. snd_pcm_set_runtime_buffer(substream, NULL);
  77. return 0;
  78. }
  79. /**
  80. * psc_dma_trigger: start and stop the DMA transfer.
  81. *
  82. * This function is called by ALSA to start, stop, pause, and resume the DMA
  83. * transfer of data.
  84. */
  85. static int psc_dma_trigger(struct snd_pcm_substream *substream, int cmd)
  86. {
  87. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  88. struct psc_dma *psc_dma = rtd->dai->cpu_dai->private_data;
  89. struct snd_pcm_runtime *runtime = substream->runtime;
  90. struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
  91. struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
  92. u16 imr;
  93. unsigned long flags;
  94. int i;
  95. switch (cmd) {
  96. case SNDRV_PCM_TRIGGER_START:
  97. dev_dbg(psc_dma->dev, "START: stream=%i fbits=%u ps=%u #p=%u\n",
  98. substream->pstr->stream, runtime->frame_bits,
  99. (int)runtime->period_size, runtime->periods);
  100. s->period_bytes = frames_to_bytes(runtime,
  101. runtime->period_size);
  102. s->period_next = 0;
  103. s->period_current = 0;
  104. s->active = 1;
  105. s->period_count = 0;
  106. s->runtime = runtime;
  107. /* Fill up the bestcomm bd queue and enable DMA.
  108. * This will begin filling the PSC's fifo.
  109. */
  110. spin_lock_irqsave(&psc_dma->lock, flags);
  111. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  112. bcom_gen_bd_rx_reset(s->bcom_task);
  113. else
  114. bcom_gen_bd_tx_reset(s->bcom_task);
  115. for (i = 0; i < runtime->periods; i++)
  116. if (!bcom_queue_full(s->bcom_task))
  117. psc_dma_bcom_enqueue_next_buffer(s);
  118. bcom_enable(s->bcom_task);
  119. spin_unlock_irqrestore(&psc_dma->lock, flags);
  120. out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
  121. break;
  122. case SNDRV_PCM_TRIGGER_STOP:
  123. dev_dbg(psc_dma->dev, "STOP: stream=%i periods_count=%i\n",
  124. substream->pstr->stream, s->period_count);
  125. s->active = 0;
  126. spin_lock_irqsave(&psc_dma->lock, flags);
  127. bcom_disable(s->bcom_task);
  128. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  129. bcom_gen_bd_rx_reset(s->bcom_task);
  130. else
  131. bcom_gen_bd_tx_reset(s->bcom_task);
  132. spin_unlock_irqrestore(&psc_dma->lock, flags);
  133. break;
  134. default:
  135. dev_dbg(psc_dma->dev, "unhandled trigger: stream=%i cmd=%i\n",
  136. substream->pstr->stream, cmd);
  137. return -EINVAL;
  138. }
  139. /* Update interrupt enable settings */
  140. imr = 0;
  141. if (psc_dma->playback.active)
  142. imr |= MPC52xx_PSC_IMR_TXEMP;
  143. if (psc_dma->capture.active)
  144. imr |= MPC52xx_PSC_IMR_ORERR;
  145. out_be16(&regs->isr_imr.imr, psc_dma->imr | imr);
  146. return 0;
  147. }
  148. /* ---------------------------------------------------------------------
  149. * The PSC DMA 'ASoC platform' driver
  150. *
  151. * Can be referenced by an 'ASoC machine' driver
  152. * This driver only deals with the audio bus; it doesn't have any
  153. * interaction with the attached codec
  154. */
  155. static const struct snd_pcm_hardware psc_dma_hardware = {
  156. .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
  157. SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
  158. SNDRV_PCM_INFO_BATCH,
  159. .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |
  160. SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE,
  161. .rate_min = 8000,
  162. .rate_max = 48000,
  163. .channels_min = 1,
  164. .channels_max = 2,
  165. .period_bytes_max = 1024 * 1024,
  166. .period_bytes_min = 32,
  167. .periods_min = 2,
  168. .periods_max = 256,
  169. .buffer_bytes_max = 2 * 1024 * 1024,
  170. .fifo_size = 512,
  171. };
  172. static int psc_dma_open(struct snd_pcm_substream *substream)
  173. {
  174. struct snd_pcm_runtime *runtime = substream->runtime;
  175. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  176. struct psc_dma *psc_dma = rtd->dai->cpu_dai->private_data;
  177. struct psc_dma_stream *s;
  178. int rc;
  179. dev_dbg(psc_dma->dev, "psc_dma_open(substream=%p)\n", substream);
  180. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  181. s = &psc_dma->capture;
  182. else
  183. s = &psc_dma->playback;
  184. snd_soc_set_runtime_hwparams(substream, &psc_dma_hardware);
  185. rc = snd_pcm_hw_constraint_integer(runtime,
  186. SNDRV_PCM_HW_PARAM_PERIODS);
  187. if (rc < 0) {
  188. dev_err(substream->pcm->card->dev, "invalid buffer size\n");
  189. return rc;
  190. }
  191. s->stream = substream;
  192. return 0;
  193. }
  194. static int psc_dma_close(struct snd_pcm_substream *substream)
  195. {
  196. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  197. struct psc_dma *psc_dma = rtd->dai->cpu_dai->private_data;
  198. struct psc_dma_stream *s;
  199. dev_dbg(psc_dma->dev, "psc_dma_close(substream=%p)\n", substream);
  200. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  201. s = &psc_dma->capture;
  202. else
  203. s = &psc_dma->playback;
  204. if (!psc_dma->playback.active &&
  205. !psc_dma->capture.active) {
  206. /* Disable all interrupts and reset the PSC */
  207. out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
  208. out_8(&psc_dma->psc_regs->command, 4 << 4); /* reset error */
  209. }
  210. s->stream = NULL;
  211. return 0;
  212. }
  213. static snd_pcm_uframes_t
  214. psc_dma_pointer(struct snd_pcm_substream *substream)
  215. {
  216. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  217. struct psc_dma *psc_dma = rtd->dai->cpu_dai->private_data;
  218. struct psc_dma_stream *s;
  219. dma_addr_t count;
  220. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  221. s = &psc_dma->capture;
  222. else
  223. s = &psc_dma->playback;
  224. count = s->period_current * s->period_bytes;
  225. return bytes_to_frames(substream->runtime, count);
  226. }
  227. static int
  228. psc_dma_hw_params(struct snd_pcm_substream *substream,
  229. struct snd_pcm_hw_params *params)
  230. {
  231. snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
  232. return 0;
  233. }
  234. static struct snd_pcm_ops psc_dma_ops = {
  235. .open = psc_dma_open,
  236. .close = psc_dma_close,
  237. .hw_free = psc_dma_hw_free,
  238. .ioctl = snd_pcm_lib_ioctl,
  239. .pointer = psc_dma_pointer,
  240. .trigger = psc_dma_trigger,
  241. .hw_params = psc_dma_hw_params,
  242. };
  243. static u64 psc_dma_dmamask = 0xffffffff;
  244. static int psc_dma_new(struct snd_card *card, struct snd_soc_dai *dai,
  245. struct snd_pcm *pcm)
  246. {
  247. struct snd_soc_pcm_runtime *rtd = pcm->private_data;
  248. struct psc_dma *psc_dma = rtd->dai->cpu_dai->private_data;
  249. size_t size = psc_dma_hardware.buffer_bytes_max;
  250. int rc = 0;
  251. dev_dbg(rtd->socdev->dev, "psc_dma_new(card=%p, dai=%p, pcm=%p)\n",
  252. card, dai, pcm);
  253. if (!card->dev->dma_mask)
  254. card->dev->dma_mask = &psc_dma_dmamask;
  255. if (!card->dev->coherent_dma_mask)
  256. card->dev->coherent_dma_mask = 0xffffffff;
  257. if (pcm->streams[0].substream) {
  258. rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
  259. size, &pcm->streams[0].substream->dma_buffer);
  260. if (rc)
  261. goto playback_alloc_err;
  262. }
  263. if (pcm->streams[1].substream) {
  264. rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
  265. size, &pcm->streams[1].substream->dma_buffer);
  266. if (rc)
  267. goto capture_alloc_err;
  268. }
  269. if (rtd->socdev->card->codec->ac97)
  270. rtd->socdev->card->codec->ac97->private_data = psc_dma;
  271. return 0;
  272. capture_alloc_err:
  273. if (pcm->streams[0].substream)
  274. snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer);
  275. playback_alloc_err:
  276. dev_err(card->dev, "Cannot allocate buffer(s)\n");
  277. return -ENOMEM;
  278. }
  279. static void psc_dma_free(struct snd_pcm *pcm)
  280. {
  281. struct snd_soc_pcm_runtime *rtd = pcm->private_data;
  282. struct snd_pcm_substream *substream;
  283. int stream;
  284. dev_dbg(rtd->socdev->dev, "psc_dma_free(pcm=%p)\n", pcm);
  285. for (stream = 0; stream < 2; stream++) {
  286. substream = pcm->streams[stream].substream;
  287. if (substream) {
  288. snd_dma_free_pages(&substream->dma_buffer);
  289. substream->dma_buffer.area = NULL;
  290. substream->dma_buffer.addr = 0;
  291. }
  292. }
  293. }
  294. struct snd_soc_platform mpc5200_audio_dma_platform = {
  295. .name = "mpc5200-psc-audio",
  296. .pcm_ops = &psc_dma_ops,
  297. .pcm_new = &psc_dma_new,
  298. .pcm_free = &psc_dma_free,
  299. };
  300. EXPORT_SYMBOL_GPL(mpc5200_audio_dma_platform);
  301. int mpc5200_audio_dma_create(struct of_device *op)
  302. {
  303. phys_addr_t fifo;
  304. struct psc_dma *psc_dma;
  305. struct resource res;
  306. int size, irq, rc;
  307. const __be32 *prop;
  308. void __iomem *regs;
  309. int ret;
  310. /* Fetch the registers and IRQ of the PSC */
  311. irq = irq_of_parse_and_map(op->node, 0);
  312. if (of_address_to_resource(op->node, 0, &res)) {
  313. dev_err(&op->dev, "Missing reg property\n");
  314. return -ENODEV;
  315. }
  316. regs = ioremap(res.start, 1 + res.end - res.start);
  317. if (!regs) {
  318. dev_err(&op->dev, "Could not map registers\n");
  319. return -ENODEV;
  320. }
  321. /* Allocate and initialize the driver private data */
  322. psc_dma = kzalloc(sizeof *psc_dma, GFP_KERNEL);
  323. if (!psc_dma) {
  324. ret = -ENOMEM;
  325. goto out_unmap;
  326. }
  327. /* Get the PSC ID */
  328. prop = of_get_property(op->node, "cell-index", &size);
  329. if (!prop || size < sizeof *prop) {
  330. ret = -ENODEV;
  331. goto out_free;
  332. }
  333. spin_lock_init(&psc_dma->lock);
  334. mutex_init(&psc_dma->mutex);
  335. psc_dma->id = be32_to_cpu(*prop);
  336. psc_dma->irq = irq;
  337. psc_dma->psc_regs = regs;
  338. psc_dma->fifo_regs = regs + sizeof *psc_dma->psc_regs;
  339. psc_dma->dev = &op->dev;
  340. psc_dma->playback.psc_dma = psc_dma;
  341. psc_dma->capture.psc_dma = psc_dma;
  342. snprintf(psc_dma->name, sizeof psc_dma->name, "PSC%u", psc_dma->id);
  343. /* Find the address of the fifo data registers and setup the
  344. * DMA tasks */
  345. fifo = res.start + offsetof(struct mpc52xx_psc, buffer.buffer_32);
  346. psc_dma->capture.bcom_task =
  347. bcom_psc_gen_bd_rx_init(psc_dma->id, 10, fifo, 512);
  348. psc_dma->playback.bcom_task =
  349. bcom_psc_gen_bd_tx_init(psc_dma->id, 10, fifo);
  350. if (!psc_dma->capture.bcom_task ||
  351. !psc_dma->playback.bcom_task) {
  352. dev_err(&op->dev, "Could not allocate bestcomm tasks\n");
  353. ret = -ENODEV;
  354. goto out_free;
  355. }
  356. /* Disable all interrupts and reset the PSC */
  357. out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
  358. /* reset receiver */
  359. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_RX);
  360. /* reset transmitter */
  361. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_TX);
  362. /* reset error */
  363. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_ERR_STAT);
  364. /* reset mode */
  365. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_SEL_MODE_REG_1);
  366. /* Set up mode register;
  367. * First write: RxRdy (FIFO Alarm) generates rx FIFO irq
  368. * Second write: register Normal mode for non loopback
  369. */
  370. out_8(&psc_dma->psc_regs->mode, 0);
  371. out_8(&psc_dma->psc_regs->mode, 0);
  372. /* Set the TX and RX fifo alarm thresholds */
  373. out_be16(&psc_dma->fifo_regs->rfalarm, 0x100);
  374. out_8(&psc_dma->fifo_regs->rfcntl, 0x4);
  375. out_be16(&psc_dma->fifo_regs->tfalarm, 0x100);
  376. out_8(&psc_dma->fifo_regs->tfcntl, 0x7);
  377. /* Lookup the IRQ numbers */
  378. psc_dma->playback.irq =
  379. bcom_get_task_irq(psc_dma->playback.bcom_task);
  380. psc_dma->capture.irq =
  381. bcom_get_task_irq(psc_dma->capture.bcom_task);
  382. rc = request_irq(psc_dma->irq, &psc_dma_status_irq, IRQF_SHARED,
  383. "psc-dma-status", psc_dma);
  384. rc |= request_irq(psc_dma->capture.irq, &psc_dma_bcom_irq, IRQF_SHARED,
  385. "psc-dma-capture", &psc_dma->capture);
  386. rc |= request_irq(psc_dma->playback.irq, &psc_dma_bcom_irq, IRQF_SHARED,
  387. "psc-dma-playback", &psc_dma->playback);
  388. if (rc) {
  389. ret = -ENODEV;
  390. goto out_irq;
  391. }
  392. /* Save what we've done so it can be found again later */
  393. dev_set_drvdata(&op->dev, psc_dma);
  394. /* Tell the ASoC OF helpers about it */
  395. return snd_soc_register_platform(&mpc5200_audio_dma_platform);
  396. out_irq:
  397. free_irq(psc_dma->irq, psc_dma);
  398. free_irq(psc_dma->capture.irq, &psc_dma->capture);
  399. free_irq(psc_dma->playback.irq, &psc_dma->playback);
  400. out_free:
  401. kfree(psc_dma);
  402. out_unmap:
  403. iounmap(regs);
  404. return ret;
  405. }
  406. EXPORT_SYMBOL_GPL(mpc5200_audio_dma_create);
  407. int mpc5200_audio_dma_destroy(struct of_device *op)
  408. {
  409. struct psc_dma *psc_dma = dev_get_drvdata(&op->dev);
  410. dev_dbg(&op->dev, "mpc5200_audio_dma_destroy()\n");
  411. snd_soc_unregister_platform(&mpc5200_audio_dma_platform);
  412. bcom_gen_bd_rx_release(psc_dma->capture.bcom_task);
  413. bcom_gen_bd_tx_release(psc_dma->playback.bcom_task);
  414. /* Release irqs */
  415. free_irq(psc_dma->irq, psc_dma);
  416. free_irq(psc_dma->capture.irq, &psc_dma->capture);
  417. free_irq(psc_dma->playback.irq, &psc_dma->playback);
  418. iounmap(psc_dma->psc_regs);
  419. kfree(psc_dma);
  420. dev_set_drvdata(&op->dev, NULL);
  421. return 0;
  422. }
  423. EXPORT_SYMBOL_GPL(mpc5200_audio_dma_destroy);
  424. MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
  425. MODULE_DESCRIPTION("Freescale MPC5200 PSC in DMA mode ASoC Driver");
  426. MODULE_LICENSE("GPL");