uda1380.c 25 KB

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  1. /*
  2. * uda1380.c - Philips UDA1380 ALSA SoC audio driver
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>
  9. *
  10. * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC
  11. * codec model.
  12. *
  13. * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
  14. * Copyright 2005 Openedhand Ltd.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/types.h>
  19. #include <linux/slab.h>
  20. #include <linux/errno.h>
  21. #include <linux/gpio.h>
  22. #include <linux/delay.h>
  23. #include <linux/i2c.h>
  24. #include <linux/workqueue.h>
  25. #include <sound/core.h>
  26. #include <sound/control.h>
  27. #include <sound/initval.h>
  28. #include <sound/soc.h>
  29. #include <sound/soc-dapm.h>
  30. #include <sound/tlv.h>
  31. #include <sound/uda1380.h>
  32. #include "uda1380.h"
  33. static struct snd_soc_codec *uda1380_codec;
  34. /* codec private data */
  35. struct uda1380_priv {
  36. struct snd_soc_codec codec;
  37. u16 reg_cache[UDA1380_CACHEREGNUM];
  38. unsigned int dac_clk;
  39. struct work_struct work;
  40. };
  41. /*
  42. * uda1380 register cache
  43. */
  44. static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
  45. 0x0502, 0x0000, 0x0000, 0x3f3f,
  46. 0x0202, 0x0000, 0x0000, 0x0000,
  47. 0x0000, 0x0000, 0x0000, 0x0000,
  48. 0x0000, 0x0000, 0x0000, 0x0000,
  49. 0x0000, 0xff00, 0x0000, 0x4800,
  50. 0x0000, 0x0000, 0x0000, 0x0000,
  51. 0x0000, 0x0000, 0x0000, 0x0000,
  52. 0x0000, 0x0000, 0x0000, 0x0000,
  53. 0x0000, 0x8000, 0x0002, 0x0000,
  54. };
  55. static unsigned long uda1380_cache_dirty;
  56. /*
  57. * read uda1380 register cache
  58. */
  59. static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec,
  60. unsigned int reg)
  61. {
  62. u16 *cache = codec->reg_cache;
  63. if (reg == UDA1380_RESET)
  64. return 0;
  65. if (reg >= UDA1380_CACHEREGNUM)
  66. return -1;
  67. return cache[reg];
  68. }
  69. /*
  70. * write uda1380 register cache
  71. */
  72. static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
  73. u16 reg, unsigned int value)
  74. {
  75. u16 *cache = codec->reg_cache;
  76. if (reg >= UDA1380_CACHEREGNUM)
  77. return;
  78. if ((reg >= 0x10) && (cache[reg] != value))
  79. set_bit(reg - 0x10, &uda1380_cache_dirty);
  80. cache[reg] = value;
  81. }
  82. /*
  83. * write to the UDA1380 register space
  84. */
  85. static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
  86. unsigned int value)
  87. {
  88. u8 data[3];
  89. /* data is
  90. * data[0] is register offset
  91. * data[1] is MS byte
  92. * data[2] is LS byte
  93. */
  94. data[0] = reg;
  95. data[1] = (value & 0xff00) >> 8;
  96. data[2] = value & 0x00ff;
  97. uda1380_write_reg_cache(codec, reg, value);
  98. /* the interpolator & decimator regs must only be written when the
  99. * codec DAI is active.
  100. */
  101. if (!codec->active && (reg >= UDA1380_MVOL))
  102. return 0;
  103. pr_debug("uda1380: hw write %x val %x\n", reg, value);
  104. if (codec->hw_write(codec->control_data, data, 3) == 3) {
  105. unsigned int val;
  106. i2c_master_send(codec->control_data, data, 1);
  107. i2c_master_recv(codec->control_data, data, 2);
  108. val = (data[0]<<8) | data[1];
  109. if (val != value) {
  110. pr_debug("uda1380: READ BACK VAL %x\n",
  111. (data[0]<<8) | data[1]);
  112. return -EIO;
  113. }
  114. if (reg >= 0x10)
  115. clear_bit(reg - 0x10, &uda1380_cache_dirty);
  116. return 0;
  117. } else
  118. return -EIO;
  119. }
  120. #define uda1380_reset(c) uda1380_write(c, UDA1380_RESET, 0)
  121. static void uda1380_flush_work(struct work_struct *work)
  122. {
  123. int bit, reg;
  124. for_each_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
  125. reg = 0x10 + bit;
  126. pr_debug("uda1380: flush reg %x val %x:\n", reg,
  127. uda1380_read_reg_cache(uda1380_codec, reg));
  128. uda1380_write(uda1380_codec, reg,
  129. uda1380_read_reg_cache(uda1380_codec, reg));
  130. clear_bit(bit, &uda1380_cache_dirty);
  131. }
  132. }
  133. /* declarations of ALSA reg_elem_REAL controls */
  134. static const char *uda1380_deemp[] = {
  135. "None",
  136. "32kHz",
  137. "44.1kHz",
  138. "48kHz",
  139. "96kHz",
  140. };
  141. static const char *uda1380_input_sel[] = {
  142. "Line",
  143. "Mic + Line R",
  144. "Line L",
  145. "Mic",
  146. };
  147. static const char *uda1380_output_sel[] = {
  148. "DAC",
  149. "Analog Mixer",
  150. };
  151. static const char *uda1380_spf_mode[] = {
  152. "Flat",
  153. "Minimum1",
  154. "Minimum2",
  155. "Maximum"
  156. };
  157. static const char *uda1380_capture_sel[] = {
  158. "ADC",
  159. "Digital Mixer"
  160. };
  161. static const char *uda1380_sel_ns[] = {
  162. "3rd-order",
  163. "5th-order"
  164. };
  165. static const char *uda1380_mix_control[] = {
  166. "off",
  167. "PCM only",
  168. "before sound processing",
  169. "after sound processing"
  170. };
  171. static const char *uda1380_sdet_setting[] = {
  172. "3200",
  173. "4800",
  174. "9600",
  175. "19200"
  176. };
  177. static const char *uda1380_os_setting[] = {
  178. "single-speed",
  179. "double-speed (no mixing)",
  180. "quad-speed (no mixing)"
  181. };
  182. static const struct soc_enum uda1380_deemp_enum[] = {
  183. SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, 5, uda1380_deemp),
  184. SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, 5, uda1380_deemp),
  185. };
  186. static const struct soc_enum uda1380_input_sel_enum =
  187. SOC_ENUM_SINGLE(UDA1380_ADC, 2, 4, uda1380_input_sel); /* SEL_MIC, SEL_LNA */
  188. static const struct soc_enum uda1380_output_sel_enum =
  189. SOC_ENUM_SINGLE(UDA1380_PM, 7, 2, uda1380_output_sel); /* R02_EN_AVC */
  190. static const struct soc_enum uda1380_spf_enum =
  191. SOC_ENUM_SINGLE(UDA1380_MODE, 14, 4, uda1380_spf_mode); /* M */
  192. static const struct soc_enum uda1380_capture_sel_enum =
  193. SOC_ENUM_SINGLE(UDA1380_IFACE, 6, 2, uda1380_capture_sel); /* SEL_SOURCE */
  194. static const struct soc_enum uda1380_sel_ns_enum =
  195. SOC_ENUM_SINGLE(UDA1380_MIXER, 14, 2, uda1380_sel_ns); /* SEL_NS */
  196. static const struct soc_enum uda1380_mix_enum =
  197. SOC_ENUM_SINGLE(UDA1380_MIXER, 12, 4, uda1380_mix_control); /* MIX, MIX_POS */
  198. static const struct soc_enum uda1380_sdet_enum =
  199. SOC_ENUM_SINGLE(UDA1380_MIXER, 4, 4, uda1380_sdet_setting); /* SD_VALUE */
  200. static const struct soc_enum uda1380_os_enum =
  201. SOC_ENUM_SINGLE(UDA1380_MIXER, 0, 3, uda1380_os_setting); /* OS */
  202. /*
  203. * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)
  204. */
  205. static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1);
  206. /*
  207. * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),
  208. * from -66 dB in 0.5 dB steps (2 dB steps, really) and
  209. * from -52 dB in 0.25 dB steps
  210. */
  211. static const unsigned int mvol_tlv[] = {
  212. TLV_DB_RANGE_HEAD(3),
  213. 0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),
  214. 16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),
  215. 44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0),
  216. };
  217. /*
  218. * from -72 dB in 1.5 dB steps (6 dB steps really),
  219. * from -66 dB in 0.75 dB steps (3 dB steps really),
  220. * from -60 dB in 0.5 dB steps (2 dB steps really) and
  221. * from -46 dB in 0.25 dB steps
  222. */
  223. static const unsigned int vc_tlv[] = {
  224. TLV_DB_RANGE_HEAD(4),
  225. 0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),
  226. 8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),
  227. 16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),
  228. 44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0),
  229. };
  230. /* from 0 to 6 dB in 2 dB steps if SPF mode != flat */
  231. static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0);
  232. /* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts
  233. * off at 18 dB max) */
  234. static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0);
  235. /* from -63 to 24 dB in 0.5 dB steps (-128...48) */
  236. static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1);
  237. /* from 0 to 24 dB in 3 dB steps */
  238. static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
  239. /* from 0 to 30 dB in 2 dB steps */
  240. static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0);
  241. static const struct snd_kcontrol_new uda1380_snd_controls[] = {
  242. SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv), /* AVCR, AVCL */
  243. SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */
  244. SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv), /* VC2 */
  245. SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv), /* VC1 */
  246. SOC_ENUM("Sound Processing Filter", uda1380_spf_enum), /* M */
  247. SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv), /* TRL, TRR */
  248. SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv), /* BBL, BBR */
  249. /**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */
  250. SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */
  251. SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */
  252. SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */
  253. SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */
  254. SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */
  255. SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */
  256. SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */
  257. SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */
  258. SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */
  259. SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */
  260. SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */
  261. /**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */
  262. SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
  263. SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */
  264. SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */
  265. SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0), /* SKIP_DCFIL (before decimator) */
  266. SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0), /* EN_DCFIL (at output of decimator) */
  267. SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0), /* TODO: enum, see table 62 */
  268. SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1), /* AGC_LEVEL */
  269. /* -5.5, -8, -11.5, -14 dBFS */
  270. SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0),
  271. };
  272. /* Input mux */
  273. static const struct snd_kcontrol_new uda1380_input_mux_control =
  274. SOC_DAPM_ENUM("Route", uda1380_input_sel_enum);
  275. /* Output mux */
  276. static const struct snd_kcontrol_new uda1380_output_mux_control =
  277. SOC_DAPM_ENUM("Route", uda1380_output_sel_enum);
  278. /* Capture mux */
  279. static const struct snd_kcontrol_new uda1380_capture_mux_control =
  280. SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum);
  281. static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = {
  282. SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
  283. &uda1380_input_mux_control),
  284. SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0,
  285. &uda1380_output_mux_control),
  286. SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
  287. &uda1380_capture_mux_control),
  288. SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0),
  289. SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0),
  290. SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0),
  291. SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0),
  292. SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0),
  293. SND_SOC_DAPM_INPUT("VINM"),
  294. SND_SOC_DAPM_INPUT("VINL"),
  295. SND_SOC_DAPM_INPUT("VINR"),
  296. SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0),
  297. SND_SOC_DAPM_OUTPUT("VOUTLHP"),
  298. SND_SOC_DAPM_OUTPUT("VOUTRHP"),
  299. SND_SOC_DAPM_OUTPUT("VOUTL"),
  300. SND_SOC_DAPM_OUTPUT("VOUTR"),
  301. SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0),
  302. SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0),
  303. };
  304. static const struct snd_soc_dapm_route audio_map[] = {
  305. /* output mux */
  306. {"HeadPhone Driver", NULL, "Output Mux"},
  307. {"VOUTR", NULL, "Output Mux"},
  308. {"VOUTL", NULL, "Output Mux"},
  309. {"Analog Mixer", NULL, "VINR"},
  310. {"Analog Mixer", NULL, "VINL"},
  311. {"Analog Mixer", NULL, "DAC"},
  312. {"Output Mux", "DAC", "DAC"},
  313. {"Output Mux", "Analog Mixer", "Analog Mixer"},
  314. /* {"DAC", "Digital Mixer", "I2S" } */
  315. /* headphone driver */
  316. {"VOUTLHP", NULL, "HeadPhone Driver"},
  317. {"VOUTRHP", NULL, "HeadPhone Driver"},
  318. /* input mux */
  319. {"Left ADC", NULL, "Input Mux"},
  320. {"Input Mux", "Mic", "Mic LNA"},
  321. {"Input Mux", "Mic + Line R", "Mic LNA"},
  322. {"Input Mux", "Line L", "Left PGA"},
  323. {"Input Mux", "Line", "Left PGA"},
  324. /* right input */
  325. {"Right ADC", "Mic + Line R", "Right PGA"},
  326. {"Right ADC", "Line", "Right PGA"},
  327. /* inputs */
  328. {"Mic LNA", NULL, "VINM"},
  329. {"Left PGA", NULL, "VINL"},
  330. {"Right PGA", NULL, "VINR"},
  331. };
  332. static int uda1380_add_widgets(struct snd_soc_codec *codec)
  333. {
  334. snd_soc_dapm_new_controls(codec, uda1380_dapm_widgets,
  335. ARRAY_SIZE(uda1380_dapm_widgets));
  336. snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
  337. return 0;
  338. }
  339. static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
  340. unsigned int fmt)
  341. {
  342. struct snd_soc_codec *codec = codec_dai->codec;
  343. int iface;
  344. /* set up DAI based upon fmt */
  345. iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
  346. iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
  347. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  348. case SND_SOC_DAIFMT_I2S:
  349. iface |= R01_SFORI_I2S | R01_SFORO_I2S;
  350. break;
  351. case SND_SOC_DAIFMT_LSB:
  352. iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
  353. break;
  354. case SND_SOC_DAIFMT_MSB:
  355. iface |= R01_SFORI_MSB | R01_SFORO_MSB;
  356. }
  357. /* DATAI is slave only, so in single-link mode, this has to be slave */
  358. if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
  359. return -EINVAL;
  360. uda1380_write(codec, UDA1380_IFACE, iface);
  361. return 0;
  362. }
  363. static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
  364. unsigned int fmt)
  365. {
  366. struct snd_soc_codec *codec = codec_dai->codec;
  367. int iface;
  368. /* set up DAI based upon fmt */
  369. iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
  370. iface &= ~R01_SFORI_MASK;
  371. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  372. case SND_SOC_DAIFMT_I2S:
  373. iface |= R01_SFORI_I2S;
  374. break;
  375. case SND_SOC_DAIFMT_LSB:
  376. iface |= R01_SFORI_LSB16;
  377. break;
  378. case SND_SOC_DAIFMT_MSB:
  379. iface |= R01_SFORI_MSB;
  380. }
  381. /* DATAI is slave only, so this has to be slave */
  382. if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
  383. return -EINVAL;
  384. uda1380_write(codec, UDA1380_IFACE, iface);
  385. return 0;
  386. }
  387. static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
  388. unsigned int fmt)
  389. {
  390. struct snd_soc_codec *codec = codec_dai->codec;
  391. int iface;
  392. /* set up DAI based upon fmt */
  393. iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
  394. iface &= ~(R01_SIM | R01_SFORO_MASK);
  395. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  396. case SND_SOC_DAIFMT_I2S:
  397. iface |= R01_SFORO_I2S;
  398. break;
  399. case SND_SOC_DAIFMT_LSB:
  400. iface |= R01_SFORO_LSB16;
  401. break;
  402. case SND_SOC_DAIFMT_MSB:
  403. iface |= R01_SFORO_MSB;
  404. }
  405. if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
  406. iface |= R01_SIM;
  407. uda1380_write(codec, UDA1380_IFACE, iface);
  408. return 0;
  409. }
  410. static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
  411. struct snd_soc_dai *dai)
  412. {
  413. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  414. struct snd_soc_device *socdev = rtd->socdev;
  415. struct snd_soc_codec *codec = socdev->card->codec;
  416. struct uda1380_priv *uda1380 = codec->private_data;
  417. int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
  418. switch (cmd) {
  419. case SNDRV_PCM_TRIGGER_START:
  420. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  421. uda1380_write_reg_cache(codec, UDA1380_MIXER,
  422. mixer & ~R14_SILENCE);
  423. schedule_work(&uda1380->work);
  424. break;
  425. case SNDRV_PCM_TRIGGER_STOP:
  426. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  427. uda1380_write_reg_cache(codec, UDA1380_MIXER,
  428. mixer | R14_SILENCE);
  429. schedule_work(&uda1380->work);
  430. break;
  431. }
  432. return 0;
  433. }
  434. static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
  435. struct snd_pcm_hw_params *params,
  436. struct snd_soc_dai *dai)
  437. {
  438. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  439. struct snd_soc_device *socdev = rtd->socdev;
  440. struct snd_soc_codec *codec = socdev->card->codec;
  441. u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
  442. /* set WSPLL power and divider if running from this clock */
  443. if (clk & R00_DAC_CLK) {
  444. int rate = params_rate(params);
  445. u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
  446. clk &= ~0x3; /* clear SEL_LOOP_DIV */
  447. switch (rate) {
  448. case 6250 ... 12500:
  449. clk |= 0x0;
  450. break;
  451. case 12501 ... 25000:
  452. clk |= 0x1;
  453. break;
  454. case 25001 ... 50000:
  455. clk |= 0x2;
  456. break;
  457. case 50001 ... 100000:
  458. clk |= 0x3;
  459. break;
  460. }
  461. uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm);
  462. }
  463. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  464. clk |= R00_EN_DAC | R00_EN_INT;
  465. else
  466. clk |= R00_EN_ADC | R00_EN_DEC;
  467. uda1380_write(codec, UDA1380_CLK, clk);
  468. return 0;
  469. }
  470. static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
  471. struct snd_soc_dai *dai)
  472. {
  473. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  474. struct snd_soc_device *socdev = rtd->socdev;
  475. struct snd_soc_codec *codec = socdev->card->codec;
  476. u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
  477. /* shut down WSPLL power if running from this clock */
  478. if (clk & R00_DAC_CLK) {
  479. u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
  480. uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm);
  481. }
  482. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  483. clk &= ~(R00_EN_DAC | R00_EN_INT);
  484. else
  485. clk &= ~(R00_EN_ADC | R00_EN_DEC);
  486. uda1380_write(codec, UDA1380_CLK, clk);
  487. }
  488. static int uda1380_set_bias_level(struct snd_soc_codec *codec,
  489. enum snd_soc_bias_level level)
  490. {
  491. int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
  492. switch (level) {
  493. case SND_SOC_BIAS_ON:
  494. case SND_SOC_BIAS_PREPARE:
  495. uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
  496. break;
  497. case SND_SOC_BIAS_STANDBY:
  498. uda1380_write(codec, UDA1380_PM, R02_PON_BIAS);
  499. break;
  500. case SND_SOC_BIAS_OFF:
  501. uda1380_write(codec, UDA1380_PM, 0x0);
  502. break;
  503. }
  504. codec->bias_level = level;
  505. return 0;
  506. }
  507. #define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  508. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
  509. SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  510. static struct snd_soc_dai_ops uda1380_dai_ops = {
  511. .hw_params = uda1380_pcm_hw_params,
  512. .shutdown = uda1380_pcm_shutdown,
  513. .trigger = uda1380_trigger,
  514. .set_fmt = uda1380_set_dai_fmt_both,
  515. };
  516. static struct snd_soc_dai_ops uda1380_dai_ops_playback = {
  517. .hw_params = uda1380_pcm_hw_params,
  518. .shutdown = uda1380_pcm_shutdown,
  519. .trigger = uda1380_trigger,
  520. .set_fmt = uda1380_set_dai_fmt_playback,
  521. };
  522. static struct snd_soc_dai_ops uda1380_dai_ops_capture = {
  523. .hw_params = uda1380_pcm_hw_params,
  524. .shutdown = uda1380_pcm_shutdown,
  525. .trigger = uda1380_trigger,
  526. .set_fmt = uda1380_set_dai_fmt_capture,
  527. };
  528. struct snd_soc_dai uda1380_dai[] = {
  529. {
  530. .name = "UDA1380",
  531. .playback = {
  532. .stream_name = "Playback",
  533. .channels_min = 1,
  534. .channels_max = 2,
  535. .rates = UDA1380_RATES,
  536. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  537. .capture = {
  538. .stream_name = "Capture",
  539. .channels_min = 1,
  540. .channels_max = 2,
  541. .rates = UDA1380_RATES,
  542. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  543. .ops = &uda1380_dai_ops,
  544. },
  545. { /* playback only - dual interface */
  546. .name = "UDA1380",
  547. .playback = {
  548. .stream_name = "Playback",
  549. .channels_min = 1,
  550. .channels_max = 2,
  551. .rates = UDA1380_RATES,
  552. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  553. },
  554. .ops = &uda1380_dai_ops_playback,
  555. },
  556. { /* capture only - dual interface*/
  557. .name = "UDA1380",
  558. .capture = {
  559. .stream_name = "Capture",
  560. .channels_min = 1,
  561. .channels_max = 2,
  562. .rates = UDA1380_RATES,
  563. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  564. },
  565. .ops = &uda1380_dai_ops_capture,
  566. },
  567. };
  568. EXPORT_SYMBOL_GPL(uda1380_dai);
  569. static int uda1380_suspend(struct platform_device *pdev, pm_message_t state)
  570. {
  571. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  572. struct snd_soc_codec *codec = socdev->card->codec;
  573. uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
  574. return 0;
  575. }
  576. static int uda1380_resume(struct platform_device *pdev)
  577. {
  578. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  579. struct snd_soc_codec *codec = socdev->card->codec;
  580. int i;
  581. u8 data[2];
  582. u16 *cache = codec->reg_cache;
  583. /* Sync reg_cache with the hardware */
  584. for (i = 0; i < ARRAY_SIZE(uda1380_reg); i++) {
  585. data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
  586. data[1] = cache[i] & 0x00ff;
  587. codec->hw_write(codec->control_data, data, 2);
  588. }
  589. uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  590. uda1380_set_bias_level(codec, codec->suspend_bias_level);
  591. return 0;
  592. }
  593. static int uda1380_probe(struct platform_device *pdev)
  594. {
  595. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  596. struct snd_soc_codec *codec;
  597. struct uda1380_platform_data *pdata;
  598. int ret = 0;
  599. if (uda1380_codec == NULL) {
  600. dev_err(&pdev->dev, "Codec device not registered\n");
  601. return -ENODEV;
  602. }
  603. socdev->card->codec = uda1380_codec;
  604. codec = uda1380_codec;
  605. pdata = codec->dev->platform_data;
  606. /* register pcms */
  607. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  608. if (ret < 0) {
  609. dev_err(codec->dev, "failed to create pcms: %d\n", ret);
  610. goto pcm_err;
  611. }
  612. /* power on device */
  613. uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  614. /* set clock input */
  615. switch (pdata->dac_clk) {
  616. case UDA1380_DAC_CLK_SYSCLK:
  617. uda1380_write(codec, UDA1380_CLK, 0);
  618. break;
  619. case UDA1380_DAC_CLK_WSPLL:
  620. uda1380_write(codec, UDA1380_CLK, R00_DAC_CLK);
  621. break;
  622. }
  623. snd_soc_add_controls(codec, uda1380_snd_controls,
  624. ARRAY_SIZE(uda1380_snd_controls));
  625. uda1380_add_widgets(codec);
  626. return ret;
  627. pcm_err:
  628. return ret;
  629. }
  630. /* power down chip */
  631. static int uda1380_remove(struct platform_device *pdev)
  632. {
  633. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  634. struct snd_soc_codec *codec = socdev->card->codec;
  635. if (codec->control_data)
  636. uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
  637. snd_soc_free_pcms(socdev);
  638. snd_soc_dapm_free(socdev);
  639. return 0;
  640. }
  641. struct snd_soc_codec_device soc_codec_dev_uda1380 = {
  642. .probe = uda1380_probe,
  643. .remove = uda1380_remove,
  644. .suspend = uda1380_suspend,
  645. .resume = uda1380_resume,
  646. };
  647. EXPORT_SYMBOL_GPL(soc_codec_dev_uda1380);
  648. static int uda1380_register(struct uda1380_priv *uda1380)
  649. {
  650. int ret, i;
  651. struct snd_soc_codec *codec = &uda1380->codec;
  652. struct uda1380_platform_data *pdata = codec->dev->platform_data;
  653. if (uda1380_codec) {
  654. dev_err(codec->dev, "Another UDA1380 is registered\n");
  655. return -EINVAL;
  656. }
  657. if (!pdata || !pdata->gpio_power || !pdata->gpio_reset)
  658. return -EINVAL;
  659. ret = gpio_request(pdata->gpio_power, "uda1380 power");
  660. if (ret)
  661. goto err_out;
  662. ret = gpio_request(pdata->gpio_reset, "uda1380 reset");
  663. if (ret)
  664. goto err_gpio;
  665. gpio_direction_output(pdata->gpio_power, 1);
  666. /* we may need to have the clock running here - pH5 */
  667. gpio_direction_output(pdata->gpio_reset, 1);
  668. udelay(5);
  669. gpio_set_value(pdata->gpio_reset, 0);
  670. mutex_init(&codec->mutex);
  671. INIT_LIST_HEAD(&codec->dapm_widgets);
  672. INIT_LIST_HEAD(&codec->dapm_paths);
  673. codec->private_data = uda1380;
  674. codec->name = "UDA1380";
  675. codec->owner = THIS_MODULE;
  676. codec->read = uda1380_read_reg_cache;
  677. codec->write = uda1380_write;
  678. codec->bias_level = SND_SOC_BIAS_OFF;
  679. codec->set_bias_level = uda1380_set_bias_level;
  680. codec->dai = uda1380_dai;
  681. codec->num_dai = ARRAY_SIZE(uda1380_dai);
  682. codec->reg_cache_size = ARRAY_SIZE(uda1380_reg);
  683. codec->reg_cache = &uda1380->reg_cache;
  684. codec->reg_cache_step = 1;
  685. memcpy(codec->reg_cache, uda1380_reg, sizeof(uda1380_reg));
  686. ret = uda1380_reset(codec);
  687. if (ret < 0) {
  688. dev_err(codec->dev, "Failed to issue reset\n");
  689. goto err_reset;
  690. }
  691. INIT_WORK(&uda1380->work, uda1380_flush_work);
  692. for (i = 0; i < ARRAY_SIZE(uda1380_dai); i++)
  693. uda1380_dai[i].dev = codec->dev;
  694. uda1380_codec = codec;
  695. ret = snd_soc_register_codec(codec);
  696. if (ret != 0) {
  697. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  698. goto err_reset;
  699. }
  700. ret = snd_soc_register_dais(uda1380_dai, ARRAY_SIZE(uda1380_dai));
  701. if (ret != 0) {
  702. dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
  703. goto err_dai;
  704. }
  705. return 0;
  706. err_dai:
  707. snd_soc_unregister_codec(codec);
  708. err_reset:
  709. gpio_set_value(pdata->gpio_power, 0);
  710. gpio_free(pdata->gpio_reset);
  711. err_gpio:
  712. gpio_free(pdata->gpio_power);
  713. err_out:
  714. return ret;
  715. }
  716. static void uda1380_unregister(struct uda1380_priv *uda1380)
  717. {
  718. struct snd_soc_codec *codec = &uda1380->codec;
  719. struct uda1380_platform_data *pdata = codec->dev->platform_data;
  720. snd_soc_unregister_dais(uda1380_dai, ARRAY_SIZE(uda1380_dai));
  721. snd_soc_unregister_codec(&uda1380->codec);
  722. gpio_set_value(pdata->gpio_power, 0);
  723. gpio_free(pdata->gpio_reset);
  724. gpio_free(pdata->gpio_power);
  725. kfree(uda1380);
  726. uda1380_codec = NULL;
  727. }
  728. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  729. static __devinit int uda1380_i2c_probe(struct i2c_client *i2c,
  730. const struct i2c_device_id *id)
  731. {
  732. struct uda1380_priv *uda1380;
  733. struct snd_soc_codec *codec;
  734. int ret;
  735. uda1380 = kzalloc(sizeof(struct uda1380_priv), GFP_KERNEL);
  736. if (uda1380 == NULL)
  737. return -ENOMEM;
  738. codec = &uda1380->codec;
  739. codec->hw_write = (hw_write_t)i2c_master_send;
  740. i2c_set_clientdata(i2c, uda1380);
  741. codec->control_data = i2c;
  742. codec->dev = &i2c->dev;
  743. ret = uda1380_register(uda1380);
  744. if (ret != 0)
  745. kfree(uda1380);
  746. return ret;
  747. }
  748. static int __devexit uda1380_i2c_remove(struct i2c_client *i2c)
  749. {
  750. struct uda1380_priv *uda1380 = i2c_get_clientdata(i2c);
  751. uda1380_unregister(uda1380);
  752. return 0;
  753. }
  754. static const struct i2c_device_id uda1380_i2c_id[] = {
  755. { "uda1380", 0 },
  756. { }
  757. };
  758. MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
  759. static struct i2c_driver uda1380_i2c_driver = {
  760. .driver = {
  761. .name = "UDA1380 I2C Codec",
  762. .owner = THIS_MODULE,
  763. },
  764. .probe = uda1380_i2c_probe,
  765. .remove = __devexit_p(uda1380_i2c_remove),
  766. .id_table = uda1380_i2c_id,
  767. };
  768. #endif
  769. static int __init uda1380_modinit(void)
  770. {
  771. int ret;
  772. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  773. ret = i2c_add_driver(&uda1380_i2c_driver);
  774. if (ret != 0)
  775. pr_err("Failed to register UDA1380 I2C driver: %d\n", ret);
  776. #endif
  777. return 0;
  778. }
  779. module_init(uda1380_modinit);
  780. static void __exit uda1380_exit(void)
  781. {
  782. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  783. i2c_del_driver(&uda1380_i2c_driver);
  784. #endif
  785. }
  786. module_exit(uda1380_exit);
  787. MODULE_AUTHOR("Giorgio Padrin");
  788. MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
  789. MODULE_LICENSE("GPL");