tlv320dac33.c 32 KB

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  1. /*
  2. * ALSA SoC Texas Instruments TLV320DAC33 codec driver
  3. *
  4. * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
  5. *
  6. * Copyright: (C) 2009 Nokia Corporation
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20. * 02110-1301 USA
  21. *
  22. */
  23. #include <linux/module.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/init.h>
  26. #include <linux/delay.h>
  27. #include <linux/pm.h>
  28. #include <linux/i2c.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/gpio.h>
  32. #include <sound/core.h>
  33. #include <sound/pcm.h>
  34. #include <sound/pcm_params.h>
  35. #include <sound/soc.h>
  36. #include <sound/soc-dapm.h>
  37. #include <sound/initval.h>
  38. #include <sound/tlv.h>
  39. #include <sound/tlv320dac33-plat.h>
  40. #include "tlv320dac33.h"
  41. #define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
  42. * 6144 stereo */
  43. #define DAC33_BUFFER_SIZE_SAMPLES 6144
  44. #define NSAMPLE_MAX 5700
  45. #define LATENCY_TIME_MS 20
  46. static struct snd_soc_codec *tlv320dac33_codec;
  47. enum dac33_state {
  48. DAC33_IDLE = 0,
  49. DAC33_PREFILL,
  50. DAC33_PLAYBACK,
  51. DAC33_FLUSH,
  52. };
  53. struct tlv320dac33_priv {
  54. struct mutex mutex;
  55. struct workqueue_struct *dac33_wq;
  56. struct work_struct work;
  57. struct snd_soc_codec codec;
  58. int power_gpio;
  59. int chip_power;
  60. int irq;
  61. unsigned int refclk;
  62. unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
  63. unsigned int nsample_min; /* nsample should not be lower than
  64. * this */
  65. unsigned int nsample_max; /* nsample should not be higher than
  66. * this */
  67. unsigned int nsample_switch; /* Use FIFO or bypass FIFO switch */
  68. unsigned int nsample; /* burst read amount from host */
  69. enum dac33_state state;
  70. };
  71. static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
  72. 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
  73. 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
  74. 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
  75. 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
  76. 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
  77. 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
  78. 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
  79. 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
  80. 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
  81. 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
  82. 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
  83. 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
  84. 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
  85. 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
  86. 0x00, 0x00, /* 0x38 - 0x39 */
  87. /* Registers 0x3a - 0x3f are reserved */
  88. 0x00, 0x00, /* 0x3a - 0x3b */
  89. 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
  90. 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
  91. 0x00, 0x80, /* 0x44 - 0x45 */
  92. /* Registers 0x46 - 0x47 are reserved */
  93. 0x80, 0x80, /* 0x46 - 0x47 */
  94. 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
  95. /* Registers 0x4b - 0x7c are reserved */
  96. 0x00, /* 0x4b */
  97. 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
  98. 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
  99. 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
  100. 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
  101. 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
  102. 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
  103. 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
  104. 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
  105. 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
  106. 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
  107. 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
  108. 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
  109. 0x00, /* 0x7c */
  110. 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
  111. };
  112. /* Register read and write */
  113. static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
  114. unsigned reg)
  115. {
  116. u8 *cache = codec->reg_cache;
  117. if (reg >= DAC33_CACHEREGNUM)
  118. return 0;
  119. return cache[reg];
  120. }
  121. static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
  122. u8 reg, u8 value)
  123. {
  124. u8 *cache = codec->reg_cache;
  125. if (reg >= DAC33_CACHEREGNUM)
  126. return;
  127. cache[reg] = value;
  128. }
  129. static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
  130. u8 *value)
  131. {
  132. struct tlv320dac33_priv *dac33 = codec->private_data;
  133. int val;
  134. *value = reg & 0xff;
  135. /* If powered off, return the cached value */
  136. if (dac33->chip_power) {
  137. val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
  138. if (val < 0) {
  139. dev_err(codec->dev, "Read failed (%d)\n", val);
  140. value[0] = dac33_read_reg_cache(codec, reg);
  141. } else {
  142. value[0] = val;
  143. dac33_write_reg_cache(codec, reg, val);
  144. }
  145. } else {
  146. value[0] = dac33_read_reg_cache(codec, reg);
  147. }
  148. return 0;
  149. }
  150. static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
  151. unsigned int value)
  152. {
  153. struct tlv320dac33_priv *dac33 = codec->private_data;
  154. u8 data[2];
  155. int ret = 0;
  156. /*
  157. * data is
  158. * D15..D8 dac33 register offset
  159. * D7...D0 register data
  160. */
  161. data[0] = reg & 0xff;
  162. data[1] = value & 0xff;
  163. dac33_write_reg_cache(codec, data[0], data[1]);
  164. if (dac33->chip_power) {
  165. ret = codec->hw_write(codec->control_data, data, 2);
  166. if (ret != 2)
  167. dev_err(codec->dev, "Write failed (%d)\n", ret);
  168. else
  169. ret = 0;
  170. }
  171. return ret;
  172. }
  173. static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
  174. unsigned int value)
  175. {
  176. struct tlv320dac33_priv *dac33 = codec->private_data;
  177. int ret;
  178. mutex_lock(&dac33->mutex);
  179. ret = dac33_write(codec, reg, value);
  180. mutex_unlock(&dac33->mutex);
  181. return ret;
  182. }
  183. #define DAC33_I2C_ADDR_AUTOINC 0x80
  184. static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
  185. unsigned int value)
  186. {
  187. struct tlv320dac33_priv *dac33 = codec->private_data;
  188. u8 data[3];
  189. int ret = 0;
  190. /*
  191. * data is
  192. * D23..D16 dac33 register offset
  193. * D15..D8 register data MSB
  194. * D7...D0 register data LSB
  195. */
  196. data[0] = reg & 0xff;
  197. data[1] = (value >> 8) & 0xff;
  198. data[2] = value & 0xff;
  199. dac33_write_reg_cache(codec, data[0], data[1]);
  200. dac33_write_reg_cache(codec, data[0] + 1, data[2]);
  201. if (dac33->chip_power) {
  202. /* We need to set autoincrement mode for 16 bit writes */
  203. data[0] |= DAC33_I2C_ADDR_AUTOINC;
  204. ret = codec->hw_write(codec->control_data, data, 3);
  205. if (ret != 3)
  206. dev_err(codec->dev, "Write failed (%d)\n", ret);
  207. else
  208. ret = 0;
  209. }
  210. return ret;
  211. }
  212. static void dac33_restore_regs(struct snd_soc_codec *codec)
  213. {
  214. struct tlv320dac33_priv *dac33 = codec->private_data;
  215. u8 *cache = codec->reg_cache;
  216. u8 data[2];
  217. int i, ret;
  218. if (!dac33->chip_power)
  219. return;
  220. for (i = DAC33_PWR_CTRL; i <= DAC33_INTP_CTRL_B; i++) {
  221. data[0] = i;
  222. data[1] = cache[i];
  223. /* Skip the read only registers */
  224. if ((i >= DAC33_INT_OSC_STATUS &&
  225. i <= DAC33_INT_OSC_FREQ_RAT_READ_B) ||
  226. (i >= DAC33_FIFO_WPTR_MSB && i <= DAC33_FIFO_IRQ_FLAG) ||
  227. i == DAC33_DAC_STATUS_FLAGS ||
  228. i == DAC33_SRC_EST_REF_CLK_RATIO_A ||
  229. i == DAC33_SRC_EST_REF_CLK_RATIO_B)
  230. continue;
  231. ret = codec->hw_write(codec->control_data, data, 2);
  232. if (ret != 2)
  233. dev_err(codec->dev, "Write failed (%d)\n", ret);
  234. }
  235. for (i = DAC33_LDAC_PWR_CTRL; i <= DAC33_LINEL_TO_LLO_VOL; i++) {
  236. data[0] = i;
  237. data[1] = cache[i];
  238. ret = codec->hw_write(codec->control_data, data, 2);
  239. if (ret != 2)
  240. dev_err(codec->dev, "Write failed (%d)\n", ret);
  241. }
  242. for (i = DAC33_LINER_TO_RLO_VOL; i <= DAC33_OSC_TRIM; i++) {
  243. data[0] = i;
  244. data[1] = cache[i];
  245. ret = codec->hw_write(codec->control_data, data, 2);
  246. if (ret != 2)
  247. dev_err(codec->dev, "Write failed (%d)\n", ret);
  248. }
  249. }
  250. static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
  251. {
  252. u8 reg;
  253. reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
  254. if (power)
  255. reg |= DAC33_PDNALLB;
  256. else
  257. reg &= ~DAC33_PDNALLB;
  258. dac33_write(codec, DAC33_PWR_CTRL, reg);
  259. }
  260. static void dac33_hard_power(struct snd_soc_codec *codec, int power)
  261. {
  262. struct tlv320dac33_priv *dac33 = codec->private_data;
  263. mutex_lock(&dac33->mutex);
  264. if (power) {
  265. if (dac33->power_gpio >= 0) {
  266. gpio_set_value(dac33->power_gpio, 1);
  267. dac33->chip_power = 1;
  268. /* Restore registers */
  269. dac33_restore_regs(codec);
  270. }
  271. dac33_soft_power(codec, 1);
  272. } else {
  273. dac33_soft_power(codec, 0);
  274. if (dac33->power_gpio >= 0) {
  275. gpio_set_value(dac33->power_gpio, 0);
  276. dac33->chip_power = 0;
  277. }
  278. }
  279. mutex_unlock(&dac33->mutex);
  280. }
  281. static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
  282. struct snd_ctl_elem_value *ucontrol)
  283. {
  284. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  285. struct tlv320dac33_priv *dac33 = codec->private_data;
  286. ucontrol->value.integer.value[0] = dac33->nsample;
  287. return 0;
  288. }
  289. static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
  290. struct snd_ctl_elem_value *ucontrol)
  291. {
  292. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  293. struct tlv320dac33_priv *dac33 = codec->private_data;
  294. int ret = 0;
  295. if (dac33->nsample == ucontrol->value.integer.value[0])
  296. return 0;
  297. if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
  298. ucontrol->value.integer.value[0] > dac33->nsample_max)
  299. ret = -EINVAL;
  300. else
  301. dac33->nsample = ucontrol->value.integer.value[0];
  302. return ret;
  303. }
  304. static int dac33_get_nsample_switch(struct snd_kcontrol *kcontrol,
  305. struct snd_ctl_elem_value *ucontrol)
  306. {
  307. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  308. struct tlv320dac33_priv *dac33 = codec->private_data;
  309. ucontrol->value.integer.value[0] = dac33->nsample_switch;
  310. return 0;
  311. }
  312. static int dac33_set_nsample_switch(struct snd_kcontrol *kcontrol,
  313. struct snd_ctl_elem_value *ucontrol)
  314. {
  315. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  316. struct tlv320dac33_priv *dac33 = codec->private_data;
  317. int ret = 0;
  318. if (dac33->nsample_switch == ucontrol->value.integer.value[0])
  319. return 0;
  320. /* Do not allow changes while stream is running*/
  321. if (codec->active)
  322. return -EPERM;
  323. if (ucontrol->value.integer.value[0] < 0 ||
  324. ucontrol->value.integer.value[0] > 1)
  325. ret = -EINVAL;
  326. else
  327. dac33->nsample_switch = ucontrol->value.integer.value[0];
  328. return ret;
  329. }
  330. /*
  331. * DACL/R digital volume control:
  332. * from 0 dB to -63.5 in 0.5 dB steps
  333. * Need to be inverted later on:
  334. * 0x00 == 0 dB
  335. * 0x7f == -63.5 dB
  336. */
  337. static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
  338. static const struct snd_kcontrol_new dac33_snd_controls[] = {
  339. SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
  340. DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
  341. 0, 0x7f, 1, dac_digivol_tlv),
  342. SOC_DOUBLE_R("DAC Digital Playback Switch",
  343. DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
  344. SOC_DOUBLE_R("Line to Line Out Volume",
  345. DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
  346. };
  347. static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
  348. SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
  349. dac33_get_nsample, dac33_set_nsample),
  350. SOC_SINGLE_EXT("nSample Switch", 0, 0, 1, 0,
  351. dac33_get_nsample_switch, dac33_set_nsample_switch),
  352. };
  353. /* Analog bypass */
  354. static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
  355. SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
  356. static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
  357. SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
  358. static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
  359. SND_SOC_DAPM_OUTPUT("LEFT_LO"),
  360. SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
  361. SND_SOC_DAPM_INPUT("LINEL"),
  362. SND_SOC_DAPM_INPUT("LINER"),
  363. SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
  364. SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
  365. /* Analog bypass */
  366. SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
  367. &dac33_dapm_abypassl_control),
  368. SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
  369. &dac33_dapm_abypassr_control),
  370. SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
  371. DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
  372. SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
  373. DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
  374. };
  375. static const struct snd_soc_dapm_route audio_map[] = {
  376. /* Analog bypass */
  377. {"Analog Left Bypass", "Switch", "LINEL"},
  378. {"Analog Right Bypass", "Switch", "LINER"},
  379. {"Output Left Amp Power", NULL, "DACL"},
  380. {"Output Right Amp Power", NULL, "DACR"},
  381. {"Output Left Amp Power", NULL, "Analog Left Bypass"},
  382. {"Output Right Amp Power", NULL, "Analog Right Bypass"},
  383. /* output */
  384. {"LEFT_LO", NULL, "Output Left Amp Power"},
  385. {"RIGHT_LO", NULL, "Output Right Amp Power"},
  386. };
  387. static int dac33_add_widgets(struct snd_soc_codec *codec)
  388. {
  389. snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
  390. ARRAY_SIZE(dac33_dapm_widgets));
  391. /* set up audio path interconnects */
  392. snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
  393. return 0;
  394. }
  395. static int dac33_set_bias_level(struct snd_soc_codec *codec,
  396. enum snd_soc_bias_level level)
  397. {
  398. switch (level) {
  399. case SND_SOC_BIAS_ON:
  400. dac33_soft_power(codec, 1);
  401. break;
  402. case SND_SOC_BIAS_PREPARE:
  403. break;
  404. case SND_SOC_BIAS_STANDBY:
  405. if (codec->bias_level == SND_SOC_BIAS_OFF)
  406. dac33_hard_power(codec, 1);
  407. dac33_soft_power(codec, 0);
  408. break;
  409. case SND_SOC_BIAS_OFF:
  410. dac33_hard_power(codec, 0);
  411. break;
  412. }
  413. codec->bias_level = level;
  414. return 0;
  415. }
  416. static void dac33_work(struct work_struct *work)
  417. {
  418. struct snd_soc_codec *codec;
  419. struct tlv320dac33_priv *dac33;
  420. u8 reg;
  421. dac33 = container_of(work, struct tlv320dac33_priv, work);
  422. codec = &dac33->codec;
  423. mutex_lock(&dac33->mutex);
  424. switch (dac33->state) {
  425. case DAC33_PREFILL:
  426. dac33->state = DAC33_PLAYBACK;
  427. dac33_write16(codec, DAC33_NSAMPLE_MSB,
  428. DAC33_THRREG(dac33->nsample));
  429. dac33_write16(codec, DAC33_PREFILL_MSB,
  430. DAC33_THRREG(dac33->alarm_threshold));
  431. break;
  432. case DAC33_PLAYBACK:
  433. dac33_write16(codec, DAC33_NSAMPLE_MSB,
  434. DAC33_THRREG(dac33->nsample));
  435. break;
  436. case DAC33_IDLE:
  437. break;
  438. case DAC33_FLUSH:
  439. dac33->state = DAC33_IDLE;
  440. /* Mask all interrupts from dac33 */
  441. dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
  442. /* flush fifo */
  443. reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
  444. reg |= DAC33_FIFOFLUSH;
  445. dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
  446. break;
  447. }
  448. mutex_unlock(&dac33->mutex);
  449. }
  450. static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
  451. {
  452. struct snd_soc_codec *codec = dev;
  453. struct tlv320dac33_priv *dac33 = codec->private_data;
  454. queue_work(dac33->dac33_wq, &dac33->work);
  455. return IRQ_HANDLED;
  456. }
  457. static void dac33_shutdown(struct snd_pcm_substream *substream,
  458. struct snd_soc_dai *dai)
  459. {
  460. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  461. struct snd_soc_device *socdev = rtd->socdev;
  462. struct snd_soc_codec *codec = socdev->card->codec;
  463. struct tlv320dac33_priv *dac33 = codec->private_data;
  464. unsigned int pwr_ctrl;
  465. /* Stop pending workqueue */
  466. if (dac33->nsample_switch)
  467. cancel_work_sync(&dac33->work);
  468. mutex_lock(&dac33->mutex);
  469. pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
  470. pwr_ctrl &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
  471. dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
  472. mutex_unlock(&dac33->mutex);
  473. }
  474. static void dac33_oscwait(struct snd_soc_codec *codec)
  475. {
  476. int timeout = 20;
  477. u8 reg;
  478. do {
  479. msleep(1);
  480. dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
  481. } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
  482. if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
  483. dev_err(codec->dev,
  484. "internal oscillator calibration failed\n");
  485. }
  486. static int dac33_hw_params(struct snd_pcm_substream *substream,
  487. struct snd_pcm_hw_params *params,
  488. struct snd_soc_dai *dai)
  489. {
  490. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  491. struct snd_soc_device *socdev = rtd->socdev;
  492. struct snd_soc_codec *codec = socdev->card->codec;
  493. /* Check parameters for validity */
  494. switch (params_rate(params)) {
  495. case 44100:
  496. case 48000:
  497. break;
  498. default:
  499. dev_err(codec->dev, "unsupported rate %d\n",
  500. params_rate(params));
  501. return -EINVAL;
  502. }
  503. switch (params_format(params)) {
  504. case SNDRV_PCM_FORMAT_S16_LE:
  505. break;
  506. default:
  507. dev_err(codec->dev, "unsupported format %d\n",
  508. params_format(params));
  509. return -EINVAL;
  510. }
  511. return 0;
  512. }
  513. #define CALC_OSCSET(rate, refclk) ( \
  514. ((((rate * 10000) / refclk) * 4096) + 5000) / 10000)
  515. #define CALC_RATIOSET(rate, refclk) ( \
  516. ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
  517. /*
  518. * tlv320dac33 is strict on the sequence of the register writes, if the register
  519. * writes happens in different order, than dac33 might end up in unknown state.
  520. * Use the known, working sequence of register writes to initialize the dac33.
  521. */
  522. static int dac33_prepare_chip(struct snd_pcm_substream *substream)
  523. {
  524. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  525. struct snd_soc_device *socdev = rtd->socdev;
  526. struct snd_soc_codec *codec = socdev->card->codec;
  527. struct tlv320dac33_priv *dac33 = codec->private_data;
  528. unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
  529. u8 aictrl_a, fifoctrl_a;
  530. switch (substream->runtime->rate) {
  531. case 44100:
  532. case 48000:
  533. oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
  534. ratioset = CALC_RATIOSET(substream->runtime->rate,
  535. dac33->refclk);
  536. break;
  537. default:
  538. dev_err(codec->dev, "unsupported rate %d\n",
  539. substream->runtime->rate);
  540. return -EINVAL;
  541. }
  542. aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
  543. aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
  544. fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
  545. fifoctrl_a &= ~DAC33_WIDTH;
  546. switch (substream->runtime->format) {
  547. case SNDRV_PCM_FORMAT_S16_LE:
  548. aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
  549. fifoctrl_a |= DAC33_WIDTH;
  550. break;
  551. default:
  552. dev_err(codec->dev, "unsupported format %d\n",
  553. substream->runtime->format);
  554. return -EINVAL;
  555. }
  556. mutex_lock(&dac33->mutex);
  557. dac33_soft_power(codec, 1);
  558. reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
  559. dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
  560. /* Write registers 0x08 and 0x09 (MSB, LSB) */
  561. dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
  562. /* calib time: 128 is a nice number ;) */
  563. dac33_write(codec, DAC33_CALIB_TIME, 128);
  564. /* adjustment treshold & step */
  565. dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
  566. DAC33_ADJSTEP(1));
  567. /* div=4 / gain=1 / div */
  568. dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
  569. pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
  570. pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
  571. dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
  572. dac33_oscwait(codec);
  573. if (dac33->nsample_switch) {
  574. /* 50-51 : ASRC Control registers */
  575. dac33_write(codec, DAC33_ASRC_CTRL_A, (1 << 4)); /* div=2 */
  576. dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
  577. /* Write registers 0x34 and 0x35 (MSB, LSB) */
  578. dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
  579. /* Set interrupts to high active */
  580. dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
  581. dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
  582. DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
  583. dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
  584. } else {
  585. /* 50-51 : ASRC Control registers */
  586. dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
  587. dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
  588. }
  589. if (dac33->nsample_switch)
  590. fifoctrl_a &= ~DAC33_FBYPAS;
  591. else
  592. fifoctrl_a |= DAC33_FBYPAS;
  593. dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
  594. dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
  595. reg_tmp = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
  596. if (dac33->nsample_switch)
  597. reg_tmp &= ~DAC33_BCLKON;
  598. else
  599. reg_tmp |= DAC33_BCLKON;
  600. dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg_tmp);
  601. if (dac33->nsample_switch) {
  602. /* 20: BCLK divide ratio */
  603. dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 3);
  604. dac33_write16(codec, DAC33_ATHR_MSB,
  605. DAC33_THRREG(dac33->alarm_threshold));
  606. } else {
  607. dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
  608. }
  609. mutex_unlock(&dac33->mutex);
  610. return 0;
  611. }
  612. static void dac33_calculate_times(struct snd_pcm_substream *substream)
  613. {
  614. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  615. struct snd_soc_device *socdev = rtd->socdev;
  616. struct snd_soc_codec *codec = socdev->card->codec;
  617. struct tlv320dac33_priv *dac33 = codec->private_data;
  618. unsigned int nsample_limit;
  619. /* Number of samples (16bit, stereo) in one period */
  620. dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
  621. /* Number of samples (16bit, stereo) in ALSA buffer */
  622. dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
  623. /* Subtract one period from the total */
  624. dac33->nsample_max -= dac33->nsample_min;
  625. /* Number of samples for LATENCY_TIME_MS / 2 */
  626. dac33->alarm_threshold = substream->runtime->rate /
  627. (1000 / (LATENCY_TIME_MS / 2));
  628. /* Find and fix up the lowest nsmaple limit */
  629. nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
  630. if (dac33->nsample_min < nsample_limit)
  631. dac33->nsample_min = nsample_limit;
  632. if (dac33->nsample < dac33->nsample_min)
  633. dac33->nsample = dac33->nsample_min;
  634. /*
  635. * Find and fix up the highest nsmaple limit
  636. * In order to not overflow the DAC33 buffer substract the
  637. * alarm_threshold value from the size of the DAC33 buffer
  638. */
  639. nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
  640. if (dac33->nsample_max > nsample_limit)
  641. dac33->nsample_max = nsample_limit;
  642. if (dac33->nsample > dac33->nsample_max)
  643. dac33->nsample = dac33->nsample_max;
  644. }
  645. static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
  646. struct snd_soc_dai *dai)
  647. {
  648. dac33_calculate_times(substream);
  649. dac33_prepare_chip(substream);
  650. return 0;
  651. }
  652. static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
  653. struct snd_soc_dai *dai)
  654. {
  655. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  656. struct snd_soc_device *socdev = rtd->socdev;
  657. struct snd_soc_codec *codec = socdev->card->codec;
  658. struct tlv320dac33_priv *dac33 = codec->private_data;
  659. int ret = 0;
  660. switch (cmd) {
  661. case SNDRV_PCM_TRIGGER_START:
  662. case SNDRV_PCM_TRIGGER_RESUME:
  663. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  664. if (dac33->nsample_switch) {
  665. dac33->state = DAC33_PREFILL;
  666. queue_work(dac33->dac33_wq, &dac33->work);
  667. }
  668. break;
  669. case SNDRV_PCM_TRIGGER_STOP:
  670. case SNDRV_PCM_TRIGGER_SUSPEND:
  671. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  672. if (dac33->nsample_switch) {
  673. dac33->state = DAC33_FLUSH;
  674. queue_work(dac33->dac33_wq, &dac33->work);
  675. }
  676. break;
  677. default:
  678. ret = -EINVAL;
  679. }
  680. return ret;
  681. }
  682. static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  683. int clk_id, unsigned int freq, int dir)
  684. {
  685. struct snd_soc_codec *codec = codec_dai->codec;
  686. struct tlv320dac33_priv *dac33 = codec->private_data;
  687. u8 ioc_reg, asrcb_reg;
  688. ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
  689. asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
  690. switch (clk_id) {
  691. case TLV320DAC33_MCLK:
  692. ioc_reg |= DAC33_REFSEL;
  693. asrcb_reg |= DAC33_SRCREFSEL;
  694. break;
  695. case TLV320DAC33_SLEEPCLK:
  696. ioc_reg &= ~DAC33_REFSEL;
  697. asrcb_reg &= ~DAC33_SRCREFSEL;
  698. break;
  699. default:
  700. dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
  701. break;
  702. }
  703. dac33->refclk = freq;
  704. dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
  705. dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
  706. return 0;
  707. }
  708. static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
  709. unsigned int fmt)
  710. {
  711. struct snd_soc_codec *codec = codec_dai->codec;
  712. u8 aictrl_a, aictrl_b;
  713. aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
  714. aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
  715. /* set master/slave audio interface */
  716. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  717. case SND_SOC_DAIFMT_CBM_CFM:
  718. /* Codec Master */
  719. aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
  720. break;
  721. case SND_SOC_DAIFMT_CBS_CFS:
  722. /* Codec Slave */
  723. aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
  724. break;
  725. default:
  726. return -EINVAL;
  727. }
  728. aictrl_a &= ~DAC33_AFMT_MASK;
  729. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  730. case SND_SOC_DAIFMT_I2S:
  731. aictrl_a |= DAC33_AFMT_I2S;
  732. break;
  733. case SND_SOC_DAIFMT_DSP_A:
  734. aictrl_a |= DAC33_AFMT_DSP;
  735. aictrl_b &= ~DAC33_DATA_DELAY_MASK;
  736. aictrl_b |= DAC33_DATA_DELAY(1); /* 1 bit delay */
  737. break;
  738. case SND_SOC_DAIFMT_DSP_B:
  739. aictrl_a |= DAC33_AFMT_DSP;
  740. aictrl_b &= ~DAC33_DATA_DELAY_MASK; /* No delay */
  741. break;
  742. case SND_SOC_DAIFMT_RIGHT_J:
  743. aictrl_a |= DAC33_AFMT_RIGHT_J;
  744. break;
  745. case SND_SOC_DAIFMT_LEFT_J:
  746. aictrl_a |= DAC33_AFMT_LEFT_J;
  747. break;
  748. default:
  749. dev_err(codec->dev, "Unsupported format (%u)\n",
  750. fmt & SND_SOC_DAIFMT_FORMAT_MASK);
  751. return -EINVAL;
  752. }
  753. dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
  754. dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
  755. return 0;
  756. }
  757. static void dac33_init_chip(struct snd_soc_codec *codec)
  758. {
  759. /* 44-46: DAC Control Registers */
  760. /* A : DAC sample rate Fsref/1.5 */
  761. dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(1));
  762. /* B : DAC src=normal, not muted */
  763. dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
  764. DAC33_DACSRCL_LEFT);
  765. /* C : (defaults) */
  766. dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
  767. /* 64-65 : L&R DAC power control
  768. Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
  769. dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
  770. dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
  771. /* 73 : volume soft stepping control,
  772. clock source = internal osc (?) */
  773. dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
  774. /* 66 : LOP/LOM Modes */
  775. dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
  776. /* 68 : LOM inverted from LOP */
  777. dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
  778. dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
  779. }
  780. static int dac33_soc_probe(struct platform_device *pdev)
  781. {
  782. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  783. struct snd_soc_codec *codec;
  784. struct tlv320dac33_priv *dac33;
  785. int ret = 0;
  786. BUG_ON(!tlv320dac33_codec);
  787. codec = tlv320dac33_codec;
  788. socdev->card->codec = codec;
  789. dac33 = codec->private_data;
  790. /* Power up the codec */
  791. dac33_hard_power(codec, 1);
  792. /* Set default configuration */
  793. dac33_init_chip(codec);
  794. /* register pcms */
  795. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  796. if (ret < 0) {
  797. dev_err(codec->dev, "failed to create pcms\n");
  798. goto pcm_err;
  799. }
  800. snd_soc_add_controls(codec, dac33_snd_controls,
  801. ARRAY_SIZE(dac33_snd_controls));
  802. /* Only add the nSample controls, if we have valid IRQ number */
  803. if (dac33->irq >= 0)
  804. snd_soc_add_controls(codec, dac33_nsample_snd_controls,
  805. ARRAY_SIZE(dac33_nsample_snd_controls));
  806. dac33_add_widgets(codec);
  807. /* power on device */
  808. dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  809. return 0;
  810. pcm_err:
  811. dac33_hard_power(codec, 0);
  812. return ret;
  813. }
  814. static int dac33_soc_remove(struct platform_device *pdev)
  815. {
  816. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  817. struct snd_soc_codec *codec = socdev->card->codec;
  818. dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
  819. snd_soc_free_pcms(socdev);
  820. snd_soc_dapm_free(socdev);
  821. return 0;
  822. }
  823. static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
  824. {
  825. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  826. struct snd_soc_codec *codec = socdev->card->codec;
  827. dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
  828. return 0;
  829. }
  830. static int dac33_soc_resume(struct platform_device *pdev)
  831. {
  832. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  833. struct snd_soc_codec *codec = socdev->card->codec;
  834. dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  835. dac33_set_bias_level(codec, codec->suspend_bias_level);
  836. return 0;
  837. }
  838. struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
  839. .probe = dac33_soc_probe,
  840. .remove = dac33_soc_remove,
  841. .suspend = dac33_soc_suspend,
  842. .resume = dac33_soc_resume,
  843. };
  844. EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
  845. #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
  846. SNDRV_PCM_RATE_48000)
  847. #define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
  848. static struct snd_soc_dai_ops dac33_dai_ops = {
  849. .shutdown = dac33_shutdown,
  850. .hw_params = dac33_hw_params,
  851. .prepare = dac33_pcm_prepare,
  852. .trigger = dac33_pcm_trigger,
  853. .set_sysclk = dac33_set_dai_sysclk,
  854. .set_fmt = dac33_set_dai_fmt,
  855. };
  856. struct snd_soc_dai dac33_dai = {
  857. .name = "tlv320dac33",
  858. .playback = {
  859. .stream_name = "Playback",
  860. .channels_min = 2,
  861. .channels_max = 2,
  862. .rates = DAC33_RATES,
  863. .formats = DAC33_FORMATS,},
  864. .ops = &dac33_dai_ops,
  865. };
  866. EXPORT_SYMBOL_GPL(dac33_dai);
  867. static int dac33_i2c_probe(struct i2c_client *client,
  868. const struct i2c_device_id *id)
  869. {
  870. struct tlv320dac33_platform_data *pdata;
  871. struct tlv320dac33_priv *dac33;
  872. struct snd_soc_codec *codec;
  873. int ret = 0;
  874. if (client->dev.platform_data == NULL) {
  875. dev_err(&client->dev, "Platform data not set\n");
  876. return -ENODEV;
  877. }
  878. pdata = client->dev.platform_data;
  879. dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
  880. if (dac33 == NULL)
  881. return -ENOMEM;
  882. codec = &dac33->codec;
  883. codec->private_data = dac33;
  884. codec->control_data = client;
  885. mutex_init(&codec->mutex);
  886. mutex_init(&dac33->mutex);
  887. INIT_LIST_HEAD(&codec->dapm_widgets);
  888. INIT_LIST_HEAD(&codec->dapm_paths);
  889. codec->name = "tlv320dac33";
  890. codec->owner = THIS_MODULE;
  891. codec->read = dac33_read_reg_cache;
  892. codec->write = dac33_write_locked;
  893. codec->hw_write = (hw_write_t) i2c_master_send;
  894. codec->bias_level = SND_SOC_BIAS_OFF;
  895. codec->set_bias_level = dac33_set_bias_level;
  896. codec->dai = &dac33_dai;
  897. codec->num_dai = 1;
  898. codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
  899. codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
  900. GFP_KERNEL);
  901. if (codec->reg_cache == NULL) {
  902. ret = -ENOMEM;
  903. goto error_reg;
  904. }
  905. i2c_set_clientdata(client, dac33);
  906. dac33->power_gpio = pdata->power_gpio;
  907. dac33->irq = client->irq;
  908. dac33->nsample = NSAMPLE_MAX;
  909. /* Disable FIFO use by default */
  910. dac33->nsample_switch = 0;
  911. tlv320dac33_codec = codec;
  912. codec->dev = &client->dev;
  913. dac33_dai.dev = codec->dev;
  914. /* Check if the reset GPIO number is valid and request it */
  915. if (dac33->power_gpio >= 0) {
  916. ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
  917. if (ret < 0) {
  918. dev_err(codec->dev,
  919. "Failed to request reset GPIO (%d)\n",
  920. dac33->power_gpio);
  921. snd_soc_unregister_dai(&dac33_dai);
  922. snd_soc_unregister_codec(codec);
  923. goto error_gpio;
  924. }
  925. gpio_direction_output(dac33->power_gpio, 0);
  926. } else {
  927. dac33->chip_power = 1;
  928. }
  929. /* Check if the IRQ number is valid and request it */
  930. if (dac33->irq >= 0) {
  931. ret = request_irq(dac33->irq, dac33_interrupt_handler,
  932. IRQF_TRIGGER_RISING | IRQF_DISABLED,
  933. codec->name, codec);
  934. if (ret < 0) {
  935. dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
  936. dac33->irq, ret);
  937. dac33->irq = -1;
  938. }
  939. if (dac33->irq != -1) {
  940. /* Setup work queue */
  941. dac33->dac33_wq =
  942. create_singlethread_workqueue("tlv320dac33");
  943. if (dac33->dac33_wq == NULL) {
  944. free_irq(dac33->irq, &dac33->codec);
  945. ret = -ENOMEM;
  946. goto error_wq;
  947. }
  948. INIT_WORK(&dac33->work, dac33_work);
  949. }
  950. }
  951. ret = snd_soc_register_codec(codec);
  952. if (ret != 0) {
  953. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  954. goto error_codec;
  955. }
  956. ret = snd_soc_register_dai(&dac33_dai);
  957. if (ret != 0) {
  958. dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
  959. snd_soc_unregister_codec(codec);
  960. goto error_codec;
  961. }
  962. /* Shut down the codec for now */
  963. dac33_hard_power(codec, 0);
  964. return ret;
  965. error_codec:
  966. if (dac33->irq >= 0) {
  967. free_irq(dac33->irq, &dac33->codec);
  968. destroy_workqueue(dac33->dac33_wq);
  969. }
  970. error_wq:
  971. if (dac33->power_gpio >= 0)
  972. gpio_free(dac33->power_gpio);
  973. error_gpio:
  974. kfree(codec->reg_cache);
  975. error_reg:
  976. tlv320dac33_codec = NULL;
  977. kfree(dac33);
  978. return ret;
  979. }
  980. static int dac33_i2c_remove(struct i2c_client *client)
  981. {
  982. struct tlv320dac33_priv *dac33;
  983. dac33 = i2c_get_clientdata(client);
  984. dac33_hard_power(&dac33->codec, 0);
  985. if (dac33->power_gpio >= 0)
  986. gpio_free(dac33->power_gpio);
  987. if (dac33->irq >= 0)
  988. free_irq(dac33->irq, &dac33->codec);
  989. destroy_workqueue(dac33->dac33_wq);
  990. snd_soc_unregister_dai(&dac33_dai);
  991. snd_soc_unregister_codec(&dac33->codec);
  992. kfree(dac33->codec.reg_cache);
  993. kfree(dac33);
  994. tlv320dac33_codec = NULL;
  995. return 0;
  996. }
  997. static const struct i2c_device_id tlv320dac33_i2c_id[] = {
  998. {
  999. .name = "tlv320dac33",
  1000. .driver_data = 0,
  1001. },
  1002. { },
  1003. };
  1004. static struct i2c_driver tlv320dac33_i2c_driver = {
  1005. .driver = {
  1006. .name = "tlv320dac33",
  1007. .owner = THIS_MODULE,
  1008. },
  1009. .probe = dac33_i2c_probe,
  1010. .remove = __devexit_p(dac33_i2c_remove),
  1011. .id_table = tlv320dac33_i2c_id,
  1012. };
  1013. static int __init dac33_module_init(void)
  1014. {
  1015. int r;
  1016. r = i2c_add_driver(&tlv320dac33_i2c_driver);
  1017. if (r < 0) {
  1018. printk(KERN_ERR "DAC33: driver registration failed\n");
  1019. return r;
  1020. }
  1021. return 0;
  1022. }
  1023. module_init(dac33_module_init);
  1024. static void __exit dac33_module_exit(void)
  1025. {
  1026. i2c_del_driver(&tlv320dac33_i2c_driver);
  1027. }
  1028. module_exit(dac33_module_exit);
  1029. MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
  1030. MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
  1031. MODULE_LICENSE("GPL");