s3c2410_wdt.c 14 KB

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  1. /* linux/drivers/char/watchdog/s3c2410_wdt.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 Watchdog Timer Support
  7. *
  8. * Based on, softdog.c by Alan Cox,
  9. * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. */
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/types.h>
  28. #include <linux/timer.h>
  29. #include <linux/miscdevice.h>
  30. #include <linux/watchdog.h>
  31. #include <linux/fs.h>
  32. #include <linux/init.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/clk.h>
  36. #include <linux/uaccess.h>
  37. #include <linux/io.h>
  38. #include <linux/cpufreq.h>
  39. #include <mach/map.h>
  40. #undef S3C_VA_WATCHDOG
  41. #define S3C_VA_WATCHDOG (0)
  42. #include <plat/regs-watchdog.h>
  43. #define PFX "s3c2410-wdt: "
  44. #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
  45. #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
  46. static int nowayout = WATCHDOG_NOWAYOUT;
  47. static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
  48. static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
  49. static int soft_noboot;
  50. static int debug;
  51. module_param(tmr_margin, int, 0);
  52. module_param(tmr_atboot, int, 0);
  53. module_param(nowayout, int, 0);
  54. module_param(soft_noboot, int, 0);
  55. module_param(debug, int, 0);
  56. MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. default="
  57. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  58. MODULE_PARM_DESC(tmr_atboot,
  59. "Watchdog is started at boot time if set to 1, default="
  60. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
  61. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  62. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  63. MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
  64. "0 to reboot (default depends on ONLY_TESTING)");
  65. MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug, (default 0)");
  66. static unsigned long open_lock;
  67. static struct device *wdt_dev; /* platform device attached to */
  68. static struct resource *wdt_mem;
  69. static struct resource *wdt_irq;
  70. static struct clk *wdt_clock;
  71. static void __iomem *wdt_base;
  72. static unsigned int wdt_count;
  73. static char expect_close;
  74. static DEFINE_SPINLOCK(wdt_lock);
  75. /* watchdog control routines */
  76. #define DBG(msg...) do { \
  77. if (debug) \
  78. printk(KERN_INFO msg); \
  79. } while (0)
  80. /* functions */
  81. static void s3c2410wdt_keepalive(void)
  82. {
  83. spin_lock(&wdt_lock);
  84. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  85. spin_unlock(&wdt_lock);
  86. }
  87. static void __s3c2410wdt_stop(void)
  88. {
  89. unsigned long wtcon;
  90. wtcon = readl(wdt_base + S3C2410_WTCON);
  91. wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
  92. writel(wtcon, wdt_base + S3C2410_WTCON);
  93. }
  94. static void s3c2410wdt_stop(void)
  95. {
  96. spin_lock(&wdt_lock);
  97. __s3c2410wdt_stop();
  98. spin_unlock(&wdt_lock);
  99. }
  100. static void s3c2410wdt_start(void)
  101. {
  102. unsigned long wtcon;
  103. spin_lock(&wdt_lock);
  104. __s3c2410wdt_stop();
  105. wtcon = readl(wdt_base + S3C2410_WTCON);
  106. wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
  107. if (soft_noboot) {
  108. wtcon |= S3C2410_WTCON_INTEN;
  109. wtcon &= ~S3C2410_WTCON_RSTEN;
  110. } else {
  111. wtcon &= ~S3C2410_WTCON_INTEN;
  112. wtcon |= S3C2410_WTCON_RSTEN;
  113. }
  114. DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
  115. __func__, wdt_count, wtcon);
  116. writel(wdt_count, wdt_base + S3C2410_WTDAT);
  117. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  118. writel(wtcon, wdt_base + S3C2410_WTCON);
  119. spin_unlock(&wdt_lock);
  120. }
  121. static inline int s3c2410wdt_is_running(void)
  122. {
  123. return readl(wdt_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
  124. }
  125. static int s3c2410wdt_set_heartbeat(int timeout)
  126. {
  127. unsigned long freq = clk_get_rate(wdt_clock);
  128. unsigned int count;
  129. unsigned int divisor = 1;
  130. unsigned long wtcon;
  131. if (timeout < 1)
  132. return -EINVAL;
  133. freq /= 128;
  134. count = timeout * freq;
  135. DBG("%s: count=%d, timeout=%d, freq=%lu\n",
  136. __func__, count, timeout, freq);
  137. /* if the count is bigger than the watchdog register,
  138. then work out what we need to do (and if) we can
  139. actually make this value
  140. */
  141. if (count >= 0x10000) {
  142. for (divisor = 1; divisor <= 0x100; divisor++) {
  143. if ((count / divisor) < 0x10000)
  144. break;
  145. }
  146. if ((count / divisor) >= 0x10000) {
  147. dev_err(wdt_dev, "timeout %d too big\n", timeout);
  148. return -EINVAL;
  149. }
  150. }
  151. tmr_margin = timeout;
  152. DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
  153. __func__, timeout, divisor, count, count/divisor);
  154. count /= divisor;
  155. wdt_count = count;
  156. /* update the pre-scaler */
  157. wtcon = readl(wdt_base + S3C2410_WTCON);
  158. wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
  159. wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
  160. writel(count, wdt_base + S3C2410_WTDAT);
  161. writel(wtcon, wdt_base + S3C2410_WTCON);
  162. return 0;
  163. }
  164. /*
  165. * /dev/watchdog handling
  166. */
  167. static int s3c2410wdt_open(struct inode *inode, struct file *file)
  168. {
  169. if (test_and_set_bit(0, &open_lock))
  170. return -EBUSY;
  171. if (nowayout)
  172. __module_get(THIS_MODULE);
  173. expect_close = 0;
  174. /* start the timer */
  175. s3c2410wdt_start();
  176. return nonseekable_open(inode, file);
  177. }
  178. static int s3c2410wdt_release(struct inode *inode, struct file *file)
  179. {
  180. /*
  181. * Shut off the timer.
  182. * Lock it in if it's a module and we set nowayout
  183. */
  184. if (expect_close == 42)
  185. s3c2410wdt_stop();
  186. else {
  187. dev_err(wdt_dev, "Unexpected close, not stopping watchdog\n");
  188. s3c2410wdt_keepalive();
  189. }
  190. expect_close = 0;
  191. clear_bit(0, &open_lock);
  192. return 0;
  193. }
  194. static ssize_t s3c2410wdt_write(struct file *file, const char __user *data,
  195. size_t len, loff_t *ppos)
  196. {
  197. /*
  198. * Refresh the timer.
  199. */
  200. if (len) {
  201. if (!nowayout) {
  202. size_t i;
  203. /* In case it was set long ago */
  204. expect_close = 0;
  205. for (i = 0; i != len; i++) {
  206. char c;
  207. if (get_user(c, data + i))
  208. return -EFAULT;
  209. if (c == 'V')
  210. expect_close = 42;
  211. }
  212. }
  213. s3c2410wdt_keepalive();
  214. }
  215. return len;
  216. }
  217. #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
  218. static const struct watchdog_info s3c2410_wdt_ident = {
  219. .options = OPTIONS,
  220. .firmware_version = 0,
  221. .identity = "S3C2410 Watchdog",
  222. };
  223. static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd,
  224. unsigned long arg)
  225. {
  226. void __user *argp = (void __user *)arg;
  227. int __user *p = argp;
  228. int new_margin;
  229. switch (cmd) {
  230. case WDIOC_GETSUPPORT:
  231. return copy_to_user(argp, &s3c2410_wdt_ident,
  232. sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0;
  233. case WDIOC_GETSTATUS:
  234. case WDIOC_GETBOOTSTATUS:
  235. return put_user(0, p);
  236. case WDIOC_KEEPALIVE:
  237. s3c2410wdt_keepalive();
  238. return 0;
  239. case WDIOC_SETTIMEOUT:
  240. if (get_user(new_margin, p))
  241. return -EFAULT;
  242. if (s3c2410wdt_set_heartbeat(new_margin))
  243. return -EINVAL;
  244. s3c2410wdt_keepalive();
  245. return put_user(tmr_margin, p);
  246. case WDIOC_GETTIMEOUT:
  247. return put_user(tmr_margin, p);
  248. default:
  249. return -ENOTTY;
  250. }
  251. }
  252. /* kernel interface */
  253. static const struct file_operations s3c2410wdt_fops = {
  254. .owner = THIS_MODULE,
  255. .llseek = no_llseek,
  256. .write = s3c2410wdt_write,
  257. .unlocked_ioctl = s3c2410wdt_ioctl,
  258. .open = s3c2410wdt_open,
  259. .release = s3c2410wdt_release,
  260. };
  261. static struct miscdevice s3c2410wdt_miscdev = {
  262. .minor = WATCHDOG_MINOR,
  263. .name = "watchdog",
  264. .fops = &s3c2410wdt_fops,
  265. };
  266. /* interrupt handler code */
  267. static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
  268. {
  269. dev_info(wdt_dev, "watchdog timer expired (irq)\n");
  270. s3c2410wdt_keepalive();
  271. return IRQ_HANDLED;
  272. }
  273. #ifdef CONFIG_CPU_FREQ
  274. static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
  275. unsigned long val, void *data)
  276. {
  277. int ret;
  278. if (!s3c2410wdt_is_running())
  279. goto done;
  280. if (val == CPUFREQ_PRECHANGE) {
  281. /* To ensure that over the change we don't cause the
  282. * watchdog to trigger, we perform an keep-alive if
  283. * the watchdog is running.
  284. */
  285. s3c2410wdt_keepalive();
  286. } else if (val == CPUFREQ_POSTCHANGE) {
  287. s3c2410wdt_stop();
  288. ret = s3c2410wdt_set_heartbeat(tmr_margin);
  289. if (ret >= 0)
  290. s3c2410wdt_start();
  291. else
  292. goto err;
  293. }
  294. done:
  295. return 0;
  296. err:
  297. dev_err(wdt_dev, "cannot set new value for timeout %d\n", tmr_margin);
  298. return ret;
  299. }
  300. static struct notifier_block s3c2410wdt_cpufreq_transition_nb = {
  301. .notifier_call = s3c2410wdt_cpufreq_transition,
  302. };
  303. static inline int s3c2410wdt_cpufreq_register(void)
  304. {
  305. return cpufreq_register_notifier(&s3c2410wdt_cpufreq_transition_nb,
  306. CPUFREQ_TRANSITION_NOTIFIER);
  307. }
  308. static inline void s3c2410wdt_cpufreq_deregister(void)
  309. {
  310. cpufreq_unregister_notifier(&s3c2410wdt_cpufreq_transition_nb,
  311. CPUFREQ_TRANSITION_NOTIFIER);
  312. }
  313. #else
  314. static inline int s3c2410wdt_cpufreq_register(void)
  315. {
  316. return 0;
  317. }
  318. static inline void s3c2410wdt_cpufreq_deregister(void)
  319. {
  320. }
  321. #endif
  322. /* device interface */
  323. static int __devinit s3c2410wdt_probe(struct platform_device *pdev)
  324. {
  325. struct resource *res;
  326. struct device *dev;
  327. unsigned int wtcon;
  328. int started = 0;
  329. int ret;
  330. int size;
  331. DBG("%s: probe=%p\n", __func__, pdev);
  332. dev = &pdev->dev;
  333. wdt_dev = &pdev->dev;
  334. /* get the memory region for the watchdog timer */
  335. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  336. if (res == NULL) {
  337. dev_err(dev, "no memory resource specified\n");
  338. return -ENOENT;
  339. }
  340. size = resource_size(res);
  341. wdt_mem = request_mem_region(res->start, size, pdev->name);
  342. if (wdt_mem == NULL) {
  343. dev_err(dev, "failed to get memory region\n");
  344. ret = -ENOENT;
  345. goto err_req;
  346. }
  347. wdt_base = ioremap(res->start, size);
  348. if (wdt_base == NULL) {
  349. dev_err(dev, "failed to ioremap() region\n");
  350. ret = -EINVAL;
  351. goto err_req;
  352. }
  353. DBG("probe: mapped wdt_base=%p\n", wdt_base);
  354. wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  355. if (wdt_irq == NULL) {
  356. dev_err(dev, "no irq resource specified\n");
  357. ret = -ENOENT;
  358. goto err_map;
  359. }
  360. ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev);
  361. if (ret != 0) {
  362. dev_err(dev, "failed to install irq (%d)\n", ret);
  363. goto err_map;
  364. }
  365. wdt_clock = clk_get(&pdev->dev, "watchdog");
  366. if (IS_ERR(wdt_clock)) {
  367. dev_err(dev, "failed to find watchdog clock source\n");
  368. ret = PTR_ERR(wdt_clock);
  369. goto err_irq;
  370. }
  371. clk_enable(wdt_clock);
  372. if (s3c2410wdt_cpufreq_register() < 0) {
  373. printk(KERN_ERR PFX "failed to register cpufreq\n");
  374. goto err_clk;
  375. }
  376. /* see if we can actually set the requested timer margin, and if
  377. * not, try the default value */
  378. if (s3c2410wdt_set_heartbeat(tmr_margin)) {
  379. started = s3c2410wdt_set_heartbeat(
  380. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  381. if (started == 0)
  382. dev_info(dev,
  383. "tmr_margin value out of range, default %d used\n",
  384. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  385. else
  386. dev_info(dev, "default timer value is out of range, "
  387. "cannot start\n");
  388. }
  389. ret = misc_register(&s3c2410wdt_miscdev);
  390. if (ret) {
  391. dev_err(dev, "cannot register miscdev on minor=%d (%d)\n",
  392. WATCHDOG_MINOR, ret);
  393. goto err_cpufreq;
  394. }
  395. if (tmr_atboot && started == 0) {
  396. dev_info(dev, "starting watchdog timer\n");
  397. s3c2410wdt_start();
  398. } else if (!tmr_atboot) {
  399. /* if we're not enabling the watchdog, then ensure it is
  400. * disabled if it has been left running from the bootloader
  401. * or other source */
  402. s3c2410wdt_stop();
  403. }
  404. /* print out a statement of readiness */
  405. wtcon = readl(wdt_base + S3C2410_WTCON);
  406. dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
  407. (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
  408. (wtcon & S3C2410_WTCON_RSTEN) ? "" : "dis",
  409. (wtcon & S3C2410_WTCON_INTEN) ? "" : "en");
  410. return 0;
  411. err_cpufreq:
  412. s3c2410wdt_cpufreq_deregister();
  413. err_clk:
  414. clk_disable(wdt_clock);
  415. clk_put(wdt_clock);
  416. err_irq:
  417. free_irq(wdt_irq->start, pdev);
  418. err_map:
  419. iounmap(wdt_base);
  420. err_req:
  421. release_resource(wdt_mem);
  422. kfree(wdt_mem);
  423. return ret;
  424. }
  425. static int __devexit s3c2410wdt_remove(struct platform_device *dev)
  426. {
  427. s3c2410wdt_cpufreq_deregister();
  428. release_resource(wdt_mem);
  429. kfree(wdt_mem);
  430. wdt_mem = NULL;
  431. free_irq(wdt_irq->start, dev);
  432. wdt_irq = NULL;
  433. clk_disable(wdt_clock);
  434. clk_put(wdt_clock);
  435. wdt_clock = NULL;
  436. iounmap(wdt_base);
  437. misc_deregister(&s3c2410wdt_miscdev);
  438. return 0;
  439. }
  440. static void s3c2410wdt_shutdown(struct platform_device *dev)
  441. {
  442. s3c2410wdt_stop();
  443. }
  444. #ifdef CONFIG_PM
  445. static unsigned long wtcon_save;
  446. static unsigned long wtdat_save;
  447. static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state)
  448. {
  449. /* Save watchdog state, and turn it off. */
  450. wtcon_save = readl(wdt_base + S3C2410_WTCON);
  451. wtdat_save = readl(wdt_base + S3C2410_WTDAT);
  452. /* Note that WTCNT doesn't need to be saved. */
  453. s3c2410wdt_stop();
  454. return 0;
  455. }
  456. static int s3c2410wdt_resume(struct platform_device *dev)
  457. {
  458. /* Restore watchdog state. */
  459. writel(wtdat_save, wdt_base + S3C2410_WTDAT);
  460. writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
  461. writel(wtcon_save, wdt_base + S3C2410_WTCON);
  462. printk(KERN_INFO PFX "watchdog %sabled\n",
  463. (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
  464. return 0;
  465. }
  466. #else
  467. #define s3c2410wdt_suspend NULL
  468. #define s3c2410wdt_resume NULL
  469. #endif /* CONFIG_PM */
  470. static struct platform_driver s3c2410wdt_driver = {
  471. .probe = s3c2410wdt_probe,
  472. .remove = __devexit_p(s3c2410wdt_remove),
  473. .shutdown = s3c2410wdt_shutdown,
  474. .suspend = s3c2410wdt_suspend,
  475. .resume = s3c2410wdt_resume,
  476. .driver = {
  477. .owner = THIS_MODULE,
  478. .name = "s3c2410-wdt",
  479. },
  480. };
  481. static char banner[] __initdata =
  482. KERN_INFO "S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n";
  483. static int __init watchdog_init(void)
  484. {
  485. printk(banner);
  486. return platform_driver_register(&s3c2410wdt_driver);
  487. }
  488. static void __exit watchdog_exit(void)
  489. {
  490. platform_driver_unregister(&s3c2410wdt_driver);
  491. }
  492. module_init(watchdog_init);
  493. module_exit(watchdog_exit);
  494. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
  495. "Dimitry Andric <dimitry.andric@tomtom.com>");
  496. MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
  497. MODULE_LICENSE("GPL");
  498. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  499. MODULE_ALIAS("platform:s3c2410-wdt");