core.c 19 KB

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  1. /*
  2. * linux/drivers/video/omap2/dss/core.c
  3. *
  4. * Copyright (C) 2009 Nokia Corporation
  5. * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  6. *
  7. * Some code and ideas taken from drivers/video/omap/ driver
  8. * by Imre Deak.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License version 2 as published by
  12. * the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but WITHOUT
  15. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  17. * more details.
  18. *
  19. * You should have received a copy of the GNU General Public License along with
  20. * this program. If not, see <http://www.gnu.org/licenses/>.
  21. */
  22. #define DSS_SUBSYS_NAME "CORE"
  23. #include <linux/kernel.h>
  24. #include <linux/module.h>
  25. #include <linux/clk.h>
  26. #include <linux/err.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/io.h>
  31. #include <linux/device.h>
  32. #include <plat/display.h>
  33. #include <plat/clock.h>
  34. #include "dss.h"
  35. static struct {
  36. struct platform_device *pdev;
  37. int ctx_id;
  38. struct clk *dss_ick;
  39. struct clk *dss1_fck;
  40. struct clk *dss2_fck;
  41. struct clk *dss_54m_fck;
  42. struct clk *dss_96m_fck;
  43. unsigned num_clks_enabled;
  44. } core;
  45. static void dss_clk_enable_all_no_ctx(void);
  46. static void dss_clk_disable_all_no_ctx(void);
  47. static void dss_clk_enable_no_ctx(enum dss_clock clks);
  48. static void dss_clk_disable_no_ctx(enum dss_clock clks);
  49. static char *def_disp_name;
  50. module_param_named(def_disp, def_disp_name, charp, 0);
  51. MODULE_PARM_DESC(def_disp_name, "default display name");
  52. #ifdef DEBUG
  53. unsigned int dss_debug;
  54. module_param_named(debug, dss_debug, bool, 0644);
  55. #endif
  56. /* CONTEXT */
  57. static int dss_get_ctx_id(void)
  58. {
  59. struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
  60. int r;
  61. if (!pdata->get_last_off_on_transaction_id)
  62. return 0;
  63. r = pdata->get_last_off_on_transaction_id(&core.pdev->dev);
  64. if (r < 0) {
  65. dev_err(&core.pdev->dev, "getting transaction ID failed, "
  66. "will force context restore\n");
  67. r = -1;
  68. }
  69. return r;
  70. }
  71. int dss_need_ctx_restore(void)
  72. {
  73. int id = dss_get_ctx_id();
  74. if (id < 0 || id != core.ctx_id) {
  75. DSSDBG("ctx id %d -> id %d\n",
  76. core.ctx_id, id);
  77. core.ctx_id = id;
  78. return 1;
  79. } else {
  80. return 0;
  81. }
  82. }
  83. static void save_all_ctx(void)
  84. {
  85. DSSDBG("save context\n");
  86. dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
  87. dss_save_context();
  88. dispc_save_context();
  89. #ifdef CONFIG_OMAP2_DSS_DSI
  90. dsi_save_context();
  91. #endif
  92. dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
  93. }
  94. static void restore_all_ctx(void)
  95. {
  96. DSSDBG("restore context\n");
  97. dss_clk_enable_all_no_ctx();
  98. dss_restore_context();
  99. dispc_restore_context();
  100. #ifdef CONFIG_OMAP2_DSS_DSI
  101. dsi_restore_context();
  102. #endif
  103. dss_clk_disable_all_no_ctx();
  104. }
  105. #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
  106. /* CLOCKS */
  107. static void core_dump_clocks(struct seq_file *s)
  108. {
  109. int i;
  110. struct clk *clocks[5] = {
  111. core.dss_ick,
  112. core.dss1_fck,
  113. core.dss2_fck,
  114. core.dss_54m_fck,
  115. core.dss_96m_fck
  116. };
  117. seq_printf(s, "- CORE -\n");
  118. seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled);
  119. for (i = 0; i < 5; i++) {
  120. if (!clocks[i])
  121. continue;
  122. seq_printf(s, "%-15s\t%lu\t%d\n",
  123. clocks[i]->name,
  124. clk_get_rate(clocks[i]),
  125. clocks[i]->usecount);
  126. }
  127. }
  128. #endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
  129. static int dss_get_clock(struct clk **clock, const char *clk_name)
  130. {
  131. struct clk *clk;
  132. clk = clk_get(&core.pdev->dev, clk_name);
  133. if (IS_ERR(clk)) {
  134. DSSERR("can't get clock %s", clk_name);
  135. return PTR_ERR(clk);
  136. }
  137. *clock = clk;
  138. DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
  139. return 0;
  140. }
  141. static int dss_get_clocks(void)
  142. {
  143. int r;
  144. core.dss_ick = NULL;
  145. core.dss1_fck = NULL;
  146. core.dss2_fck = NULL;
  147. core.dss_54m_fck = NULL;
  148. core.dss_96m_fck = NULL;
  149. r = dss_get_clock(&core.dss_ick, "ick");
  150. if (r)
  151. goto err;
  152. r = dss_get_clock(&core.dss1_fck, "dss1_fck");
  153. if (r)
  154. goto err;
  155. r = dss_get_clock(&core.dss2_fck, "dss2_fck");
  156. if (r)
  157. goto err;
  158. r = dss_get_clock(&core.dss_54m_fck, "tv_fck");
  159. if (r)
  160. goto err;
  161. r = dss_get_clock(&core.dss_96m_fck, "video_fck");
  162. if (r)
  163. goto err;
  164. return 0;
  165. err:
  166. if (core.dss_ick)
  167. clk_put(core.dss_ick);
  168. if (core.dss1_fck)
  169. clk_put(core.dss1_fck);
  170. if (core.dss2_fck)
  171. clk_put(core.dss2_fck);
  172. if (core.dss_54m_fck)
  173. clk_put(core.dss_54m_fck);
  174. if (core.dss_96m_fck)
  175. clk_put(core.dss_96m_fck);
  176. return r;
  177. }
  178. static void dss_put_clocks(void)
  179. {
  180. if (core.dss_96m_fck)
  181. clk_put(core.dss_96m_fck);
  182. clk_put(core.dss_54m_fck);
  183. clk_put(core.dss1_fck);
  184. clk_put(core.dss2_fck);
  185. clk_put(core.dss_ick);
  186. }
  187. unsigned long dss_clk_get_rate(enum dss_clock clk)
  188. {
  189. switch (clk) {
  190. case DSS_CLK_ICK:
  191. return clk_get_rate(core.dss_ick);
  192. case DSS_CLK_FCK1:
  193. return clk_get_rate(core.dss1_fck);
  194. case DSS_CLK_FCK2:
  195. return clk_get_rate(core.dss2_fck);
  196. case DSS_CLK_54M:
  197. return clk_get_rate(core.dss_54m_fck);
  198. case DSS_CLK_96M:
  199. return clk_get_rate(core.dss_96m_fck);
  200. }
  201. BUG();
  202. return 0;
  203. }
  204. static unsigned count_clk_bits(enum dss_clock clks)
  205. {
  206. unsigned num_clks = 0;
  207. if (clks & DSS_CLK_ICK)
  208. ++num_clks;
  209. if (clks & DSS_CLK_FCK1)
  210. ++num_clks;
  211. if (clks & DSS_CLK_FCK2)
  212. ++num_clks;
  213. if (clks & DSS_CLK_54M)
  214. ++num_clks;
  215. if (clks & DSS_CLK_96M)
  216. ++num_clks;
  217. return num_clks;
  218. }
  219. static void dss_clk_enable_no_ctx(enum dss_clock clks)
  220. {
  221. unsigned num_clks = count_clk_bits(clks);
  222. if (clks & DSS_CLK_ICK)
  223. clk_enable(core.dss_ick);
  224. if (clks & DSS_CLK_FCK1)
  225. clk_enable(core.dss1_fck);
  226. if (clks & DSS_CLK_FCK2)
  227. clk_enable(core.dss2_fck);
  228. if (clks & DSS_CLK_54M)
  229. clk_enable(core.dss_54m_fck);
  230. if (clks & DSS_CLK_96M)
  231. clk_enable(core.dss_96m_fck);
  232. core.num_clks_enabled += num_clks;
  233. }
  234. void dss_clk_enable(enum dss_clock clks)
  235. {
  236. dss_clk_enable_no_ctx(clks);
  237. if (cpu_is_omap34xx() && dss_need_ctx_restore())
  238. restore_all_ctx();
  239. }
  240. static void dss_clk_disable_no_ctx(enum dss_clock clks)
  241. {
  242. unsigned num_clks = count_clk_bits(clks);
  243. if (clks & DSS_CLK_ICK)
  244. clk_disable(core.dss_ick);
  245. if (clks & DSS_CLK_FCK1)
  246. clk_disable(core.dss1_fck);
  247. if (clks & DSS_CLK_FCK2)
  248. clk_disable(core.dss2_fck);
  249. if (clks & DSS_CLK_54M)
  250. clk_disable(core.dss_54m_fck);
  251. if (clks & DSS_CLK_96M)
  252. clk_disable(core.dss_96m_fck);
  253. core.num_clks_enabled -= num_clks;
  254. }
  255. void dss_clk_disable(enum dss_clock clks)
  256. {
  257. if (cpu_is_omap34xx()) {
  258. unsigned num_clks = count_clk_bits(clks);
  259. BUG_ON(core.num_clks_enabled < num_clks);
  260. if (core.num_clks_enabled == num_clks)
  261. save_all_ctx();
  262. }
  263. dss_clk_disable_no_ctx(clks);
  264. }
  265. static void dss_clk_enable_all_no_ctx(void)
  266. {
  267. enum dss_clock clks;
  268. clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
  269. if (cpu_is_omap34xx())
  270. clks |= DSS_CLK_96M;
  271. dss_clk_enable_no_ctx(clks);
  272. }
  273. static void dss_clk_disable_all_no_ctx(void)
  274. {
  275. enum dss_clock clks;
  276. clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
  277. if (cpu_is_omap34xx())
  278. clks |= DSS_CLK_96M;
  279. dss_clk_disable_no_ctx(clks);
  280. }
  281. static void dss_clk_disable_all(void)
  282. {
  283. enum dss_clock clks;
  284. clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
  285. if (cpu_is_omap34xx())
  286. clks |= DSS_CLK_96M;
  287. dss_clk_disable(clks);
  288. }
  289. /* DEBUGFS */
  290. #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
  291. static void dss_debug_dump_clocks(struct seq_file *s)
  292. {
  293. core_dump_clocks(s);
  294. dss_dump_clocks(s);
  295. dispc_dump_clocks(s);
  296. #ifdef CONFIG_OMAP2_DSS_DSI
  297. dsi_dump_clocks(s);
  298. #endif
  299. }
  300. static int dss_debug_show(struct seq_file *s, void *unused)
  301. {
  302. void (*func)(struct seq_file *) = s->private;
  303. func(s);
  304. return 0;
  305. }
  306. static int dss_debug_open(struct inode *inode, struct file *file)
  307. {
  308. return single_open(file, dss_debug_show, inode->i_private);
  309. }
  310. static const struct file_operations dss_debug_fops = {
  311. .open = dss_debug_open,
  312. .read = seq_read,
  313. .llseek = seq_lseek,
  314. .release = single_release,
  315. };
  316. static struct dentry *dss_debugfs_dir;
  317. static int dss_initialize_debugfs(void)
  318. {
  319. dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
  320. if (IS_ERR(dss_debugfs_dir)) {
  321. int err = PTR_ERR(dss_debugfs_dir);
  322. dss_debugfs_dir = NULL;
  323. return err;
  324. }
  325. debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
  326. &dss_debug_dump_clocks, &dss_debug_fops);
  327. debugfs_create_file("dispc_irq", S_IRUGO, dss_debugfs_dir,
  328. &dispc_dump_irqs, &dss_debug_fops);
  329. #ifdef CONFIG_OMAP2_DSS_DSI
  330. debugfs_create_file("dsi_irq", S_IRUGO, dss_debugfs_dir,
  331. &dsi_dump_irqs, &dss_debug_fops);
  332. #endif
  333. debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir,
  334. &dss_dump_regs, &dss_debug_fops);
  335. debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir,
  336. &dispc_dump_regs, &dss_debug_fops);
  337. #ifdef CONFIG_OMAP2_DSS_RFBI
  338. debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir,
  339. &rfbi_dump_regs, &dss_debug_fops);
  340. #endif
  341. #ifdef CONFIG_OMAP2_DSS_DSI
  342. debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir,
  343. &dsi_dump_regs, &dss_debug_fops);
  344. #endif
  345. #ifdef CONFIG_OMAP2_DSS_VENC
  346. debugfs_create_file("venc", S_IRUGO, dss_debugfs_dir,
  347. &venc_dump_regs, &dss_debug_fops);
  348. #endif
  349. return 0;
  350. }
  351. static void dss_uninitialize_debugfs(void)
  352. {
  353. if (dss_debugfs_dir)
  354. debugfs_remove_recursive(dss_debugfs_dir);
  355. }
  356. #endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */
  357. /* PLATFORM DEVICE */
  358. static int omap_dss_probe(struct platform_device *pdev)
  359. {
  360. struct omap_dss_board_info *pdata = pdev->dev.platform_data;
  361. int skip_init = 0;
  362. int r;
  363. int i;
  364. core.pdev = pdev;
  365. dss_init_overlay_managers(pdev);
  366. dss_init_overlays(pdev);
  367. r = dss_get_clocks();
  368. if (r)
  369. goto fail0;
  370. dss_clk_enable_all_no_ctx();
  371. core.ctx_id = dss_get_ctx_id();
  372. DSSDBG("initial ctx id %u\n", core.ctx_id);
  373. #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
  374. /* DISPC_CONTROL */
  375. if (omap_readl(0x48050440) & 1) /* LCD enabled? */
  376. skip_init = 1;
  377. #endif
  378. r = dss_init(skip_init);
  379. if (r) {
  380. DSSERR("Failed to initialize DSS\n");
  381. goto fail0;
  382. }
  383. #ifdef CONFIG_OMAP2_DSS_RFBI
  384. r = rfbi_init();
  385. if (r) {
  386. DSSERR("Failed to initialize rfbi\n");
  387. goto fail0;
  388. }
  389. #endif
  390. r = dpi_init();
  391. if (r) {
  392. DSSERR("Failed to initialize dpi\n");
  393. goto fail0;
  394. }
  395. r = dispc_init();
  396. if (r) {
  397. DSSERR("Failed to initialize dispc\n");
  398. goto fail0;
  399. }
  400. #ifdef CONFIG_OMAP2_DSS_VENC
  401. r = venc_init(pdev);
  402. if (r) {
  403. DSSERR("Failed to initialize venc\n");
  404. goto fail0;
  405. }
  406. #endif
  407. if (cpu_is_omap34xx()) {
  408. #ifdef CONFIG_OMAP2_DSS_SDI
  409. r = sdi_init(skip_init);
  410. if (r) {
  411. DSSERR("Failed to initialize SDI\n");
  412. goto fail0;
  413. }
  414. #endif
  415. #ifdef CONFIG_OMAP2_DSS_DSI
  416. r = dsi_init(pdev);
  417. if (r) {
  418. DSSERR("Failed to initialize DSI\n");
  419. goto fail0;
  420. }
  421. #endif
  422. }
  423. #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
  424. r = dss_initialize_debugfs();
  425. if (r)
  426. goto fail0;
  427. #endif
  428. for (i = 0; i < pdata->num_devices; ++i) {
  429. struct omap_dss_device *dssdev = pdata->devices[i];
  430. r = omap_dss_register_device(dssdev);
  431. if (r)
  432. DSSERR("device reg failed %d\n", i);
  433. if (def_disp_name && strcmp(def_disp_name, dssdev->name) == 0)
  434. pdata->default_device = dssdev;
  435. }
  436. dss_clk_disable_all();
  437. return 0;
  438. /* XXX fail correctly */
  439. fail0:
  440. return r;
  441. }
  442. static int omap_dss_remove(struct platform_device *pdev)
  443. {
  444. struct omap_dss_board_info *pdata = pdev->dev.platform_data;
  445. int i;
  446. int c;
  447. #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
  448. dss_uninitialize_debugfs();
  449. #endif
  450. #ifdef CONFIG_OMAP2_DSS_VENC
  451. venc_exit();
  452. #endif
  453. dispc_exit();
  454. dpi_exit();
  455. #ifdef CONFIG_OMAP2_DSS_RFBI
  456. rfbi_exit();
  457. #endif
  458. if (cpu_is_omap34xx()) {
  459. #ifdef CONFIG_OMAP2_DSS_DSI
  460. dsi_exit();
  461. #endif
  462. #ifdef CONFIG_OMAP2_DSS_SDI
  463. sdi_exit();
  464. #endif
  465. }
  466. dss_exit();
  467. /* these should be removed at some point */
  468. c = core.dss_ick->usecount;
  469. if (c > 0) {
  470. DSSERR("warning: dss_ick usecount %d, disabling\n", c);
  471. while (c-- > 0)
  472. clk_disable(core.dss_ick);
  473. }
  474. c = core.dss1_fck->usecount;
  475. if (c > 0) {
  476. DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
  477. while (c-- > 0)
  478. clk_disable(core.dss1_fck);
  479. }
  480. c = core.dss2_fck->usecount;
  481. if (c > 0) {
  482. DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
  483. while (c-- > 0)
  484. clk_disable(core.dss2_fck);
  485. }
  486. c = core.dss_54m_fck->usecount;
  487. if (c > 0) {
  488. DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
  489. while (c-- > 0)
  490. clk_disable(core.dss_54m_fck);
  491. }
  492. if (core.dss_96m_fck) {
  493. c = core.dss_96m_fck->usecount;
  494. if (c > 0) {
  495. DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
  496. c);
  497. while (c-- > 0)
  498. clk_disable(core.dss_96m_fck);
  499. }
  500. }
  501. dss_put_clocks();
  502. dss_uninit_overlays(pdev);
  503. dss_uninit_overlay_managers(pdev);
  504. for (i = 0; i < pdata->num_devices; ++i)
  505. omap_dss_unregister_device(pdata->devices[i]);
  506. return 0;
  507. }
  508. static void omap_dss_shutdown(struct platform_device *pdev)
  509. {
  510. DSSDBG("shutdown\n");
  511. dss_disable_all_devices();
  512. }
  513. static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state)
  514. {
  515. DSSDBG("suspend %d\n", state.event);
  516. return dss_suspend_all_devices();
  517. }
  518. static int omap_dss_resume(struct platform_device *pdev)
  519. {
  520. DSSDBG("resume\n");
  521. return dss_resume_all_devices();
  522. }
  523. static struct platform_driver omap_dss_driver = {
  524. .probe = omap_dss_probe,
  525. .remove = omap_dss_remove,
  526. .shutdown = omap_dss_shutdown,
  527. .suspend = omap_dss_suspend,
  528. .resume = omap_dss_resume,
  529. .driver = {
  530. .name = "omapdss",
  531. .owner = THIS_MODULE,
  532. },
  533. };
  534. /* BUS */
  535. static int dss_bus_match(struct device *dev, struct device_driver *driver)
  536. {
  537. struct omap_dss_device *dssdev = to_dss_device(dev);
  538. DSSDBG("bus_match. dev %s/%s, drv %s\n",
  539. dev_name(dev), dssdev->driver_name, driver->name);
  540. return strcmp(dssdev->driver_name, driver->name) == 0;
  541. }
  542. static ssize_t device_name_show(struct device *dev,
  543. struct device_attribute *attr, char *buf)
  544. {
  545. struct omap_dss_device *dssdev = to_dss_device(dev);
  546. return snprintf(buf, PAGE_SIZE, "%s\n",
  547. dssdev->name ?
  548. dssdev->name : "");
  549. }
  550. static struct device_attribute default_dev_attrs[] = {
  551. __ATTR(name, S_IRUGO, device_name_show, NULL),
  552. __ATTR_NULL,
  553. };
  554. static ssize_t driver_name_show(struct device_driver *drv, char *buf)
  555. {
  556. struct omap_dss_driver *dssdrv = to_dss_driver(drv);
  557. return snprintf(buf, PAGE_SIZE, "%s\n",
  558. dssdrv->driver.name ?
  559. dssdrv->driver.name : "");
  560. }
  561. static struct driver_attribute default_drv_attrs[] = {
  562. __ATTR(name, S_IRUGO, driver_name_show, NULL),
  563. __ATTR_NULL,
  564. };
  565. static struct bus_type dss_bus_type = {
  566. .name = "omapdss",
  567. .match = dss_bus_match,
  568. .dev_attrs = default_dev_attrs,
  569. .drv_attrs = default_drv_attrs,
  570. };
  571. static void dss_bus_release(struct device *dev)
  572. {
  573. DSSDBG("bus_release\n");
  574. }
  575. static struct device dss_bus = {
  576. .release = dss_bus_release,
  577. };
  578. struct bus_type *dss_get_bus(void)
  579. {
  580. return &dss_bus_type;
  581. }
  582. /* DRIVER */
  583. static int dss_driver_probe(struct device *dev)
  584. {
  585. int r;
  586. struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
  587. struct omap_dss_device *dssdev = to_dss_device(dev);
  588. struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
  589. bool force;
  590. DSSDBG("driver_probe: dev %s/%s, drv %s\n",
  591. dev_name(dev), dssdev->driver_name,
  592. dssdrv->driver.name);
  593. dss_init_device(core.pdev, dssdev);
  594. /* skip this if the device is behind a ctrl */
  595. if (!dssdev->panel.ctrl) {
  596. force = pdata->default_device == dssdev;
  597. dss_recheck_connections(dssdev, force);
  598. }
  599. r = dssdrv->probe(dssdev);
  600. if (r) {
  601. DSSERR("driver probe failed: %d\n", r);
  602. return r;
  603. }
  604. DSSDBG("probe done for device %s\n", dev_name(dev));
  605. dssdev->driver = dssdrv;
  606. return 0;
  607. }
  608. static int dss_driver_remove(struct device *dev)
  609. {
  610. struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
  611. struct omap_dss_device *dssdev = to_dss_device(dev);
  612. DSSDBG("driver_remove: dev %s/%s\n", dev_name(dev),
  613. dssdev->driver_name);
  614. dssdrv->remove(dssdev);
  615. dss_uninit_device(core.pdev, dssdev);
  616. dssdev->driver = NULL;
  617. return 0;
  618. }
  619. int omap_dss_register_driver(struct omap_dss_driver *dssdriver)
  620. {
  621. dssdriver->driver.bus = &dss_bus_type;
  622. dssdriver->driver.probe = dss_driver_probe;
  623. dssdriver->driver.remove = dss_driver_remove;
  624. return driver_register(&dssdriver->driver);
  625. }
  626. EXPORT_SYMBOL(omap_dss_register_driver);
  627. void omap_dss_unregister_driver(struct omap_dss_driver *dssdriver)
  628. {
  629. driver_unregister(&dssdriver->driver);
  630. }
  631. EXPORT_SYMBOL(omap_dss_unregister_driver);
  632. /* DEVICE */
  633. static void reset_device(struct device *dev, int check)
  634. {
  635. u8 *dev_p = (u8 *)dev;
  636. u8 *dev_end = dev_p + sizeof(*dev);
  637. void *saved_pdata;
  638. saved_pdata = dev->platform_data;
  639. if (check) {
  640. /*
  641. * Check if there is any other setting than platform_data
  642. * in struct device; warn that these will be reset by our
  643. * init.
  644. */
  645. dev->platform_data = NULL;
  646. while (dev_p < dev_end) {
  647. if (*dev_p) {
  648. WARN("%s: struct device fields will be "
  649. "discarded\n",
  650. __func__);
  651. break;
  652. }
  653. dev_p++;
  654. }
  655. }
  656. memset(dev, 0, sizeof(*dev));
  657. dev->platform_data = saved_pdata;
  658. }
  659. static void omap_dss_dev_release(struct device *dev)
  660. {
  661. reset_device(dev, 0);
  662. }
  663. int omap_dss_register_device(struct omap_dss_device *dssdev)
  664. {
  665. static int dev_num;
  666. static int panel_num;
  667. int r;
  668. WARN_ON(!dssdev->driver_name);
  669. reset_device(&dssdev->dev, 1);
  670. dssdev->dev.bus = &dss_bus_type;
  671. dssdev->dev.parent = &dss_bus;
  672. dssdev->dev.release = omap_dss_dev_release;
  673. dev_set_name(&dssdev->dev, "display%d", dev_num++);
  674. r = device_register(&dssdev->dev);
  675. if (r)
  676. return r;
  677. if (dssdev->ctrl.panel) {
  678. struct omap_dss_device *panel = dssdev->ctrl.panel;
  679. panel->panel.ctrl = dssdev;
  680. reset_device(&panel->dev, 1);
  681. panel->dev.bus = &dss_bus_type;
  682. panel->dev.parent = &dssdev->dev;
  683. panel->dev.release = omap_dss_dev_release;
  684. dev_set_name(&panel->dev, "panel%d", panel_num++);
  685. r = device_register(&panel->dev);
  686. if (r)
  687. return r;
  688. }
  689. return 0;
  690. }
  691. void omap_dss_unregister_device(struct omap_dss_device *dssdev)
  692. {
  693. device_unregister(&dssdev->dev);
  694. if (dssdev->ctrl.panel) {
  695. struct omap_dss_device *panel = dssdev->ctrl.panel;
  696. device_unregister(&panel->dev);
  697. }
  698. }
  699. /* BUS */
  700. static int omap_dss_bus_register(void)
  701. {
  702. int r;
  703. r = bus_register(&dss_bus_type);
  704. if (r) {
  705. DSSERR("bus register failed\n");
  706. return r;
  707. }
  708. dev_set_name(&dss_bus, "omapdss");
  709. r = device_register(&dss_bus);
  710. if (r) {
  711. DSSERR("bus driver register failed\n");
  712. bus_unregister(&dss_bus_type);
  713. return r;
  714. }
  715. return 0;
  716. }
  717. /* INIT */
  718. #ifdef CONFIG_OMAP2_DSS_MODULE
  719. static void omap_dss_bus_unregister(void)
  720. {
  721. device_unregister(&dss_bus);
  722. bus_unregister(&dss_bus_type);
  723. }
  724. static int __init omap_dss_init(void)
  725. {
  726. int r;
  727. r = omap_dss_bus_register();
  728. if (r)
  729. return r;
  730. r = platform_driver_register(&omap_dss_driver);
  731. if (r) {
  732. omap_dss_bus_unregister();
  733. return r;
  734. }
  735. return 0;
  736. }
  737. static void __exit omap_dss_exit(void)
  738. {
  739. platform_driver_unregister(&omap_dss_driver);
  740. omap_dss_bus_unregister();
  741. }
  742. module_init(omap_dss_init);
  743. module_exit(omap_dss_exit);
  744. #else
  745. static int __init omap_dss_init(void)
  746. {
  747. return omap_dss_bus_register();
  748. }
  749. static int __init omap_dss_init2(void)
  750. {
  751. return platform_driver_register(&omap_dss_driver);
  752. }
  753. core_initcall(omap_dss_init);
  754. device_initcall(omap_dss_init2);
  755. #endif
  756. MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
  757. MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
  758. MODULE_LICENSE("GPL v2");