ep93xx-fb.c 17 KB

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  1. /*
  2. * linux/drivers/video/ep93xx-fb.c
  3. *
  4. * Framebuffer support for the EP93xx series.
  5. *
  6. * Copyright (C) 2007 Bluewater Systems Ltd
  7. * Author: Ryan Mallon <ryan@bluewatersys.com>
  8. *
  9. * Copyright (c) 2009 H Hartley Sweeten <hsweeten@visionengravers.com>
  10. *
  11. * Based on the Cirrus Logic ep93xxfb driver, and various other ep93xxfb
  12. * drivers.
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License version 2 as
  16. * published by the Free Software Foundation.
  17. *
  18. */
  19. #include <linux/platform_device.h>
  20. #include <linux/dma-mapping.h>
  21. #include <linux/clk.h>
  22. #include <linux/fb.h>
  23. #include <mach/fb.h>
  24. /* Vertical Frame Timing Registers */
  25. #define EP93XXFB_VLINES_TOTAL 0x0000 /* SW locked */
  26. #define EP93XXFB_VSYNC 0x0004 /* SW locked */
  27. #define EP93XXFB_VACTIVE 0x0008 /* SW locked */
  28. #define EP93XXFB_VBLANK 0x0228 /* SW locked */
  29. #define EP93XXFB_VCLK 0x000c /* SW locked */
  30. /* Horizontal Frame Timing Registers */
  31. #define EP93XXFB_HCLKS_TOTAL 0x0010 /* SW locked */
  32. #define EP93XXFB_HSYNC 0x0014 /* SW locked */
  33. #define EP93XXFB_HACTIVE 0x0018 /* SW locked */
  34. #define EP93XXFB_HBLANK 0x022c /* SW locked */
  35. #define EP93XXFB_HCLK 0x001c /* SW locked */
  36. /* Frame Buffer Memory Configuration Registers */
  37. #define EP93XXFB_SCREEN_PAGE 0x0028
  38. #define EP93XXFB_SCREEN_HPAGE 0x002c
  39. #define EP93XXFB_SCREEN_LINES 0x0030
  40. #define EP93XXFB_LINE_LENGTH 0x0034
  41. #define EP93XXFB_VLINE_STEP 0x0038
  42. #define EP93XXFB_LINE_CARRY 0x003c /* SW locked */
  43. #define EP93XXFB_EOL_OFFSET 0x0230
  44. /* Other Video Registers */
  45. #define EP93XXFB_BRIGHTNESS 0x0020
  46. #define EP93XXFB_ATTRIBS 0x0024 /* SW locked */
  47. #define EP93XXFB_SWLOCK 0x007c /* SW locked */
  48. #define EP93XXFB_AC_RATE 0x0214
  49. #define EP93XXFB_FIFO_LEVEL 0x0234
  50. #define EP93XXFB_PIXELMODE 0x0054
  51. #define EP93XXFB_PIXELMODE_32BPP (0x7 << 0)
  52. #define EP93XXFB_PIXELMODE_24BPP (0x6 << 0)
  53. #define EP93XXFB_PIXELMODE_16BPP (0x4 << 0)
  54. #define EP93XXFB_PIXELMODE_8BPP (0x2 << 0)
  55. #define EP93XXFB_PIXELMODE_SHIFT_1P_24B (0x0 << 3)
  56. #define EP93XXFB_PIXELMODE_SHIFT_1P_18B (0x1 << 3)
  57. #define EP93XXFB_PIXELMODE_COLOR_LUT (0x0 << 10)
  58. #define EP93XXFB_PIXELMODE_COLOR_888 (0x4 << 10)
  59. #define EP93XXFB_PIXELMODE_COLOR_555 (0x5 << 10)
  60. #define EP93XXFB_PARL_IF_OUT 0x0058
  61. #define EP93XXFB_PARL_IF_IN 0x005c
  62. /* Blink Control Registers */
  63. #define EP93XXFB_BLINK_RATE 0x0040
  64. #define EP93XXFB_BLINK_MASK 0x0044
  65. #define EP93XXFB_BLINK_PATTRN 0x0048
  66. #define EP93XXFB_PATTRN_MASK 0x004c
  67. #define EP93XXFB_BKGRND_OFFSET 0x0050
  68. /* Hardware Cursor Registers */
  69. #define EP93XXFB_CURSOR_ADR_START 0x0060
  70. #define EP93XXFB_CURSOR_ADR_RESET 0x0064
  71. #define EP93XXFB_CURSOR_SIZE 0x0068
  72. #define EP93XXFB_CURSOR_COLOR1 0x006c
  73. #define EP93XXFB_CURSOR_COLOR2 0x0070
  74. #define EP93XXFB_CURSOR_BLINK_COLOR1 0x021c
  75. #define EP93XXFB_CURSOR_BLINK_COLOR2 0x0220
  76. #define EP93XXFB_CURSOR_XY_LOC 0x0074
  77. #define EP93XXFB_CURSOR_DSCAN_HY_LOC 0x0078
  78. #define EP93XXFB_CURSOR_BLINK_RATE_CTRL 0x0224
  79. /* LUT Registers */
  80. #define EP93XXFB_GRY_SCL_LUTR 0x0080
  81. #define EP93XXFB_GRY_SCL_LUTG 0x0280
  82. #define EP93XXFB_GRY_SCL_LUTB 0x0300
  83. #define EP93XXFB_LUT_SW_CONTROL 0x0218
  84. #define EP93XXFB_LUT_SW_CONTROL_SWTCH (1 << 0)
  85. #define EP93XXFB_LUT_SW_CONTROL_SSTAT (1 << 1)
  86. #define EP93XXFB_COLOR_LUT 0x0400
  87. /* Video Signature Registers */
  88. #define EP93XXFB_VID_SIG_RSLT_VAL 0x0200
  89. #define EP93XXFB_VID_SIG_CTRL 0x0204
  90. #define EP93XXFB_VSIG 0x0208
  91. #define EP93XXFB_HSIG 0x020c
  92. #define EP93XXFB_SIG_CLR_STR 0x0210
  93. /* Minimum / Maximum resolutions supported */
  94. #define EP93XXFB_MIN_XRES 64
  95. #define EP93XXFB_MIN_YRES 64
  96. #define EP93XXFB_MAX_XRES 1024
  97. #define EP93XXFB_MAX_YRES 768
  98. struct ep93xx_fbi {
  99. struct ep93xxfb_mach_info *mach_info;
  100. struct clk *clk;
  101. struct resource *res;
  102. void __iomem *mmio_base;
  103. unsigned int pseudo_palette[256];
  104. };
  105. static int check_screenpage_bug = 1;
  106. module_param(check_screenpage_bug, int, 0644);
  107. MODULE_PARM_DESC(check_screenpage_bug,
  108. "Check for bit 27 screen page bug. Default = 1");
  109. static inline unsigned int ep93xxfb_readl(struct ep93xx_fbi *fbi,
  110. unsigned int off)
  111. {
  112. return __raw_readl(fbi->mmio_base + off);
  113. }
  114. static inline void ep93xxfb_writel(struct ep93xx_fbi *fbi,
  115. unsigned int val, unsigned int off)
  116. {
  117. __raw_writel(val, fbi->mmio_base + off);
  118. }
  119. /*
  120. * Write to one of the locked raster registers.
  121. */
  122. static inline void ep93xxfb_out_locked(struct ep93xx_fbi *fbi,
  123. unsigned int val, unsigned int reg)
  124. {
  125. /*
  126. * We don't need a lock or delay here since the raster register
  127. * block will remain unlocked until the next access.
  128. */
  129. ep93xxfb_writel(fbi, 0xaa, EP93XXFB_SWLOCK);
  130. ep93xxfb_writel(fbi, val, reg);
  131. }
  132. static void ep93xxfb_set_video_attribs(struct fb_info *info)
  133. {
  134. struct ep93xx_fbi *fbi = info->par;
  135. unsigned int attribs;
  136. attribs = EP93XXFB_ENABLE;
  137. attribs |= fbi->mach_info->flags;
  138. ep93xxfb_out_locked(fbi, attribs, EP93XXFB_ATTRIBS);
  139. }
  140. static int ep93xxfb_set_pixelmode(struct fb_info *info)
  141. {
  142. struct ep93xx_fbi *fbi = info->par;
  143. unsigned int val;
  144. info->var.transp.offset = 0;
  145. info->var.transp.length = 0;
  146. switch (info->var.bits_per_pixel) {
  147. case 8:
  148. val = EP93XXFB_PIXELMODE_8BPP | EP93XXFB_PIXELMODE_COLOR_LUT |
  149. EP93XXFB_PIXELMODE_SHIFT_1P_18B;
  150. info->var.red.offset = 0;
  151. info->var.red.length = 8;
  152. info->var.green.offset = 0;
  153. info->var.green.length = 8;
  154. info->var.blue.offset = 0;
  155. info->var.blue.length = 8;
  156. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  157. break;
  158. case 16:
  159. val = EP93XXFB_PIXELMODE_16BPP | EP93XXFB_PIXELMODE_COLOR_555 |
  160. EP93XXFB_PIXELMODE_SHIFT_1P_18B;
  161. info->var.red.offset = 11;
  162. info->var.red.length = 5;
  163. info->var.green.offset = 5;
  164. info->var.green.length = 6;
  165. info->var.blue.offset = 0;
  166. info->var.blue.length = 5;
  167. info->fix.visual = FB_VISUAL_TRUECOLOR;
  168. break;
  169. case 24:
  170. val = EP93XXFB_PIXELMODE_24BPP | EP93XXFB_PIXELMODE_COLOR_888 |
  171. EP93XXFB_PIXELMODE_SHIFT_1P_24B;
  172. info->var.red.offset = 16;
  173. info->var.red.length = 8;
  174. info->var.green.offset = 8;
  175. info->var.green.length = 8;
  176. info->var.blue.offset = 0;
  177. info->var.blue.length = 8;
  178. info->fix.visual = FB_VISUAL_TRUECOLOR;
  179. break;
  180. case 32:
  181. val = EP93XXFB_PIXELMODE_32BPP | EP93XXFB_PIXELMODE_COLOR_888 |
  182. EP93XXFB_PIXELMODE_SHIFT_1P_24B;
  183. info->var.red.offset = 16;
  184. info->var.red.length = 8;
  185. info->var.green.offset = 8;
  186. info->var.green.length = 8;
  187. info->var.blue.offset = 0;
  188. info->var.blue.length = 8;
  189. info->fix.visual = FB_VISUAL_TRUECOLOR;
  190. break;
  191. default:
  192. return -EINVAL;
  193. }
  194. ep93xxfb_writel(fbi, val, EP93XXFB_PIXELMODE);
  195. return 0;
  196. }
  197. static void ep93xxfb_set_timing(struct fb_info *info)
  198. {
  199. struct ep93xx_fbi *fbi = info->par;
  200. unsigned int vlines_total, hclks_total, start, stop;
  201. vlines_total = info->var.yres + info->var.upper_margin +
  202. info->var.lower_margin + info->var.vsync_len - 1;
  203. hclks_total = info->var.xres + info->var.left_margin +
  204. info->var.right_margin + info->var.hsync_len - 1;
  205. ep93xxfb_out_locked(fbi, vlines_total, EP93XXFB_VLINES_TOTAL);
  206. ep93xxfb_out_locked(fbi, hclks_total, EP93XXFB_HCLKS_TOTAL);
  207. start = vlines_total;
  208. stop = vlines_total - info->var.vsync_len;
  209. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VSYNC);
  210. start = vlines_total - info->var.vsync_len - info->var.upper_margin;
  211. stop = info->var.lower_margin - 1;
  212. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VBLANK);
  213. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VACTIVE);
  214. start = vlines_total;
  215. stop = vlines_total + 1;
  216. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VCLK);
  217. start = hclks_total;
  218. stop = hclks_total - info->var.hsync_len;
  219. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HSYNC);
  220. start = hclks_total - info->var.hsync_len - info->var.left_margin;
  221. stop = info->var.right_margin - 1;
  222. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HBLANK);
  223. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HACTIVE);
  224. start = hclks_total;
  225. stop = hclks_total;
  226. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HCLK);
  227. ep93xxfb_out_locked(fbi, 0x0, EP93XXFB_LINE_CARRY);
  228. }
  229. static int ep93xxfb_set_par(struct fb_info *info)
  230. {
  231. struct ep93xx_fbi *fbi = info->par;
  232. clk_set_rate(fbi->clk, 1000 * PICOS2KHZ(info->var.pixclock));
  233. ep93xxfb_set_timing(info);
  234. info->fix.line_length = info->var.xres_virtual *
  235. info->var.bits_per_pixel / 8;
  236. ep93xxfb_writel(fbi, info->fix.smem_start, EP93XXFB_SCREEN_PAGE);
  237. ep93xxfb_writel(fbi, info->var.yres - 1, EP93XXFB_SCREEN_LINES);
  238. ep93xxfb_writel(fbi, ((info->var.xres * info->var.bits_per_pixel)
  239. / 32) - 1, EP93XXFB_LINE_LENGTH);
  240. ep93xxfb_writel(fbi, info->fix.line_length / 4, EP93XXFB_VLINE_STEP);
  241. ep93xxfb_set_video_attribs(info);
  242. return 0;
  243. }
  244. static int ep93xxfb_check_var(struct fb_var_screeninfo *var,
  245. struct fb_info *info)
  246. {
  247. int err;
  248. err = ep93xxfb_set_pixelmode(info);
  249. if (err)
  250. return err;
  251. var->xres = max_t(unsigned int, var->xres, EP93XXFB_MIN_XRES);
  252. var->xres = min_t(unsigned int, var->xres, EP93XXFB_MAX_XRES);
  253. var->xres_virtual = max(var->xres_virtual, var->xres);
  254. var->yres = max_t(unsigned int, var->yres, EP93XXFB_MIN_YRES);
  255. var->yres = min_t(unsigned int, var->yres, EP93XXFB_MAX_YRES);
  256. var->yres_virtual = max(var->yres_virtual, var->yres);
  257. return 0;
  258. }
  259. static int ep93xxfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
  260. {
  261. unsigned int offset = vma->vm_pgoff << PAGE_SHIFT;
  262. if (offset < info->fix.smem_len) {
  263. return dma_mmap_writecombine(info->dev, vma, info->screen_base,
  264. info->fix.smem_start,
  265. info->fix.smem_len);
  266. }
  267. return -EINVAL;
  268. }
  269. static int ep93xxfb_blank(int blank_mode, struct fb_info *info)
  270. {
  271. struct ep93xx_fbi *fbi = info->par;
  272. unsigned int attribs = ep93xxfb_readl(fbi, EP93XXFB_ATTRIBS);
  273. if (blank_mode) {
  274. if (fbi->mach_info->blank)
  275. fbi->mach_info->blank(blank_mode, info);
  276. ep93xxfb_out_locked(fbi, attribs & ~EP93XXFB_ENABLE,
  277. EP93XXFB_ATTRIBS);
  278. clk_disable(fbi->clk);
  279. } else {
  280. clk_enable(fbi->clk);
  281. ep93xxfb_out_locked(fbi, attribs | EP93XXFB_ENABLE,
  282. EP93XXFB_ATTRIBS);
  283. if (fbi->mach_info->blank)
  284. fbi->mach_info->blank(blank_mode, info);
  285. }
  286. return 0;
  287. }
  288. static inline int ep93xxfb_convert_color(int val, int width)
  289. {
  290. return ((val << width) + 0x7fff - val) >> 16;
  291. }
  292. static int ep93xxfb_setcolreg(unsigned int regno, unsigned int red,
  293. unsigned int green, unsigned int blue,
  294. unsigned int transp, struct fb_info *info)
  295. {
  296. struct ep93xx_fbi *fbi = info->par;
  297. unsigned int *pal = info->pseudo_palette;
  298. unsigned int ctrl, i, rgb, lut_current, lut_stat;
  299. switch (info->fix.visual) {
  300. case FB_VISUAL_PSEUDOCOLOR:
  301. if (regno > 255)
  302. return 1;
  303. rgb = ((red & 0xff00) << 8) | (green & 0xff00) |
  304. ((blue & 0xff00) >> 8);
  305. pal[regno] = rgb;
  306. ep93xxfb_writel(fbi, rgb, (EP93XXFB_COLOR_LUT + (regno << 2)));
  307. ctrl = ep93xxfb_readl(fbi, EP93XXFB_LUT_SW_CONTROL);
  308. lut_stat = !!(ctrl & EP93XXFB_LUT_SW_CONTROL_SSTAT);
  309. lut_current = !!(ctrl & EP93XXFB_LUT_SW_CONTROL_SWTCH);
  310. if (lut_stat == lut_current) {
  311. for (i = 0; i < 256; i++) {
  312. ep93xxfb_writel(fbi, pal[i],
  313. EP93XXFB_COLOR_LUT + (i << 2));
  314. }
  315. ep93xxfb_writel(fbi,
  316. ctrl ^ EP93XXFB_LUT_SW_CONTROL_SWTCH,
  317. EP93XXFB_LUT_SW_CONTROL);
  318. }
  319. break;
  320. case FB_VISUAL_TRUECOLOR:
  321. if (regno > 16)
  322. return 1;
  323. red = ep93xxfb_convert_color(red, info->var.red.length);
  324. green = ep93xxfb_convert_color(green, info->var.green.length);
  325. blue = ep93xxfb_convert_color(blue, info->var.blue.length);
  326. transp = ep93xxfb_convert_color(transp,
  327. info->var.transp.length);
  328. pal[regno] = (red << info->var.red.offset) |
  329. (green << info->var.green.offset) |
  330. (blue << info->var.blue.offset) |
  331. (transp << info->var.transp.offset);
  332. break;
  333. default:
  334. return 1;
  335. }
  336. return 0;
  337. }
  338. static struct fb_ops ep93xxfb_ops = {
  339. .owner = THIS_MODULE,
  340. .fb_check_var = ep93xxfb_check_var,
  341. .fb_set_par = ep93xxfb_set_par,
  342. .fb_blank = ep93xxfb_blank,
  343. .fb_fillrect = cfb_fillrect,
  344. .fb_copyarea = cfb_copyarea,
  345. .fb_imageblit = cfb_imageblit,
  346. .fb_setcolreg = ep93xxfb_setcolreg,
  347. .fb_mmap = ep93xxfb_mmap,
  348. };
  349. static int __init ep93xxfb_calc_fbsize(struct ep93xxfb_mach_info *mach_info)
  350. {
  351. int i, fb_size = 0;
  352. if (mach_info->num_modes == EP93XXFB_USE_MODEDB) {
  353. fb_size = EP93XXFB_MAX_XRES * EP93XXFB_MAX_YRES *
  354. mach_info->bpp / 8;
  355. } else {
  356. for (i = 0; i < mach_info->num_modes; i++) {
  357. const struct fb_videomode *mode;
  358. int size;
  359. mode = &mach_info->modes[i];
  360. size = mode->xres * mode->yres * mach_info->bpp / 8;
  361. if (size > fb_size)
  362. fb_size = size;
  363. }
  364. }
  365. return fb_size;
  366. }
  367. static int __init ep93xxfb_alloc_videomem(struct fb_info *info)
  368. {
  369. struct ep93xx_fbi *fbi = info->par;
  370. char __iomem *virt_addr;
  371. dma_addr_t phys_addr;
  372. unsigned int fb_size;
  373. fb_size = ep93xxfb_calc_fbsize(fbi->mach_info);
  374. virt_addr = dma_alloc_writecombine(info->dev, fb_size,
  375. &phys_addr, GFP_KERNEL);
  376. if (!virt_addr)
  377. return -ENOMEM;
  378. /*
  379. * There is a bug in the ep93xx framebuffer which causes problems
  380. * if bit 27 of the physical address is set.
  381. * See: http://marc.info/?l=linux-arm-kernel&m=110061245502000&w=2
  382. * There does not seem to be any offical errata for this, but I
  383. * have confirmed the problem exists on my hardware (ep9315) at
  384. * least.
  385. */
  386. if (check_screenpage_bug && phys_addr & (1 << 27)) {
  387. dev_err(info->dev, "ep93xx framebuffer bug. phys addr (0x%x) "
  388. "has bit 27 set: cannot init framebuffer\n",
  389. phys_addr);
  390. dma_free_coherent(info->dev, fb_size, virt_addr, phys_addr);
  391. return -ENOMEM;
  392. }
  393. info->fix.smem_start = phys_addr;
  394. info->fix.smem_len = fb_size;
  395. info->screen_base = virt_addr;
  396. return 0;
  397. }
  398. static void ep93xxfb_dealloc_videomem(struct fb_info *info)
  399. {
  400. if (info->screen_base)
  401. dma_free_coherent(info->dev, info->fix.smem_len,
  402. info->screen_base, info->fix.smem_start);
  403. }
  404. static int __init ep93xxfb_probe(struct platform_device *pdev)
  405. {
  406. struct ep93xxfb_mach_info *mach_info = pdev->dev.platform_data;
  407. struct fb_info *info;
  408. struct ep93xx_fbi *fbi;
  409. struct resource *res;
  410. char *video_mode;
  411. int err;
  412. if (!mach_info)
  413. return -EINVAL;
  414. info = framebuffer_alloc(sizeof(struct ep93xx_fbi), &pdev->dev);
  415. if (!info)
  416. return -ENOMEM;
  417. info->dev = &pdev->dev;
  418. platform_set_drvdata(pdev, info);
  419. fbi = info->par;
  420. fbi->mach_info = mach_info;
  421. err = fb_alloc_cmap(&info->cmap, 256, 0);
  422. if (err)
  423. goto failed;
  424. err = ep93xxfb_alloc_videomem(info);
  425. if (err)
  426. goto failed;
  427. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  428. if (!res) {
  429. err = -ENXIO;
  430. goto failed;
  431. }
  432. res = request_mem_region(res->start, resource_size(res), pdev->name);
  433. if (!res) {
  434. err = -EBUSY;
  435. goto failed;
  436. }
  437. fbi->res = res;
  438. fbi->mmio_base = ioremap(res->start, resource_size(res));
  439. if (!fbi->mmio_base) {
  440. err = -ENXIO;
  441. goto failed;
  442. }
  443. strcpy(info->fix.id, pdev->name);
  444. info->fbops = &ep93xxfb_ops;
  445. info->fix.type = FB_TYPE_PACKED_PIXELS;
  446. info->fix.accel = FB_ACCEL_NONE;
  447. info->var.activate = FB_ACTIVATE_NOW;
  448. info->var.vmode = FB_VMODE_NONINTERLACED;
  449. info->flags = FBINFO_DEFAULT;
  450. info->node = -1;
  451. info->state = FBINFO_STATE_RUNNING;
  452. info->pseudo_palette = &fbi->pseudo_palette;
  453. fb_get_options("ep93xx-fb", &video_mode);
  454. err = fb_find_mode(&info->var, info, video_mode,
  455. fbi->mach_info->modes, fbi->mach_info->num_modes,
  456. fbi->mach_info->default_mode, fbi->mach_info->bpp);
  457. if (err == 0) {
  458. dev_err(info->dev, "No suitable video mode found\n");
  459. err = -EINVAL;
  460. goto failed;
  461. }
  462. if (mach_info->setup) {
  463. err = mach_info->setup(pdev);
  464. if (err)
  465. return err;
  466. }
  467. err = ep93xxfb_check_var(&info->var, info);
  468. if (err)
  469. goto failed;
  470. fbi->clk = clk_get(info->dev, NULL);
  471. if (IS_ERR(fbi->clk)) {
  472. err = PTR_ERR(fbi->clk);
  473. fbi->clk = NULL;
  474. goto failed;
  475. }
  476. ep93xxfb_set_par(info);
  477. clk_enable(fbi->clk);
  478. err = register_framebuffer(info);
  479. if (err)
  480. goto failed;
  481. dev_info(info->dev, "registered. Mode = %dx%d-%d\n",
  482. info->var.xres, info->var.yres, info->var.bits_per_pixel);
  483. return 0;
  484. failed:
  485. if (fbi->clk)
  486. clk_put(fbi->clk);
  487. if (fbi->mmio_base)
  488. iounmap(fbi->mmio_base);
  489. if (fbi->res)
  490. release_mem_region(fbi->res->start, resource_size(fbi->res));
  491. ep93xxfb_dealloc_videomem(info);
  492. if (&info->cmap)
  493. fb_dealloc_cmap(&info->cmap);
  494. if (fbi->mach_info->teardown)
  495. fbi->mach_info->teardown(pdev);
  496. kfree(info);
  497. platform_set_drvdata(pdev, NULL);
  498. return err;
  499. }
  500. static int ep93xxfb_remove(struct platform_device *pdev)
  501. {
  502. struct fb_info *info = platform_get_drvdata(pdev);
  503. struct ep93xx_fbi *fbi = info->par;
  504. unregister_framebuffer(info);
  505. clk_disable(fbi->clk);
  506. clk_put(fbi->clk);
  507. iounmap(fbi->mmio_base);
  508. release_mem_region(fbi->res->start, resource_size(fbi->res));
  509. ep93xxfb_dealloc_videomem(info);
  510. fb_dealloc_cmap(&info->cmap);
  511. if (fbi->mach_info->teardown)
  512. fbi->mach_info->teardown(pdev);
  513. kfree(info);
  514. platform_set_drvdata(pdev, NULL);
  515. return 0;
  516. }
  517. static struct platform_driver ep93xxfb_driver = {
  518. .probe = ep93xxfb_probe,
  519. .remove = ep93xxfb_remove,
  520. .driver = {
  521. .name = "ep93xx-fb",
  522. .owner = THIS_MODULE,
  523. },
  524. };
  525. static int __devinit ep93xxfb_init(void)
  526. {
  527. return platform_driver_register(&ep93xxfb_driver);
  528. }
  529. static void __exit ep93xxfb_exit(void)
  530. {
  531. platform_driver_unregister(&ep93xxfb_driver);
  532. }
  533. module_init(ep93xxfb_init);
  534. module_exit(ep93xxfb_exit);
  535. MODULE_DESCRIPTION("EP93XX Framebuffer Driver");
  536. MODULE_ALIAS("platform:ep93xx-fb");
  537. MODULE_AUTHOR("Ryan Mallon <ryan&bluewatersys.com>, "
  538. "H Hartley Sweeten <hsweeten@visionengravers.com");
  539. MODULE_LICENSE("GPL");