xhci-hcd.c 56 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/irq.h>
  23. #include <linux/module.h>
  24. #include <linux/moduleparam.h>
  25. #include "xhci.h"
  26. #define DRIVER_AUTHOR "Sarah Sharp"
  27. #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
  28. /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
  29. static int link_quirk;
  30. module_param(link_quirk, int, S_IRUGO | S_IWUSR);
  31. MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
  32. /* TODO: copied from ehci-hcd.c - can this be refactored? */
  33. /*
  34. * handshake - spin reading hc until handshake completes or fails
  35. * @ptr: address of hc register to be read
  36. * @mask: bits to look at in result of read
  37. * @done: value of those bits when handshake succeeds
  38. * @usec: timeout in microseconds
  39. *
  40. * Returns negative errno, or zero on success
  41. *
  42. * Success happens when the "mask" bits have the specified value (hardware
  43. * handshake done). There are two failure modes: "usec" have passed (major
  44. * hardware flakeout), or the register reads as all-ones (hardware removed).
  45. */
  46. static int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
  47. u32 mask, u32 done, int usec)
  48. {
  49. u32 result;
  50. do {
  51. result = xhci_readl(xhci, ptr);
  52. if (result == ~(u32)0) /* card removed */
  53. return -ENODEV;
  54. result &= mask;
  55. if (result == done)
  56. return 0;
  57. udelay(1);
  58. usec--;
  59. } while (usec > 0);
  60. return -ETIMEDOUT;
  61. }
  62. /*
  63. * Disable interrupts and begin the xHCI halting process.
  64. */
  65. void xhci_quiesce(struct xhci_hcd *xhci)
  66. {
  67. u32 halted;
  68. u32 cmd;
  69. u32 mask;
  70. mask = ~(XHCI_IRQS);
  71. halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
  72. if (!halted)
  73. mask &= ~CMD_RUN;
  74. cmd = xhci_readl(xhci, &xhci->op_regs->command);
  75. cmd &= mask;
  76. xhci_writel(xhci, cmd, &xhci->op_regs->command);
  77. }
  78. /*
  79. * Force HC into halt state.
  80. *
  81. * Disable any IRQs and clear the run/stop bit.
  82. * HC will complete any current and actively pipelined transactions, and
  83. * should halt within 16 microframes of the run/stop bit being cleared.
  84. * Read HC Halted bit in the status register to see when the HC is finished.
  85. * XXX: shouldn't we set HC_STATE_HALT here somewhere?
  86. */
  87. int xhci_halt(struct xhci_hcd *xhci)
  88. {
  89. xhci_dbg(xhci, "// Halt the HC\n");
  90. xhci_quiesce(xhci);
  91. return handshake(xhci, &xhci->op_regs->status,
  92. STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
  93. }
  94. /*
  95. * Reset a halted HC, and set the internal HC state to HC_STATE_HALT.
  96. *
  97. * This resets pipelines, timers, counters, state machines, etc.
  98. * Transactions will be terminated immediately, and operational registers
  99. * will be set to their defaults.
  100. */
  101. int xhci_reset(struct xhci_hcd *xhci)
  102. {
  103. u32 command;
  104. u32 state;
  105. state = xhci_readl(xhci, &xhci->op_regs->status);
  106. if ((state & STS_HALT) == 0) {
  107. xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
  108. return 0;
  109. }
  110. xhci_dbg(xhci, "// Reset the HC\n");
  111. command = xhci_readl(xhci, &xhci->op_regs->command);
  112. command |= CMD_RESET;
  113. xhci_writel(xhci, command, &xhci->op_regs->command);
  114. /* XXX: Why does EHCI set this here? Shouldn't other code do this? */
  115. xhci_to_hcd(xhci)->state = HC_STATE_HALT;
  116. return handshake(xhci, &xhci->op_regs->command, CMD_RESET, 0, 250 * 1000);
  117. }
  118. #if 0
  119. /* Set up MSI-X table for entry 0 (may claim other entries later) */
  120. static int xhci_setup_msix(struct xhci_hcd *xhci)
  121. {
  122. int ret;
  123. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  124. xhci->msix_count = 0;
  125. /* XXX: did I do this right? ixgbe does kcalloc for more than one */
  126. xhci->msix_entries = kmalloc(sizeof(struct msix_entry), GFP_KERNEL);
  127. if (!xhci->msix_entries) {
  128. xhci_err(xhci, "Failed to allocate MSI-X entries\n");
  129. return -ENOMEM;
  130. }
  131. xhci->msix_entries[0].entry = 0;
  132. ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
  133. if (ret) {
  134. xhci_err(xhci, "Failed to enable MSI-X\n");
  135. goto free_entries;
  136. }
  137. /*
  138. * Pass the xhci pointer value as the request_irq "cookie".
  139. * If more irqs are added, this will need to be unique for each one.
  140. */
  141. ret = request_irq(xhci->msix_entries[0].vector, &xhci_irq, 0,
  142. "xHCI", xhci_to_hcd(xhci));
  143. if (ret) {
  144. xhci_err(xhci, "Failed to allocate MSI-X interrupt\n");
  145. goto disable_msix;
  146. }
  147. xhci_dbg(xhci, "Finished setting up MSI-X\n");
  148. return 0;
  149. disable_msix:
  150. pci_disable_msix(pdev);
  151. free_entries:
  152. kfree(xhci->msix_entries);
  153. xhci->msix_entries = NULL;
  154. return ret;
  155. }
  156. /* XXX: code duplication; can xhci_setup_msix call this? */
  157. /* Free any IRQs and disable MSI-X */
  158. static void xhci_cleanup_msix(struct xhci_hcd *xhci)
  159. {
  160. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  161. if (!xhci->msix_entries)
  162. return;
  163. free_irq(xhci->msix_entries[0].vector, xhci);
  164. pci_disable_msix(pdev);
  165. kfree(xhci->msix_entries);
  166. xhci->msix_entries = NULL;
  167. xhci_dbg(xhci, "Finished cleaning up MSI-X\n");
  168. }
  169. #endif
  170. /*
  171. * Initialize memory for HCD and xHC (one-time init).
  172. *
  173. * Program the PAGESIZE register, initialize the device context array, create
  174. * device contexts (?), set up a command ring segment (or two?), create event
  175. * ring (one for now).
  176. */
  177. int xhci_init(struct usb_hcd *hcd)
  178. {
  179. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  180. int retval = 0;
  181. xhci_dbg(xhci, "xhci_init\n");
  182. spin_lock_init(&xhci->lock);
  183. if (link_quirk) {
  184. xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
  185. xhci->quirks |= XHCI_LINK_TRB_QUIRK;
  186. } else {
  187. xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
  188. }
  189. retval = xhci_mem_init(xhci, GFP_KERNEL);
  190. xhci_dbg(xhci, "Finished xhci_init\n");
  191. return retval;
  192. }
  193. /*
  194. * Called in interrupt context when there might be work
  195. * queued on the event ring
  196. *
  197. * xhci->lock must be held by caller.
  198. */
  199. static void xhci_work(struct xhci_hcd *xhci)
  200. {
  201. u32 temp;
  202. u64 temp_64;
  203. /*
  204. * Clear the op reg interrupt status first,
  205. * so we can receive interrupts from other MSI-X interrupters.
  206. * Write 1 to clear the interrupt status.
  207. */
  208. temp = xhci_readl(xhci, &xhci->op_regs->status);
  209. temp |= STS_EINT;
  210. xhci_writel(xhci, temp, &xhci->op_regs->status);
  211. /* FIXME when MSI-X is supported and there are multiple vectors */
  212. /* Clear the MSI-X event interrupt status */
  213. /* Acknowledge the interrupt */
  214. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  215. temp |= 0x3;
  216. xhci_writel(xhci, temp, &xhci->ir_set->irq_pending);
  217. /* Flush posted writes */
  218. xhci_readl(xhci, &xhci->ir_set->irq_pending);
  219. if (xhci->xhc_state & XHCI_STATE_DYING)
  220. xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
  221. "Shouldn't IRQs be disabled?\n");
  222. else
  223. /* FIXME this should be a delayed service routine
  224. * that clears the EHB.
  225. */
  226. xhci_handle_event(xhci);
  227. /* Clear the event handler busy flag (RW1C); the event ring should be empty. */
  228. temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  229. xhci_write_64(xhci, temp_64 | ERST_EHB, &xhci->ir_set->erst_dequeue);
  230. /* Flush posted writes -- FIXME is this necessary? */
  231. xhci_readl(xhci, &xhci->ir_set->irq_pending);
  232. }
  233. /*-------------------------------------------------------------------------*/
  234. /*
  235. * xHCI spec says we can get an interrupt, and if the HC has an error condition,
  236. * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
  237. * indicators of an event TRB error, but we check the status *first* to be safe.
  238. */
  239. irqreturn_t xhci_irq(struct usb_hcd *hcd)
  240. {
  241. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  242. u32 temp, temp2;
  243. union xhci_trb *trb;
  244. spin_lock(&xhci->lock);
  245. trb = xhci->event_ring->dequeue;
  246. /* Check if the xHC generated the interrupt, or the irq is shared */
  247. temp = xhci_readl(xhci, &xhci->op_regs->status);
  248. temp2 = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  249. if (temp == 0xffffffff && temp2 == 0xffffffff)
  250. goto hw_died;
  251. if (!(temp & STS_EINT) && !ER_IRQ_PENDING(temp2)) {
  252. spin_unlock(&xhci->lock);
  253. return IRQ_NONE;
  254. }
  255. xhci_dbg(xhci, "op reg status = %08x\n", temp);
  256. xhci_dbg(xhci, "ir set irq_pending = %08x\n", temp2);
  257. xhci_dbg(xhci, "Event ring dequeue ptr:\n");
  258. xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n",
  259. (unsigned long long)xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb),
  260. lower_32_bits(trb->link.segment_ptr),
  261. upper_32_bits(trb->link.segment_ptr),
  262. (unsigned int) trb->link.intr_target,
  263. (unsigned int) trb->link.control);
  264. if (temp & STS_FATAL) {
  265. xhci_warn(xhci, "WARNING: Host System Error\n");
  266. xhci_halt(xhci);
  267. hw_died:
  268. xhci_to_hcd(xhci)->state = HC_STATE_HALT;
  269. spin_unlock(&xhci->lock);
  270. return -ESHUTDOWN;
  271. }
  272. xhci_work(xhci);
  273. spin_unlock(&xhci->lock);
  274. return IRQ_HANDLED;
  275. }
  276. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  277. void xhci_event_ring_work(unsigned long arg)
  278. {
  279. unsigned long flags;
  280. int temp;
  281. u64 temp_64;
  282. struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
  283. int i, j;
  284. xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
  285. spin_lock_irqsave(&xhci->lock, flags);
  286. temp = xhci_readl(xhci, &xhci->op_regs->status);
  287. xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
  288. if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING)) {
  289. xhci_dbg(xhci, "HW died, polling stopped.\n");
  290. spin_unlock_irqrestore(&xhci->lock, flags);
  291. return;
  292. }
  293. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  294. xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
  295. xhci_dbg(xhci, "No-op commands handled = %d\n", xhci->noops_handled);
  296. xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
  297. xhci->error_bitmask = 0;
  298. xhci_dbg(xhci, "Event ring:\n");
  299. xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
  300. xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
  301. temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  302. temp_64 &= ~ERST_PTR_MASK;
  303. xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
  304. xhci_dbg(xhci, "Command ring:\n");
  305. xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
  306. xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
  307. xhci_dbg_cmd_ptrs(xhci);
  308. for (i = 0; i < MAX_HC_SLOTS; ++i) {
  309. if (!xhci->devs[i])
  310. continue;
  311. for (j = 0; j < 31; ++j) {
  312. struct xhci_ring *ring = xhci->devs[i]->eps[j].ring;
  313. if (!ring)
  314. continue;
  315. xhci_dbg(xhci, "Dev %d endpoint ring %d:\n", i, j);
  316. xhci_debug_segment(xhci, ring->deq_seg);
  317. }
  318. }
  319. if (xhci->noops_submitted != NUM_TEST_NOOPS)
  320. if (xhci_setup_one_noop(xhci))
  321. xhci_ring_cmd_db(xhci);
  322. spin_unlock_irqrestore(&xhci->lock, flags);
  323. if (!xhci->zombie)
  324. mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
  325. else
  326. xhci_dbg(xhci, "Quit polling the event ring.\n");
  327. }
  328. #endif
  329. /*
  330. * Start the HC after it was halted.
  331. *
  332. * This function is called by the USB core when the HC driver is added.
  333. * Its opposite is xhci_stop().
  334. *
  335. * xhci_init() must be called once before this function can be called.
  336. * Reset the HC, enable device slot contexts, program DCBAAP, and
  337. * set command ring pointer and event ring pointer.
  338. *
  339. * Setup MSI-X vectors and enable interrupts.
  340. */
  341. int xhci_run(struct usb_hcd *hcd)
  342. {
  343. u32 temp;
  344. u64 temp_64;
  345. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  346. void (*doorbell)(struct xhci_hcd *) = NULL;
  347. hcd->uses_new_polling = 1;
  348. hcd->poll_rh = 0;
  349. xhci_dbg(xhci, "xhci_run\n");
  350. #if 0 /* FIXME: MSI not setup yet */
  351. /* Do this at the very last minute */
  352. ret = xhci_setup_msix(xhci);
  353. if (!ret)
  354. return ret;
  355. return -ENOSYS;
  356. #endif
  357. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  358. init_timer(&xhci->event_ring_timer);
  359. xhci->event_ring_timer.data = (unsigned long) xhci;
  360. xhci->event_ring_timer.function = xhci_event_ring_work;
  361. /* Poll the event ring */
  362. xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
  363. xhci->zombie = 0;
  364. xhci_dbg(xhci, "Setting event ring polling timer\n");
  365. add_timer(&xhci->event_ring_timer);
  366. #endif
  367. xhci_dbg(xhci, "Command ring memory map follows:\n");
  368. xhci_debug_ring(xhci, xhci->cmd_ring);
  369. xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
  370. xhci_dbg_cmd_ptrs(xhci);
  371. xhci_dbg(xhci, "ERST memory map follows:\n");
  372. xhci_dbg_erst(xhci, &xhci->erst);
  373. xhci_dbg(xhci, "Event ring:\n");
  374. xhci_debug_ring(xhci, xhci->event_ring);
  375. xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
  376. temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  377. temp_64 &= ~ERST_PTR_MASK;
  378. xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
  379. xhci_dbg(xhci, "// Set the interrupt modulation register\n");
  380. temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
  381. temp &= ~ER_IRQ_INTERVAL_MASK;
  382. temp |= (u32) 160;
  383. xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
  384. /* Set the HCD state before we enable the irqs */
  385. hcd->state = HC_STATE_RUNNING;
  386. temp = xhci_readl(xhci, &xhci->op_regs->command);
  387. temp |= (CMD_EIE);
  388. xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
  389. temp);
  390. xhci_writel(xhci, temp, &xhci->op_regs->command);
  391. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  392. xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
  393. xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
  394. xhci_writel(xhci, ER_IRQ_ENABLE(temp),
  395. &xhci->ir_set->irq_pending);
  396. xhci_print_ir_set(xhci, xhci->ir_set, 0);
  397. if (NUM_TEST_NOOPS > 0)
  398. doorbell = xhci_setup_one_noop(xhci);
  399. temp = xhci_readl(xhci, &xhci->op_regs->command);
  400. temp |= (CMD_RUN);
  401. xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
  402. temp);
  403. xhci_writel(xhci, temp, &xhci->op_regs->command);
  404. /* Flush PCI posted writes */
  405. temp = xhci_readl(xhci, &xhci->op_regs->command);
  406. xhci_dbg(xhci, "// @%p = 0x%x\n", &xhci->op_regs->command, temp);
  407. if (doorbell)
  408. (*doorbell)(xhci);
  409. xhci_dbg(xhci, "Finished xhci_run\n");
  410. return 0;
  411. }
  412. /*
  413. * Stop xHCI driver.
  414. *
  415. * This function is called by the USB core when the HC driver is removed.
  416. * Its opposite is xhci_run().
  417. *
  418. * Disable device contexts, disable IRQs, and quiesce the HC.
  419. * Reset the HC, finish any completed transactions, and cleanup memory.
  420. */
  421. void xhci_stop(struct usb_hcd *hcd)
  422. {
  423. u32 temp;
  424. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  425. spin_lock_irq(&xhci->lock);
  426. xhci_halt(xhci);
  427. xhci_reset(xhci);
  428. spin_unlock_irq(&xhci->lock);
  429. #if 0 /* No MSI yet */
  430. xhci_cleanup_msix(xhci);
  431. #endif
  432. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  433. /* Tell the event ring poll function not to reschedule */
  434. xhci->zombie = 1;
  435. del_timer_sync(&xhci->event_ring_timer);
  436. #endif
  437. xhci_dbg(xhci, "// Disabling event ring interrupts\n");
  438. temp = xhci_readl(xhci, &xhci->op_regs->status);
  439. xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
  440. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  441. xhci_writel(xhci, ER_IRQ_DISABLE(temp),
  442. &xhci->ir_set->irq_pending);
  443. xhci_print_ir_set(xhci, xhci->ir_set, 0);
  444. xhci_dbg(xhci, "cleaning up memory\n");
  445. xhci_mem_cleanup(xhci);
  446. xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
  447. xhci_readl(xhci, &xhci->op_regs->status));
  448. }
  449. /*
  450. * Shutdown HC (not bus-specific)
  451. *
  452. * This is called when the machine is rebooting or halting. We assume that the
  453. * machine will be powered off, and the HC's internal state will be reset.
  454. * Don't bother to free memory.
  455. */
  456. void xhci_shutdown(struct usb_hcd *hcd)
  457. {
  458. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  459. spin_lock_irq(&xhci->lock);
  460. xhci_halt(xhci);
  461. spin_unlock_irq(&xhci->lock);
  462. #if 0
  463. xhci_cleanup_msix(xhci);
  464. #endif
  465. xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
  466. xhci_readl(xhci, &xhci->op_regs->status));
  467. }
  468. /*-------------------------------------------------------------------------*/
  469. /**
  470. * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
  471. * HCDs. Find the index for an endpoint given its descriptor. Use the return
  472. * value to right shift 1 for the bitmask.
  473. *
  474. * Index = (epnum * 2) + direction - 1,
  475. * where direction = 0 for OUT, 1 for IN.
  476. * For control endpoints, the IN index is used (OUT index is unused), so
  477. * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
  478. */
  479. unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
  480. {
  481. unsigned int index;
  482. if (usb_endpoint_xfer_control(desc))
  483. index = (unsigned int) (usb_endpoint_num(desc)*2);
  484. else
  485. index = (unsigned int) (usb_endpoint_num(desc)*2) +
  486. (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
  487. return index;
  488. }
  489. /* Find the flag for this endpoint (for use in the control context). Use the
  490. * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
  491. * bit 1, etc.
  492. */
  493. unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
  494. {
  495. return 1 << (xhci_get_endpoint_index(desc) + 1);
  496. }
  497. /* Find the flag for this endpoint (for use in the control context). Use the
  498. * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
  499. * bit 1, etc.
  500. */
  501. unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
  502. {
  503. return 1 << (ep_index + 1);
  504. }
  505. /* Compute the last valid endpoint context index. Basically, this is the
  506. * endpoint index plus one. For slot contexts with more than valid endpoint,
  507. * we find the most significant bit set in the added contexts flags.
  508. * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
  509. * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
  510. */
  511. unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
  512. {
  513. return fls(added_ctxs) - 1;
  514. }
  515. /* Returns 1 if the arguments are OK;
  516. * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
  517. */
  518. int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
  519. struct usb_host_endpoint *ep, int check_ep, const char *func) {
  520. if (!hcd || (check_ep && !ep) || !udev) {
  521. printk(KERN_DEBUG "xHCI %s called with invalid args\n",
  522. func);
  523. return -EINVAL;
  524. }
  525. if (!udev->parent) {
  526. printk(KERN_DEBUG "xHCI %s called for root hub\n",
  527. func);
  528. return 0;
  529. }
  530. if (!udev->slot_id) {
  531. printk(KERN_DEBUG "xHCI %s called with unaddressed device\n",
  532. func);
  533. return -EINVAL;
  534. }
  535. return 1;
  536. }
  537. static int xhci_configure_endpoint(struct xhci_hcd *xhci,
  538. struct usb_device *udev, struct xhci_command *command,
  539. bool ctx_change, bool must_succeed);
  540. /*
  541. * Full speed devices may have a max packet size greater than 8 bytes, but the
  542. * USB core doesn't know that until it reads the first 8 bytes of the
  543. * descriptor. If the usb_device's max packet size changes after that point,
  544. * we need to issue an evaluate context command and wait on it.
  545. */
  546. static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
  547. unsigned int ep_index, struct urb *urb)
  548. {
  549. struct xhci_container_ctx *in_ctx;
  550. struct xhci_container_ctx *out_ctx;
  551. struct xhci_input_control_ctx *ctrl_ctx;
  552. struct xhci_ep_ctx *ep_ctx;
  553. int max_packet_size;
  554. int hw_max_packet_size;
  555. int ret = 0;
  556. out_ctx = xhci->devs[slot_id]->out_ctx;
  557. ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  558. hw_max_packet_size = MAX_PACKET_DECODED(ep_ctx->ep_info2);
  559. max_packet_size = urb->dev->ep0.desc.wMaxPacketSize;
  560. if (hw_max_packet_size != max_packet_size) {
  561. xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
  562. xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
  563. max_packet_size);
  564. xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
  565. hw_max_packet_size);
  566. xhci_dbg(xhci, "Issuing evaluate context command.\n");
  567. /* Set up the modified control endpoint 0 */
  568. xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
  569. xhci->devs[slot_id]->out_ctx, ep_index);
  570. in_ctx = xhci->devs[slot_id]->in_ctx;
  571. ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
  572. ep_ctx->ep_info2 &= ~MAX_PACKET_MASK;
  573. ep_ctx->ep_info2 |= MAX_PACKET(max_packet_size);
  574. /* Set up the input context flags for the command */
  575. /* FIXME: This won't work if a non-default control endpoint
  576. * changes max packet sizes.
  577. */
  578. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  579. ctrl_ctx->add_flags = EP0_FLAG;
  580. ctrl_ctx->drop_flags = 0;
  581. xhci_dbg(xhci, "Slot %d input context\n", slot_id);
  582. xhci_dbg_ctx(xhci, in_ctx, ep_index);
  583. xhci_dbg(xhci, "Slot %d output context\n", slot_id);
  584. xhci_dbg_ctx(xhci, out_ctx, ep_index);
  585. ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
  586. true, false);
  587. /* Clean up the input context for later use by bandwidth
  588. * functions.
  589. */
  590. ctrl_ctx->add_flags = SLOT_FLAG;
  591. }
  592. return ret;
  593. }
  594. /*
  595. * non-error returns are a promise to giveback() the urb later
  596. * we drop ownership so next owner (or urb unlink) can get it
  597. */
  598. int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
  599. {
  600. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  601. unsigned long flags;
  602. int ret = 0;
  603. unsigned int slot_id, ep_index;
  604. if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, true, __func__) <= 0)
  605. return -EINVAL;
  606. slot_id = urb->dev->slot_id;
  607. ep_index = xhci_get_endpoint_index(&urb->ep->desc);
  608. if (!xhci->devs || !xhci->devs[slot_id]) {
  609. if (!in_interrupt())
  610. dev_warn(&urb->dev->dev, "WARN: urb submitted for dev with no Slot ID\n");
  611. ret = -EINVAL;
  612. goto exit;
  613. }
  614. if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
  615. if (!in_interrupt())
  616. xhci_dbg(xhci, "urb submitted during PCI suspend\n");
  617. ret = -ESHUTDOWN;
  618. goto exit;
  619. }
  620. if (usb_endpoint_xfer_control(&urb->ep->desc)) {
  621. /* Check to see if the max packet size for the default control
  622. * endpoint changed during FS device enumeration
  623. */
  624. if (urb->dev->speed == USB_SPEED_FULL) {
  625. ret = xhci_check_maxpacket(xhci, slot_id,
  626. ep_index, urb);
  627. if (ret < 0)
  628. return ret;
  629. }
  630. /* We have a spinlock and interrupts disabled, so we must pass
  631. * atomic context to this function, which may allocate memory.
  632. */
  633. spin_lock_irqsave(&xhci->lock, flags);
  634. if (xhci->xhc_state & XHCI_STATE_DYING)
  635. goto dying;
  636. ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
  637. slot_id, ep_index);
  638. spin_unlock_irqrestore(&xhci->lock, flags);
  639. } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
  640. spin_lock_irqsave(&xhci->lock, flags);
  641. if (xhci->xhc_state & XHCI_STATE_DYING)
  642. goto dying;
  643. ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
  644. slot_id, ep_index);
  645. spin_unlock_irqrestore(&xhci->lock, flags);
  646. } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
  647. spin_lock_irqsave(&xhci->lock, flags);
  648. if (xhci->xhc_state & XHCI_STATE_DYING)
  649. goto dying;
  650. ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
  651. slot_id, ep_index);
  652. spin_unlock_irqrestore(&xhci->lock, flags);
  653. } else {
  654. ret = -EINVAL;
  655. }
  656. exit:
  657. return ret;
  658. dying:
  659. xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
  660. "non-responsive xHCI host.\n",
  661. urb->ep->desc.bEndpointAddress, urb);
  662. spin_unlock_irqrestore(&xhci->lock, flags);
  663. return -ESHUTDOWN;
  664. }
  665. /*
  666. * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
  667. * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
  668. * should pick up where it left off in the TD, unless a Set Transfer Ring
  669. * Dequeue Pointer is issued.
  670. *
  671. * The TRBs that make up the buffers for the canceled URB will be "removed" from
  672. * the ring. Since the ring is a contiguous structure, they can't be physically
  673. * removed. Instead, there are two options:
  674. *
  675. * 1) If the HC is in the middle of processing the URB to be canceled, we
  676. * simply move the ring's dequeue pointer past those TRBs using the Set
  677. * Transfer Ring Dequeue Pointer command. This will be the common case,
  678. * when drivers timeout on the last submitted URB and attempt to cancel.
  679. *
  680. * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
  681. * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
  682. * HC will need to invalidate the any TRBs it has cached after the stop
  683. * endpoint command, as noted in the xHCI 0.95 errata.
  684. *
  685. * 3) The TD may have completed by the time the Stop Endpoint Command
  686. * completes, so software needs to handle that case too.
  687. *
  688. * This function should protect against the TD enqueueing code ringing the
  689. * doorbell while this code is waiting for a Stop Endpoint command to complete.
  690. * It also needs to account for multiple cancellations on happening at the same
  691. * time for the same endpoint.
  692. *
  693. * Note that this function can be called in any context, or so says
  694. * usb_hcd_unlink_urb()
  695. */
  696. int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  697. {
  698. unsigned long flags;
  699. int ret;
  700. u32 temp;
  701. struct xhci_hcd *xhci;
  702. struct xhci_td *td;
  703. unsigned int ep_index;
  704. struct xhci_ring *ep_ring;
  705. struct xhci_virt_ep *ep;
  706. xhci = hcd_to_xhci(hcd);
  707. spin_lock_irqsave(&xhci->lock, flags);
  708. /* Make sure the URB hasn't completed or been unlinked already */
  709. ret = usb_hcd_check_unlink_urb(hcd, urb, status);
  710. if (ret || !urb->hcpriv)
  711. goto done;
  712. temp = xhci_readl(xhci, &xhci->op_regs->status);
  713. if (temp == 0xffffffff) {
  714. xhci_dbg(xhci, "HW died, freeing TD.\n");
  715. td = (struct xhci_td *) urb->hcpriv;
  716. usb_hcd_unlink_urb_from_ep(hcd, urb);
  717. spin_unlock_irqrestore(&xhci->lock, flags);
  718. usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, -ESHUTDOWN);
  719. kfree(td);
  720. return ret;
  721. }
  722. if (xhci->xhc_state & XHCI_STATE_DYING) {
  723. xhci_dbg(xhci, "Ep 0x%x: URB %p to be canceled on "
  724. "non-responsive xHCI host.\n",
  725. urb->ep->desc.bEndpointAddress, urb);
  726. /* Let the stop endpoint command watchdog timer (which set this
  727. * state) finish cleaning up the endpoint TD lists. We must
  728. * have caught it in the middle of dropping a lock and giving
  729. * back an URB.
  730. */
  731. goto done;
  732. }
  733. xhci_dbg(xhci, "Cancel URB %p\n", urb);
  734. xhci_dbg(xhci, "Event ring:\n");
  735. xhci_debug_ring(xhci, xhci->event_ring);
  736. ep_index = xhci_get_endpoint_index(&urb->ep->desc);
  737. ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
  738. ep_ring = ep->ring;
  739. xhci_dbg(xhci, "Endpoint ring:\n");
  740. xhci_debug_ring(xhci, ep_ring);
  741. td = (struct xhci_td *) urb->hcpriv;
  742. list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
  743. /* Queue a stop endpoint command, but only if this is
  744. * the first cancellation to be handled.
  745. */
  746. if (!(ep->ep_state & EP_HALT_PENDING)) {
  747. ep->ep_state |= EP_HALT_PENDING;
  748. ep->stop_cmds_pending++;
  749. ep->stop_cmd_timer.expires = jiffies +
  750. XHCI_STOP_EP_CMD_TIMEOUT * HZ;
  751. add_timer(&ep->stop_cmd_timer);
  752. xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index);
  753. xhci_ring_cmd_db(xhci);
  754. }
  755. done:
  756. spin_unlock_irqrestore(&xhci->lock, flags);
  757. return ret;
  758. }
  759. /* Drop an endpoint from a new bandwidth configuration for this device.
  760. * Only one call to this function is allowed per endpoint before
  761. * check_bandwidth() or reset_bandwidth() must be called.
  762. * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
  763. * add the endpoint to the schedule with possibly new parameters denoted by a
  764. * different endpoint descriptor in usb_host_endpoint.
  765. * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
  766. * not allowed.
  767. *
  768. * The USB core will not allow URBs to be queued to an endpoint that is being
  769. * disabled, so there's no need for mutual exclusion to protect
  770. * the xhci->devs[slot_id] structure.
  771. */
  772. int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  773. struct usb_host_endpoint *ep)
  774. {
  775. struct xhci_hcd *xhci;
  776. struct xhci_container_ctx *in_ctx, *out_ctx;
  777. struct xhci_input_control_ctx *ctrl_ctx;
  778. struct xhci_slot_ctx *slot_ctx;
  779. unsigned int last_ctx;
  780. unsigned int ep_index;
  781. struct xhci_ep_ctx *ep_ctx;
  782. u32 drop_flag;
  783. u32 new_add_flags, new_drop_flags, new_slot_info;
  784. int ret;
  785. ret = xhci_check_args(hcd, udev, ep, 1, __func__);
  786. if (ret <= 0)
  787. return ret;
  788. xhci = hcd_to_xhci(hcd);
  789. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  790. drop_flag = xhci_get_endpoint_flag(&ep->desc);
  791. if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
  792. xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
  793. __func__, drop_flag);
  794. return 0;
  795. }
  796. if (!xhci->devs || !xhci->devs[udev->slot_id]) {
  797. xhci_warn(xhci, "xHCI %s called with unaddressed device\n",
  798. __func__);
  799. return -EINVAL;
  800. }
  801. in_ctx = xhci->devs[udev->slot_id]->in_ctx;
  802. out_ctx = xhci->devs[udev->slot_id]->out_ctx;
  803. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  804. ep_index = xhci_get_endpoint_index(&ep->desc);
  805. ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  806. /* If the HC already knows the endpoint is disabled,
  807. * or the HCD has noted it is disabled, ignore this request
  808. */
  809. if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED ||
  810. ctrl_ctx->drop_flags & xhci_get_endpoint_flag(&ep->desc)) {
  811. xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
  812. __func__, ep);
  813. return 0;
  814. }
  815. ctrl_ctx->drop_flags |= drop_flag;
  816. new_drop_flags = ctrl_ctx->drop_flags;
  817. ctrl_ctx->add_flags &= ~drop_flag;
  818. new_add_flags = ctrl_ctx->add_flags;
  819. last_ctx = xhci_last_valid_endpoint(ctrl_ctx->add_flags);
  820. slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
  821. /* Update the last valid endpoint context, if we deleted the last one */
  822. if ((slot_ctx->dev_info & LAST_CTX_MASK) > LAST_CTX(last_ctx)) {
  823. slot_ctx->dev_info &= ~LAST_CTX_MASK;
  824. slot_ctx->dev_info |= LAST_CTX(last_ctx);
  825. }
  826. new_slot_info = slot_ctx->dev_info;
  827. xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
  828. xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
  829. (unsigned int) ep->desc.bEndpointAddress,
  830. udev->slot_id,
  831. (unsigned int) new_drop_flags,
  832. (unsigned int) new_add_flags,
  833. (unsigned int) new_slot_info);
  834. return 0;
  835. }
  836. /* Add an endpoint to a new possible bandwidth configuration for this device.
  837. * Only one call to this function is allowed per endpoint before
  838. * check_bandwidth() or reset_bandwidth() must be called.
  839. * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
  840. * add the endpoint to the schedule with possibly new parameters denoted by a
  841. * different endpoint descriptor in usb_host_endpoint.
  842. * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
  843. * not allowed.
  844. *
  845. * The USB core will not allow URBs to be queued to an endpoint until the
  846. * configuration or alt setting is installed in the device, so there's no need
  847. * for mutual exclusion to protect the xhci->devs[slot_id] structure.
  848. */
  849. int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  850. struct usb_host_endpoint *ep)
  851. {
  852. struct xhci_hcd *xhci;
  853. struct xhci_container_ctx *in_ctx, *out_ctx;
  854. unsigned int ep_index;
  855. struct xhci_ep_ctx *ep_ctx;
  856. struct xhci_slot_ctx *slot_ctx;
  857. struct xhci_input_control_ctx *ctrl_ctx;
  858. u32 added_ctxs;
  859. unsigned int last_ctx;
  860. u32 new_add_flags, new_drop_flags, new_slot_info;
  861. int ret = 0;
  862. ret = xhci_check_args(hcd, udev, ep, 1, __func__);
  863. if (ret <= 0) {
  864. /* So we won't queue a reset ep command for a root hub */
  865. ep->hcpriv = NULL;
  866. return ret;
  867. }
  868. xhci = hcd_to_xhci(hcd);
  869. added_ctxs = xhci_get_endpoint_flag(&ep->desc);
  870. last_ctx = xhci_last_valid_endpoint(added_ctxs);
  871. if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
  872. /* FIXME when we have to issue an evaluate endpoint command to
  873. * deal with ep0 max packet size changing once we get the
  874. * descriptors
  875. */
  876. xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
  877. __func__, added_ctxs);
  878. return 0;
  879. }
  880. if (!xhci->devs || !xhci->devs[udev->slot_id]) {
  881. xhci_warn(xhci, "xHCI %s called with unaddressed device\n",
  882. __func__);
  883. return -EINVAL;
  884. }
  885. in_ctx = xhci->devs[udev->slot_id]->in_ctx;
  886. out_ctx = xhci->devs[udev->slot_id]->out_ctx;
  887. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  888. ep_index = xhci_get_endpoint_index(&ep->desc);
  889. ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  890. /* If the HCD has already noted the endpoint is enabled,
  891. * ignore this request.
  892. */
  893. if (ctrl_ctx->add_flags & xhci_get_endpoint_flag(&ep->desc)) {
  894. xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
  895. __func__, ep);
  896. return 0;
  897. }
  898. /*
  899. * Configuration and alternate setting changes must be done in
  900. * process context, not interrupt context (or so documenation
  901. * for usb_set_interface() and usb_set_configuration() claim).
  902. */
  903. if (xhci_endpoint_init(xhci, xhci->devs[udev->slot_id],
  904. udev, ep, GFP_KERNEL) < 0) {
  905. dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
  906. __func__, ep->desc.bEndpointAddress);
  907. return -ENOMEM;
  908. }
  909. ctrl_ctx->add_flags |= added_ctxs;
  910. new_add_flags = ctrl_ctx->add_flags;
  911. /* If xhci_endpoint_disable() was called for this endpoint, but the
  912. * xHC hasn't been notified yet through the check_bandwidth() call,
  913. * this re-adds a new state for the endpoint from the new endpoint
  914. * descriptors. We must drop and re-add this endpoint, so we leave the
  915. * drop flags alone.
  916. */
  917. new_drop_flags = ctrl_ctx->drop_flags;
  918. slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
  919. /* Update the last valid endpoint context, if we just added one past */
  920. if ((slot_ctx->dev_info & LAST_CTX_MASK) < LAST_CTX(last_ctx)) {
  921. slot_ctx->dev_info &= ~LAST_CTX_MASK;
  922. slot_ctx->dev_info |= LAST_CTX(last_ctx);
  923. }
  924. new_slot_info = slot_ctx->dev_info;
  925. /* Store the usb_device pointer for later use */
  926. ep->hcpriv = udev;
  927. xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
  928. (unsigned int) ep->desc.bEndpointAddress,
  929. udev->slot_id,
  930. (unsigned int) new_drop_flags,
  931. (unsigned int) new_add_flags,
  932. (unsigned int) new_slot_info);
  933. return 0;
  934. }
  935. static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
  936. {
  937. struct xhci_input_control_ctx *ctrl_ctx;
  938. struct xhci_ep_ctx *ep_ctx;
  939. struct xhci_slot_ctx *slot_ctx;
  940. int i;
  941. /* When a device's add flag and drop flag are zero, any subsequent
  942. * configure endpoint command will leave that endpoint's state
  943. * untouched. Make sure we don't leave any old state in the input
  944. * endpoint contexts.
  945. */
  946. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  947. ctrl_ctx->drop_flags = 0;
  948. ctrl_ctx->add_flags = 0;
  949. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
  950. slot_ctx->dev_info &= ~LAST_CTX_MASK;
  951. /* Endpoint 0 is always valid */
  952. slot_ctx->dev_info |= LAST_CTX(1);
  953. for (i = 1; i < 31; ++i) {
  954. ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
  955. ep_ctx->ep_info = 0;
  956. ep_ctx->ep_info2 = 0;
  957. ep_ctx->deq = 0;
  958. ep_ctx->tx_info = 0;
  959. }
  960. }
  961. static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
  962. struct usb_device *udev, int *cmd_status)
  963. {
  964. int ret;
  965. switch (*cmd_status) {
  966. case COMP_ENOMEM:
  967. dev_warn(&udev->dev, "Not enough host controller resources "
  968. "for new device state.\n");
  969. ret = -ENOMEM;
  970. /* FIXME: can we allocate more resources for the HC? */
  971. break;
  972. case COMP_BW_ERR:
  973. dev_warn(&udev->dev, "Not enough bandwidth "
  974. "for new device state.\n");
  975. ret = -ENOSPC;
  976. /* FIXME: can we go back to the old state? */
  977. break;
  978. case COMP_TRB_ERR:
  979. /* the HCD set up something wrong */
  980. dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
  981. "add flag = 1, "
  982. "and endpoint is not disabled.\n");
  983. ret = -EINVAL;
  984. break;
  985. case COMP_SUCCESS:
  986. dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
  987. ret = 0;
  988. break;
  989. default:
  990. xhci_err(xhci, "ERROR: unexpected command completion "
  991. "code 0x%x.\n", *cmd_status);
  992. ret = -EINVAL;
  993. break;
  994. }
  995. return ret;
  996. }
  997. static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
  998. struct usb_device *udev, int *cmd_status)
  999. {
  1000. int ret;
  1001. struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
  1002. switch (*cmd_status) {
  1003. case COMP_EINVAL:
  1004. dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
  1005. "context command.\n");
  1006. ret = -EINVAL;
  1007. break;
  1008. case COMP_EBADSLT:
  1009. dev_warn(&udev->dev, "WARN: slot not enabled for"
  1010. "evaluate context command.\n");
  1011. case COMP_CTX_STATE:
  1012. dev_warn(&udev->dev, "WARN: invalid context state for "
  1013. "evaluate context command.\n");
  1014. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
  1015. ret = -EINVAL;
  1016. break;
  1017. case COMP_SUCCESS:
  1018. dev_dbg(&udev->dev, "Successful evaluate context command\n");
  1019. ret = 0;
  1020. break;
  1021. default:
  1022. xhci_err(xhci, "ERROR: unexpected command completion "
  1023. "code 0x%x.\n", *cmd_status);
  1024. ret = -EINVAL;
  1025. break;
  1026. }
  1027. return ret;
  1028. }
  1029. /* Issue a configure endpoint command or evaluate context command
  1030. * and wait for it to finish.
  1031. */
  1032. static int xhci_configure_endpoint(struct xhci_hcd *xhci,
  1033. struct usb_device *udev,
  1034. struct xhci_command *command,
  1035. bool ctx_change, bool must_succeed)
  1036. {
  1037. int ret;
  1038. int timeleft;
  1039. unsigned long flags;
  1040. struct xhci_container_ctx *in_ctx;
  1041. struct completion *cmd_completion;
  1042. int *cmd_status;
  1043. struct xhci_virt_device *virt_dev;
  1044. spin_lock_irqsave(&xhci->lock, flags);
  1045. virt_dev = xhci->devs[udev->slot_id];
  1046. if (command) {
  1047. in_ctx = command->in_ctx;
  1048. cmd_completion = command->completion;
  1049. cmd_status = &command->status;
  1050. command->command_trb = xhci->cmd_ring->enqueue;
  1051. list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
  1052. } else {
  1053. in_ctx = virt_dev->in_ctx;
  1054. cmd_completion = &virt_dev->cmd_completion;
  1055. cmd_status = &virt_dev->cmd_status;
  1056. }
  1057. if (!ctx_change)
  1058. ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
  1059. udev->slot_id, must_succeed);
  1060. else
  1061. ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
  1062. udev->slot_id);
  1063. if (ret < 0) {
  1064. spin_unlock_irqrestore(&xhci->lock, flags);
  1065. xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
  1066. return -ENOMEM;
  1067. }
  1068. xhci_ring_cmd_db(xhci);
  1069. spin_unlock_irqrestore(&xhci->lock, flags);
  1070. /* Wait for the configure endpoint command to complete */
  1071. timeleft = wait_for_completion_interruptible_timeout(
  1072. cmd_completion,
  1073. USB_CTRL_SET_TIMEOUT);
  1074. if (timeleft <= 0) {
  1075. xhci_warn(xhci, "%s while waiting for %s command\n",
  1076. timeleft == 0 ? "Timeout" : "Signal",
  1077. ctx_change == 0 ?
  1078. "configure endpoint" :
  1079. "evaluate context");
  1080. /* FIXME cancel the configure endpoint command */
  1081. return -ETIME;
  1082. }
  1083. if (!ctx_change)
  1084. return xhci_configure_endpoint_result(xhci, udev, cmd_status);
  1085. return xhci_evaluate_context_result(xhci, udev, cmd_status);
  1086. }
  1087. /* Called after one or more calls to xhci_add_endpoint() or
  1088. * xhci_drop_endpoint(). If this call fails, the USB core is expected
  1089. * to call xhci_reset_bandwidth().
  1090. *
  1091. * Since we are in the middle of changing either configuration or
  1092. * installing a new alt setting, the USB core won't allow URBs to be
  1093. * enqueued for any endpoint on the old config or interface. Nothing
  1094. * else should be touching the xhci->devs[slot_id] structure, so we
  1095. * don't need to take the xhci->lock for manipulating that.
  1096. */
  1097. int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
  1098. {
  1099. int i;
  1100. int ret = 0;
  1101. struct xhci_hcd *xhci;
  1102. struct xhci_virt_device *virt_dev;
  1103. struct xhci_input_control_ctx *ctrl_ctx;
  1104. struct xhci_slot_ctx *slot_ctx;
  1105. ret = xhci_check_args(hcd, udev, NULL, 0, __func__);
  1106. if (ret <= 0)
  1107. return ret;
  1108. xhci = hcd_to_xhci(hcd);
  1109. if (!udev->slot_id || !xhci->devs || !xhci->devs[udev->slot_id]) {
  1110. xhci_warn(xhci, "xHCI %s called with unaddressed device\n",
  1111. __func__);
  1112. return -EINVAL;
  1113. }
  1114. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  1115. virt_dev = xhci->devs[udev->slot_id];
  1116. /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
  1117. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  1118. ctrl_ctx->add_flags |= SLOT_FLAG;
  1119. ctrl_ctx->add_flags &= ~EP0_FLAG;
  1120. ctrl_ctx->drop_flags &= ~SLOT_FLAG;
  1121. ctrl_ctx->drop_flags &= ~EP0_FLAG;
  1122. xhci_dbg(xhci, "New Input Control Context:\n");
  1123. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
  1124. xhci_dbg_ctx(xhci, virt_dev->in_ctx,
  1125. LAST_CTX_TO_EP_NUM(slot_ctx->dev_info));
  1126. ret = xhci_configure_endpoint(xhci, udev, NULL,
  1127. false, false);
  1128. if (ret) {
  1129. /* Callee should call reset_bandwidth() */
  1130. return ret;
  1131. }
  1132. xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
  1133. xhci_dbg_ctx(xhci, virt_dev->out_ctx,
  1134. LAST_CTX_TO_EP_NUM(slot_ctx->dev_info));
  1135. xhci_zero_in_ctx(xhci, virt_dev);
  1136. /* Install new rings and free or cache any old rings */
  1137. for (i = 1; i < 31; ++i) {
  1138. int rings_cached;
  1139. if (!virt_dev->eps[i].new_ring)
  1140. continue;
  1141. /* Only cache or free the old ring if it exists.
  1142. * It may not if this is the first add of an endpoint.
  1143. */
  1144. if (virt_dev->eps[i].ring) {
  1145. rings_cached = virt_dev->num_rings_cached;
  1146. if (rings_cached < XHCI_MAX_RINGS_CACHED) {
  1147. virt_dev->num_rings_cached++;
  1148. rings_cached = virt_dev->num_rings_cached;
  1149. virt_dev->ring_cache[rings_cached] =
  1150. virt_dev->eps[i].ring;
  1151. xhci_dbg(xhci, "Cached old ring, "
  1152. "%d ring%s cached\n",
  1153. rings_cached,
  1154. (rings_cached > 1) ? "s" : "");
  1155. } else {
  1156. xhci_ring_free(xhci, virt_dev->eps[i].ring);
  1157. xhci_dbg(xhci, "Ring cache full (%d rings), "
  1158. "freeing ring\n",
  1159. virt_dev->num_rings_cached);
  1160. }
  1161. }
  1162. virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
  1163. virt_dev->eps[i].new_ring = NULL;
  1164. }
  1165. return ret;
  1166. }
  1167. void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
  1168. {
  1169. struct xhci_hcd *xhci;
  1170. struct xhci_virt_device *virt_dev;
  1171. int i, ret;
  1172. ret = xhci_check_args(hcd, udev, NULL, 0, __func__);
  1173. if (ret <= 0)
  1174. return;
  1175. xhci = hcd_to_xhci(hcd);
  1176. if (!xhci->devs || !xhci->devs[udev->slot_id]) {
  1177. xhci_warn(xhci, "xHCI %s called with unaddressed device\n",
  1178. __func__);
  1179. return;
  1180. }
  1181. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  1182. virt_dev = xhci->devs[udev->slot_id];
  1183. /* Free any rings allocated for added endpoints */
  1184. for (i = 0; i < 31; ++i) {
  1185. if (virt_dev->eps[i].new_ring) {
  1186. xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
  1187. virt_dev->eps[i].new_ring = NULL;
  1188. }
  1189. }
  1190. xhci_zero_in_ctx(xhci, virt_dev);
  1191. }
  1192. static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
  1193. struct xhci_container_ctx *in_ctx,
  1194. struct xhci_container_ctx *out_ctx,
  1195. u32 add_flags, u32 drop_flags)
  1196. {
  1197. struct xhci_input_control_ctx *ctrl_ctx;
  1198. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  1199. ctrl_ctx->add_flags = add_flags;
  1200. ctrl_ctx->drop_flags = drop_flags;
  1201. xhci_slot_copy(xhci, in_ctx, out_ctx);
  1202. ctrl_ctx->add_flags |= SLOT_FLAG;
  1203. xhci_dbg(xhci, "Input Context:\n");
  1204. xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
  1205. }
  1206. void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
  1207. unsigned int slot_id, unsigned int ep_index,
  1208. struct xhci_dequeue_state *deq_state)
  1209. {
  1210. struct xhci_container_ctx *in_ctx;
  1211. struct xhci_ep_ctx *ep_ctx;
  1212. u32 added_ctxs;
  1213. dma_addr_t addr;
  1214. xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
  1215. xhci->devs[slot_id]->out_ctx, ep_index);
  1216. in_ctx = xhci->devs[slot_id]->in_ctx;
  1217. ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
  1218. addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
  1219. deq_state->new_deq_ptr);
  1220. if (addr == 0) {
  1221. xhci_warn(xhci, "WARN Cannot submit config ep after "
  1222. "reset ep command\n");
  1223. xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
  1224. deq_state->new_deq_seg,
  1225. deq_state->new_deq_ptr);
  1226. return;
  1227. }
  1228. ep_ctx->deq = addr | deq_state->new_cycle_state;
  1229. added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
  1230. xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
  1231. xhci->devs[slot_id]->out_ctx, added_ctxs, added_ctxs);
  1232. }
  1233. void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
  1234. struct usb_device *udev, unsigned int ep_index)
  1235. {
  1236. struct xhci_dequeue_state deq_state;
  1237. struct xhci_virt_ep *ep;
  1238. xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
  1239. ep = &xhci->devs[udev->slot_id]->eps[ep_index];
  1240. /* We need to move the HW's dequeue pointer past this TD,
  1241. * or it will attempt to resend it on the next doorbell ring.
  1242. */
  1243. xhci_find_new_dequeue_state(xhci, udev->slot_id,
  1244. ep_index, ep->stopped_td,
  1245. &deq_state);
  1246. /* HW with the reset endpoint quirk will use the saved dequeue state to
  1247. * issue a configure endpoint command later.
  1248. */
  1249. if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
  1250. xhci_dbg(xhci, "Queueing new dequeue state\n");
  1251. xhci_queue_new_dequeue_state(xhci, udev->slot_id,
  1252. ep_index, &deq_state);
  1253. } else {
  1254. /* Better hope no one uses the input context between now and the
  1255. * reset endpoint completion!
  1256. */
  1257. xhci_dbg(xhci, "Setting up input context for "
  1258. "configure endpoint command\n");
  1259. xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
  1260. ep_index, &deq_state);
  1261. }
  1262. }
  1263. /* Deal with stalled endpoints. The core should have sent the control message
  1264. * to clear the halt condition. However, we need to make the xHCI hardware
  1265. * reset its sequence number, since a device will expect a sequence number of
  1266. * zero after the halt condition is cleared.
  1267. * Context: in_interrupt
  1268. */
  1269. void xhci_endpoint_reset(struct usb_hcd *hcd,
  1270. struct usb_host_endpoint *ep)
  1271. {
  1272. struct xhci_hcd *xhci;
  1273. struct usb_device *udev;
  1274. unsigned int ep_index;
  1275. unsigned long flags;
  1276. int ret;
  1277. struct xhci_virt_ep *virt_ep;
  1278. xhci = hcd_to_xhci(hcd);
  1279. udev = (struct usb_device *) ep->hcpriv;
  1280. /* Called with a root hub endpoint (or an endpoint that wasn't added
  1281. * with xhci_add_endpoint()
  1282. */
  1283. if (!ep->hcpriv)
  1284. return;
  1285. ep_index = xhci_get_endpoint_index(&ep->desc);
  1286. virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
  1287. if (!virt_ep->stopped_td) {
  1288. xhci_dbg(xhci, "Endpoint 0x%x not halted, refusing to reset.\n",
  1289. ep->desc.bEndpointAddress);
  1290. return;
  1291. }
  1292. if (usb_endpoint_xfer_control(&ep->desc)) {
  1293. xhci_dbg(xhci, "Control endpoint stall already handled.\n");
  1294. return;
  1295. }
  1296. xhci_dbg(xhci, "Queueing reset endpoint command\n");
  1297. spin_lock_irqsave(&xhci->lock, flags);
  1298. ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
  1299. /*
  1300. * Can't change the ring dequeue pointer until it's transitioned to the
  1301. * stopped state, which is only upon a successful reset endpoint
  1302. * command. Better hope that last command worked!
  1303. */
  1304. if (!ret) {
  1305. xhci_cleanup_stalled_ring(xhci, udev, ep_index);
  1306. kfree(virt_ep->stopped_td);
  1307. xhci_ring_cmd_db(xhci);
  1308. }
  1309. spin_unlock_irqrestore(&xhci->lock, flags);
  1310. if (ret)
  1311. xhci_warn(xhci, "FIXME allocate a new ring segment\n");
  1312. }
  1313. /*
  1314. * At this point, the struct usb_device is about to go away, the device has
  1315. * disconnected, and all traffic has been stopped and the endpoints have been
  1316. * disabled. Free any HC data structures associated with that device.
  1317. */
  1318. void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
  1319. {
  1320. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1321. struct xhci_virt_device *virt_dev;
  1322. unsigned long flags;
  1323. u32 state;
  1324. int i;
  1325. if (udev->slot_id == 0)
  1326. return;
  1327. virt_dev = xhci->devs[udev->slot_id];
  1328. if (!virt_dev)
  1329. return;
  1330. /* Stop any wayward timer functions (which may grab the lock) */
  1331. for (i = 0; i < 31; ++i) {
  1332. virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
  1333. del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
  1334. }
  1335. spin_lock_irqsave(&xhci->lock, flags);
  1336. /* Don't disable the slot if the host controller is dead. */
  1337. state = xhci_readl(xhci, &xhci->op_regs->status);
  1338. if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING)) {
  1339. xhci_free_virt_device(xhci, udev->slot_id);
  1340. spin_unlock_irqrestore(&xhci->lock, flags);
  1341. return;
  1342. }
  1343. if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
  1344. spin_unlock_irqrestore(&xhci->lock, flags);
  1345. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  1346. return;
  1347. }
  1348. xhci_ring_cmd_db(xhci);
  1349. spin_unlock_irqrestore(&xhci->lock, flags);
  1350. /*
  1351. * Event command completion handler will free any data structures
  1352. * associated with the slot. XXX Can free sleep?
  1353. */
  1354. }
  1355. /*
  1356. * Returns 0 if the xHC ran out of device slots, the Enable Slot command
  1357. * timed out, or allocating memory failed. Returns 1 on success.
  1358. */
  1359. int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
  1360. {
  1361. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1362. unsigned long flags;
  1363. int timeleft;
  1364. int ret;
  1365. spin_lock_irqsave(&xhci->lock, flags);
  1366. ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
  1367. if (ret) {
  1368. spin_unlock_irqrestore(&xhci->lock, flags);
  1369. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  1370. return 0;
  1371. }
  1372. xhci_ring_cmd_db(xhci);
  1373. spin_unlock_irqrestore(&xhci->lock, flags);
  1374. /* XXX: how much time for xHC slot assignment? */
  1375. timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
  1376. USB_CTRL_SET_TIMEOUT);
  1377. if (timeleft <= 0) {
  1378. xhci_warn(xhci, "%s while waiting for a slot\n",
  1379. timeleft == 0 ? "Timeout" : "Signal");
  1380. /* FIXME cancel the enable slot request */
  1381. return 0;
  1382. }
  1383. if (!xhci->slot_id) {
  1384. xhci_err(xhci, "Error while assigning device slot ID\n");
  1385. return 0;
  1386. }
  1387. /* xhci_alloc_virt_device() does not touch rings; no need to lock */
  1388. if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_KERNEL)) {
  1389. /* Disable slot, if we can do it without mem alloc */
  1390. xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
  1391. spin_lock_irqsave(&xhci->lock, flags);
  1392. if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
  1393. xhci_ring_cmd_db(xhci);
  1394. spin_unlock_irqrestore(&xhci->lock, flags);
  1395. return 0;
  1396. }
  1397. udev->slot_id = xhci->slot_id;
  1398. /* Is this a LS or FS device under a HS hub? */
  1399. /* Hub or peripherial? */
  1400. return 1;
  1401. }
  1402. /*
  1403. * Issue an Address Device command (which will issue a SetAddress request to
  1404. * the device).
  1405. * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
  1406. * we should only issue and wait on one address command at the same time.
  1407. *
  1408. * We add one to the device address issued by the hardware because the USB core
  1409. * uses address 1 for the root hubs (even though they're not really devices).
  1410. */
  1411. int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
  1412. {
  1413. unsigned long flags;
  1414. int timeleft;
  1415. struct xhci_virt_device *virt_dev;
  1416. int ret = 0;
  1417. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1418. struct xhci_slot_ctx *slot_ctx;
  1419. struct xhci_input_control_ctx *ctrl_ctx;
  1420. u64 temp_64;
  1421. if (!udev->slot_id) {
  1422. xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
  1423. return -EINVAL;
  1424. }
  1425. virt_dev = xhci->devs[udev->slot_id];
  1426. /* If this is a Set Address to an unconfigured device, setup ep 0 */
  1427. if (!udev->config)
  1428. xhci_setup_addressable_virt_dev(xhci, udev);
  1429. /* Otherwise, assume the core has the device configured how it wants */
  1430. xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
  1431. xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
  1432. spin_lock_irqsave(&xhci->lock, flags);
  1433. ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
  1434. udev->slot_id);
  1435. if (ret) {
  1436. spin_unlock_irqrestore(&xhci->lock, flags);
  1437. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  1438. return ret;
  1439. }
  1440. xhci_ring_cmd_db(xhci);
  1441. spin_unlock_irqrestore(&xhci->lock, flags);
  1442. /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
  1443. timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
  1444. USB_CTRL_SET_TIMEOUT);
  1445. /* FIXME: From section 4.3.4: "Software shall be responsible for timing
  1446. * the SetAddress() "recovery interval" required by USB and aborting the
  1447. * command on a timeout.
  1448. */
  1449. if (timeleft <= 0) {
  1450. xhci_warn(xhci, "%s while waiting for a slot\n",
  1451. timeleft == 0 ? "Timeout" : "Signal");
  1452. /* FIXME cancel the address device command */
  1453. return -ETIME;
  1454. }
  1455. switch (virt_dev->cmd_status) {
  1456. case COMP_CTX_STATE:
  1457. case COMP_EBADSLT:
  1458. xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
  1459. udev->slot_id);
  1460. ret = -EINVAL;
  1461. break;
  1462. case COMP_TX_ERR:
  1463. dev_warn(&udev->dev, "Device not responding to set address.\n");
  1464. ret = -EPROTO;
  1465. break;
  1466. case COMP_SUCCESS:
  1467. xhci_dbg(xhci, "Successful Address Device command\n");
  1468. break;
  1469. default:
  1470. xhci_err(xhci, "ERROR: unexpected command completion "
  1471. "code 0x%x.\n", virt_dev->cmd_status);
  1472. xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
  1473. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
  1474. ret = -EINVAL;
  1475. break;
  1476. }
  1477. if (ret) {
  1478. return ret;
  1479. }
  1480. temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
  1481. xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64);
  1482. xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n",
  1483. udev->slot_id,
  1484. &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
  1485. (unsigned long long)
  1486. xhci->dcbaa->dev_context_ptrs[udev->slot_id]);
  1487. xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
  1488. (unsigned long long)virt_dev->out_ctx->dma);
  1489. xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
  1490. xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
  1491. xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
  1492. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
  1493. /*
  1494. * USB core uses address 1 for the roothubs, so we add one to the
  1495. * address given back to us by the HC.
  1496. */
  1497. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
  1498. udev->devnum = (slot_ctx->dev_state & DEV_ADDR_MASK) + 1;
  1499. /* Zero the input context control for later use */
  1500. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  1501. ctrl_ctx->add_flags = 0;
  1502. ctrl_ctx->drop_flags = 0;
  1503. xhci_dbg(xhci, "Device address = %d\n", udev->devnum);
  1504. /* XXX Meh, not sure if anyone else but choose_address uses this. */
  1505. set_bit(udev->devnum, udev->bus->devmap.devicemap);
  1506. return 0;
  1507. }
  1508. /* Once a hub descriptor is fetched for a device, we need to update the xHC's
  1509. * internal data structures for the device.
  1510. */
  1511. int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
  1512. struct usb_tt *tt, gfp_t mem_flags)
  1513. {
  1514. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1515. struct xhci_virt_device *vdev;
  1516. struct xhci_command *config_cmd;
  1517. struct xhci_input_control_ctx *ctrl_ctx;
  1518. struct xhci_slot_ctx *slot_ctx;
  1519. unsigned long flags;
  1520. unsigned think_time;
  1521. int ret;
  1522. /* Ignore root hubs */
  1523. if (!hdev->parent)
  1524. return 0;
  1525. vdev = xhci->devs[hdev->slot_id];
  1526. if (!vdev) {
  1527. xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
  1528. return -EINVAL;
  1529. }
  1530. config_cmd = xhci_alloc_command(xhci, true, mem_flags);
  1531. if (!config_cmd) {
  1532. xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
  1533. return -ENOMEM;
  1534. }
  1535. spin_lock_irqsave(&xhci->lock, flags);
  1536. xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
  1537. ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
  1538. ctrl_ctx->add_flags |= SLOT_FLAG;
  1539. slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
  1540. slot_ctx->dev_info |= DEV_HUB;
  1541. if (tt->multi)
  1542. slot_ctx->dev_info |= DEV_MTT;
  1543. if (xhci->hci_version > 0x95) {
  1544. xhci_dbg(xhci, "xHCI version %x needs hub "
  1545. "TT think time and number of ports\n",
  1546. (unsigned int) xhci->hci_version);
  1547. slot_ctx->dev_info2 |= XHCI_MAX_PORTS(hdev->maxchild);
  1548. /* Set TT think time - convert from ns to FS bit times.
  1549. * 0 = 8 FS bit times, 1 = 16 FS bit times,
  1550. * 2 = 24 FS bit times, 3 = 32 FS bit times.
  1551. */
  1552. think_time = tt->think_time;
  1553. if (think_time != 0)
  1554. think_time = (think_time / 666) - 1;
  1555. slot_ctx->tt_info |= TT_THINK_TIME(think_time);
  1556. } else {
  1557. xhci_dbg(xhci, "xHCI version %x doesn't need hub "
  1558. "TT think time or number of ports\n",
  1559. (unsigned int) xhci->hci_version);
  1560. }
  1561. slot_ctx->dev_state = 0;
  1562. spin_unlock_irqrestore(&xhci->lock, flags);
  1563. xhci_dbg(xhci, "Set up %s for hub device.\n",
  1564. (xhci->hci_version > 0x95) ?
  1565. "configure endpoint" : "evaluate context");
  1566. xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
  1567. xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
  1568. /* Issue and wait for the configure endpoint or
  1569. * evaluate context command.
  1570. */
  1571. if (xhci->hci_version > 0x95)
  1572. ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
  1573. false, false);
  1574. else
  1575. ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
  1576. true, false);
  1577. xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
  1578. xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
  1579. xhci_free_command(xhci, config_cmd);
  1580. return ret;
  1581. }
  1582. int xhci_get_frame(struct usb_hcd *hcd)
  1583. {
  1584. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1585. /* EHCI mods by the periodic size. Why? */
  1586. return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
  1587. }
  1588. MODULE_DESCRIPTION(DRIVER_DESC);
  1589. MODULE_AUTHOR(DRIVER_AUTHOR);
  1590. MODULE_LICENSE("GPL");
  1591. static int __init xhci_hcd_init(void)
  1592. {
  1593. #ifdef CONFIG_PCI
  1594. int retval = 0;
  1595. retval = xhci_register_pci();
  1596. if (retval < 0) {
  1597. printk(KERN_DEBUG "Problem registering PCI driver.");
  1598. return retval;
  1599. }
  1600. #endif
  1601. /*
  1602. * Check the compiler generated sizes of structures that must be laid
  1603. * out in specific ways for hardware access.
  1604. */
  1605. BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
  1606. BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
  1607. BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
  1608. /* xhci_device_control has eight fields, and also
  1609. * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
  1610. */
  1611. BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
  1612. BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
  1613. BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
  1614. BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
  1615. BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
  1616. /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
  1617. BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
  1618. BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
  1619. return 0;
  1620. }
  1621. module_init(xhci_hcd_init);
  1622. static void __exit xhci_hcd_cleanup(void)
  1623. {
  1624. #ifdef CONFIG_PCI
  1625. xhci_unregister_pci();
  1626. #endif
  1627. }
  1628. module_exit(xhci_hcd_cleanup);