oxu210hp-hcd.c 99 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984
  1. /*
  2. * Copyright (c) 2008 Rodolfo Giometti <giometti@linux.it>
  3. * Copyright (c) 2008 Eurotech S.p.A. <info@eurtech.it>
  4. *
  5. * This code is *strongly* based on EHCI-HCD code by David Brownell since
  6. * the chip is a quasi-EHCI compatible.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/dmapool.h>
  25. #include <linux/kernel.h>
  26. #include <linux/delay.h>
  27. #include <linux/ioport.h>
  28. #include <linux/sched.h>
  29. #include <linux/slab.h>
  30. #include <linux/errno.h>
  31. #include <linux/init.h>
  32. #include <linux/timer.h>
  33. #include <linux/list.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/usb.h>
  36. #include <linux/moduleparam.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/io.h>
  39. #include "../core/hcd.h"
  40. #include <asm/irq.h>
  41. #include <asm/system.h>
  42. #include <asm/unaligned.h>
  43. #include <linux/irq.h>
  44. #include <linux/platform_device.h>
  45. #include "oxu210hp.h"
  46. #define DRIVER_VERSION "0.0.50"
  47. /*
  48. * Main defines
  49. */
  50. #define oxu_dbg(oxu, fmt, args...) \
  51. dev_dbg(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
  52. #define oxu_err(oxu, fmt, args...) \
  53. dev_err(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
  54. #define oxu_info(oxu, fmt, args...) \
  55. dev_info(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
  56. static inline struct usb_hcd *oxu_to_hcd(struct oxu_hcd *oxu)
  57. {
  58. return container_of((void *) oxu, struct usb_hcd, hcd_priv);
  59. }
  60. static inline struct oxu_hcd *hcd_to_oxu(struct usb_hcd *hcd)
  61. {
  62. return (struct oxu_hcd *) (hcd->hcd_priv);
  63. }
  64. /*
  65. * Debug stuff
  66. */
  67. #undef OXU_URB_TRACE
  68. #undef OXU_VERBOSE_DEBUG
  69. #ifdef OXU_VERBOSE_DEBUG
  70. #define oxu_vdbg oxu_dbg
  71. #else
  72. #define oxu_vdbg(oxu, fmt, args...) /* Nop */
  73. #endif
  74. #ifdef DEBUG
  75. static int __attribute__((__unused__))
  76. dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
  77. {
  78. return scnprintf(buf, len, "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s",
  79. label, label[0] ? " " : "", status,
  80. (status & STS_ASS) ? " Async" : "",
  81. (status & STS_PSS) ? " Periodic" : "",
  82. (status & STS_RECL) ? " Recl" : "",
  83. (status & STS_HALT) ? " Halt" : "",
  84. (status & STS_IAA) ? " IAA" : "",
  85. (status & STS_FATAL) ? " FATAL" : "",
  86. (status & STS_FLR) ? " FLR" : "",
  87. (status & STS_PCD) ? " PCD" : "",
  88. (status & STS_ERR) ? " ERR" : "",
  89. (status & STS_INT) ? " INT" : ""
  90. );
  91. }
  92. static int __attribute__((__unused__))
  93. dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
  94. {
  95. return scnprintf(buf, len, "%s%sintrenable %02x%s%s%s%s%s%s",
  96. label, label[0] ? " " : "", enable,
  97. (enable & STS_IAA) ? " IAA" : "",
  98. (enable & STS_FATAL) ? " FATAL" : "",
  99. (enable & STS_FLR) ? " FLR" : "",
  100. (enable & STS_PCD) ? " PCD" : "",
  101. (enable & STS_ERR) ? " ERR" : "",
  102. (enable & STS_INT) ? " INT" : ""
  103. );
  104. }
  105. static const char *const fls_strings[] =
  106. { "1024", "512", "256", "??" };
  107. static int dbg_command_buf(char *buf, unsigned len,
  108. const char *label, u32 command)
  109. {
  110. return scnprintf(buf, len,
  111. "%s%scommand %06x %s=%d ithresh=%d%s%s%s%s period=%s%s %s",
  112. label, label[0] ? " " : "", command,
  113. (command & CMD_PARK) ? "park" : "(park)",
  114. CMD_PARK_CNT(command),
  115. (command >> 16) & 0x3f,
  116. (command & CMD_LRESET) ? " LReset" : "",
  117. (command & CMD_IAAD) ? " IAAD" : "",
  118. (command & CMD_ASE) ? " Async" : "",
  119. (command & CMD_PSE) ? " Periodic" : "",
  120. fls_strings[(command >> 2) & 0x3],
  121. (command & CMD_RESET) ? " Reset" : "",
  122. (command & CMD_RUN) ? "RUN" : "HALT"
  123. );
  124. }
  125. static int dbg_port_buf(char *buf, unsigned len, const char *label,
  126. int port, u32 status)
  127. {
  128. char *sig;
  129. /* signaling state */
  130. switch (status & (3 << 10)) {
  131. case 0 << 10:
  132. sig = "se0";
  133. break;
  134. case 1 << 10:
  135. sig = "k"; /* low speed */
  136. break;
  137. case 2 << 10:
  138. sig = "j";
  139. break;
  140. default:
  141. sig = "?";
  142. break;
  143. }
  144. return scnprintf(buf, len,
  145. "%s%sport %d status %06x%s%s sig=%s%s%s%s%s%s%s%s%s%s",
  146. label, label[0] ? " " : "", port, status,
  147. (status & PORT_POWER) ? " POWER" : "",
  148. (status & PORT_OWNER) ? " OWNER" : "",
  149. sig,
  150. (status & PORT_RESET) ? " RESET" : "",
  151. (status & PORT_SUSPEND) ? " SUSPEND" : "",
  152. (status & PORT_RESUME) ? " RESUME" : "",
  153. (status & PORT_OCC) ? " OCC" : "",
  154. (status & PORT_OC) ? " OC" : "",
  155. (status & PORT_PEC) ? " PEC" : "",
  156. (status & PORT_PE) ? " PE" : "",
  157. (status & PORT_CSC) ? " CSC" : "",
  158. (status & PORT_CONNECT) ? " CONNECT" : ""
  159. );
  160. }
  161. #else
  162. static inline int __attribute__((__unused__))
  163. dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
  164. { return 0; }
  165. static inline int __attribute__((__unused__))
  166. dbg_command_buf(char *buf, unsigned len, const char *label, u32 command)
  167. { return 0; }
  168. static inline int __attribute__((__unused__))
  169. dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
  170. { return 0; }
  171. static inline int __attribute__((__unused__))
  172. dbg_port_buf(char *buf, unsigned len, const char *label, int port, u32 status)
  173. { return 0; }
  174. #endif /* DEBUG */
  175. /* functions have the "wrong" filename when they're output... */
  176. #define dbg_status(oxu, label, status) { \
  177. char _buf[80]; \
  178. dbg_status_buf(_buf, sizeof _buf, label, status); \
  179. oxu_dbg(oxu, "%s\n", _buf); \
  180. }
  181. #define dbg_cmd(oxu, label, command) { \
  182. char _buf[80]; \
  183. dbg_command_buf(_buf, sizeof _buf, label, command); \
  184. oxu_dbg(oxu, "%s\n", _buf); \
  185. }
  186. #define dbg_port(oxu, label, port, status) { \
  187. char _buf[80]; \
  188. dbg_port_buf(_buf, sizeof _buf, label, port, status); \
  189. oxu_dbg(oxu, "%s\n", _buf); \
  190. }
  191. /*
  192. * Module parameters
  193. */
  194. /* Initial IRQ latency: faster than hw default */
  195. static int log2_irq_thresh; /* 0 to 6 */
  196. module_param(log2_irq_thresh, int, S_IRUGO);
  197. MODULE_PARM_DESC(log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
  198. /* Initial park setting: slower than hw default */
  199. static unsigned park;
  200. module_param(park, uint, S_IRUGO);
  201. MODULE_PARM_DESC(park, "park setting; 1-3 back-to-back async packets");
  202. /* For flakey hardware, ignore overcurrent indicators */
  203. static int ignore_oc;
  204. module_param(ignore_oc, bool, S_IRUGO);
  205. MODULE_PARM_DESC(ignore_oc, "ignore bogus hardware overcurrent indications");
  206. static void ehci_work(struct oxu_hcd *oxu);
  207. static int oxu_hub_control(struct usb_hcd *hcd,
  208. u16 typeReq, u16 wValue, u16 wIndex,
  209. char *buf, u16 wLength);
  210. /*
  211. * Local functions
  212. */
  213. /* Low level read/write registers functions */
  214. static inline u32 oxu_readl(void *base, u32 reg)
  215. {
  216. return readl(base + reg);
  217. }
  218. static inline void oxu_writel(void *base, u32 reg, u32 val)
  219. {
  220. writel(val, base + reg);
  221. }
  222. static inline void timer_action_done(struct oxu_hcd *oxu,
  223. enum ehci_timer_action action)
  224. {
  225. clear_bit(action, &oxu->actions);
  226. }
  227. static inline void timer_action(struct oxu_hcd *oxu,
  228. enum ehci_timer_action action)
  229. {
  230. if (!test_and_set_bit(action, &oxu->actions)) {
  231. unsigned long t;
  232. switch (action) {
  233. case TIMER_IAA_WATCHDOG:
  234. t = EHCI_IAA_JIFFIES;
  235. break;
  236. case TIMER_IO_WATCHDOG:
  237. t = EHCI_IO_JIFFIES;
  238. break;
  239. case TIMER_ASYNC_OFF:
  240. t = EHCI_ASYNC_JIFFIES;
  241. break;
  242. case TIMER_ASYNC_SHRINK:
  243. default:
  244. t = EHCI_SHRINK_JIFFIES;
  245. break;
  246. }
  247. t += jiffies;
  248. /* all timings except IAA watchdog can be overridden.
  249. * async queue SHRINK often precedes IAA. while it's ready
  250. * to go OFF neither can matter, and afterwards the IO
  251. * watchdog stops unless there's still periodic traffic.
  252. */
  253. if (action != TIMER_IAA_WATCHDOG
  254. && t > oxu->watchdog.expires
  255. && timer_pending(&oxu->watchdog))
  256. return;
  257. mod_timer(&oxu->watchdog, t);
  258. }
  259. }
  260. /*
  261. * handshake - spin reading hc until handshake completes or fails
  262. * @ptr: address of hc register to be read
  263. * @mask: bits to look at in result of read
  264. * @done: value of those bits when handshake succeeds
  265. * @usec: timeout in microseconds
  266. *
  267. * Returns negative errno, or zero on success
  268. *
  269. * Success happens when the "mask" bits have the specified value (hardware
  270. * handshake done). There are two failure modes: "usec" have passed (major
  271. * hardware flakeout), or the register reads as all-ones (hardware removed).
  272. *
  273. * That last failure should_only happen in cases like physical cardbus eject
  274. * before driver shutdown. But it also seems to be caused by bugs in cardbus
  275. * bridge shutdown: shutting down the bridge before the devices using it.
  276. */
  277. static int handshake(struct oxu_hcd *oxu, void __iomem *ptr,
  278. u32 mask, u32 done, int usec)
  279. {
  280. u32 result;
  281. do {
  282. result = readl(ptr);
  283. if (result == ~(u32)0) /* card removed */
  284. return -ENODEV;
  285. result &= mask;
  286. if (result == done)
  287. return 0;
  288. udelay(1);
  289. usec--;
  290. } while (usec > 0);
  291. return -ETIMEDOUT;
  292. }
  293. /* Force HC to halt state from unknown (EHCI spec section 2.3) */
  294. static int ehci_halt(struct oxu_hcd *oxu)
  295. {
  296. u32 temp = readl(&oxu->regs->status);
  297. /* disable any irqs left enabled by previous code */
  298. writel(0, &oxu->regs->intr_enable);
  299. if ((temp & STS_HALT) != 0)
  300. return 0;
  301. temp = readl(&oxu->regs->command);
  302. temp &= ~CMD_RUN;
  303. writel(temp, &oxu->regs->command);
  304. return handshake(oxu, &oxu->regs->status,
  305. STS_HALT, STS_HALT, 16 * 125);
  306. }
  307. /* Put TDI/ARC silicon into EHCI mode */
  308. static void tdi_reset(struct oxu_hcd *oxu)
  309. {
  310. u32 __iomem *reg_ptr;
  311. u32 tmp;
  312. reg_ptr = (u32 __iomem *)(((u8 __iomem *)oxu->regs) + 0x68);
  313. tmp = readl(reg_ptr);
  314. tmp |= 0x3;
  315. writel(tmp, reg_ptr);
  316. }
  317. /* Reset a non-running (STS_HALT == 1) controller */
  318. static int ehci_reset(struct oxu_hcd *oxu)
  319. {
  320. int retval;
  321. u32 command = readl(&oxu->regs->command);
  322. command |= CMD_RESET;
  323. dbg_cmd(oxu, "reset", command);
  324. writel(command, &oxu->regs->command);
  325. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  326. oxu->next_statechange = jiffies;
  327. retval = handshake(oxu, &oxu->regs->command,
  328. CMD_RESET, 0, 250 * 1000);
  329. if (retval)
  330. return retval;
  331. tdi_reset(oxu);
  332. return retval;
  333. }
  334. /* Idle the controller (from running) */
  335. static void ehci_quiesce(struct oxu_hcd *oxu)
  336. {
  337. u32 temp;
  338. #ifdef DEBUG
  339. if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
  340. BUG();
  341. #endif
  342. /* wait for any schedule enables/disables to take effect */
  343. temp = readl(&oxu->regs->command) << 10;
  344. temp &= STS_ASS | STS_PSS;
  345. if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS,
  346. temp, 16 * 125) != 0) {
  347. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  348. return;
  349. }
  350. /* then disable anything that's still active */
  351. temp = readl(&oxu->regs->command);
  352. temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
  353. writel(temp, &oxu->regs->command);
  354. /* hardware can take 16 microframes to turn off ... */
  355. if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS,
  356. 0, 16 * 125) != 0) {
  357. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  358. return;
  359. }
  360. }
  361. static int check_reset_complete(struct oxu_hcd *oxu, int index,
  362. u32 __iomem *status_reg, int port_status)
  363. {
  364. if (!(port_status & PORT_CONNECT)) {
  365. oxu->reset_done[index] = 0;
  366. return port_status;
  367. }
  368. /* if reset finished and it's still not enabled -- handoff */
  369. if (!(port_status & PORT_PE)) {
  370. oxu_dbg(oxu, "Failed to enable port %d on root hub TT\n",
  371. index+1);
  372. return port_status;
  373. } else
  374. oxu_dbg(oxu, "port %d high speed\n", index + 1);
  375. return port_status;
  376. }
  377. static void ehci_hub_descriptor(struct oxu_hcd *oxu,
  378. struct usb_hub_descriptor *desc)
  379. {
  380. int ports = HCS_N_PORTS(oxu->hcs_params);
  381. u16 temp;
  382. desc->bDescriptorType = 0x29;
  383. desc->bPwrOn2PwrGood = 10; /* oxu 1.0, 2.3.9 says 20ms max */
  384. desc->bHubContrCurrent = 0;
  385. desc->bNbrPorts = ports;
  386. temp = 1 + (ports / 8);
  387. desc->bDescLength = 7 + 2 * temp;
  388. /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
  389. memset(&desc->bitmap[0], 0, temp);
  390. memset(&desc->bitmap[temp], 0xff, temp);
  391. temp = 0x0008; /* per-port overcurrent reporting */
  392. if (HCS_PPC(oxu->hcs_params))
  393. temp |= 0x0001; /* per-port power control */
  394. else
  395. temp |= 0x0002; /* no power switching */
  396. desc->wHubCharacteristics = (__force __u16)cpu_to_le16(temp);
  397. }
  398. /* Allocate an OXU210HP on-chip memory data buffer
  399. *
  400. * An on-chip memory data buffer is required for each OXU210HP USB transfer.
  401. * Each transfer descriptor has one or more on-chip memory data buffers.
  402. *
  403. * Data buffers are allocated from a fix sized pool of data blocks.
  404. * To minimise fragmentation and give reasonable memory utlisation,
  405. * data buffers are allocated with sizes the power of 2 multiples of
  406. * the block size, starting on an address a multiple of the allocated size.
  407. *
  408. * FIXME: callers of this function require a buffer to be allocated for
  409. * len=0. This is a waste of on-chip memory and should be fix. Then this
  410. * function should be changed to not allocate a buffer for len=0.
  411. */
  412. static int oxu_buf_alloc(struct oxu_hcd *oxu, struct ehci_qtd *qtd, int len)
  413. {
  414. int n_blocks; /* minium blocks needed to hold len */
  415. int a_blocks; /* blocks allocated */
  416. int i, j;
  417. /* Don't allocte bigger than supported */
  418. if (len > BUFFER_SIZE * BUFFER_NUM) {
  419. oxu_err(oxu, "buffer too big (%d)\n", len);
  420. return -ENOMEM;
  421. }
  422. spin_lock(&oxu->mem_lock);
  423. /* Number of blocks needed to hold len */
  424. n_blocks = (len + BUFFER_SIZE - 1) / BUFFER_SIZE;
  425. /* Round the number of blocks up to the power of 2 */
  426. for (a_blocks = 1; a_blocks < n_blocks; a_blocks <<= 1)
  427. ;
  428. /* Find a suitable available data buffer */
  429. for (i = 0; i < BUFFER_NUM;
  430. i += max(a_blocks, (int)oxu->db_used[i])) {
  431. /* Check all the required blocks are available */
  432. for (j = 0; j < a_blocks; j++)
  433. if (oxu->db_used[i + j])
  434. break;
  435. if (j != a_blocks)
  436. continue;
  437. /* Allocate blocks found! */
  438. qtd->buffer = (void *) &oxu->mem->db_pool[i];
  439. qtd->buffer_dma = virt_to_phys(qtd->buffer);
  440. qtd->qtd_buffer_len = BUFFER_SIZE * a_blocks;
  441. oxu->db_used[i] = a_blocks;
  442. spin_unlock(&oxu->mem_lock);
  443. return 0;
  444. }
  445. /* Failed */
  446. spin_unlock(&oxu->mem_lock);
  447. return -ENOMEM;
  448. }
  449. static void oxu_buf_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd)
  450. {
  451. int index;
  452. spin_lock(&oxu->mem_lock);
  453. index = (qtd->buffer - (void *) &oxu->mem->db_pool[0])
  454. / BUFFER_SIZE;
  455. oxu->db_used[index] = 0;
  456. qtd->qtd_buffer_len = 0;
  457. qtd->buffer_dma = 0;
  458. qtd->buffer = NULL;
  459. spin_unlock(&oxu->mem_lock);
  460. return;
  461. }
  462. static inline void ehci_qtd_init(struct ehci_qtd *qtd, dma_addr_t dma)
  463. {
  464. memset(qtd, 0, sizeof *qtd);
  465. qtd->qtd_dma = dma;
  466. qtd->hw_token = cpu_to_le32(QTD_STS_HALT);
  467. qtd->hw_next = EHCI_LIST_END;
  468. qtd->hw_alt_next = EHCI_LIST_END;
  469. INIT_LIST_HEAD(&qtd->qtd_list);
  470. }
  471. static inline void oxu_qtd_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd)
  472. {
  473. int index;
  474. if (qtd->buffer)
  475. oxu_buf_free(oxu, qtd);
  476. spin_lock(&oxu->mem_lock);
  477. index = qtd - &oxu->mem->qtd_pool[0];
  478. oxu->qtd_used[index] = 0;
  479. spin_unlock(&oxu->mem_lock);
  480. return;
  481. }
  482. static struct ehci_qtd *ehci_qtd_alloc(struct oxu_hcd *oxu)
  483. {
  484. int i;
  485. struct ehci_qtd *qtd = NULL;
  486. spin_lock(&oxu->mem_lock);
  487. for (i = 0; i < QTD_NUM; i++)
  488. if (!oxu->qtd_used[i])
  489. break;
  490. if (i < QTD_NUM) {
  491. qtd = (struct ehci_qtd *) &oxu->mem->qtd_pool[i];
  492. memset(qtd, 0, sizeof *qtd);
  493. qtd->hw_token = cpu_to_le32(QTD_STS_HALT);
  494. qtd->hw_next = EHCI_LIST_END;
  495. qtd->hw_alt_next = EHCI_LIST_END;
  496. INIT_LIST_HEAD(&qtd->qtd_list);
  497. qtd->qtd_dma = virt_to_phys(qtd);
  498. oxu->qtd_used[i] = 1;
  499. }
  500. spin_unlock(&oxu->mem_lock);
  501. return qtd;
  502. }
  503. static void oxu_qh_free(struct oxu_hcd *oxu, struct ehci_qh *qh)
  504. {
  505. int index;
  506. spin_lock(&oxu->mem_lock);
  507. index = qh - &oxu->mem->qh_pool[0];
  508. oxu->qh_used[index] = 0;
  509. spin_unlock(&oxu->mem_lock);
  510. return;
  511. }
  512. static void qh_destroy(struct kref *kref)
  513. {
  514. struct ehci_qh *qh = container_of(kref, struct ehci_qh, kref);
  515. struct oxu_hcd *oxu = qh->oxu;
  516. /* clean qtds first, and know this is not linked */
  517. if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) {
  518. oxu_dbg(oxu, "unused qh not empty!\n");
  519. BUG();
  520. }
  521. if (qh->dummy)
  522. oxu_qtd_free(oxu, qh->dummy);
  523. oxu_qh_free(oxu, qh);
  524. }
  525. static struct ehci_qh *oxu_qh_alloc(struct oxu_hcd *oxu)
  526. {
  527. int i;
  528. struct ehci_qh *qh = NULL;
  529. spin_lock(&oxu->mem_lock);
  530. for (i = 0; i < QHEAD_NUM; i++)
  531. if (!oxu->qh_used[i])
  532. break;
  533. if (i < QHEAD_NUM) {
  534. qh = (struct ehci_qh *) &oxu->mem->qh_pool[i];
  535. memset(qh, 0, sizeof *qh);
  536. kref_init(&qh->kref);
  537. qh->oxu = oxu;
  538. qh->qh_dma = virt_to_phys(qh);
  539. INIT_LIST_HEAD(&qh->qtd_list);
  540. /* dummy td enables safe urb queuing */
  541. qh->dummy = ehci_qtd_alloc(oxu);
  542. if (qh->dummy == NULL) {
  543. oxu_dbg(oxu, "no dummy td\n");
  544. oxu->qh_used[i] = 0;
  545. return NULL;
  546. }
  547. oxu->qh_used[i] = 1;
  548. }
  549. spin_unlock(&oxu->mem_lock);
  550. return qh;
  551. }
  552. /* to share a qh (cpu threads, or hc) */
  553. static inline struct ehci_qh *qh_get(struct ehci_qh *qh)
  554. {
  555. kref_get(&qh->kref);
  556. return qh;
  557. }
  558. static inline void qh_put(struct ehci_qh *qh)
  559. {
  560. kref_put(&qh->kref, qh_destroy);
  561. }
  562. static void oxu_murb_free(struct oxu_hcd *oxu, struct oxu_murb *murb)
  563. {
  564. int index;
  565. spin_lock(&oxu->mem_lock);
  566. index = murb - &oxu->murb_pool[0];
  567. oxu->murb_used[index] = 0;
  568. spin_unlock(&oxu->mem_lock);
  569. return;
  570. }
  571. static struct oxu_murb *oxu_murb_alloc(struct oxu_hcd *oxu)
  572. {
  573. int i;
  574. struct oxu_murb *murb = NULL;
  575. spin_lock(&oxu->mem_lock);
  576. for (i = 0; i < MURB_NUM; i++)
  577. if (!oxu->murb_used[i])
  578. break;
  579. if (i < MURB_NUM) {
  580. murb = &(oxu->murb_pool)[i];
  581. oxu->murb_used[i] = 1;
  582. }
  583. spin_unlock(&oxu->mem_lock);
  584. return murb;
  585. }
  586. /* The queue heads and transfer descriptors are managed from pools tied
  587. * to each of the "per device" structures.
  588. * This is the initialisation and cleanup code.
  589. */
  590. static void ehci_mem_cleanup(struct oxu_hcd *oxu)
  591. {
  592. kfree(oxu->murb_pool);
  593. oxu->murb_pool = NULL;
  594. if (oxu->async)
  595. qh_put(oxu->async);
  596. oxu->async = NULL;
  597. del_timer(&oxu->urb_timer);
  598. oxu->periodic = NULL;
  599. /* shadow periodic table */
  600. kfree(oxu->pshadow);
  601. oxu->pshadow = NULL;
  602. }
  603. /* Remember to add cleanup code (above) if you add anything here.
  604. */
  605. static int ehci_mem_init(struct oxu_hcd *oxu, gfp_t flags)
  606. {
  607. int i;
  608. for (i = 0; i < oxu->periodic_size; i++)
  609. oxu->mem->frame_list[i] = EHCI_LIST_END;
  610. for (i = 0; i < QHEAD_NUM; i++)
  611. oxu->qh_used[i] = 0;
  612. for (i = 0; i < QTD_NUM; i++)
  613. oxu->qtd_used[i] = 0;
  614. oxu->murb_pool = kcalloc(MURB_NUM, sizeof(struct oxu_murb), flags);
  615. if (!oxu->murb_pool)
  616. goto fail;
  617. for (i = 0; i < MURB_NUM; i++)
  618. oxu->murb_used[i] = 0;
  619. oxu->async = oxu_qh_alloc(oxu);
  620. if (!oxu->async)
  621. goto fail;
  622. oxu->periodic = (__le32 *) &oxu->mem->frame_list;
  623. oxu->periodic_dma = virt_to_phys(oxu->periodic);
  624. for (i = 0; i < oxu->periodic_size; i++)
  625. oxu->periodic[i] = EHCI_LIST_END;
  626. /* software shadow of hardware table */
  627. oxu->pshadow = kcalloc(oxu->periodic_size, sizeof(void *), flags);
  628. if (oxu->pshadow != NULL)
  629. return 0;
  630. fail:
  631. oxu_dbg(oxu, "couldn't init memory\n");
  632. ehci_mem_cleanup(oxu);
  633. return -ENOMEM;
  634. }
  635. /* Fill a qtd, returning how much of the buffer we were able to queue up.
  636. */
  637. static int qtd_fill(struct ehci_qtd *qtd, dma_addr_t buf, size_t len,
  638. int token, int maxpacket)
  639. {
  640. int i, count;
  641. u64 addr = buf;
  642. /* one buffer entry per 4K ... first might be short or unaligned */
  643. qtd->hw_buf[0] = cpu_to_le32((u32)addr);
  644. qtd->hw_buf_hi[0] = cpu_to_le32((u32)(addr >> 32));
  645. count = 0x1000 - (buf & 0x0fff); /* rest of that page */
  646. if (likely(len < count)) /* ... iff needed */
  647. count = len;
  648. else {
  649. buf += 0x1000;
  650. buf &= ~0x0fff;
  651. /* per-qtd limit: from 16K to 20K (best alignment) */
  652. for (i = 1; count < len && i < 5; i++) {
  653. addr = buf;
  654. qtd->hw_buf[i] = cpu_to_le32((u32)addr);
  655. qtd->hw_buf_hi[i] = cpu_to_le32((u32)(addr >> 32));
  656. buf += 0x1000;
  657. if ((count + 0x1000) < len)
  658. count += 0x1000;
  659. else
  660. count = len;
  661. }
  662. /* short packets may only terminate transfers */
  663. if (count != len)
  664. count -= (count % maxpacket);
  665. }
  666. qtd->hw_token = cpu_to_le32((count << 16) | token);
  667. qtd->length = count;
  668. return count;
  669. }
  670. static inline void qh_update(struct oxu_hcd *oxu,
  671. struct ehci_qh *qh, struct ehci_qtd *qtd)
  672. {
  673. /* writes to an active overlay are unsafe */
  674. BUG_ON(qh->qh_state != QH_STATE_IDLE);
  675. qh->hw_qtd_next = QTD_NEXT(qtd->qtd_dma);
  676. qh->hw_alt_next = EHCI_LIST_END;
  677. /* Except for control endpoints, we make hardware maintain data
  678. * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
  679. * and set the pseudo-toggle in udev. Only usb_clear_halt() will
  680. * ever clear it.
  681. */
  682. if (!(qh->hw_info1 & cpu_to_le32(1 << 14))) {
  683. unsigned is_out, epnum;
  684. is_out = !(qtd->hw_token & cpu_to_le32(1 << 8));
  685. epnum = (le32_to_cpup(&qh->hw_info1) >> 8) & 0x0f;
  686. if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) {
  687. qh->hw_token &= ~cpu_to_le32(QTD_TOGGLE);
  688. usb_settoggle(qh->dev, epnum, is_out, 1);
  689. }
  690. }
  691. /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */
  692. wmb();
  693. qh->hw_token &= cpu_to_le32(QTD_TOGGLE | QTD_STS_PING);
  694. }
  695. /* If it weren't for a common silicon quirk (writing the dummy into the qh
  696. * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
  697. * recovery (including urb dequeue) would need software changes to a QH...
  698. */
  699. static void qh_refresh(struct oxu_hcd *oxu, struct ehci_qh *qh)
  700. {
  701. struct ehci_qtd *qtd;
  702. if (list_empty(&qh->qtd_list))
  703. qtd = qh->dummy;
  704. else {
  705. qtd = list_entry(qh->qtd_list.next,
  706. struct ehci_qtd, qtd_list);
  707. /* first qtd may already be partially processed */
  708. if (cpu_to_le32(qtd->qtd_dma) == qh->hw_current)
  709. qtd = NULL;
  710. }
  711. if (qtd)
  712. qh_update(oxu, qh, qtd);
  713. }
  714. static void qtd_copy_status(struct oxu_hcd *oxu, struct urb *urb,
  715. size_t length, u32 token)
  716. {
  717. /* count IN/OUT bytes, not SETUP (even short packets) */
  718. if (likely(QTD_PID(token) != 2))
  719. urb->actual_length += length - QTD_LENGTH(token);
  720. /* don't modify error codes */
  721. if (unlikely(urb->status != -EINPROGRESS))
  722. return;
  723. /* force cleanup after short read; not always an error */
  724. if (unlikely(IS_SHORT_READ(token)))
  725. urb->status = -EREMOTEIO;
  726. /* serious "can't proceed" faults reported by the hardware */
  727. if (token & QTD_STS_HALT) {
  728. if (token & QTD_STS_BABBLE) {
  729. /* FIXME "must" disable babbling device's port too */
  730. urb->status = -EOVERFLOW;
  731. } else if (token & QTD_STS_MMF) {
  732. /* fs/ls interrupt xfer missed the complete-split */
  733. urb->status = -EPROTO;
  734. } else if (token & QTD_STS_DBE) {
  735. urb->status = (QTD_PID(token) == 1) /* IN ? */
  736. ? -ENOSR /* hc couldn't read data */
  737. : -ECOMM; /* hc couldn't write data */
  738. } else if (token & QTD_STS_XACT) {
  739. /* timeout, bad crc, wrong PID, etc; retried */
  740. if (QTD_CERR(token))
  741. urb->status = -EPIPE;
  742. else {
  743. oxu_dbg(oxu, "devpath %s ep%d%s 3strikes\n",
  744. urb->dev->devpath,
  745. usb_pipeendpoint(urb->pipe),
  746. usb_pipein(urb->pipe) ? "in" : "out");
  747. urb->status = -EPROTO;
  748. }
  749. /* CERR nonzero + no errors + halt --> stall */
  750. } else if (QTD_CERR(token))
  751. urb->status = -EPIPE;
  752. else /* unknown */
  753. urb->status = -EPROTO;
  754. oxu_vdbg(oxu, "dev%d ep%d%s qtd token %08x --> status %d\n",
  755. usb_pipedevice(urb->pipe),
  756. usb_pipeendpoint(urb->pipe),
  757. usb_pipein(urb->pipe) ? "in" : "out",
  758. token, urb->status);
  759. }
  760. }
  761. static void ehci_urb_done(struct oxu_hcd *oxu, struct urb *urb)
  762. __releases(oxu->lock)
  763. __acquires(oxu->lock)
  764. {
  765. if (likely(urb->hcpriv != NULL)) {
  766. struct ehci_qh *qh = (struct ehci_qh *) urb->hcpriv;
  767. /* S-mask in a QH means it's an interrupt urb */
  768. if ((qh->hw_info2 & cpu_to_le32(QH_SMASK)) != 0) {
  769. /* ... update hc-wide periodic stats (for usbfs) */
  770. oxu_to_hcd(oxu)->self.bandwidth_int_reqs--;
  771. }
  772. qh_put(qh);
  773. }
  774. urb->hcpriv = NULL;
  775. switch (urb->status) {
  776. case -EINPROGRESS: /* success */
  777. urb->status = 0;
  778. default: /* fault */
  779. break;
  780. case -EREMOTEIO: /* fault or normal */
  781. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  782. urb->status = 0;
  783. break;
  784. case -ECONNRESET: /* canceled */
  785. case -ENOENT:
  786. break;
  787. }
  788. #ifdef OXU_URB_TRACE
  789. oxu_dbg(oxu, "%s %s urb %p ep%d%s status %d len %d/%d\n",
  790. __func__, urb->dev->devpath, urb,
  791. usb_pipeendpoint(urb->pipe),
  792. usb_pipein(urb->pipe) ? "in" : "out",
  793. urb->status,
  794. urb->actual_length, urb->transfer_buffer_length);
  795. #endif
  796. /* complete() can reenter this HCD */
  797. spin_unlock(&oxu->lock);
  798. usb_hcd_giveback_urb(oxu_to_hcd(oxu), urb, urb->status);
  799. spin_lock(&oxu->lock);
  800. }
  801. static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh);
  802. static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh);
  803. static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh);
  804. static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh);
  805. #define HALT_BIT cpu_to_le32(QTD_STS_HALT)
  806. /* Process and free completed qtds for a qh, returning URBs to drivers.
  807. * Chases up to qh->hw_current. Returns number of completions called,
  808. * indicating how much "real" work we did.
  809. */
  810. static unsigned qh_completions(struct oxu_hcd *oxu, struct ehci_qh *qh)
  811. {
  812. struct ehci_qtd *last = NULL, *end = qh->dummy;
  813. struct list_head *entry, *tmp;
  814. int stopped;
  815. unsigned count = 0;
  816. int do_status = 0;
  817. u8 state;
  818. struct oxu_murb *murb = NULL;
  819. if (unlikely(list_empty(&qh->qtd_list)))
  820. return count;
  821. /* completions (or tasks on other cpus) must never clobber HALT
  822. * till we've gone through and cleaned everything up, even when
  823. * they add urbs to this qh's queue or mark them for unlinking.
  824. *
  825. * NOTE: unlinking expects to be done in queue order.
  826. */
  827. state = qh->qh_state;
  828. qh->qh_state = QH_STATE_COMPLETING;
  829. stopped = (state == QH_STATE_IDLE);
  830. /* remove de-activated QTDs from front of queue.
  831. * after faults (including short reads), cleanup this urb
  832. * then let the queue advance.
  833. * if queue is stopped, handles unlinks.
  834. */
  835. list_for_each_safe(entry, tmp, &qh->qtd_list) {
  836. struct ehci_qtd *qtd;
  837. struct urb *urb;
  838. u32 token = 0;
  839. qtd = list_entry(entry, struct ehci_qtd, qtd_list);
  840. urb = qtd->urb;
  841. /* Clean up any state from previous QTD ...*/
  842. if (last) {
  843. if (likely(last->urb != urb)) {
  844. if (last->urb->complete == NULL) {
  845. murb = (struct oxu_murb *) last->urb;
  846. last->urb = murb->main;
  847. if (murb->last) {
  848. ehci_urb_done(oxu, last->urb);
  849. count++;
  850. }
  851. oxu_murb_free(oxu, murb);
  852. } else {
  853. ehci_urb_done(oxu, last->urb);
  854. count++;
  855. }
  856. }
  857. oxu_qtd_free(oxu, last);
  858. last = NULL;
  859. }
  860. /* ignore urbs submitted during completions we reported */
  861. if (qtd == end)
  862. break;
  863. /* hardware copies qtd out of qh overlay */
  864. rmb();
  865. token = le32_to_cpu(qtd->hw_token);
  866. /* always clean up qtds the hc de-activated */
  867. if ((token & QTD_STS_ACTIVE) == 0) {
  868. if ((token & QTD_STS_HALT) != 0) {
  869. stopped = 1;
  870. /* magic dummy for some short reads; qh won't advance.
  871. * that silicon quirk can kick in with this dummy too.
  872. */
  873. } else if (IS_SHORT_READ(token) &&
  874. !(qtd->hw_alt_next & EHCI_LIST_END)) {
  875. stopped = 1;
  876. goto halt;
  877. }
  878. /* stop scanning when we reach qtds the hc is using */
  879. } else if (likely(!stopped &&
  880. HC_IS_RUNNING(oxu_to_hcd(oxu)->state))) {
  881. break;
  882. } else {
  883. stopped = 1;
  884. if (unlikely(!HC_IS_RUNNING(oxu_to_hcd(oxu)->state)))
  885. urb->status = -ESHUTDOWN;
  886. /* ignore active urbs unless some previous qtd
  887. * for the urb faulted (including short read) or
  888. * its urb was canceled. we may patch qh or qtds.
  889. */
  890. if (likely(urb->status == -EINPROGRESS))
  891. continue;
  892. /* issue status after short control reads */
  893. if (unlikely(do_status != 0)
  894. && QTD_PID(token) == 0 /* OUT */) {
  895. do_status = 0;
  896. continue;
  897. }
  898. /* token in overlay may be most current */
  899. if (state == QH_STATE_IDLE
  900. && cpu_to_le32(qtd->qtd_dma)
  901. == qh->hw_current)
  902. token = le32_to_cpu(qh->hw_token);
  903. /* force halt for unlinked or blocked qh, so we'll
  904. * patch the qh later and so that completions can't
  905. * activate it while we "know" it's stopped.
  906. */
  907. if ((HALT_BIT & qh->hw_token) == 0) {
  908. halt:
  909. qh->hw_token |= HALT_BIT;
  910. wmb();
  911. }
  912. }
  913. /* Remove it from the queue */
  914. qtd_copy_status(oxu, urb->complete ?
  915. urb : ((struct oxu_murb *) urb)->main,
  916. qtd->length, token);
  917. if ((usb_pipein(qtd->urb->pipe)) &&
  918. (NULL != qtd->transfer_buffer))
  919. memcpy(qtd->transfer_buffer, qtd->buffer, qtd->length);
  920. do_status = (urb->status == -EREMOTEIO)
  921. && usb_pipecontrol(urb->pipe);
  922. if (stopped && qtd->qtd_list.prev != &qh->qtd_list) {
  923. last = list_entry(qtd->qtd_list.prev,
  924. struct ehci_qtd, qtd_list);
  925. last->hw_next = qtd->hw_next;
  926. }
  927. list_del(&qtd->qtd_list);
  928. last = qtd;
  929. }
  930. /* last urb's completion might still need calling */
  931. if (likely(last != NULL)) {
  932. if (last->urb->complete == NULL) {
  933. murb = (struct oxu_murb *) last->urb;
  934. last->urb = murb->main;
  935. if (murb->last) {
  936. ehci_urb_done(oxu, last->urb);
  937. count++;
  938. }
  939. oxu_murb_free(oxu, murb);
  940. } else {
  941. ehci_urb_done(oxu, last->urb);
  942. count++;
  943. }
  944. oxu_qtd_free(oxu, last);
  945. }
  946. /* restore original state; caller must unlink or relink */
  947. qh->qh_state = state;
  948. /* be sure the hardware's done with the qh before refreshing
  949. * it after fault cleanup, or recovering from silicon wrongly
  950. * overlaying the dummy qtd (which reduces DMA chatter).
  951. */
  952. if (stopped != 0 || qh->hw_qtd_next == EHCI_LIST_END) {
  953. switch (state) {
  954. case QH_STATE_IDLE:
  955. qh_refresh(oxu, qh);
  956. break;
  957. case QH_STATE_LINKED:
  958. /* should be rare for periodic transfers,
  959. * except maybe high bandwidth ...
  960. */
  961. if ((cpu_to_le32(QH_SMASK)
  962. & qh->hw_info2) != 0) {
  963. intr_deschedule(oxu, qh);
  964. (void) qh_schedule(oxu, qh);
  965. } else
  966. unlink_async(oxu, qh);
  967. break;
  968. /* otherwise, unlink already started */
  969. }
  970. }
  971. return count;
  972. }
  973. /* High bandwidth multiplier, as encoded in highspeed endpoint descriptors */
  974. #define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
  975. /* ... and packet size, for any kind of endpoint descriptor */
  976. #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
  977. /* Reverse of qh_urb_transaction: free a list of TDs.
  978. * used for cleanup after errors, before HC sees an URB's TDs.
  979. */
  980. static void qtd_list_free(struct oxu_hcd *oxu,
  981. struct urb *urb, struct list_head *qtd_list)
  982. {
  983. struct list_head *entry, *temp;
  984. list_for_each_safe(entry, temp, qtd_list) {
  985. struct ehci_qtd *qtd;
  986. qtd = list_entry(entry, struct ehci_qtd, qtd_list);
  987. list_del(&qtd->qtd_list);
  988. oxu_qtd_free(oxu, qtd);
  989. }
  990. }
  991. /* Create a list of filled qtds for this URB; won't link into qh.
  992. */
  993. static struct list_head *qh_urb_transaction(struct oxu_hcd *oxu,
  994. struct urb *urb,
  995. struct list_head *head,
  996. gfp_t flags)
  997. {
  998. struct ehci_qtd *qtd, *qtd_prev;
  999. dma_addr_t buf;
  1000. int len, maxpacket;
  1001. int is_input;
  1002. u32 token;
  1003. void *transfer_buf = NULL;
  1004. int ret;
  1005. /*
  1006. * URBs map to sequences of QTDs: one logical transaction
  1007. */
  1008. qtd = ehci_qtd_alloc(oxu);
  1009. if (unlikely(!qtd))
  1010. return NULL;
  1011. list_add_tail(&qtd->qtd_list, head);
  1012. qtd->urb = urb;
  1013. token = QTD_STS_ACTIVE;
  1014. token |= (EHCI_TUNE_CERR << 10);
  1015. /* for split transactions, SplitXState initialized to zero */
  1016. len = urb->transfer_buffer_length;
  1017. is_input = usb_pipein(urb->pipe);
  1018. if (!urb->transfer_buffer && urb->transfer_buffer_length && is_input)
  1019. urb->transfer_buffer = phys_to_virt(urb->transfer_dma);
  1020. if (usb_pipecontrol(urb->pipe)) {
  1021. /* SETUP pid */
  1022. ret = oxu_buf_alloc(oxu, qtd, sizeof(struct usb_ctrlrequest));
  1023. if (ret)
  1024. goto cleanup;
  1025. qtd_fill(qtd, qtd->buffer_dma, sizeof(struct usb_ctrlrequest),
  1026. token | (2 /* "setup" */ << 8), 8);
  1027. memcpy(qtd->buffer, qtd->urb->setup_packet,
  1028. sizeof(struct usb_ctrlrequest));
  1029. /* ... and always at least one more pid */
  1030. token ^= QTD_TOGGLE;
  1031. qtd_prev = qtd;
  1032. qtd = ehci_qtd_alloc(oxu);
  1033. if (unlikely(!qtd))
  1034. goto cleanup;
  1035. qtd->urb = urb;
  1036. qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
  1037. list_add_tail(&qtd->qtd_list, head);
  1038. /* for zero length DATA stages, STATUS is always IN */
  1039. if (len == 0)
  1040. token |= (1 /* "in" */ << 8);
  1041. }
  1042. /*
  1043. * Data transfer stage: buffer setup
  1044. */
  1045. ret = oxu_buf_alloc(oxu, qtd, len);
  1046. if (ret)
  1047. goto cleanup;
  1048. buf = qtd->buffer_dma;
  1049. transfer_buf = urb->transfer_buffer;
  1050. if (!is_input)
  1051. memcpy(qtd->buffer, qtd->urb->transfer_buffer, len);
  1052. if (is_input)
  1053. token |= (1 /* "in" */ << 8);
  1054. /* else it's already initted to "out" pid (0 << 8) */
  1055. maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
  1056. /*
  1057. * buffer gets wrapped in one or more qtds;
  1058. * last one may be "short" (including zero len)
  1059. * and may serve as a control status ack
  1060. */
  1061. for (;;) {
  1062. int this_qtd_len;
  1063. this_qtd_len = qtd_fill(qtd, buf, len, token, maxpacket);
  1064. qtd->transfer_buffer = transfer_buf;
  1065. len -= this_qtd_len;
  1066. buf += this_qtd_len;
  1067. transfer_buf += this_qtd_len;
  1068. if (is_input)
  1069. qtd->hw_alt_next = oxu->async->hw_alt_next;
  1070. /* qh makes control packets use qtd toggle; maybe switch it */
  1071. if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
  1072. token ^= QTD_TOGGLE;
  1073. if (likely(len <= 0))
  1074. break;
  1075. qtd_prev = qtd;
  1076. qtd = ehci_qtd_alloc(oxu);
  1077. if (unlikely(!qtd))
  1078. goto cleanup;
  1079. if (likely(len > 0)) {
  1080. ret = oxu_buf_alloc(oxu, qtd, len);
  1081. if (ret)
  1082. goto cleanup;
  1083. }
  1084. qtd->urb = urb;
  1085. qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
  1086. list_add_tail(&qtd->qtd_list, head);
  1087. }
  1088. /* unless the bulk/interrupt caller wants a chance to clean
  1089. * up after short reads, hc should advance qh past this urb
  1090. */
  1091. if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0
  1092. || usb_pipecontrol(urb->pipe)))
  1093. qtd->hw_alt_next = EHCI_LIST_END;
  1094. /*
  1095. * control requests may need a terminating data "status" ack;
  1096. * bulk ones may need a terminating short packet (zero length).
  1097. */
  1098. if (likely(urb->transfer_buffer_length != 0)) {
  1099. int one_more = 0;
  1100. if (usb_pipecontrol(urb->pipe)) {
  1101. one_more = 1;
  1102. token ^= 0x0100; /* "in" <--> "out" */
  1103. token |= QTD_TOGGLE; /* force DATA1 */
  1104. } else if (usb_pipebulk(urb->pipe)
  1105. && (urb->transfer_flags & URB_ZERO_PACKET)
  1106. && !(urb->transfer_buffer_length % maxpacket)) {
  1107. one_more = 1;
  1108. }
  1109. if (one_more) {
  1110. qtd_prev = qtd;
  1111. qtd = ehci_qtd_alloc(oxu);
  1112. if (unlikely(!qtd))
  1113. goto cleanup;
  1114. qtd->urb = urb;
  1115. qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
  1116. list_add_tail(&qtd->qtd_list, head);
  1117. /* never any data in such packets */
  1118. qtd_fill(qtd, 0, 0, token, 0);
  1119. }
  1120. }
  1121. /* by default, enable interrupt on urb completion */
  1122. qtd->hw_token |= cpu_to_le32(QTD_IOC);
  1123. return head;
  1124. cleanup:
  1125. qtd_list_free(oxu, urb, head);
  1126. return NULL;
  1127. }
  1128. /* Each QH holds a qtd list; a QH is used for everything except iso.
  1129. *
  1130. * For interrupt urbs, the scheduler must set the microframe scheduling
  1131. * mask(s) each time the QH gets scheduled. For highspeed, that's
  1132. * just one microframe in the s-mask. For split interrupt transactions
  1133. * there are additional complications: c-mask, maybe FSTNs.
  1134. */
  1135. static struct ehci_qh *qh_make(struct oxu_hcd *oxu,
  1136. struct urb *urb, gfp_t flags)
  1137. {
  1138. struct ehci_qh *qh = oxu_qh_alloc(oxu);
  1139. u32 info1 = 0, info2 = 0;
  1140. int is_input, type;
  1141. int maxp = 0;
  1142. if (!qh)
  1143. return qh;
  1144. /*
  1145. * init endpoint/device data for this QH
  1146. */
  1147. info1 |= usb_pipeendpoint(urb->pipe) << 8;
  1148. info1 |= usb_pipedevice(urb->pipe) << 0;
  1149. is_input = usb_pipein(urb->pipe);
  1150. type = usb_pipetype(urb->pipe);
  1151. maxp = usb_maxpacket(urb->dev, urb->pipe, !is_input);
  1152. /* Compute interrupt scheduling parameters just once, and save.
  1153. * - allowing for high bandwidth, how many nsec/uframe are used?
  1154. * - split transactions need a second CSPLIT uframe; same question
  1155. * - splits also need a schedule gap (for full/low speed I/O)
  1156. * - qh has a polling interval
  1157. *
  1158. * For control/bulk requests, the HC or TT handles these.
  1159. */
  1160. if (type == PIPE_INTERRUPT) {
  1161. qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH,
  1162. is_input, 0,
  1163. hb_mult(maxp) * max_packet(maxp)));
  1164. qh->start = NO_FRAME;
  1165. if (urb->dev->speed == USB_SPEED_HIGH) {
  1166. qh->c_usecs = 0;
  1167. qh->gap_uf = 0;
  1168. qh->period = urb->interval >> 3;
  1169. if (qh->period == 0 && urb->interval != 1) {
  1170. /* NOTE interval 2 or 4 uframes could work.
  1171. * But interval 1 scheduling is simpler, and
  1172. * includes high bandwidth.
  1173. */
  1174. dbg("intr period %d uframes, NYET!",
  1175. urb->interval);
  1176. goto done;
  1177. }
  1178. } else {
  1179. struct usb_tt *tt = urb->dev->tt;
  1180. int think_time;
  1181. /* gap is f(FS/LS transfer times) */
  1182. qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed,
  1183. is_input, 0, maxp) / (125 * 1000);
  1184. /* FIXME this just approximates SPLIT/CSPLIT times */
  1185. if (is_input) { /* SPLIT, gap, CSPLIT+DATA */
  1186. qh->c_usecs = qh->usecs + HS_USECS(0);
  1187. qh->usecs = HS_USECS(1);
  1188. } else { /* SPLIT+DATA, gap, CSPLIT */
  1189. qh->usecs += HS_USECS(1);
  1190. qh->c_usecs = HS_USECS(0);
  1191. }
  1192. think_time = tt ? tt->think_time : 0;
  1193. qh->tt_usecs = NS_TO_US(think_time +
  1194. usb_calc_bus_time(urb->dev->speed,
  1195. is_input, 0, max_packet(maxp)));
  1196. qh->period = urb->interval;
  1197. }
  1198. }
  1199. /* support for tt scheduling, and access to toggles */
  1200. qh->dev = urb->dev;
  1201. /* using TT? */
  1202. switch (urb->dev->speed) {
  1203. case USB_SPEED_LOW:
  1204. info1 |= (1 << 12); /* EPS "low" */
  1205. /* FALL THROUGH */
  1206. case USB_SPEED_FULL:
  1207. /* EPS 0 means "full" */
  1208. if (type != PIPE_INTERRUPT)
  1209. info1 |= (EHCI_TUNE_RL_TT << 28);
  1210. if (type == PIPE_CONTROL) {
  1211. info1 |= (1 << 27); /* for TT */
  1212. info1 |= 1 << 14; /* toggle from qtd */
  1213. }
  1214. info1 |= maxp << 16;
  1215. info2 |= (EHCI_TUNE_MULT_TT << 30);
  1216. info2 |= urb->dev->ttport << 23;
  1217. /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */
  1218. break;
  1219. case USB_SPEED_HIGH: /* no TT involved */
  1220. info1 |= (2 << 12); /* EPS "high" */
  1221. if (type == PIPE_CONTROL) {
  1222. info1 |= (EHCI_TUNE_RL_HS << 28);
  1223. info1 |= 64 << 16; /* usb2 fixed maxpacket */
  1224. info1 |= 1 << 14; /* toggle from qtd */
  1225. info2 |= (EHCI_TUNE_MULT_HS << 30);
  1226. } else if (type == PIPE_BULK) {
  1227. info1 |= (EHCI_TUNE_RL_HS << 28);
  1228. info1 |= 512 << 16; /* usb2 fixed maxpacket */
  1229. info2 |= (EHCI_TUNE_MULT_HS << 30);
  1230. } else { /* PIPE_INTERRUPT */
  1231. info1 |= max_packet(maxp) << 16;
  1232. info2 |= hb_mult(maxp) << 30;
  1233. }
  1234. break;
  1235. default:
  1236. dbg("bogus dev %p speed %d", urb->dev, urb->dev->speed);
  1237. done:
  1238. qh_put(qh);
  1239. return NULL;
  1240. }
  1241. /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */
  1242. /* init as live, toggle clear, advance to dummy */
  1243. qh->qh_state = QH_STATE_IDLE;
  1244. qh->hw_info1 = cpu_to_le32(info1);
  1245. qh->hw_info2 = cpu_to_le32(info2);
  1246. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1);
  1247. qh_refresh(oxu, qh);
  1248. return qh;
  1249. }
  1250. /* Move qh (and its qtds) onto async queue; maybe enable queue.
  1251. */
  1252. static void qh_link_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1253. {
  1254. __le32 dma = QH_NEXT(qh->qh_dma);
  1255. struct ehci_qh *head;
  1256. /* (re)start the async schedule? */
  1257. head = oxu->async;
  1258. timer_action_done(oxu, TIMER_ASYNC_OFF);
  1259. if (!head->qh_next.qh) {
  1260. u32 cmd = readl(&oxu->regs->command);
  1261. if (!(cmd & CMD_ASE)) {
  1262. /* in case a clear of CMD_ASE didn't take yet */
  1263. (void)handshake(oxu, &oxu->regs->status,
  1264. STS_ASS, 0, 150);
  1265. cmd |= CMD_ASE | CMD_RUN;
  1266. writel(cmd, &oxu->regs->command);
  1267. oxu_to_hcd(oxu)->state = HC_STATE_RUNNING;
  1268. /* posted write need not be known to HC yet ... */
  1269. }
  1270. }
  1271. /* clear halt and/or toggle; and maybe recover from silicon quirk */
  1272. if (qh->qh_state == QH_STATE_IDLE)
  1273. qh_refresh(oxu, qh);
  1274. /* splice right after start */
  1275. qh->qh_next = head->qh_next;
  1276. qh->hw_next = head->hw_next;
  1277. wmb();
  1278. head->qh_next.qh = qh;
  1279. head->hw_next = dma;
  1280. qh->qh_state = QH_STATE_LINKED;
  1281. /* qtd completions reported later by interrupt */
  1282. }
  1283. #define QH_ADDR_MASK cpu_to_le32(0x7f)
  1284. /*
  1285. * For control/bulk/interrupt, return QH with these TDs appended.
  1286. * Allocates and initializes the QH if necessary.
  1287. * Returns null if it can't allocate a QH it needs to.
  1288. * If the QH has TDs (urbs) already, that's great.
  1289. */
  1290. static struct ehci_qh *qh_append_tds(struct oxu_hcd *oxu,
  1291. struct urb *urb, struct list_head *qtd_list,
  1292. int epnum, void **ptr)
  1293. {
  1294. struct ehci_qh *qh = NULL;
  1295. qh = (struct ehci_qh *) *ptr;
  1296. if (unlikely(qh == NULL)) {
  1297. /* can't sleep here, we have oxu->lock... */
  1298. qh = qh_make(oxu, urb, GFP_ATOMIC);
  1299. *ptr = qh;
  1300. }
  1301. if (likely(qh != NULL)) {
  1302. struct ehci_qtd *qtd;
  1303. if (unlikely(list_empty(qtd_list)))
  1304. qtd = NULL;
  1305. else
  1306. qtd = list_entry(qtd_list->next, struct ehci_qtd,
  1307. qtd_list);
  1308. /* control qh may need patching ... */
  1309. if (unlikely(epnum == 0)) {
  1310. /* usb_reset_device() briefly reverts to address 0 */
  1311. if (usb_pipedevice(urb->pipe) == 0)
  1312. qh->hw_info1 &= ~QH_ADDR_MASK;
  1313. }
  1314. /* just one way to queue requests: swap with the dummy qtd.
  1315. * only hc or qh_refresh() ever modify the overlay.
  1316. */
  1317. if (likely(qtd != NULL)) {
  1318. struct ehci_qtd *dummy;
  1319. dma_addr_t dma;
  1320. __le32 token;
  1321. /* to avoid racing the HC, use the dummy td instead of
  1322. * the first td of our list (becomes new dummy). both
  1323. * tds stay deactivated until we're done, when the
  1324. * HC is allowed to fetch the old dummy (4.10.2).
  1325. */
  1326. token = qtd->hw_token;
  1327. qtd->hw_token = HALT_BIT;
  1328. wmb();
  1329. dummy = qh->dummy;
  1330. dma = dummy->qtd_dma;
  1331. *dummy = *qtd;
  1332. dummy->qtd_dma = dma;
  1333. list_del(&qtd->qtd_list);
  1334. list_add(&dummy->qtd_list, qtd_list);
  1335. list_splice(qtd_list, qh->qtd_list.prev);
  1336. ehci_qtd_init(qtd, qtd->qtd_dma);
  1337. qh->dummy = qtd;
  1338. /* hc must see the new dummy at list end */
  1339. dma = qtd->qtd_dma;
  1340. qtd = list_entry(qh->qtd_list.prev,
  1341. struct ehci_qtd, qtd_list);
  1342. qtd->hw_next = QTD_NEXT(dma);
  1343. /* let the hc process these next qtds */
  1344. dummy->hw_token = (token & ~(0x80));
  1345. wmb();
  1346. dummy->hw_token = token;
  1347. urb->hcpriv = qh_get(qh);
  1348. }
  1349. }
  1350. return qh;
  1351. }
  1352. static int submit_async(struct oxu_hcd *oxu, struct urb *urb,
  1353. struct list_head *qtd_list, gfp_t mem_flags)
  1354. {
  1355. struct ehci_qtd *qtd;
  1356. int epnum;
  1357. unsigned long flags;
  1358. struct ehci_qh *qh = NULL;
  1359. int rc = 0;
  1360. qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list);
  1361. epnum = urb->ep->desc.bEndpointAddress;
  1362. #ifdef OXU_URB_TRACE
  1363. oxu_dbg(oxu, "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
  1364. __func__, urb->dev->devpath, urb,
  1365. epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out",
  1366. urb->transfer_buffer_length,
  1367. qtd, urb->ep->hcpriv);
  1368. #endif
  1369. spin_lock_irqsave(&oxu->lock, flags);
  1370. if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
  1371. &oxu_to_hcd(oxu)->flags))) {
  1372. rc = -ESHUTDOWN;
  1373. goto done;
  1374. }
  1375. qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv);
  1376. if (unlikely(qh == NULL)) {
  1377. rc = -ENOMEM;
  1378. goto done;
  1379. }
  1380. /* Control/bulk operations through TTs don't need scheduling,
  1381. * the HC and TT handle it when the TT has a buffer ready.
  1382. */
  1383. if (likely(qh->qh_state == QH_STATE_IDLE))
  1384. qh_link_async(oxu, qh_get(qh));
  1385. done:
  1386. spin_unlock_irqrestore(&oxu->lock, flags);
  1387. if (unlikely(qh == NULL))
  1388. qtd_list_free(oxu, urb, qtd_list);
  1389. return rc;
  1390. }
  1391. /* The async qh for the qtds being reclaimed are now unlinked from the HC */
  1392. static void end_unlink_async(struct oxu_hcd *oxu)
  1393. {
  1394. struct ehci_qh *qh = oxu->reclaim;
  1395. struct ehci_qh *next;
  1396. timer_action_done(oxu, TIMER_IAA_WATCHDOG);
  1397. qh->qh_state = QH_STATE_IDLE;
  1398. qh->qh_next.qh = NULL;
  1399. qh_put(qh); /* refcount from reclaim */
  1400. /* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */
  1401. next = qh->reclaim;
  1402. oxu->reclaim = next;
  1403. oxu->reclaim_ready = 0;
  1404. qh->reclaim = NULL;
  1405. qh_completions(oxu, qh);
  1406. if (!list_empty(&qh->qtd_list)
  1407. && HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
  1408. qh_link_async(oxu, qh);
  1409. else {
  1410. qh_put(qh); /* refcount from async list */
  1411. /* it's not free to turn the async schedule on/off; leave it
  1412. * active but idle for a while once it empties.
  1413. */
  1414. if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state)
  1415. && oxu->async->qh_next.qh == NULL)
  1416. timer_action(oxu, TIMER_ASYNC_OFF);
  1417. }
  1418. if (next) {
  1419. oxu->reclaim = NULL;
  1420. start_unlink_async(oxu, next);
  1421. }
  1422. }
  1423. /* makes sure the async qh will become idle */
  1424. /* caller must own oxu->lock */
  1425. static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1426. {
  1427. int cmd = readl(&oxu->regs->command);
  1428. struct ehci_qh *prev;
  1429. #ifdef DEBUG
  1430. assert_spin_locked(&oxu->lock);
  1431. if (oxu->reclaim || (qh->qh_state != QH_STATE_LINKED
  1432. && qh->qh_state != QH_STATE_UNLINK_WAIT))
  1433. BUG();
  1434. #endif
  1435. /* stop async schedule right now? */
  1436. if (unlikely(qh == oxu->async)) {
  1437. /* can't get here without STS_ASS set */
  1438. if (oxu_to_hcd(oxu)->state != HC_STATE_HALT
  1439. && !oxu->reclaim) {
  1440. /* ... and CMD_IAAD clear */
  1441. writel(cmd & ~CMD_ASE, &oxu->regs->command);
  1442. wmb();
  1443. /* handshake later, if we need to */
  1444. timer_action_done(oxu, TIMER_ASYNC_OFF);
  1445. }
  1446. return;
  1447. }
  1448. qh->qh_state = QH_STATE_UNLINK;
  1449. oxu->reclaim = qh = qh_get(qh);
  1450. prev = oxu->async;
  1451. while (prev->qh_next.qh != qh)
  1452. prev = prev->qh_next.qh;
  1453. prev->hw_next = qh->hw_next;
  1454. prev->qh_next = qh->qh_next;
  1455. wmb();
  1456. if (unlikely(oxu_to_hcd(oxu)->state == HC_STATE_HALT)) {
  1457. /* if (unlikely(qh->reclaim != 0))
  1458. * this will recurse, probably not much
  1459. */
  1460. end_unlink_async(oxu);
  1461. return;
  1462. }
  1463. oxu->reclaim_ready = 0;
  1464. cmd |= CMD_IAAD;
  1465. writel(cmd, &oxu->regs->command);
  1466. (void) readl(&oxu->regs->command);
  1467. timer_action(oxu, TIMER_IAA_WATCHDOG);
  1468. }
  1469. static void scan_async(struct oxu_hcd *oxu)
  1470. {
  1471. struct ehci_qh *qh;
  1472. enum ehci_timer_action action = TIMER_IO_WATCHDOG;
  1473. if (!++(oxu->stamp))
  1474. oxu->stamp++;
  1475. timer_action_done(oxu, TIMER_ASYNC_SHRINK);
  1476. rescan:
  1477. qh = oxu->async->qh_next.qh;
  1478. if (likely(qh != NULL)) {
  1479. do {
  1480. /* clean any finished work for this qh */
  1481. if (!list_empty(&qh->qtd_list)
  1482. && qh->stamp != oxu->stamp) {
  1483. int temp;
  1484. /* unlinks could happen here; completion
  1485. * reporting drops the lock. rescan using
  1486. * the latest schedule, but don't rescan
  1487. * qhs we already finished (no looping).
  1488. */
  1489. qh = qh_get(qh);
  1490. qh->stamp = oxu->stamp;
  1491. temp = qh_completions(oxu, qh);
  1492. qh_put(qh);
  1493. if (temp != 0)
  1494. goto rescan;
  1495. }
  1496. /* unlink idle entries, reducing HC PCI usage as well
  1497. * as HCD schedule-scanning costs. delay for any qh
  1498. * we just scanned, there's a not-unusual case that it
  1499. * doesn't stay idle for long.
  1500. * (plus, avoids some kind of re-activation race.)
  1501. */
  1502. if (list_empty(&qh->qtd_list)) {
  1503. if (qh->stamp == oxu->stamp)
  1504. action = TIMER_ASYNC_SHRINK;
  1505. else if (!oxu->reclaim
  1506. && qh->qh_state == QH_STATE_LINKED)
  1507. start_unlink_async(oxu, qh);
  1508. }
  1509. qh = qh->qh_next.qh;
  1510. } while (qh);
  1511. }
  1512. if (action == TIMER_ASYNC_SHRINK)
  1513. timer_action(oxu, TIMER_ASYNC_SHRINK);
  1514. }
  1515. /*
  1516. * periodic_next_shadow - return "next" pointer on shadow list
  1517. * @periodic: host pointer to qh/itd/sitd
  1518. * @tag: hardware tag for type of this record
  1519. */
  1520. static union ehci_shadow *periodic_next_shadow(union ehci_shadow *periodic,
  1521. __le32 tag)
  1522. {
  1523. switch (tag) {
  1524. default:
  1525. case Q_TYPE_QH:
  1526. return &periodic->qh->qh_next;
  1527. }
  1528. }
  1529. /* caller must hold oxu->lock */
  1530. static void periodic_unlink(struct oxu_hcd *oxu, unsigned frame, void *ptr)
  1531. {
  1532. union ehci_shadow *prev_p = &oxu->pshadow[frame];
  1533. __le32 *hw_p = &oxu->periodic[frame];
  1534. union ehci_shadow here = *prev_p;
  1535. /* find predecessor of "ptr"; hw and shadow lists are in sync */
  1536. while (here.ptr && here.ptr != ptr) {
  1537. prev_p = periodic_next_shadow(prev_p, Q_NEXT_TYPE(*hw_p));
  1538. hw_p = here.hw_next;
  1539. here = *prev_p;
  1540. }
  1541. /* an interrupt entry (at list end) could have been shared */
  1542. if (!here.ptr)
  1543. return;
  1544. /* update shadow and hardware lists ... the old "next" pointers
  1545. * from ptr may still be in use, the caller updates them.
  1546. */
  1547. *prev_p = *periodic_next_shadow(&here, Q_NEXT_TYPE(*hw_p));
  1548. *hw_p = *here.hw_next;
  1549. }
  1550. /* how many of the uframe's 125 usecs are allocated? */
  1551. static unsigned short periodic_usecs(struct oxu_hcd *oxu,
  1552. unsigned frame, unsigned uframe)
  1553. {
  1554. __le32 *hw_p = &oxu->periodic[frame];
  1555. union ehci_shadow *q = &oxu->pshadow[frame];
  1556. unsigned usecs = 0;
  1557. while (q->ptr) {
  1558. switch (Q_NEXT_TYPE(*hw_p)) {
  1559. case Q_TYPE_QH:
  1560. default:
  1561. /* is it in the S-mask? */
  1562. if (q->qh->hw_info2 & cpu_to_le32(1 << uframe))
  1563. usecs += q->qh->usecs;
  1564. /* ... or C-mask? */
  1565. if (q->qh->hw_info2 & cpu_to_le32(1 << (8 + uframe)))
  1566. usecs += q->qh->c_usecs;
  1567. hw_p = &q->qh->hw_next;
  1568. q = &q->qh->qh_next;
  1569. break;
  1570. }
  1571. }
  1572. #ifdef DEBUG
  1573. if (usecs > 100)
  1574. oxu_err(oxu, "uframe %d sched overrun: %d usecs\n",
  1575. frame * 8 + uframe, usecs);
  1576. #endif
  1577. return usecs;
  1578. }
  1579. static int enable_periodic(struct oxu_hcd *oxu)
  1580. {
  1581. u32 cmd;
  1582. int status;
  1583. /* did clearing PSE did take effect yet?
  1584. * takes effect only at frame boundaries...
  1585. */
  1586. status = handshake(oxu, &oxu->regs->status, STS_PSS, 0, 9 * 125);
  1587. if (status != 0) {
  1588. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  1589. return status;
  1590. }
  1591. cmd = readl(&oxu->regs->command) | CMD_PSE;
  1592. writel(cmd, &oxu->regs->command);
  1593. /* posted write ... PSS happens later */
  1594. oxu_to_hcd(oxu)->state = HC_STATE_RUNNING;
  1595. /* make sure ehci_work scans these */
  1596. oxu->next_uframe = readl(&oxu->regs->frame_index)
  1597. % (oxu->periodic_size << 3);
  1598. return 0;
  1599. }
  1600. static int disable_periodic(struct oxu_hcd *oxu)
  1601. {
  1602. u32 cmd;
  1603. int status;
  1604. /* did setting PSE not take effect yet?
  1605. * takes effect only at frame boundaries...
  1606. */
  1607. status = handshake(oxu, &oxu->regs->status, STS_PSS, STS_PSS, 9 * 125);
  1608. if (status != 0) {
  1609. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  1610. return status;
  1611. }
  1612. cmd = readl(&oxu->regs->command) & ~CMD_PSE;
  1613. writel(cmd, &oxu->regs->command);
  1614. /* posted write ... */
  1615. oxu->next_uframe = -1;
  1616. return 0;
  1617. }
  1618. /* periodic schedule slots have iso tds (normal or split) first, then a
  1619. * sparse tree for active interrupt transfers.
  1620. *
  1621. * this just links in a qh; caller guarantees uframe masks are set right.
  1622. * no FSTN support (yet; oxu 0.96+)
  1623. */
  1624. static int qh_link_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1625. {
  1626. unsigned i;
  1627. unsigned period = qh->period;
  1628. dev_dbg(&qh->dev->dev,
  1629. "link qh%d-%04x/%p start %d [%d/%d us]\n",
  1630. period, le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK),
  1631. qh, qh->start, qh->usecs, qh->c_usecs);
  1632. /* high bandwidth, or otherwise every microframe */
  1633. if (period == 0)
  1634. period = 1;
  1635. for (i = qh->start; i < oxu->periodic_size; i += period) {
  1636. union ehci_shadow *prev = &oxu->pshadow[i];
  1637. __le32 *hw_p = &oxu->periodic[i];
  1638. union ehci_shadow here = *prev;
  1639. __le32 type = 0;
  1640. /* skip the iso nodes at list head */
  1641. while (here.ptr) {
  1642. type = Q_NEXT_TYPE(*hw_p);
  1643. if (type == Q_TYPE_QH)
  1644. break;
  1645. prev = periodic_next_shadow(prev, type);
  1646. hw_p = &here.qh->hw_next;
  1647. here = *prev;
  1648. }
  1649. /* sorting each branch by period (slow-->fast)
  1650. * enables sharing interior tree nodes
  1651. */
  1652. while (here.ptr && qh != here.qh) {
  1653. if (qh->period > here.qh->period)
  1654. break;
  1655. prev = &here.qh->qh_next;
  1656. hw_p = &here.qh->hw_next;
  1657. here = *prev;
  1658. }
  1659. /* link in this qh, unless some earlier pass did that */
  1660. if (qh != here.qh) {
  1661. qh->qh_next = here;
  1662. if (here.qh)
  1663. qh->hw_next = *hw_p;
  1664. wmb();
  1665. prev->qh = qh;
  1666. *hw_p = QH_NEXT(qh->qh_dma);
  1667. }
  1668. }
  1669. qh->qh_state = QH_STATE_LINKED;
  1670. qh_get(qh);
  1671. /* update per-qh bandwidth for usbfs */
  1672. oxu_to_hcd(oxu)->self.bandwidth_allocated += qh->period
  1673. ? ((qh->usecs + qh->c_usecs) / qh->period)
  1674. : (qh->usecs * 8);
  1675. /* maybe enable periodic schedule processing */
  1676. if (!oxu->periodic_sched++)
  1677. return enable_periodic(oxu);
  1678. return 0;
  1679. }
  1680. static void qh_unlink_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1681. {
  1682. unsigned i;
  1683. unsigned period;
  1684. /* FIXME:
  1685. * IF this isn't high speed
  1686. * and this qh is active in the current uframe
  1687. * (and overlay token SplitXstate is false?)
  1688. * THEN
  1689. * qh->hw_info1 |= cpu_to_le32(1 << 7 "ignore");
  1690. */
  1691. /* high bandwidth, or otherwise part of every microframe */
  1692. period = qh->period;
  1693. if (period == 0)
  1694. period = 1;
  1695. for (i = qh->start; i < oxu->periodic_size; i += period)
  1696. periodic_unlink(oxu, i, qh);
  1697. /* update per-qh bandwidth for usbfs */
  1698. oxu_to_hcd(oxu)->self.bandwidth_allocated -= qh->period
  1699. ? ((qh->usecs + qh->c_usecs) / qh->period)
  1700. : (qh->usecs * 8);
  1701. dev_dbg(&qh->dev->dev,
  1702. "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
  1703. qh->period,
  1704. le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK),
  1705. qh, qh->start, qh->usecs, qh->c_usecs);
  1706. /* qh->qh_next still "live" to HC */
  1707. qh->qh_state = QH_STATE_UNLINK;
  1708. qh->qh_next.ptr = NULL;
  1709. qh_put(qh);
  1710. /* maybe turn off periodic schedule */
  1711. oxu->periodic_sched--;
  1712. if (!oxu->periodic_sched)
  1713. (void) disable_periodic(oxu);
  1714. }
  1715. static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1716. {
  1717. unsigned wait;
  1718. qh_unlink_periodic(oxu, qh);
  1719. /* simple/paranoid: always delay, expecting the HC needs to read
  1720. * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
  1721. * expect khubd to clean up after any CSPLITs we won't issue.
  1722. * active high speed queues may need bigger delays...
  1723. */
  1724. if (list_empty(&qh->qtd_list)
  1725. || (cpu_to_le32(QH_CMASK) & qh->hw_info2) != 0)
  1726. wait = 2;
  1727. else
  1728. wait = 55; /* worst case: 3 * 1024 */
  1729. udelay(wait);
  1730. qh->qh_state = QH_STATE_IDLE;
  1731. qh->hw_next = EHCI_LIST_END;
  1732. wmb();
  1733. }
  1734. static int check_period(struct oxu_hcd *oxu,
  1735. unsigned frame, unsigned uframe,
  1736. unsigned period, unsigned usecs)
  1737. {
  1738. int claimed;
  1739. /* complete split running into next frame?
  1740. * given FSTN support, we could sometimes check...
  1741. */
  1742. if (uframe >= 8)
  1743. return 0;
  1744. /*
  1745. * 80% periodic == 100 usec/uframe available
  1746. * convert "usecs we need" to "max already claimed"
  1747. */
  1748. usecs = 100 - usecs;
  1749. /* we "know" 2 and 4 uframe intervals were rejected; so
  1750. * for period 0, check _every_ microframe in the schedule.
  1751. */
  1752. if (unlikely(period == 0)) {
  1753. do {
  1754. for (uframe = 0; uframe < 7; uframe++) {
  1755. claimed = periodic_usecs(oxu, frame, uframe);
  1756. if (claimed > usecs)
  1757. return 0;
  1758. }
  1759. } while ((frame += 1) < oxu->periodic_size);
  1760. /* just check the specified uframe, at that period */
  1761. } else {
  1762. do {
  1763. claimed = periodic_usecs(oxu, frame, uframe);
  1764. if (claimed > usecs)
  1765. return 0;
  1766. } while ((frame += period) < oxu->periodic_size);
  1767. }
  1768. return 1;
  1769. }
  1770. static int check_intr_schedule(struct oxu_hcd *oxu,
  1771. unsigned frame, unsigned uframe,
  1772. const struct ehci_qh *qh, __le32 *c_maskp)
  1773. {
  1774. int retval = -ENOSPC;
  1775. if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
  1776. goto done;
  1777. if (!check_period(oxu, frame, uframe, qh->period, qh->usecs))
  1778. goto done;
  1779. if (!qh->c_usecs) {
  1780. retval = 0;
  1781. *c_maskp = 0;
  1782. goto done;
  1783. }
  1784. done:
  1785. return retval;
  1786. }
  1787. /* "first fit" scheduling policy used the first time through,
  1788. * or when the previous schedule slot can't be re-used.
  1789. */
  1790. static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1791. {
  1792. int status;
  1793. unsigned uframe;
  1794. __le32 c_mask;
  1795. unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
  1796. qh_refresh(oxu, qh);
  1797. qh->hw_next = EHCI_LIST_END;
  1798. frame = qh->start;
  1799. /* reuse the previous schedule slots, if we can */
  1800. if (frame < qh->period) {
  1801. uframe = ffs(le32_to_cpup(&qh->hw_info2) & QH_SMASK);
  1802. status = check_intr_schedule(oxu, frame, --uframe,
  1803. qh, &c_mask);
  1804. } else {
  1805. uframe = 0;
  1806. c_mask = 0;
  1807. status = -ENOSPC;
  1808. }
  1809. /* else scan the schedule to find a group of slots such that all
  1810. * uframes have enough periodic bandwidth available.
  1811. */
  1812. if (status) {
  1813. /* "normal" case, uframing flexible except with splits */
  1814. if (qh->period) {
  1815. frame = qh->period - 1;
  1816. do {
  1817. for (uframe = 0; uframe < 8; uframe++) {
  1818. status = check_intr_schedule(oxu,
  1819. frame, uframe, qh,
  1820. &c_mask);
  1821. if (status == 0)
  1822. break;
  1823. }
  1824. } while (status && frame--);
  1825. /* qh->period == 0 means every uframe */
  1826. } else {
  1827. frame = 0;
  1828. status = check_intr_schedule(oxu, 0, 0, qh, &c_mask);
  1829. }
  1830. if (status)
  1831. goto done;
  1832. qh->start = frame;
  1833. /* reset S-frame and (maybe) C-frame masks */
  1834. qh->hw_info2 &= cpu_to_le32(~(QH_CMASK | QH_SMASK));
  1835. qh->hw_info2 |= qh->period
  1836. ? cpu_to_le32(1 << uframe)
  1837. : cpu_to_le32(QH_SMASK);
  1838. qh->hw_info2 |= c_mask;
  1839. } else
  1840. oxu_dbg(oxu, "reused qh %p schedule\n", qh);
  1841. /* stuff into the periodic schedule */
  1842. status = qh_link_periodic(oxu, qh);
  1843. done:
  1844. return status;
  1845. }
  1846. static int intr_submit(struct oxu_hcd *oxu, struct urb *urb,
  1847. struct list_head *qtd_list, gfp_t mem_flags)
  1848. {
  1849. unsigned epnum;
  1850. unsigned long flags;
  1851. struct ehci_qh *qh;
  1852. int status = 0;
  1853. struct list_head empty;
  1854. /* get endpoint and transfer/schedule data */
  1855. epnum = urb->ep->desc.bEndpointAddress;
  1856. spin_lock_irqsave(&oxu->lock, flags);
  1857. if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
  1858. &oxu_to_hcd(oxu)->flags))) {
  1859. status = -ESHUTDOWN;
  1860. goto done;
  1861. }
  1862. /* get qh and force any scheduling errors */
  1863. INIT_LIST_HEAD(&empty);
  1864. qh = qh_append_tds(oxu, urb, &empty, epnum, &urb->ep->hcpriv);
  1865. if (qh == NULL) {
  1866. status = -ENOMEM;
  1867. goto done;
  1868. }
  1869. if (qh->qh_state == QH_STATE_IDLE) {
  1870. status = qh_schedule(oxu, qh);
  1871. if (status != 0)
  1872. goto done;
  1873. }
  1874. /* then queue the urb's tds to the qh */
  1875. qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv);
  1876. BUG_ON(qh == NULL);
  1877. /* ... update usbfs periodic stats */
  1878. oxu_to_hcd(oxu)->self.bandwidth_int_reqs++;
  1879. done:
  1880. spin_unlock_irqrestore(&oxu->lock, flags);
  1881. if (status)
  1882. qtd_list_free(oxu, urb, qtd_list);
  1883. return status;
  1884. }
  1885. static inline int itd_submit(struct oxu_hcd *oxu, struct urb *urb,
  1886. gfp_t mem_flags)
  1887. {
  1888. oxu_dbg(oxu, "iso support is missing!\n");
  1889. return -ENOSYS;
  1890. }
  1891. static inline int sitd_submit(struct oxu_hcd *oxu, struct urb *urb,
  1892. gfp_t mem_flags)
  1893. {
  1894. oxu_dbg(oxu, "split iso support is missing!\n");
  1895. return -ENOSYS;
  1896. }
  1897. static void scan_periodic(struct oxu_hcd *oxu)
  1898. {
  1899. unsigned frame, clock, now_uframe, mod;
  1900. unsigned modified;
  1901. mod = oxu->periodic_size << 3;
  1902. /*
  1903. * When running, scan from last scan point up to "now"
  1904. * else clean up by scanning everything that's left.
  1905. * Touches as few pages as possible: cache-friendly.
  1906. */
  1907. now_uframe = oxu->next_uframe;
  1908. if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
  1909. clock = readl(&oxu->regs->frame_index);
  1910. else
  1911. clock = now_uframe + mod - 1;
  1912. clock %= mod;
  1913. for (;;) {
  1914. union ehci_shadow q, *q_p;
  1915. __le32 type, *hw_p;
  1916. unsigned uframes;
  1917. /* don't scan past the live uframe */
  1918. frame = now_uframe >> 3;
  1919. if (frame == (clock >> 3))
  1920. uframes = now_uframe & 0x07;
  1921. else {
  1922. /* safe to scan the whole frame at once */
  1923. now_uframe |= 0x07;
  1924. uframes = 8;
  1925. }
  1926. restart:
  1927. /* scan each element in frame's queue for completions */
  1928. q_p = &oxu->pshadow[frame];
  1929. hw_p = &oxu->periodic[frame];
  1930. q.ptr = q_p->ptr;
  1931. type = Q_NEXT_TYPE(*hw_p);
  1932. modified = 0;
  1933. while (q.ptr != NULL) {
  1934. union ehci_shadow temp;
  1935. int live;
  1936. live = HC_IS_RUNNING(oxu_to_hcd(oxu)->state);
  1937. switch (type) {
  1938. case Q_TYPE_QH:
  1939. /* handle any completions */
  1940. temp.qh = qh_get(q.qh);
  1941. type = Q_NEXT_TYPE(q.qh->hw_next);
  1942. q = q.qh->qh_next;
  1943. modified = qh_completions(oxu, temp.qh);
  1944. if (unlikely(list_empty(&temp.qh->qtd_list)))
  1945. intr_deschedule(oxu, temp.qh);
  1946. qh_put(temp.qh);
  1947. break;
  1948. default:
  1949. dbg("corrupt type %d frame %d shadow %p",
  1950. type, frame, q.ptr);
  1951. q.ptr = NULL;
  1952. }
  1953. /* assume completion callbacks modify the queue */
  1954. if (unlikely(modified))
  1955. goto restart;
  1956. }
  1957. /* Stop when we catch up to the HC */
  1958. /* FIXME: this assumes we won't get lapped when
  1959. * latencies climb; that should be rare, but...
  1960. * detect it, and just go all the way around.
  1961. * FLR might help detect this case, so long as latencies
  1962. * don't exceed periodic_size msec (default 1.024 sec).
  1963. */
  1964. /* FIXME: likewise assumes HC doesn't halt mid-scan */
  1965. if (now_uframe == clock) {
  1966. unsigned now;
  1967. if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
  1968. break;
  1969. oxu->next_uframe = now_uframe;
  1970. now = readl(&oxu->regs->frame_index) % mod;
  1971. if (now_uframe == now)
  1972. break;
  1973. /* rescan the rest of this frame, then ... */
  1974. clock = now;
  1975. } else {
  1976. now_uframe++;
  1977. now_uframe %= mod;
  1978. }
  1979. }
  1980. }
  1981. /* On some systems, leaving remote wakeup enabled prevents system shutdown.
  1982. * The firmware seems to think that powering off is a wakeup event!
  1983. * This routine turns off remote wakeup and everything else, on all ports.
  1984. */
  1985. static void ehci_turn_off_all_ports(struct oxu_hcd *oxu)
  1986. {
  1987. int port = HCS_N_PORTS(oxu->hcs_params);
  1988. while (port--)
  1989. writel(PORT_RWC_BITS, &oxu->regs->port_status[port]);
  1990. }
  1991. static void ehci_port_power(struct oxu_hcd *oxu, int is_on)
  1992. {
  1993. unsigned port;
  1994. if (!HCS_PPC(oxu->hcs_params))
  1995. return;
  1996. oxu_dbg(oxu, "...power%s ports...\n", is_on ? "up" : "down");
  1997. for (port = HCS_N_PORTS(oxu->hcs_params); port > 0; )
  1998. (void) oxu_hub_control(oxu_to_hcd(oxu),
  1999. is_on ? SetPortFeature : ClearPortFeature,
  2000. USB_PORT_FEAT_POWER,
  2001. port--, NULL, 0);
  2002. msleep(20);
  2003. }
  2004. /* Called from some interrupts, timers, and so on.
  2005. * It calls driver completion functions, after dropping oxu->lock.
  2006. */
  2007. static void ehci_work(struct oxu_hcd *oxu)
  2008. {
  2009. timer_action_done(oxu, TIMER_IO_WATCHDOG);
  2010. if (oxu->reclaim_ready)
  2011. end_unlink_async(oxu);
  2012. /* another CPU may drop oxu->lock during a schedule scan while
  2013. * it reports urb completions. this flag guards against bogus
  2014. * attempts at re-entrant schedule scanning.
  2015. */
  2016. if (oxu->scanning)
  2017. return;
  2018. oxu->scanning = 1;
  2019. scan_async(oxu);
  2020. if (oxu->next_uframe != -1)
  2021. scan_periodic(oxu);
  2022. oxu->scanning = 0;
  2023. /* the IO watchdog guards against hardware or driver bugs that
  2024. * misplace IRQs, and should let us run completely without IRQs.
  2025. * such lossage has been observed on both VT6202 and VT8235.
  2026. */
  2027. if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state) &&
  2028. (oxu->async->qh_next.ptr != NULL ||
  2029. oxu->periodic_sched != 0))
  2030. timer_action(oxu, TIMER_IO_WATCHDOG);
  2031. }
  2032. static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
  2033. {
  2034. /* if we need to use IAA and it's busy, defer */
  2035. if (qh->qh_state == QH_STATE_LINKED
  2036. && oxu->reclaim
  2037. && HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) {
  2038. struct ehci_qh *last;
  2039. for (last = oxu->reclaim;
  2040. last->reclaim;
  2041. last = last->reclaim)
  2042. continue;
  2043. qh->qh_state = QH_STATE_UNLINK_WAIT;
  2044. last->reclaim = qh;
  2045. /* bypass IAA if the hc can't care */
  2046. } else if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state) && oxu->reclaim)
  2047. end_unlink_async(oxu);
  2048. /* something else might have unlinked the qh by now */
  2049. if (qh->qh_state == QH_STATE_LINKED)
  2050. start_unlink_async(oxu, qh);
  2051. }
  2052. /*
  2053. * USB host controller methods
  2054. */
  2055. static irqreturn_t oxu210_hcd_irq(struct usb_hcd *hcd)
  2056. {
  2057. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2058. u32 status, pcd_status = 0;
  2059. int bh;
  2060. spin_lock(&oxu->lock);
  2061. status = readl(&oxu->regs->status);
  2062. /* e.g. cardbus physical eject */
  2063. if (status == ~(u32) 0) {
  2064. oxu_dbg(oxu, "device removed\n");
  2065. goto dead;
  2066. }
  2067. status &= INTR_MASK;
  2068. if (!status) { /* irq sharing? */
  2069. spin_unlock(&oxu->lock);
  2070. return IRQ_NONE;
  2071. }
  2072. /* clear (just) interrupts */
  2073. writel(status, &oxu->regs->status);
  2074. readl(&oxu->regs->command); /* unblock posted write */
  2075. bh = 0;
  2076. #ifdef OXU_VERBOSE_DEBUG
  2077. /* unrequested/ignored: Frame List Rollover */
  2078. dbg_status(oxu, "irq", status);
  2079. #endif
  2080. /* INT, ERR, and IAA interrupt rates can be throttled */
  2081. /* normal [4.15.1.2] or error [4.15.1.1] completion */
  2082. if (likely((status & (STS_INT|STS_ERR)) != 0))
  2083. bh = 1;
  2084. /* complete the unlinking of some qh [4.15.2.3] */
  2085. if (status & STS_IAA) {
  2086. oxu->reclaim_ready = 1;
  2087. bh = 1;
  2088. }
  2089. /* remote wakeup [4.3.1] */
  2090. if (status & STS_PCD) {
  2091. unsigned i = HCS_N_PORTS(oxu->hcs_params);
  2092. pcd_status = status;
  2093. /* resume root hub? */
  2094. if (!(readl(&oxu->regs->command) & CMD_RUN))
  2095. usb_hcd_resume_root_hub(hcd);
  2096. while (i--) {
  2097. int pstatus = readl(&oxu->regs->port_status[i]);
  2098. if (pstatus & PORT_OWNER)
  2099. continue;
  2100. if (!(pstatus & PORT_RESUME)
  2101. || oxu->reset_done[i] != 0)
  2102. continue;
  2103. /* start 20 msec resume signaling from this port,
  2104. * and make khubd collect PORT_STAT_C_SUSPEND to
  2105. * stop that signaling.
  2106. */
  2107. oxu->reset_done[i] = jiffies + msecs_to_jiffies(20);
  2108. oxu_dbg(oxu, "port %d remote wakeup\n", i + 1);
  2109. mod_timer(&hcd->rh_timer, oxu->reset_done[i]);
  2110. }
  2111. }
  2112. /* PCI errors [4.15.2.4] */
  2113. if (unlikely((status & STS_FATAL) != 0)) {
  2114. /* bogus "fatal" IRQs appear on some chips... why? */
  2115. status = readl(&oxu->regs->status);
  2116. dbg_cmd(oxu, "fatal", readl(&oxu->regs->command));
  2117. dbg_status(oxu, "fatal", status);
  2118. if (status & STS_HALT) {
  2119. oxu_err(oxu, "fatal error\n");
  2120. dead:
  2121. ehci_reset(oxu);
  2122. writel(0, &oxu->regs->configured_flag);
  2123. /* generic layer kills/unlinks all urbs, then
  2124. * uses oxu_stop to clean up the rest
  2125. */
  2126. bh = 1;
  2127. }
  2128. }
  2129. if (bh)
  2130. ehci_work(oxu);
  2131. spin_unlock(&oxu->lock);
  2132. if (pcd_status & STS_PCD)
  2133. usb_hcd_poll_rh_status(hcd);
  2134. return IRQ_HANDLED;
  2135. }
  2136. static irqreturn_t oxu_irq(struct usb_hcd *hcd)
  2137. {
  2138. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2139. int ret = IRQ_HANDLED;
  2140. u32 status = oxu_readl(hcd->regs, OXU_CHIPIRQSTATUS);
  2141. u32 enable = oxu_readl(hcd->regs, OXU_CHIPIRQEN_SET);
  2142. /* Disable all interrupt */
  2143. oxu_writel(hcd->regs, OXU_CHIPIRQEN_CLR, enable);
  2144. if ((oxu->is_otg && (status & OXU_USBOTGI)) ||
  2145. (!oxu->is_otg && (status & OXU_USBSPHI)))
  2146. oxu210_hcd_irq(hcd);
  2147. else
  2148. ret = IRQ_NONE;
  2149. /* Enable all interrupt back */
  2150. oxu_writel(hcd->regs, OXU_CHIPIRQEN_SET, enable);
  2151. return ret;
  2152. }
  2153. static void oxu_watchdog(unsigned long param)
  2154. {
  2155. struct oxu_hcd *oxu = (struct oxu_hcd *) param;
  2156. unsigned long flags;
  2157. spin_lock_irqsave(&oxu->lock, flags);
  2158. /* lost IAA irqs wedge things badly; seen with a vt8235 */
  2159. if (oxu->reclaim) {
  2160. u32 status = readl(&oxu->regs->status);
  2161. if (status & STS_IAA) {
  2162. oxu_vdbg(oxu, "lost IAA\n");
  2163. writel(STS_IAA, &oxu->regs->status);
  2164. oxu->reclaim_ready = 1;
  2165. }
  2166. }
  2167. /* stop async processing after it's idled a bit */
  2168. if (test_bit(TIMER_ASYNC_OFF, &oxu->actions))
  2169. start_unlink_async(oxu, oxu->async);
  2170. /* oxu could run by timer, without IRQs ... */
  2171. ehci_work(oxu);
  2172. spin_unlock_irqrestore(&oxu->lock, flags);
  2173. }
  2174. /* One-time init, only for memory state.
  2175. */
  2176. static int oxu_hcd_init(struct usb_hcd *hcd)
  2177. {
  2178. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2179. u32 temp;
  2180. int retval;
  2181. u32 hcc_params;
  2182. spin_lock_init(&oxu->lock);
  2183. init_timer(&oxu->watchdog);
  2184. oxu->watchdog.function = oxu_watchdog;
  2185. oxu->watchdog.data = (unsigned long) oxu;
  2186. /*
  2187. * hw default: 1K periodic list heads, one per frame.
  2188. * periodic_size can shrink by USBCMD update if hcc_params allows.
  2189. */
  2190. oxu->periodic_size = DEFAULT_I_TDPS;
  2191. retval = ehci_mem_init(oxu, GFP_KERNEL);
  2192. if (retval < 0)
  2193. return retval;
  2194. /* controllers may cache some of the periodic schedule ... */
  2195. hcc_params = readl(&oxu->caps->hcc_params);
  2196. if (HCC_ISOC_CACHE(hcc_params)) /* full frame cache */
  2197. oxu->i_thresh = 8;
  2198. else /* N microframes cached */
  2199. oxu->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
  2200. oxu->reclaim = NULL;
  2201. oxu->reclaim_ready = 0;
  2202. oxu->next_uframe = -1;
  2203. /*
  2204. * dedicate a qh for the async ring head, since we couldn't unlink
  2205. * a 'real' qh without stopping the async schedule [4.8]. use it
  2206. * as the 'reclamation list head' too.
  2207. * its dummy is used in hw_alt_next of many tds, to prevent the qh
  2208. * from automatically advancing to the next td after short reads.
  2209. */
  2210. oxu->async->qh_next.qh = NULL;
  2211. oxu->async->hw_next = QH_NEXT(oxu->async->qh_dma);
  2212. oxu->async->hw_info1 = cpu_to_le32(QH_HEAD);
  2213. oxu->async->hw_token = cpu_to_le32(QTD_STS_HALT);
  2214. oxu->async->hw_qtd_next = EHCI_LIST_END;
  2215. oxu->async->qh_state = QH_STATE_LINKED;
  2216. oxu->async->hw_alt_next = QTD_NEXT(oxu->async->dummy->qtd_dma);
  2217. /* clear interrupt enables, set irq latency */
  2218. if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
  2219. log2_irq_thresh = 0;
  2220. temp = 1 << (16 + log2_irq_thresh);
  2221. if (HCC_CANPARK(hcc_params)) {
  2222. /* HW default park == 3, on hardware that supports it (like
  2223. * NVidia and ALI silicon), maximizes throughput on the async
  2224. * schedule by avoiding QH fetches between transfers.
  2225. *
  2226. * With fast usb storage devices and NForce2, "park" seems to
  2227. * make problems: throughput reduction (!), data errors...
  2228. */
  2229. if (park) {
  2230. park = min(park, (unsigned) 3);
  2231. temp |= CMD_PARK;
  2232. temp |= park << 8;
  2233. }
  2234. oxu_dbg(oxu, "park %d\n", park);
  2235. }
  2236. if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
  2237. /* periodic schedule size can be smaller than default */
  2238. temp &= ~(3 << 2);
  2239. temp |= (EHCI_TUNE_FLS << 2);
  2240. }
  2241. oxu->command = temp;
  2242. return 0;
  2243. }
  2244. /* Called during probe() after chip reset completes.
  2245. */
  2246. static int oxu_reset(struct usb_hcd *hcd)
  2247. {
  2248. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2249. int ret;
  2250. spin_lock_init(&oxu->mem_lock);
  2251. INIT_LIST_HEAD(&oxu->urb_list);
  2252. oxu->urb_len = 0;
  2253. /* FIMXE */
  2254. hcd->self.controller->dma_mask = NULL;
  2255. if (oxu->is_otg) {
  2256. oxu->caps = hcd->regs + OXU_OTG_CAP_OFFSET;
  2257. oxu->regs = hcd->regs + OXU_OTG_CAP_OFFSET + \
  2258. HC_LENGTH(readl(&oxu->caps->hc_capbase));
  2259. oxu->mem = hcd->regs + OXU_SPH_MEM;
  2260. } else {
  2261. oxu->caps = hcd->regs + OXU_SPH_CAP_OFFSET;
  2262. oxu->regs = hcd->regs + OXU_SPH_CAP_OFFSET + \
  2263. HC_LENGTH(readl(&oxu->caps->hc_capbase));
  2264. oxu->mem = hcd->regs + OXU_OTG_MEM;
  2265. }
  2266. oxu->hcs_params = readl(&oxu->caps->hcs_params);
  2267. oxu->sbrn = 0x20;
  2268. ret = oxu_hcd_init(hcd);
  2269. if (ret)
  2270. return ret;
  2271. return 0;
  2272. }
  2273. static int oxu_run(struct usb_hcd *hcd)
  2274. {
  2275. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2276. int retval;
  2277. u32 temp, hcc_params;
  2278. hcd->uses_new_polling = 1;
  2279. hcd->poll_rh = 0;
  2280. /* EHCI spec section 4.1 */
  2281. retval = ehci_reset(oxu);
  2282. if (retval != 0) {
  2283. ehci_mem_cleanup(oxu);
  2284. return retval;
  2285. }
  2286. writel(oxu->periodic_dma, &oxu->regs->frame_list);
  2287. writel((u32) oxu->async->qh_dma, &oxu->regs->async_next);
  2288. /* hcc_params controls whether oxu->regs->segment must (!!!)
  2289. * be used; it constrains QH/ITD/SITD and QTD locations.
  2290. * pci_pool consistent memory always uses segment zero.
  2291. * streaming mappings for I/O buffers, like pci_map_single(),
  2292. * can return segments above 4GB, if the device allows.
  2293. *
  2294. * NOTE: the dma mask is visible through dma_supported(), so
  2295. * drivers can pass this info along ... like NETIF_F_HIGHDMA,
  2296. * Scsi_Host.highmem_io, and so forth. It's readonly to all
  2297. * host side drivers though.
  2298. */
  2299. hcc_params = readl(&oxu->caps->hcc_params);
  2300. if (HCC_64BIT_ADDR(hcc_params))
  2301. writel(0, &oxu->regs->segment);
  2302. oxu->command &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE |
  2303. CMD_ASE | CMD_RESET);
  2304. oxu->command |= CMD_RUN;
  2305. writel(oxu->command, &oxu->regs->command);
  2306. dbg_cmd(oxu, "init", oxu->command);
  2307. /*
  2308. * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
  2309. * are explicitly handed to companion controller(s), so no TT is
  2310. * involved with the root hub. (Except where one is integrated,
  2311. * and there's no companion controller unless maybe for USB OTG.)
  2312. */
  2313. hcd->state = HC_STATE_RUNNING;
  2314. writel(FLAG_CF, &oxu->regs->configured_flag);
  2315. readl(&oxu->regs->command); /* unblock posted writes */
  2316. temp = HC_VERSION(readl(&oxu->caps->hc_capbase));
  2317. oxu_info(oxu, "USB %x.%x started, quasi-EHCI %x.%02x, driver %s%s\n",
  2318. ((oxu->sbrn & 0xf0)>>4), (oxu->sbrn & 0x0f),
  2319. temp >> 8, temp & 0xff, DRIVER_VERSION,
  2320. ignore_oc ? ", overcurrent ignored" : "");
  2321. writel(INTR_MASK, &oxu->regs->intr_enable); /* Turn On Interrupts */
  2322. return 0;
  2323. }
  2324. static void oxu_stop(struct usb_hcd *hcd)
  2325. {
  2326. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2327. /* Turn off port power on all root hub ports. */
  2328. ehci_port_power(oxu, 0);
  2329. /* no more interrupts ... */
  2330. del_timer_sync(&oxu->watchdog);
  2331. spin_lock_irq(&oxu->lock);
  2332. if (HC_IS_RUNNING(hcd->state))
  2333. ehci_quiesce(oxu);
  2334. ehci_reset(oxu);
  2335. writel(0, &oxu->regs->intr_enable);
  2336. spin_unlock_irq(&oxu->lock);
  2337. /* let companion controllers work when we aren't */
  2338. writel(0, &oxu->regs->configured_flag);
  2339. /* root hub is shut down separately (first, when possible) */
  2340. spin_lock_irq(&oxu->lock);
  2341. if (oxu->async)
  2342. ehci_work(oxu);
  2343. spin_unlock_irq(&oxu->lock);
  2344. ehci_mem_cleanup(oxu);
  2345. dbg_status(oxu, "oxu_stop completed", readl(&oxu->regs->status));
  2346. }
  2347. /* Kick in for silicon on any bus (not just pci, etc).
  2348. * This forcibly disables dma and IRQs, helping kexec and other cases
  2349. * where the next system software may expect clean state.
  2350. */
  2351. static void oxu_shutdown(struct usb_hcd *hcd)
  2352. {
  2353. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2354. (void) ehci_halt(oxu);
  2355. ehci_turn_off_all_ports(oxu);
  2356. /* make BIOS/etc use companion controller during reboot */
  2357. writel(0, &oxu->regs->configured_flag);
  2358. /* unblock posted writes */
  2359. readl(&oxu->regs->configured_flag);
  2360. }
  2361. /* Non-error returns are a promise to giveback() the urb later
  2362. * we drop ownership so next owner (or urb unlink) can get it
  2363. *
  2364. * urb + dev is in hcd.self.controller.urb_list
  2365. * we're queueing TDs onto software and hardware lists
  2366. *
  2367. * hcd-specific init for hcpriv hasn't been done yet
  2368. *
  2369. * NOTE: control, bulk, and interrupt share the same code to append TDs
  2370. * to a (possibly active) QH, and the same QH scanning code.
  2371. */
  2372. static int __oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
  2373. gfp_t mem_flags)
  2374. {
  2375. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2376. struct list_head qtd_list;
  2377. INIT_LIST_HEAD(&qtd_list);
  2378. switch (usb_pipetype(urb->pipe)) {
  2379. case PIPE_CONTROL:
  2380. case PIPE_BULK:
  2381. default:
  2382. if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags))
  2383. return -ENOMEM;
  2384. return submit_async(oxu, urb, &qtd_list, mem_flags);
  2385. case PIPE_INTERRUPT:
  2386. if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags))
  2387. return -ENOMEM;
  2388. return intr_submit(oxu, urb, &qtd_list, mem_flags);
  2389. case PIPE_ISOCHRONOUS:
  2390. if (urb->dev->speed == USB_SPEED_HIGH)
  2391. return itd_submit(oxu, urb, mem_flags);
  2392. else
  2393. return sitd_submit(oxu, urb, mem_flags);
  2394. }
  2395. }
  2396. /* This function is responsible for breaking URBs with big data size
  2397. * into smaller size and processing small urbs in sequence.
  2398. */
  2399. static int oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
  2400. gfp_t mem_flags)
  2401. {
  2402. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2403. int num, rem;
  2404. int transfer_buffer_length;
  2405. void *transfer_buffer;
  2406. struct urb *murb;
  2407. int i, ret;
  2408. /* If not bulk pipe just enqueue the URB */
  2409. if (!usb_pipebulk(urb->pipe))
  2410. return __oxu_urb_enqueue(hcd, urb, mem_flags);
  2411. /* Otherwise we should verify the USB transfer buffer size! */
  2412. transfer_buffer = urb->transfer_buffer;
  2413. transfer_buffer_length = urb->transfer_buffer_length;
  2414. num = urb->transfer_buffer_length / 4096;
  2415. rem = urb->transfer_buffer_length % 4096;
  2416. if (rem != 0)
  2417. num++;
  2418. /* If URB is smaller than 4096 bytes just enqueue it! */
  2419. if (num == 1)
  2420. return __oxu_urb_enqueue(hcd, urb, mem_flags);
  2421. /* Ok, we have more job to do! :) */
  2422. for (i = 0; i < num - 1; i++) {
  2423. /* Get free micro URB poll till a free urb is recieved */
  2424. do {
  2425. murb = (struct urb *) oxu_murb_alloc(oxu);
  2426. if (!murb)
  2427. schedule();
  2428. } while (!murb);
  2429. /* Coping the urb */
  2430. memcpy(murb, urb, sizeof(struct urb));
  2431. murb->transfer_buffer_length = 4096;
  2432. murb->transfer_buffer = transfer_buffer + i * 4096;
  2433. /* Null pointer for the encodes that this is a micro urb */
  2434. murb->complete = NULL;
  2435. ((struct oxu_murb *) murb)->main = urb;
  2436. ((struct oxu_murb *) murb)->last = 0;
  2437. /* This loop is to guarantee urb to be processed when there's
  2438. * not enough resources at a particular time by retrying.
  2439. */
  2440. do {
  2441. ret = __oxu_urb_enqueue(hcd, murb, mem_flags);
  2442. if (ret)
  2443. schedule();
  2444. } while (ret);
  2445. }
  2446. /* Last urb requires special handling */
  2447. /* Get free micro URB poll till a free urb is recieved */
  2448. do {
  2449. murb = (struct urb *) oxu_murb_alloc(oxu);
  2450. if (!murb)
  2451. schedule();
  2452. } while (!murb);
  2453. /* Coping the urb */
  2454. memcpy(murb, urb, sizeof(struct urb));
  2455. murb->transfer_buffer_length = rem > 0 ? rem : 4096;
  2456. murb->transfer_buffer = transfer_buffer + (num - 1) * 4096;
  2457. /* Null pointer for the encodes that this is a micro urb */
  2458. murb->complete = NULL;
  2459. ((struct oxu_murb *) murb)->main = urb;
  2460. ((struct oxu_murb *) murb)->last = 1;
  2461. do {
  2462. ret = __oxu_urb_enqueue(hcd, murb, mem_flags);
  2463. if (ret)
  2464. schedule();
  2465. } while (ret);
  2466. return ret;
  2467. }
  2468. /* Remove from hardware lists.
  2469. * Completions normally happen asynchronously
  2470. */
  2471. static int oxu_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  2472. {
  2473. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2474. struct ehci_qh *qh;
  2475. unsigned long flags;
  2476. spin_lock_irqsave(&oxu->lock, flags);
  2477. switch (usb_pipetype(urb->pipe)) {
  2478. case PIPE_CONTROL:
  2479. case PIPE_BULK:
  2480. default:
  2481. qh = (struct ehci_qh *) urb->hcpriv;
  2482. if (!qh)
  2483. break;
  2484. unlink_async(oxu, qh);
  2485. break;
  2486. case PIPE_INTERRUPT:
  2487. qh = (struct ehci_qh *) urb->hcpriv;
  2488. if (!qh)
  2489. break;
  2490. switch (qh->qh_state) {
  2491. case QH_STATE_LINKED:
  2492. intr_deschedule(oxu, qh);
  2493. /* FALL THROUGH */
  2494. case QH_STATE_IDLE:
  2495. qh_completions(oxu, qh);
  2496. break;
  2497. default:
  2498. oxu_dbg(oxu, "bogus qh %p state %d\n",
  2499. qh, qh->qh_state);
  2500. goto done;
  2501. }
  2502. /* reschedule QH iff another request is queued */
  2503. if (!list_empty(&qh->qtd_list)
  2504. && HC_IS_RUNNING(hcd->state)) {
  2505. int status;
  2506. status = qh_schedule(oxu, qh);
  2507. spin_unlock_irqrestore(&oxu->lock, flags);
  2508. if (status != 0) {
  2509. /* shouldn't happen often, but ...
  2510. * FIXME kill those tds' urbs
  2511. */
  2512. err("can't reschedule qh %p, err %d",
  2513. qh, status);
  2514. }
  2515. return status;
  2516. }
  2517. break;
  2518. }
  2519. done:
  2520. spin_unlock_irqrestore(&oxu->lock, flags);
  2521. return 0;
  2522. }
  2523. /* Bulk qh holds the data toggle */
  2524. static void oxu_endpoint_disable(struct usb_hcd *hcd,
  2525. struct usb_host_endpoint *ep)
  2526. {
  2527. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2528. unsigned long flags;
  2529. struct ehci_qh *qh, *tmp;
  2530. /* ASSERT: any requests/urbs are being unlinked */
  2531. /* ASSERT: nobody can be submitting urbs for this any more */
  2532. rescan:
  2533. spin_lock_irqsave(&oxu->lock, flags);
  2534. qh = ep->hcpriv;
  2535. if (!qh)
  2536. goto done;
  2537. /* endpoints can be iso streams. for now, we don't
  2538. * accelerate iso completions ... so spin a while.
  2539. */
  2540. if (qh->hw_info1 == 0) {
  2541. oxu_vdbg(oxu, "iso delay\n");
  2542. goto idle_timeout;
  2543. }
  2544. if (!HC_IS_RUNNING(hcd->state))
  2545. qh->qh_state = QH_STATE_IDLE;
  2546. switch (qh->qh_state) {
  2547. case QH_STATE_LINKED:
  2548. for (tmp = oxu->async->qh_next.qh;
  2549. tmp && tmp != qh;
  2550. tmp = tmp->qh_next.qh)
  2551. continue;
  2552. /* periodic qh self-unlinks on empty */
  2553. if (!tmp)
  2554. goto nogood;
  2555. unlink_async(oxu, qh);
  2556. /* FALL THROUGH */
  2557. case QH_STATE_UNLINK: /* wait for hw to finish? */
  2558. idle_timeout:
  2559. spin_unlock_irqrestore(&oxu->lock, flags);
  2560. schedule_timeout_uninterruptible(1);
  2561. goto rescan;
  2562. case QH_STATE_IDLE: /* fully unlinked */
  2563. if (list_empty(&qh->qtd_list)) {
  2564. qh_put(qh);
  2565. break;
  2566. }
  2567. /* else FALL THROUGH */
  2568. default:
  2569. nogood:
  2570. /* caller was supposed to have unlinked any requests;
  2571. * that's not our job. just leak this memory.
  2572. */
  2573. oxu_err(oxu, "qh %p (#%02x) state %d%s\n",
  2574. qh, ep->desc.bEndpointAddress, qh->qh_state,
  2575. list_empty(&qh->qtd_list) ? "" : "(has tds)");
  2576. break;
  2577. }
  2578. ep->hcpriv = NULL;
  2579. done:
  2580. spin_unlock_irqrestore(&oxu->lock, flags);
  2581. return;
  2582. }
  2583. static int oxu_get_frame(struct usb_hcd *hcd)
  2584. {
  2585. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2586. return (readl(&oxu->regs->frame_index) >> 3) %
  2587. oxu->periodic_size;
  2588. }
  2589. /* Build "status change" packet (one or two bytes) from HC registers */
  2590. static int oxu_hub_status_data(struct usb_hcd *hcd, char *buf)
  2591. {
  2592. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2593. u32 temp, mask, status = 0;
  2594. int ports, i, retval = 1;
  2595. unsigned long flags;
  2596. /* if !USB_SUSPEND, root hub timers won't get shut down ... */
  2597. if (!HC_IS_RUNNING(hcd->state))
  2598. return 0;
  2599. /* init status to no-changes */
  2600. buf[0] = 0;
  2601. ports = HCS_N_PORTS(oxu->hcs_params);
  2602. if (ports > 7) {
  2603. buf[1] = 0;
  2604. retval++;
  2605. }
  2606. /* Some boards (mostly VIA?) report bogus overcurrent indications,
  2607. * causing massive log spam unless we completely ignore them. It
  2608. * may be relevant that VIA VT8235 controlers, where PORT_POWER is
  2609. * always set, seem to clear PORT_OCC and PORT_CSC when writing to
  2610. * PORT_POWER; that's surprising, but maybe within-spec.
  2611. */
  2612. if (!ignore_oc)
  2613. mask = PORT_CSC | PORT_PEC | PORT_OCC;
  2614. else
  2615. mask = PORT_CSC | PORT_PEC;
  2616. /* no hub change reports (bit 0) for now (power, ...) */
  2617. /* port N changes (bit N)? */
  2618. spin_lock_irqsave(&oxu->lock, flags);
  2619. for (i = 0; i < ports; i++) {
  2620. temp = readl(&oxu->regs->port_status[i]);
  2621. /*
  2622. * Return status information even for ports with OWNER set.
  2623. * Otherwise khubd wouldn't see the disconnect event when a
  2624. * high-speed device is switched over to the companion
  2625. * controller by the user.
  2626. */
  2627. if (!(temp & PORT_CONNECT))
  2628. oxu->reset_done[i] = 0;
  2629. if ((temp & mask) != 0 || ((temp & PORT_RESUME) != 0 &&
  2630. time_after_eq(jiffies, oxu->reset_done[i]))) {
  2631. if (i < 7)
  2632. buf[0] |= 1 << (i + 1);
  2633. else
  2634. buf[1] |= 1 << (i - 7);
  2635. status = STS_PCD;
  2636. }
  2637. }
  2638. /* FIXME autosuspend idle root hubs */
  2639. spin_unlock_irqrestore(&oxu->lock, flags);
  2640. return status ? retval : 0;
  2641. }
  2642. /* Returns the speed of a device attached to a port on the root hub. */
  2643. static inline unsigned int oxu_port_speed(struct oxu_hcd *oxu,
  2644. unsigned int portsc)
  2645. {
  2646. switch ((portsc >> 26) & 3) {
  2647. case 0:
  2648. return 0;
  2649. case 1:
  2650. return 1 << USB_PORT_FEAT_LOWSPEED;
  2651. case 2:
  2652. default:
  2653. return 1 << USB_PORT_FEAT_HIGHSPEED;
  2654. }
  2655. }
  2656. #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
  2657. static int oxu_hub_control(struct usb_hcd *hcd, u16 typeReq,
  2658. u16 wValue, u16 wIndex, char *buf, u16 wLength)
  2659. {
  2660. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2661. int ports = HCS_N_PORTS(oxu->hcs_params);
  2662. u32 __iomem *status_reg = &oxu->regs->port_status[wIndex - 1];
  2663. u32 temp, status;
  2664. unsigned long flags;
  2665. int retval = 0;
  2666. unsigned selector;
  2667. /*
  2668. * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
  2669. * HCS_INDICATOR may say we can change LEDs to off/amber/green.
  2670. * (track current state ourselves) ... blink for diagnostics,
  2671. * power, "this is the one", etc. EHCI spec supports this.
  2672. */
  2673. spin_lock_irqsave(&oxu->lock, flags);
  2674. switch (typeReq) {
  2675. case ClearHubFeature:
  2676. switch (wValue) {
  2677. case C_HUB_LOCAL_POWER:
  2678. case C_HUB_OVER_CURRENT:
  2679. /* no hub-wide feature/status flags */
  2680. break;
  2681. default:
  2682. goto error;
  2683. }
  2684. break;
  2685. case ClearPortFeature:
  2686. if (!wIndex || wIndex > ports)
  2687. goto error;
  2688. wIndex--;
  2689. temp = readl(status_reg);
  2690. /*
  2691. * Even if OWNER is set, so the port is owned by the
  2692. * companion controller, khubd needs to be able to clear
  2693. * the port-change status bits (especially
  2694. * USB_PORT_FEAT_C_CONNECTION).
  2695. */
  2696. switch (wValue) {
  2697. case USB_PORT_FEAT_ENABLE:
  2698. writel(temp & ~PORT_PE, status_reg);
  2699. break;
  2700. case USB_PORT_FEAT_C_ENABLE:
  2701. writel((temp & ~PORT_RWC_BITS) | PORT_PEC, status_reg);
  2702. break;
  2703. case USB_PORT_FEAT_SUSPEND:
  2704. if (temp & PORT_RESET)
  2705. goto error;
  2706. if (temp & PORT_SUSPEND) {
  2707. if ((temp & PORT_PE) == 0)
  2708. goto error;
  2709. /* resume signaling for 20 msec */
  2710. temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
  2711. writel(temp | PORT_RESUME, status_reg);
  2712. oxu->reset_done[wIndex] = jiffies
  2713. + msecs_to_jiffies(20);
  2714. }
  2715. break;
  2716. case USB_PORT_FEAT_C_SUSPEND:
  2717. /* we auto-clear this feature */
  2718. break;
  2719. case USB_PORT_FEAT_POWER:
  2720. if (HCS_PPC(oxu->hcs_params))
  2721. writel(temp & ~(PORT_RWC_BITS | PORT_POWER),
  2722. status_reg);
  2723. break;
  2724. case USB_PORT_FEAT_C_CONNECTION:
  2725. writel((temp & ~PORT_RWC_BITS) | PORT_CSC, status_reg);
  2726. break;
  2727. case USB_PORT_FEAT_C_OVER_CURRENT:
  2728. writel((temp & ~PORT_RWC_BITS) | PORT_OCC, status_reg);
  2729. break;
  2730. case USB_PORT_FEAT_C_RESET:
  2731. /* GetPortStatus clears reset */
  2732. break;
  2733. default:
  2734. goto error;
  2735. }
  2736. readl(&oxu->regs->command); /* unblock posted write */
  2737. break;
  2738. case GetHubDescriptor:
  2739. ehci_hub_descriptor(oxu, (struct usb_hub_descriptor *)
  2740. buf);
  2741. break;
  2742. case GetHubStatus:
  2743. /* no hub-wide feature/status flags */
  2744. memset(buf, 0, 4);
  2745. break;
  2746. case GetPortStatus:
  2747. if (!wIndex || wIndex > ports)
  2748. goto error;
  2749. wIndex--;
  2750. status = 0;
  2751. temp = readl(status_reg);
  2752. /* wPortChange bits */
  2753. if (temp & PORT_CSC)
  2754. status |= 1 << USB_PORT_FEAT_C_CONNECTION;
  2755. if (temp & PORT_PEC)
  2756. status |= 1 << USB_PORT_FEAT_C_ENABLE;
  2757. if ((temp & PORT_OCC) && !ignore_oc)
  2758. status |= 1 << USB_PORT_FEAT_C_OVER_CURRENT;
  2759. /* whoever resumes must GetPortStatus to complete it!! */
  2760. if (temp & PORT_RESUME) {
  2761. /* Remote Wakeup received? */
  2762. if (!oxu->reset_done[wIndex]) {
  2763. /* resume signaling for 20 msec */
  2764. oxu->reset_done[wIndex] = jiffies
  2765. + msecs_to_jiffies(20);
  2766. /* check the port again */
  2767. mod_timer(&oxu_to_hcd(oxu)->rh_timer,
  2768. oxu->reset_done[wIndex]);
  2769. }
  2770. /* resume completed? */
  2771. else if (time_after_eq(jiffies,
  2772. oxu->reset_done[wIndex])) {
  2773. status |= 1 << USB_PORT_FEAT_C_SUSPEND;
  2774. oxu->reset_done[wIndex] = 0;
  2775. /* stop resume signaling */
  2776. temp = readl(status_reg);
  2777. writel(temp & ~(PORT_RWC_BITS | PORT_RESUME),
  2778. status_reg);
  2779. retval = handshake(oxu, status_reg,
  2780. PORT_RESUME, 0, 2000 /* 2msec */);
  2781. if (retval != 0) {
  2782. oxu_err(oxu,
  2783. "port %d resume error %d\n",
  2784. wIndex + 1, retval);
  2785. goto error;
  2786. }
  2787. temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
  2788. }
  2789. }
  2790. /* whoever resets must GetPortStatus to complete it!! */
  2791. if ((temp & PORT_RESET)
  2792. && time_after_eq(jiffies,
  2793. oxu->reset_done[wIndex])) {
  2794. status |= 1 << USB_PORT_FEAT_C_RESET;
  2795. oxu->reset_done[wIndex] = 0;
  2796. /* force reset to complete */
  2797. writel(temp & ~(PORT_RWC_BITS | PORT_RESET),
  2798. status_reg);
  2799. /* REVISIT: some hardware needs 550+ usec to clear
  2800. * this bit; seems too long to spin routinely...
  2801. */
  2802. retval = handshake(oxu, status_reg,
  2803. PORT_RESET, 0, 750);
  2804. if (retval != 0) {
  2805. oxu_err(oxu, "port %d reset error %d\n",
  2806. wIndex + 1, retval);
  2807. goto error;
  2808. }
  2809. /* see what we found out */
  2810. temp = check_reset_complete(oxu, wIndex, status_reg,
  2811. readl(status_reg));
  2812. }
  2813. /* transfer dedicated ports to the companion hc */
  2814. if ((temp & PORT_CONNECT) &&
  2815. test_bit(wIndex, &oxu->companion_ports)) {
  2816. temp &= ~PORT_RWC_BITS;
  2817. temp |= PORT_OWNER;
  2818. writel(temp, status_reg);
  2819. oxu_dbg(oxu, "port %d --> companion\n", wIndex + 1);
  2820. temp = readl(status_reg);
  2821. }
  2822. /*
  2823. * Even if OWNER is set, there's no harm letting khubd
  2824. * see the wPortStatus values (they should all be 0 except
  2825. * for PORT_POWER anyway).
  2826. */
  2827. if (temp & PORT_CONNECT) {
  2828. status |= 1 << USB_PORT_FEAT_CONNECTION;
  2829. /* status may be from integrated TT */
  2830. status |= oxu_port_speed(oxu, temp);
  2831. }
  2832. if (temp & PORT_PE)
  2833. status |= 1 << USB_PORT_FEAT_ENABLE;
  2834. if (temp & (PORT_SUSPEND|PORT_RESUME))
  2835. status |= 1 << USB_PORT_FEAT_SUSPEND;
  2836. if (temp & PORT_OC)
  2837. status |= 1 << USB_PORT_FEAT_OVER_CURRENT;
  2838. if (temp & PORT_RESET)
  2839. status |= 1 << USB_PORT_FEAT_RESET;
  2840. if (temp & PORT_POWER)
  2841. status |= 1 << USB_PORT_FEAT_POWER;
  2842. #ifndef OXU_VERBOSE_DEBUG
  2843. if (status & ~0xffff) /* only if wPortChange is interesting */
  2844. #endif
  2845. dbg_port(oxu, "GetStatus", wIndex + 1, temp);
  2846. put_unaligned(cpu_to_le32(status), (__le32 *) buf);
  2847. break;
  2848. case SetHubFeature:
  2849. switch (wValue) {
  2850. case C_HUB_LOCAL_POWER:
  2851. case C_HUB_OVER_CURRENT:
  2852. /* no hub-wide feature/status flags */
  2853. break;
  2854. default:
  2855. goto error;
  2856. }
  2857. break;
  2858. case SetPortFeature:
  2859. selector = wIndex >> 8;
  2860. wIndex &= 0xff;
  2861. if (!wIndex || wIndex > ports)
  2862. goto error;
  2863. wIndex--;
  2864. temp = readl(status_reg);
  2865. if (temp & PORT_OWNER)
  2866. break;
  2867. temp &= ~PORT_RWC_BITS;
  2868. switch (wValue) {
  2869. case USB_PORT_FEAT_SUSPEND:
  2870. if ((temp & PORT_PE) == 0
  2871. || (temp & PORT_RESET) != 0)
  2872. goto error;
  2873. if (device_may_wakeup(&hcd->self.root_hub->dev))
  2874. temp |= PORT_WAKE_BITS;
  2875. writel(temp | PORT_SUSPEND, status_reg);
  2876. break;
  2877. case USB_PORT_FEAT_POWER:
  2878. if (HCS_PPC(oxu->hcs_params))
  2879. writel(temp | PORT_POWER, status_reg);
  2880. break;
  2881. case USB_PORT_FEAT_RESET:
  2882. if (temp & PORT_RESUME)
  2883. goto error;
  2884. /* line status bits may report this as low speed,
  2885. * which can be fine if this root hub has a
  2886. * transaction translator built in.
  2887. */
  2888. oxu_vdbg(oxu, "port %d reset\n", wIndex + 1);
  2889. temp |= PORT_RESET;
  2890. temp &= ~PORT_PE;
  2891. /*
  2892. * caller must wait, then call GetPortStatus
  2893. * usb 2.0 spec says 50 ms resets on root
  2894. */
  2895. oxu->reset_done[wIndex] = jiffies
  2896. + msecs_to_jiffies(50);
  2897. writel(temp, status_reg);
  2898. break;
  2899. /* For downstream facing ports (these): one hub port is put
  2900. * into test mode according to USB2 11.24.2.13, then the hub
  2901. * must be reset (which for root hub now means rmmod+modprobe,
  2902. * or else system reboot). See EHCI 2.3.9 and 4.14 for info
  2903. * about the EHCI-specific stuff.
  2904. */
  2905. case USB_PORT_FEAT_TEST:
  2906. if (!selector || selector > 5)
  2907. goto error;
  2908. ehci_quiesce(oxu);
  2909. ehci_halt(oxu);
  2910. temp |= selector << 16;
  2911. writel(temp, status_reg);
  2912. break;
  2913. default:
  2914. goto error;
  2915. }
  2916. readl(&oxu->regs->command); /* unblock posted writes */
  2917. break;
  2918. default:
  2919. error:
  2920. /* "stall" on error */
  2921. retval = -EPIPE;
  2922. }
  2923. spin_unlock_irqrestore(&oxu->lock, flags);
  2924. return retval;
  2925. }
  2926. #ifdef CONFIG_PM
  2927. static int oxu_bus_suspend(struct usb_hcd *hcd)
  2928. {
  2929. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2930. int port;
  2931. int mask;
  2932. oxu_dbg(oxu, "suspend root hub\n");
  2933. if (time_before(jiffies, oxu->next_statechange))
  2934. msleep(5);
  2935. port = HCS_N_PORTS(oxu->hcs_params);
  2936. spin_lock_irq(&oxu->lock);
  2937. /* stop schedules, clean any completed work */
  2938. if (HC_IS_RUNNING(hcd->state)) {
  2939. ehci_quiesce(oxu);
  2940. hcd->state = HC_STATE_QUIESCING;
  2941. }
  2942. oxu->command = readl(&oxu->regs->command);
  2943. if (oxu->reclaim)
  2944. oxu->reclaim_ready = 1;
  2945. ehci_work(oxu);
  2946. /* Unlike other USB host controller types, EHCI doesn't have
  2947. * any notion of "global" or bus-wide suspend. The driver has
  2948. * to manually suspend all the active unsuspended ports, and
  2949. * then manually resume them in the bus_resume() routine.
  2950. */
  2951. oxu->bus_suspended = 0;
  2952. while (port--) {
  2953. u32 __iomem *reg = &oxu->regs->port_status[port];
  2954. u32 t1 = readl(reg) & ~PORT_RWC_BITS;
  2955. u32 t2 = t1;
  2956. /* keep track of which ports we suspend */
  2957. if ((t1 & PORT_PE) && !(t1 & PORT_OWNER) &&
  2958. !(t1 & PORT_SUSPEND)) {
  2959. t2 |= PORT_SUSPEND;
  2960. set_bit(port, &oxu->bus_suspended);
  2961. }
  2962. /* enable remote wakeup on all ports */
  2963. if (device_may_wakeup(&hcd->self.root_hub->dev))
  2964. t2 |= PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E;
  2965. else
  2966. t2 &= ~(PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E);
  2967. if (t1 != t2) {
  2968. oxu_vdbg(oxu, "port %d, %08x -> %08x\n",
  2969. port + 1, t1, t2);
  2970. writel(t2, reg);
  2971. }
  2972. }
  2973. /* turn off now-idle HC */
  2974. del_timer_sync(&oxu->watchdog);
  2975. ehci_halt(oxu);
  2976. hcd->state = HC_STATE_SUSPENDED;
  2977. /* allow remote wakeup */
  2978. mask = INTR_MASK;
  2979. if (!device_may_wakeup(&hcd->self.root_hub->dev))
  2980. mask &= ~STS_PCD;
  2981. writel(mask, &oxu->regs->intr_enable);
  2982. readl(&oxu->regs->intr_enable);
  2983. oxu->next_statechange = jiffies + msecs_to_jiffies(10);
  2984. spin_unlock_irq(&oxu->lock);
  2985. return 0;
  2986. }
  2987. /* Caller has locked the root hub, and should reset/reinit on error */
  2988. static int oxu_bus_resume(struct usb_hcd *hcd)
  2989. {
  2990. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2991. u32 temp;
  2992. int i;
  2993. if (time_before(jiffies, oxu->next_statechange))
  2994. msleep(5);
  2995. spin_lock_irq(&oxu->lock);
  2996. /* Ideally and we've got a real resume here, and no port's power
  2997. * was lost. (For PCI, that means Vaux was maintained.) But we
  2998. * could instead be restoring a swsusp snapshot -- so that BIOS was
  2999. * the last user of the controller, not reset/pm hardware keeping
  3000. * state we gave to it.
  3001. */
  3002. temp = readl(&oxu->regs->intr_enable);
  3003. oxu_dbg(oxu, "resume root hub%s\n", temp ? "" : " after power loss");
  3004. /* at least some APM implementations will try to deliver
  3005. * IRQs right away, so delay them until we're ready.
  3006. */
  3007. writel(0, &oxu->regs->intr_enable);
  3008. /* re-init operational registers */
  3009. writel(0, &oxu->regs->segment);
  3010. writel(oxu->periodic_dma, &oxu->regs->frame_list);
  3011. writel((u32) oxu->async->qh_dma, &oxu->regs->async_next);
  3012. /* restore CMD_RUN, framelist size, and irq threshold */
  3013. writel(oxu->command, &oxu->regs->command);
  3014. /* Some controller/firmware combinations need a delay during which
  3015. * they set up the port statuses. See Bugzilla #8190. */
  3016. mdelay(8);
  3017. /* manually resume the ports we suspended during bus_suspend() */
  3018. i = HCS_N_PORTS(oxu->hcs_params);
  3019. while (i--) {
  3020. temp = readl(&oxu->regs->port_status[i]);
  3021. temp &= ~(PORT_RWC_BITS
  3022. | PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E);
  3023. if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) {
  3024. oxu->reset_done[i] = jiffies + msecs_to_jiffies(20);
  3025. temp |= PORT_RESUME;
  3026. }
  3027. writel(temp, &oxu->regs->port_status[i]);
  3028. }
  3029. i = HCS_N_PORTS(oxu->hcs_params);
  3030. mdelay(20);
  3031. while (i--) {
  3032. temp = readl(&oxu->regs->port_status[i]);
  3033. if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) {
  3034. temp &= ~(PORT_RWC_BITS | PORT_RESUME);
  3035. writel(temp, &oxu->regs->port_status[i]);
  3036. oxu_vdbg(oxu, "resumed port %d\n", i + 1);
  3037. }
  3038. }
  3039. (void) readl(&oxu->regs->command);
  3040. /* maybe re-activate the schedule(s) */
  3041. temp = 0;
  3042. if (oxu->async->qh_next.qh)
  3043. temp |= CMD_ASE;
  3044. if (oxu->periodic_sched)
  3045. temp |= CMD_PSE;
  3046. if (temp) {
  3047. oxu->command |= temp;
  3048. writel(oxu->command, &oxu->regs->command);
  3049. }
  3050. oxu->next_statechange = jiffies + msecs_to_jiffies(5);
  3051. hcd->state = HC_STATE_RUNNING;
  3052. /* Now we can safely re-enable irqs */
  3053. writel(INTR_MASK, &oxu->regs->intr_enable);
  3054. spin_unlock_irq(&oxu->lock);
  3055. return 0;
  3056. }
  3057. #else
  3058. static int oxu_bus_suspend(struct usb_hcd *hcd)
  3059. {
  3060. return 0;
  3061. }
  3062. static int oxu_bus_resume(struct usb_hcd *hcd)
  3063. {
  3064. return 0;
  3065. }
  3066. #endif /* CONFIG_PM */
  3067. static const struct hc_driver oxu_hc_driver = {
  3068. .description = "oxu210hp_hcd",
  3069. .product_desc = "oxu210hp HCD",
  3070. .hcd_priv_size = sizeof(struct oxu_hcd),
  3071. /*
  3072. * Generic hardware linkage
  3073. */
  3074. .irq = oxu_irq,
  3075. .flags = HCD_MEMORY | HCD_USB2,
  3076. /*
  3077. * Basic lifecycle operations
  3078. */
  3079. .reset = oxu_reset,
  3080. .start = oxu_run,
  3081. .stop = oxu_stop,
  3082. .shutdown = oxu_shutdown,
  3083. /*
  3084. * Managing i/o requests and associated device resources
  3085. */
  3086. .urb_enqueue = oxu_urb_enqueue,
  3087. .urb_dequeue = oxu_urb_dequeue,
  3088. .endpoint_disable = oxu_endpoint_disable,
  3089. /*
  3090. * Scheduling support
  3091. */
  3092. .get_frame_number = oxu_get_frame,
  3093. /*
  3094. * Root hub support
  3095. */
  3096. .hub_status_data = oxu_hub_status_data,
  3097. .hub_control = oxu_hub_control,
  3098. .bus_suspend = oxu_bus_suspend,
  3099. .bus_resume = oxu_bus_resume,
  3100. };
  3101. /*
  3102. * Module stuff
  3103. */
  3104. static void oxu_configuration(struct platform_device *pdev, void *base)
  3105. {
  3106. u32 tmp;
  3107. /* Initialize top level registers.
  3108. * First write ever
  3109. */
  3110. oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D);
  3111. oxu_writel(base, OXU_SOFTRESET, OXU_SRESET);
  3112. oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D);
  3113. tmp = oxu_readl(base, OXU_PIOBURSTREADCTRL);
  3114. oxu_writel(base, OXU_PIOBURSTREADCTRL, tmp | 0x0040);
  3115. oxu_writel(base, OXU_ASO, OXU_SPHPOEN | OXU_OVRCCURPUPDEN |
  3116. OXU_COMPARATOR | OXU_ASO_OP);
  3117. tmp = oxu_readl(base, OXU_CLKCTRL_SET);
  3118. oxu_writel(base, OXU_CLKCTRL_SET, tmp | OXU_SYSCLKEN | OXU_USBOTGCLKEN);
  3119. /* Clear all top interrupt enable */
  3120. oxu_writel(base, OXU_CHIPIRQEN_CLR, 0xff);
  3121. /* Clear all top interrupt status */
  3122. oxu_writel(base, OXU_CHIPIRQSTATUS, 0xff);
  3123. /* Enable all needed top interrupt except OTG SPH core */
  3124. oxu_writel(base, OXU_CHIPIRQEN_SET, OXU_USBSPHLPWUI | OXU_USBOTGLPWUI);
  3125. }
  3126. static int oxu_verify_id(struct platform_device *pdev, void *base)
  3127. {
  3128. u32 id;
  3129. char *bo[] = {
  3130. "reserved",
  3131. "128-pin LQFP",
  3132. "84-pin TFBGA",
  3133. "reserved",
  3134. };
  3135. /* Read controller signature register to find a match */
  3136. id = oxu_readl(base, OXU_DEVICEID);
  3137. dev_info(&pdev->dev, "device ID %x\n", id);
  3138. if ((id & OXU_REV_MASK) != (OXU_REV_2100 << OXU_REV_SHIFT))
  3139. return -1;
  3140. dev_info(&pdev->dev, "found device %x %s (%04x:%04x)\n",
  3141. id >> OXU_REV_SHIFT,
  3142. bo[(id & OXU_BO_MASK) >> OXU_BO_SHIFT],
  3143. (id & OXU_MAJ_REV_MASK) >> OXU_MAJ_REV_SHIFT,
  3144. (id & OXU_MIN_REV_MASK) >> OXU_MIN_REV_SHIFT);
  3145. return 0;
  3146. }
  3147. static const struct hc_driver oxu_hc_driver;
  3148. static struct usb_hcd *oxu_create(struct platform_device *pdev,
  3149. unsigned long memstart, unsigned long memlen,
  3150. void *base, int irq, int otg)
  3151. {
  3152. struct device *dev = &pdev->dev;
  3153. struct usb_hcd *hcd;
  3154. struct oxu_hcd *oxu;
  3155. int ret;
  3156. /* Set endian mode and host mode */
  3157. oxu_writel(base + (otg ? OXU_OTG_CORE_OFFSET : OXU_SPH_CORE_OFFSET),
  3158. OXU_USBMODE,
  3159. OXU_CM_HOST_ONLY | OXU_ES_LITTLE | OXU_VBPS);
  3160. hcd = usb_create_hcd(&oxu_hc_driver, dev,
  3161. otg ? "oxu210hp_otg" : "oxu210hp_sph");
  3162. if (!hcd)
  3163. return ERR_PTR(-ENOMEM);
  3164. hcd->rsrc_start = memstart;
  3165. hcd->rsrc_len = memlen;
  3166. hcd->regs = base;
  3167. hcd->irq = irq;
  3168. hcd->state = HC_STATE_HALT;
  3169. oxu = hcd_to_oxu(hcd);
  3170. oxu->is_otg = otg;
  3171. ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
  3172. if (ret < 0)
  3173. return ERR_PTR(ret);
  3174. return hcd;
  3175. }
  3176. static int oxu_init(struct platform_device *pdev,
  3177. unsigned long memstart, unsigned long memlen,
  3178. void *base, int irq)
  3179. {
  3180. struct oxu_info *info = platform_get_drvdata(pdev);
  3181. struct usb_hcd *hcd;
  3182. int ret;
  3183. /* First time configuration at start up */
  3184. oxu_configuration(pdev, base);
  3185. ret = oxu_verify_id(pdev, base);
  3186. if (ret) {
  3187. dev_err(&pdev->dev, "no devices found!\n");
  3188. return -ENODEV;
  3189. }
  3190. /* Create the OTG controller */
  3191. hcd = oxu_create(pdev, memstart, memlen, base, irq, 1);
  3192. if (IS_ERR(hcd)) {
  3193. dev_err(&pdev->dev, "cannot create OTG controller!\n");
  3194. ret = PTR_ERR(hcd);
  3195. goto error_create_otg;
  3196. }
  3197. info->hcd[0] = hcd;
  3198. /* Create the SPH host controller */
  3199. hcd = oxu_create(pdev, memstart, memlen, base, irq, 0);
  3200. if (IS_ERR(hcd)) {
  3201. dev_err(&pdev->dev, "cannot create SPH controller!\n");
  3202. ret = PTR_ERR(hcd);
  3203. goto error_create_sph;
  3204. }
  3205. info->hcd[1] = hcd;
  3206. oxu_writel(base, OXU_CHIPIRQEN_SET,
  3207. oxu_readl(base, OXU_CHIPIRQEN_SET) | 3);
  3208. return 0;
  3209. error_create_sph:
  3210. usb_remove_hcd(info->hcd[0]);
  3211. usb_put_hcd(info->hcd[0]);
  3212. error_create_otg:
  3213. return ret;
  3214. }
  3215. static int oxu_drv_probe(struct platform_device *pdev)
  3216. {
  3217. struct resource *res;
  3218. void *base;
  3219. unsigned long memstart, memlen;
  3220. int irq, ret;
  3221. struct oxu_info *info;
  3222. if (usb_disabled())
  3223. return -ENODEV;
  3224. /*
  3225. * Get the platform resources
  3226. */
  3227. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  3228. if (!res) {
  3229. dev_err(&pdev->dev,
  3230. "no IRQ! Check %s setup!\n", dev_name(&pdev->dev));
  3231. return -ENODEV;
  3232. }
  3233. irq = res->start;
  3234. dev_dbg(&pdev->dev, "IRQ resource %d\n", irq);
  3235. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  3236. if (!res) {
  3237. dev_err(&pdev->dev, "no registers address! Check %s setup!\n",
  3238. dev_name(&pdev->dev));
  3239. return -ENODEV;
  3240. }
  3241. memstart = res->start;
  3242. memlen = res->end - res->start + 1;
  3243. dev_dbg(&pdev->dev, "MEM resource %lx-%lx\n", memstart, memlen);
  3244. if (!request_mem_region(memstart, memlen,
  3245. oxu_hc_driver.description)) {
  3246. dev_dbg(&pdev->dev, "memory area already in use\n");
  3247. return -EBUSY;
  3248. }
  3249. ret = set_irq_type(irq, IRQF_TRIGGER_FALLING);
  3250. if (ret) {
  3251. dev_err(&pdev->dev, "error setting irq type\n");
  3252. ret = -EFAULT;
  3253. goto error_set_irq_type;
  3254. }
  3255. base = ioremap(memstart, memlen);
  3256. if (!base) {
  3257. dev_dbg(&pdev->dev, "error mapping memory\n");
  3258. ret = -EFAULT;
  3259. goto error_ioremap;
  3260. }
  3261. /* Allocate a driver data struct to hold useful info for both
  3262. * SPH & OTG devices
  3263. */
  3264. info = kzalloc(sizeof(struct oxu_info), GFP_KERNEL);
  3265. if (!info) {
  3266. dev_dbg(&pdev->dev, "error allocating memory\n");
  3267. ret = -EFAULT;
  3268. goto error_alloc;
  3269. }
  3270. platform_set_drvdata(pdev, info);
  3271. ret = oxu_init(pdev, memstart, memlen, base, irq);
  3272. if (ret < 0) {
  3273. dev_dbg(&pdev->dev, "cannot init USB devices\n");
  3274. goto error_init;
  3275. }
  3276. dev_info(&pdev->dev, "devices enabled and running\n");
  3277. platform_set_drvdata(pdev, info);
  3278. return 0;
  3279. error_init:
  3280. kfree(info);
  3281. platform_set_drvdata(pdev, NULL);
  3282. error_alloc:
  3283. iounmap(base);
  3284. error_set_irq_type:
  3285. error_ioremap:
  3286. release_mem_region(memstart, memlen);
  3287. dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), ret);
  3288. return ret;
  3289. }
  3290. static void oxu_remove(struct platform_device *pdev, struct usb_hcd *hcd)
  3291. {
  3292. usb_remove_hcd(hcd);
  3293. usb_put_hcd(hcd);
  3294. }
  3295. static int oxu_drv_remove(struct platform_device *pdev)
  3296. {
  3297. struct oxu_info *info = platform_get_drvdata(pdev);
  3298. unsigned long memstart = info->hcd[0]->rsrc_start,
  3299. memlen = info->hcd[0]->rsrc_len;
  3300. void *base = info->hcd[0]->regs;
  3301. oxu_remove(pdev, info->hcd[0]);
  3302. oxu_remove(pdev, info->hcd[1]);
  3303. iounmap(base);
  3304. release_mem_region(memstart, memlen);
  3305. kfree(info);
  3306. platform_set_drvdata(pdev, NULL);
  3307. return 0;
  3308. }
  3309. static void oxu_drv_shutdown(struct platform_device *pdev)
  3310. {
  3311. oxu_drv_remove(pdev);
  3312. }
  3313. #if 0
  3314. /* FIXME: TODO */
  3315. static int oxu_drv_suspend(struct device *dev)
  3316. {
  3317. struct platform_device *pdev = to_platform_device(dev);
  3318. struct usb_hcd *hcd = dev_get_drvdata(dev);
  3319. return 0;
  3320. }
  3321. static int oxu_drv_resume(struct device *dev)
  3322. {
  3323. struct platform_device *pdev = to_platform_device(dev);
  3324. struct usb_hcd *hcd = dev_get_drvdata(dev);
  3325. return 0;
  3326. }
  3327. #else
  3328. #define oxu_drv_suspend NULL
  3329. #define oxu_drv_resume NULL
  3330. #endif
  3331. static struct platform_driver oxu_driver = {
  3332. .probe = oxu_drv_probe,
  3333. .remove = oxu_drv_remove,
  3334. .shutdown = oxu_drv_shutdown,
  3335. .suspend = oxu_drv_suspend,
  3336. .resume = oxu_drv_resume,
  3337. .driver = {
  3338. .name = "oxu210hp-hcd",
  3339. .bus = &platform_bus_type
  3340. }
  3341. };
  3342. static int __init oxu_module_init(void)
  3343. {
  3344. int retval = 0;
  3345. retval = platform_driver_register(&oxu_driver);
  3346. if (retval < 0)
  3347. return retval;
  3348. return retval;
  3349. }
  3350. static void __exit oxu_module_cleanup(void)
  3351. {
  3352. platform_driver_unregister(&oxu_driver);
  3353. }
  3354. module_init(oxu_module_init);
  3355. module_exit(oxu_module_cleanup);
  3356. MODULE_DESCRIPTION("Oxford OXU210HP HCD driver - ver. " DRIVER_VERSION);
  3357. MODULE_AUTHOR("Rodolfo Giometti <giometti@linux.it>");
  3358. MODULE_LICENSE("GPL");