r8a66597-udc.c 41 KB

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  1. /*
  2. * R8A66597 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2009 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/clk.h>
  28. #include <linux/usb/ch9.h>
  29. #include <linux/usb/gadget.h>
  30. #include "r8a66597-udc.h"
  31. #define DRIVER_VERSION "2009-08-18"
  32. static const char udc_name[] = "r8a66597_udc";
  33. static const char *r8a66597_ep_name[] = {
  34. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7",
  35. "ep8", "ep9",
  36. };
  37. static void disable_controller(struct r8a66597 *r8a66597);
  38. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req);
  39. static void irq_packet_write(struct r8a66597_ep *ep,
  40. struct r8a66597_request *req);
  41. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  42. gfp_t gfp_flags);
  43. static void transfer_complete(struct r8a66597_ep *ep,
  44. struct r8a66597_request *req, int status);
  45. /*-------------------------------------------------------------------------*/
  46. static inline u16 get_usb_speed(struct r8a66597 *r8a66597)
  47. {
  48. return r8a66597_read(r8a66597, DVSTCTR0) & RHST;
  49. }
  50. static void enable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  51. unsigned long reg)
  52. {
  53. u16 tmp;
  54. tmp = r8a66597_read(r8a66597, INTENB0);
  55. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  56. INTENB0);
  57. r8a66597_bset(r8a66597, (1 << pipenum), reg);
  58. r8a66597_write(r8a66597, tmp, INTENB0);
  59. }
  60. static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  61. unsigned long reg)
  62. {
  63. u16 tmp;
  64. tmp = r8a66597_read(r8a66597, INTENB0);
  65. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  66. INTENB0);
  67. r8a66597_bclr(r8a66597, (1 << pipenum), reg);
  68. r8a66597_write(r8a66597, tmp, INTENB0);
  69. }
  70. static void r8a66597_usb_connect(struct r8a66597 *r8a66597)
  71. {
  72. r8a66597_bset(r8a66597, CTRE, INTENB0);
  73. r8a66597_bset(r8a66597, BEMPE | BRDYE, INTENB0);
  74. r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
  75. }
  76. static void r8a66597_usb_disconnect(struct r8a66597 *r8a66597)
  77. __releases(r8a66597->lock)
  78. __acquires(r8a66597->lock)
  79. {
  80. r8a66597_bclr(r8a66597, CTRE, INTENB0);
  81. r8a66597_bclr(r8a66597, BEMPE | BRDYE, INTENB0);
  82. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  83. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  84. spin_unlock(&r8a66597->lock);
  85. r8a66597->driver->disconnect(&r8a66597->gadget);
  86. spin_lock(&r8a66597->lock);
  87. disable_controller(r8a66597);
  88. INIT_LIST_HEAD(&r8a66597->ep[0].queue);
  89. }
  90. static inline u16 control_reg_get_pid(struct r8a66597 *r8a66597, u16 pipenum)
  91. {
  92. u16 pid = 0;
  93. unsigned long offset;
  94. if (pipenum == 0)
  95. pid = r8a66597_read(r8a66597, DCPCTR) & PID;
  96. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  97. offset = get_pipectr_addr(pipenum);
  98. pid = r8a66597_read(r8a66597, offset) & PID;
  99. } else
  100. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  101. return pid;
  102. }
  103. static inline void control_reg_set_pid(struct r8a66597 *r8a66597, u16 pipenum,
  104. u16 pid)
  105. {
  106. unsigned long offset;
  107. if (pipenum == 0)
  108. r8a66597_mdfy(r8a66597, pid, PID, DCPCTR);
  109. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  110. offset = get_pipectr_addr(pipenum);
  111. r8a66597_mdfy(r8a66597, pid, PID, offset);
  112. } else
  113. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  114. }
  115. static inline void pipe_start(struct r8a66597 *r8a66597, u16 pipenum)
  116. {
  117. control_reg_set_pid(r8a66597, pipenum, PID_BUF);
  118. }
  119. static inline void pipe_stop(struct r8a66597 *r8a66597, u16 pipenum)
  120. {
  121. control_reg_set_pid(r8a66597, pipenum, PID_NAK);
  122. }
  123. static inline void pipe_stall(struct r8a66597 *r8a66597, u16 pipenum)
  124. {
  125. control_reg_set_pid(r8a66597, pipenum, PID_STALL);
  126. }
  127. static inline u16 control_reg_get(struct r8a66597 *r8a66597, u16 pipenum)
  128. {
  129. u16 ret = 0;
  130. unsigned long offset;
  131. if (pipenum == 0)
  132. ret = r8a66597_read(r8a66597, DCPCTR);
  133. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  134. offset = get_pipectr_addr(pipenum);
  135. ret = r8a66597_read(r8a66597, offset);
  136. } else
  137. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  138. return ret;
  139. }
  140. static inline void control_reg_sqclr(struct r8a66597 *r8a66597, u16 pipenum)
  141. {
  142. unsigned long offset;
  143. pipe_stop(r8a66597, pipenum);
  144. if (pipenum == 0)
  145. r8a66597_bset(r8a66597, SQCLR, DCPCTR);
  146. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  147. offset = get_pipectr_addr(pipenum);
  148. r8a66597_bset(r8a66597, SQCLR, offset);
  149. } else
  150. printk(KERN_ERR "unexpect pipe num(%d)\n", pipenum);
  151. }
  152. static inline int get_buffer_size(struct r8a66597 *r8a66597, u16 pipenum)
  153. {
  154. u16 tmp;
  155. int size;
  156. if (pipenum == 0) {
  157. tmp = r8a66597_read(r8a66597, DCPCFG);
  158. if ((tmp & R8A66597_CNTMD) != 0)
  159. size = 256;
  160. else {
  161. tmp = r8a66597_read(r8a66597, DCPMAXP);
  162. size = tmp & MAXP;
  163. }
  164. } else {
  165. r8a66597_write(r8a66597, pipenum, PIPESEL);
  166. tmp = r8a66597_read(r8a66597, PIPECFG);
  167. if ((tmp & R8A66597_CNTMD) != 0) {
  168. tmp = r8a66597_read(r8a66597, PIPEBUF);
  169. size = ((tmp >> 10) + 1) * 64;
  170. } else {
  171. tmp = r8a66597_read(r8a66597, PIPEMAXP);
  172. size = tmp & MXPS;
  173. }
  174. }
  175. return size;
  176. }
  177. static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
  178. {
  179. if (r8a66597->pdata->on_chip)
  180. return MBW_32;
  181. else
  182. return MBW_16;
  183. }
  184. static inline void pipe_change(struct r8a66597 *r8a66597, u16 pipenum)
  185. {
  186. struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
  187. if (ep->use_dma)
  188. return;
  189. r8a66597_mdfy(r8a66597, pipenum, CURPIPE, ep->fifosel);
  190. ndelay(450);
  191. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  192. }
  193. static int pipe_buffer_setting(struct r8a66597 *r8a66597,
  194. struct r8a66597_pipe_info *info)
  195. {
  196. u16 bufnum = 0, buf_bsize = 0;
  197. u16 pipecfg = 0;
  198. if (info->pipe == 0)
  199. return -EINVAL;
  200. r8a66597_write(r8a66597, info->pipe, PIPESEL);
  201. if (info->dir_in)
  202. pipecfg |= R8A66597_DIR;
  203. pipecfg |= info->type;
  204. pipecfg |= info->epnum;
  205. switch (info->type) {
  206. case R8A66597_INT:
  207. bufnum = 4 + (info->pipe - R8A66597_BASE_PIPENUM_INT);
  208. buf_bsize = 0;
  209. break;
  210. case R8A66597_BULK:
  211. /* isochronous pipes may be used as bulk pipes */
  212. if (info->pipe > R8A66597_BASE_PIPENUM_BULK)
  213. bufnum = info->pipe - R8A66597_BASE_PIPENUM_BULK;
  214. else
  215. bufnum = info->pipe - R8A66597_BASE_PIPENUM_ISOC;
  216. bufnum = R8A66597_BASE_BUFNUM + (bufnum * 16);
  217. buf_bsize = 7;
  218. pipecfg |= R8A66597_DBLB;
  219. if (!info->dir_in)
  220. pipecfg |= R8A66597_SHTNAK;
  221. break;
  222. case R8A66597_ISO:
  223. bufnum = R8A66597_BASE_BUFNUM +
  224. (info->pipe - R8A66597_BASE_PIPENUM_ISOC) * 16;
  225. buf_bsize = 7;
  226. break;
  227. }
  228. if (buf_bsize && ((bufnum + 16) >= R8A66597_MAX_BUFNUM)) {
  229. pr_err(KERN_ERR "r8a66597 pipe memory is insufficient\n");
  230. return -ENOMEM;
  231. }
  232. r8a66597_write(r8a66597, pipecfg, PIPECFG);
  233. r8a66597_write(r8a66597, (buf_bsize << 10) | (bufnum), PIPEBUF);
  234. r8a66597_write(r8a66597, info->maxpacket, PIPEMAXP);
  235. if (info->interval)
  236. info->interval--;
  237. r8a66597_write(r8a66597, info->interval, PIPEPERI);
  238. return 0;
  239. }
  240. static void pipe_buffer_release(struct r8a66597 *r8a66597,
  241. struct r8a66597_pipe_info *info)
  242. {
  243. if (info->pipe == 0)
  244. return;
  245. if (is_bulk_pipe(info->pipe))
  246. r8a66597->bulk--;
  247. else if (is_interrupt_pipe(info->pipe))
  248. r8a66597->interrupt--;
  249. else if (is_isoc_pipe(info->pipe)) {
  250. r8a66597->isochronous--;
  251. if (info->type == R8A66597_BULK)
  252. r8a66597->bulk--;
  253. } else
  254. printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
  255. info->pipe);
  256. }
  257. static void pipe_initialize(struct r8a66597_ep *ep)
  258. {
  259. struct r8a66597 *r8a66597 = ep->r8a66597;
  260. r8a66597_mdfy(r8a66597, 0, CURPIPE, ep->fifosel);
  261. r8a66597_write(r8a66597, ACLRM, ep->pipectr);
  262. r8a66597_write(r8a66597, 0, ep->pipectr);
  263. r8a66597_write(r8a66597, SQCLR, ep->pipectr);
  264. if (ep->use_dma) {
  265. r8a66597_mdfy(r8a66597, ep->pipenum, CURPIPE, ep->fifosel);
  266. ndelay(450);
  267. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  268. }
  269. }
  270. static void r8a66597_ep_setting(struct r8a66597 *r8a66597,
  271. struct r8a66597_ep *ep,
  272. const struct usb_endpoint_descriptor *desc,
  273. u16 pipenum, int dma)
  274. {
  275. ep->use_dma = 0;
  276. ep->fifoaddr = CFIFO;
  277. ep->fifosel = CFIFOSEL;
  278. ep->fifoctr = CFIFOCTR;
  279. ep->fifotrn = 0;
  280. ep->pipectr = get_pipectr_addr(pipenum);
  281. ep->pipenum = pipenum;
  282. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  283. r8a66597->pipenum2ep[pipenum] = ep;
  284. r8a66597->epaddr2ep[desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK]
  285. = ep;
  286. INIT_LIST_HEAD(&ep->queue);
  287. }
  288. static void r8a66597_ep_release(struct r8a66597_ep *ep)
  289. {
  290. struct r8a66597 *r8a66597 = ep->r8a66597;
  291. u16 pipenum = ep->pipenum;
  292. if (pipenum == 0)
  293. return;
  294. if (ep->use_dma)
  295. r8a66597->num_dma--;
  296. ep->pipenum = 0;
  297. ep->busy = 0;
  298. ep->use_dma = 0;
  299. }
  300. static int alloc_pipe_config(struct r8a66597_ep *ep,
  301. const struct usb_endpoint_descriptor *desc)
  302. {
  303. struct r8a66597 *r8a66597 = ep->r8a66597;
  304. struct r8a66597_pipe_info info;
  305. int dma = 0;
  306. unsigned char *counter;
  307. int ret;
  308. ep->desc = desc;
  309. if (ep->pipenum) /* already allocated pipe */
  310. return 0;
  311. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  312. case USB_ENDPOINT_XFER_BULK:
  313. if (r8a66597->bulk >= R8A66597_MAX_NUM_BULK) {
  314. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  315. printk(KERN_ERR "bulk pipe is insufficient\n");
  316. return -ENODEV;
  317. } else {
  318. info.pipe = R8A66597_BASE_PIPENUM_ISOC
  319. + r8a66597->isochronous;
  320. counter = &r8a66597->isochronous;
  321. }
  322. } else {
  323. info.pipe = R8A66597_BASE_PIPENUM_BULK + r8a66597->bulk;
  324. counter = &r8a66597->bulk;
  325. }
  326. info.type = R8A66597_BULK;
  327. dma = 1;
  328. break;
  329. case USB_ENDPOINT_XFER_INT:
  330. if (r8a66597->interrupt >= R8A66597_MAX_NUM_INT) {
  331. printk(KERN_ERR "interrupt pipe is insufficient\n");
  332. return -ENODEV;
  333. }
  334. info.pipe = R8A66597_BASE_PIPENUM_INT + r8a66597->interrupt;
  335. info.type = R8A66597_INT;
  336. counter = &r8a66597->interrupt;
  337. break;
  338. case USB_ENDPOINT_XFER_ISOC:
  339. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  340. printk(KERN_ERR "isochronous pipe is insufficient\n");
  341. return -ENODEV;
  342. }
  343. info.pipe = R8A66597_BASE_PIPENUM_ISOC + r8a66597->isochronous;
  344. info.type = R8A66597_ISO;
  345. counter = &r8a66597->isochronous;
  346. break;
  347. default:
  348. printk(KERN_ERR "unexpect xfer type\n");
  349. return -EINVAL;
  350. }
  351. ep->type = info.type;
  352. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  353. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  354. info.interval = desc->bInterval;
  355. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  356. info.dir_in = 1;
  357. else
  358. info.dir_in = 0;
  359. ret = pipe_buffer_setting(r8a66597, &info);
  360. if (ret < 0) {
  361. printk(KERN_ERR "pipe_buffer_setting fail\n");
  362. return ret;
  363. }
  364. (*counter)++;
  365. if ((counter == &r8a66597->isochronous) && info.type == R8A66597_BULK)
  366. r8a66597->bulk++;
  367. r8a66597_ep_setting(r8a66597, ep, desc, info.pipe, dma);
  368. pipe_initialize(ep);
  369. return 0;
  370. }
  371. static int free_pipe_config(struct r8a66597_ep *ep)
  372. {
  373. struct r8a66597 *r8a66597 = ep->r8a66597;
  374. struct r8a66597_pipe_info info;
  375. info.pipe = ep->pipenum;
  376. info.type = ep->type;
  377. pipe_buffer_release(r8a66597, &info);
  378. r8a66597_ep_release(ep);
  379. return 0;
  380. }
  381. /*-------------------------------------------------------------------------*/
  382. static void pipe_irq_enable(struct r8a66597 *r8a66597, u16 pipenum)
  383. {
  384. enable_irq_ready(r8a66597, pipenum);
  385. enable_irq_nrdy(r8a66597, pipenum);
  386. }
  387. static void pipe_irq_disable(struct r8a66597 *r8a66597, u16 pipenum)
  388. {
  389. disable_irq_ready(r8a66597, pipenum);
  390. disable_irq_nrdy(r8a66597, pipenum);
  391. }
  392. /* if complete is true, gadget driver complete function is not call */
  393. static void control_end(struct r8a66597 *r8a66597, unsigned ccpl)
  394. {
  395. r8a66597->ep[0].internal_ccpl = ccpl;
  396. pipe_start(r8a66597, 0);
  397. r8a66597_bset(r8a66597, CCPL, DCPCTR);
  398. }
  399. static void start_ep0_write(struct r8a66597_ep *ep,
  400. struct r8a66597_request *req)
  401. {
  402. struct r8a66597 *r8a66597 = ep->r8a66597;
  403. pipe_change(r8a66597, ep->pipenum);
  404. r8a66597_mdfy(r8a66597, ISEL, (ISEL | CURPIPE), CFIFOSEL);
  405. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  406. if (req->req.length == 0) {
  407. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  408. pipe_start(r8a66597, 0);
  409. transfer_complete(ep, req, 0);
  410. } else {
  411. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  412. irq_ep0_write(ep, req);
  413. }
  414. }
  415. static void start_packet_write(struct r8a66597_ep *ep,
  416. struct r8a66597_request *req)
  417. {
  418. struct r8a66597 *r8a66597 = ep->r8a66597;
  419. u16 tmp;
  420. pipe_change(r8a66597, ep->pipenum);
  421. disable_irq_empty(r8a66597, ep->pipenum);
  422. pipe_start(r8a66597, ep->pipenum);
  423. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  424. if (unlikely((tmp & FRDY) == 0))
  425. pipe_irq_enable(r8a66597, ep->pipenum);
  426. else
  427. irq_packet_write(ep, req);
  428. }
  429. static void start_packet_read(struct r8a66597_ep *ep,
  430. struct r8a66597_request *req)
  431. {
  432. struct r8a66597 *r8a66597 = ep->r8a66597;
  433. u16 pipenum = ep->pipenum;
  434. if (ep->pipenum == 0) {
  435. r8a66597_mdfy(r8a66597, 0, (ISEL | CURPIPE), CFIFOSEL);
  436. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  437. pipe_start(r8a66597, pipenum);
  438. pipe_irq_enable(r8a66597, pipenum);
  439. } else {
  440. if (ep->use_dma) {
  441. r8a66597_bset(r8a66597, TRCLR, ep->fifosel);
  442. pipe_change(r8a66597, pipenum);
  443. r8a66597_bset(r8a66597, TRENB, ep->fifosel);
  444. r8a66597_write(r8a66597,
  445. (req->req.length + ep->ep.maxpacket - 1)
  446. / ep->ep.maxpacket,
  447. ep->fifotrn);
  448. }
  449. pipe_start(r8a66597, pipenum); /* trigger once */
  450. pipe_irq_enable(r8a66597, pipenum);
  451. }
  452. }
  453. static void start_packet(struct r8a66597_ep *ep, struct r8a66597_request *req)
  454. {
  455. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  456. start_packet_write(ep, req);
  457. else
  458. start_packet_read(ep, req);
  459. }
  460. static void start_ep0(struct r8a66597_ep *ep, struct r8a66597_request *req)
  461. {
  462. u16 ctsq;
  463. ctsq = r8a66597_read(ep->r8a66597, INTSTS0) & CTSQ;
  464. switch (ctsq) {
  465. case CS_RDDS:
  466. start_ep0_write(ep, req);
  467. break;
  468. case CS_WRDS:
  469. start_packet_read(ep, req);
  470. break;
  471. case CS_WRND:
  472. control_end(ep->r8a66597, 0);
  473. break;
  474. default:
  475. printk(KERN_ERR "start_ep0: unexpect ctsq(%x)\n", ctsq);
  476. break;
  477. }
  478. }
  479. static void init_controller(struct r8a66597 *r8a66597)
  480. {
  481. u16 vif = r8a66597->pdata->vif ? LDRV : 0;
  482. u16 irq_sense = r8a66597->irq_sense_low ? INTL : 0;
  483. u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
  484. if (r8a66597->pdata->on_chip) {
  485. r8a66597_bset(r8a66597, 0x04, SYSCFG1);
  486. r8a66597_bset(r8a66597, HSE, SYSCFG0);
  487. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  488. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  489. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  490. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  491. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  492. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  493. DMA0CFG);
  494. } else {
  495. r8a66597_bset(r8a66597, vif | endian, PINCFG);
  496. r8a66597_bset(r8a66597, HSE, SYSCFG0); /* High spd */
  497. r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
  498. XTAL, SYSCFG0);
  499. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  500. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  501. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  502. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  503. msleep(3);
  504. r8a66597_bset(r8a66597, PLLC, SYSCFG0);
  505. msleep(1);
  506. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  507. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  508. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  509. DMA0CFG);
  510. }
  511. }
  512. static void disable_controller(struct r8a66597 *r8a66597)
  513. {
  514. if (r8a66597->pdata->on_chip) {
  515. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  516. /* disable interrupts */
  517. r8a66597_write(r8a66597, 0, INTENB0);
  518. r8a66597_write(r8a66597, 0, INTENB1);
  519. r8a66597_write(r8a66597, 0, BRDYENB);
  520. r8a66597_write(r8a66597, 0, BEMPENB);
  521. r8a66597_write(r8a66597, 0, NRDYENB);
  522. /* clear status */
  523. r8a66597_write(r8a66597, 0, BRDYSTS);
  524. r8a66597_write(r8a66597, 0, NRDYSTS);
  525. r8a66597_write(r8a66597, 0, BEMPSTS);
  526. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  527. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  528. } else {
  529. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  530. udelay(1);
  531. r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
  532. udelay(1);
  533. udelay(1);
  534. r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
  535. }
  536. }
  537. static void r8a66597_start_xclock(struct r8a66597 *r8a66597)
  538. {
  539. u16 tmp;
  540. if (!r8a66597->pdata->on_chip) {
  541. tmp = r8a66597_read(r8a66597, SYSCFG0);
  542. if (!(tmp & XCKE))
  543. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  544. }
  545. }
  546. static struct r8a66597_request *get_request_from_ep(struct r8a66597_ep *ep)
  547. {
  548. return list_entry(ep->queue.next, struct r8a66597_request, queue);
  549. }
  550. /*-------------------------------------------------------------------------*/
  551. static void transfer_complete(struct r8a66597_ep *ep,
  552. struct r8a66597_request *req, int status)
  553. __releases(r8a66597->lock)
  554. __acquires(r8a66597->lock)
  555. {
  556. int restart = 0;
  557. if (unlikely(ep->pipenum == 0)) {
  558. if (ep->internal_ccpl) {
  559. ep->internal_ccpl = 0;
  560. return;
  561. }
  562. }
  563. list_del_init(&req->queue);
  564. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  565. req->req.status = -ESHUTDOWN;
  566. else
  567. req->req.status = status;
  568. if (!list_empty(&ep->queue))
  569. restart = 1;
  570. spin_unlock(&ep->r8a66597->lock);
  571. req->req.complete(&ep->ep, &req->req);
  572. spin_lock(&ep->r8a66597->lock);
  573. if (restart) {
  574. req = get_request_from_ep(ep);
  575. if (ep->desc)
  576. start_packet(ep, req);
  577. }
  578. }
  579. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req)
  580. {
  581. int i;
  582. u16 tmp;
  583. unsigned bufsize;
  584. size_t size;
  585. void *buf;
  586. u16 pipenum = ep->pipenum;
  587. struct r8a66597 *r8a66597 = ep->r8a66597;
  588. pipe_change(r8a66597, pipenum);
  589. r8a66597_bset(r8a66597, ISEL, ep->fifosel);
  590. i = 0;
  591. do {
  592. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  593. if (i++ > 100000) {
  594. printk(KERN_ERR "pipe0 is busy. maybe cpu i/o bus"
  595. "conflict. please power off this controller.");
  596. return;
  597. }
  598. ndelay(1);
  599. } while ((tmp & FRDY) == 0);
  600. /* prepare parameters */
  601. bufsize = get_buffer_size(r8a66597, pipenum);
  602. buf = req->req.buf + req->req.actual;
  603. size = min(bufsize, req->req.length - req->req.actual);
  604. /* write fifo */
  605. if (req->req.buf) {
  606. if (size > 0)
  607. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  608. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  609. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  610. }
  611. /* update parameters */
  612. req->req.actual += size;
  613. /* check transfer finish */
  614. if ((!req->req.zero && (req->req.actual == req->req.length))
  615. || (size % ep->ep.maxpacket)
  616. || (size == 0)) {
  617. disable_irq_ready(r8a66597, pipenum);
  618. disable_irq_empty(r8a66597, pipenum);
  619. } else {
  620. disable_irq_ready(r8a66597, pipenum);
  621. enable_irq_empty(r8a66597, pipenum);
  622. }
  623. pipe_start(r8a66597, pipenum);
  624. }
  625. static void irq_packet_write(struct r8a66597_ep *ep,
  626. struct r8a66597_request *req)
  627. {
  628. u16 tmp;
  629. unsigned bufsize;
  630. size_t size;
  631. void *buf;
  632. u16 pipenum = ep->pipenum;
  633. struct r8a66597 *r8a66597 = ep->r8a66597;
  634. pipe_change(r8a66597, pipenum);
  635. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  636. if (unlikely((tmp & FRDY) == 0)) {
  637. pipe_stop(r8a66597, pipenum);
  638. pipe_irq_disable(r8a66597, pipenum);
  639. printk(KERN_ERR "write fifo not ready. pipnum=%d\n", pipenum);
  640. return;
  641. }
  642. /* prepare parameters */
  643. bufsize = get_buffer_size(r8a66597, pipenum);
  644. buf = req->req.buf + req->req.actual;
  645. size = min(bufsize, req->req.length - req->req.actual);
  646. /* write fifo */
  647. if (req->req.buf) {
  648. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  649. if ((size == 0)
  650. || ((size % ep->ep.maxpacket) != 0)
  651. || ((bufsize != ep->ep.maxpacket)
  652. && (bufsize > size)))
  653. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  654. }
  655. /* update parameters */
  656. req->req.actual += size;
  657. /* check transfer finish */
  658. if ((!req->req.zero && (req->req.actual == req->req.length))
  659. || (size % ep->ep.maxpacket)
  660. || (size == 0)) {
  661. disable_irq_ready(r8a66597, pipenum);
  662. enable_irq_empty(r8a66597, pipenum);
  663. } else {
  664. disable_irq_empty(r8a66597, pipenum);
  665. pipe_irq_enable(r8a66597, pipenum);
  666. }
  667. }
  668. static void irq_packet_read(struct r8a66597_ep *ep,
  669. struct r8a66597_request *req)
  670. {
  671. u16 tmp;
  672. int rcv_len, bufsize, req_len;
  673. int size;
  674. void *buf;
  675. u16 pipenum = ep->pipenum;
  676. struct r8a66597 *r8a66597 = ep->r8a66597;
  677. int finish = 0;
  678. pipe_change(r8a66597, pipenum);
  679. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  680. if (unlikely((tmp & FRDY) == 0)) {
  681. req->req.status = -EPIPE;
  682. pipe_stop(r8a66597, pipenum);
  683. pipe_irq_disable(r8a66597, pipenum);
  684. printk(KERN_ERR "read fifo not ready");
  685. return;
  686. }
  687. /* prepare parameters */
  688. rcv_len = tmp & DTLN;
  689. bufsize = get_buffer_size(r8a66597, pipenum);
  690. buf = req->req.buf + req->req.actual;
  691. req_len = req->req.length - req->req.actual;
  692. if (rcv_len < bufsize)
  693. size = min(rcv_len, req_len);
  694. else
  695. size = min(bufsize, req_len);
  696. /* update parameters */
  697. req->req.actual += size;
  698. /* check transfer finish */
  699. if ((!req->req.zero && (req->req.actual == req->req.length))
  700. || (size % ep->ep.maxpacket)
  701. || (size == 0)) {
  702. pipe_stop(r8a66597, pipenum);
  703. pipe_irq_disable(r8a66597, pipenum);
  704. finish = 1;
  705. }
  706. /* read fifo */
  707. if (req->req.buf) {
  708. if (size == 0)
  709. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  710. else
  711. r8a66597_read_fifo(r8a66597, ep->fifoaddr, buf, size);
  712. }
  713. if ((ep->pipenum != 0) && finish)
  714. transfer_complete(ep, req, 0);
  715. }
  716. static void irq_pipe_ready(struct r8a66597 *r8a66597, u16 status, u16 enb)
  717. {
  718. u16 check;
  719. u16 pipenum;
  720. struct r8a66597_ep *ep;
  721. struct r8a66597_request *req;
  722. if ((status & BRDY0) && (enb & BRDY0)) {
  723. r8a66597_write(r8a66597, ~BRDY0, BRDYSTS);
  724. r8a66597_mdfy(r8a66597, 0, CURPIPE, CFIFOSEL);
  725. ep = &r8a66597->ep[0];
  726. req = get_request_from_ep(ep);
  727. irq_packet_read(ep, req);
  728. } else {
  729. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  730. check = 1 << pipenum;
  731. if ((status & check) && (enb & check)) {
  732. r8a66597_write(r8a66597, ~check, BRDYSTS);
  733. ep = r8a66597->pipenum2ep[pipenum];
  734. req = get_request_from_ep(ep);
  735. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  736. irq_packet_write(ep, req);
  737. else
  738. irq_packet_read(ep, req);
  739. }
  740. }
  741. }
  742. }
  743. static void irq_pipe_empty(struct r8a66597 *r8a66597, u16 status, u16 enb)
  744. {
  745. u16 tmp;
  746. u16 check;
  747. u16 pipenum;
  748. struct r8a66597_ep *ep;
  749. struct r8a66597_request *req;
  750. if ((status & BEMP0) && (enb & BEMP0)) {
  751. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  752. ep = &r8a66597->ep[0];
  753. req = get_request_from_ep(ep);
  754. irq_ep0_write(ep, req);
  755. } else {
  756. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  757. check = 1 << pipenum;
  758. if ((status & check) && (enb & check)) {
  759. r8a66597_write(r8a66597, ~check, BEMPSTS);
  760. tmp = control_reg_get(r8a66597, pipenum);
  761. if ((tmp & INBUFM) == 0) {
  762. disable_irq_empty(r8a66597, pipenum);
  763. pipe_irq_disable(r8a66597, pipenum);
  764. pipe_stop(r8a66597, pipenum);
  765. ep = r8a66597->pipenum2ep[pipenum];
  766. req = get_request_from_ep(ep);
  767. if (!list_empty(&ep->queue))
  768. transfer_complete(ep, req, 0);
  769. }
  770. }
  771. }
  772. }
  773. }
  774. static void get_status(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  775. __releases(r8a66597->lock)
  776. __acquires(r8a66597->lock)
  777. {
  778. struct r8a66597_ep *ep;
  779. u16 pid;
  780. u16 status = 0;
  781. u16 w_index = le16_to_cpu(ctrl->wIndex);
  782. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  783. case USB_RECIP_DEVICE:
  784. status = 1 << USB_DEVICE_SELF_POWERED;
  785. break;
  786. case USB_RECIP_INTERFACE:
  787. status = 0;
  788. break;
  789. case USB_RECIP_ENDPOINT:
  790. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  791. pid = control_reg_get_pid(r8a66597, ep->pipenum);
  792. if (pid == PID_STALL)
  793. status = 1 << USB_ENDPOINT_HALT;
  794. else
  795. status = 0;
  796. break;
  797. default:
  798. pipe_stall(r8a66597, 0);
  799. return; /* exit */
  800. }
  801. r8a66597->ep0_data = cpu_to_le16(status);
  802. r8a66597->ep0_req->buf = &r8a66597->ep0_data;
  803. r8a66597->ep0_req->length = 2;
  804. /* AV: what happens if we get called again before that gets through? */
  805. spin_unlock(&r8a66597->lock);
  806. r8a66597_queue(r8a66597->gadget.ep0, r8a66597->ep0_req, GFP_KERNEL);
  807. spin_lock(&r8a66597->lock);
  808. }
  809. static void clear_feature(struct r8a66597 *r8a66597,
  810. struct usb_ctrlrequest *ctrl)
  811. {
  812. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  813. case USB_RECIP_DEVICE:
  814. control_end(r8a66597, 1);
  815. break;
  816. case USB_RECIP_INTERFACE:
  817. control_end(r8a66597, 1);
  818. break;
  819. case USB_RECIP_ENDPOINT: {
  820. struct r8a66597_ep *ep;
  821. struct r8a66597_request *req;
  822. u16 w_index = le16_to_cpu(ctrl->wIndex);
  823. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  824. if (!ep->wedge) {
  825. pipe_stop(r8a66597, ep->pipenum);
  826. control_reg_sqclr(r8a66597, ep->pipenum);
  827. spin_unlock(&r8a66597->lock);
  828. usb_ep_clear_halt(&ep->ep);
  829. spin_lock(&r8a66597->lock);
  830. }
  831. control_end(r8a66597, 1);
  832. req = get_request_from_ep(ep);
  833. if (ep->busy) {
  834. ep->busy = 0;
  835. if (list_empty(&ep->queue))
  836. break;
  837. start_packet(ep, req);
  838. } else if (!list_empty(&ep->queue))
  839. pipe_start(r8a66597, ep->pipenum);
  840. }
  841. break;
  842. default:
  843. pipe_stall(r8a66597, 0);
  844. break;
  845. }
  846. }
  847. static void set_feature(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  848. {
  849. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  850. case USB_RECIP_DEVICE:
  851. control_end(r8a66597, 1);
  852. break;
  853. case USB_RECIP_INTERFACE:
  854. control_end(r8a66597, 1);
  855. break;
  856. case USB_RECIP_ENDPOINT: {
  857. struct r8a66597_ep *ep;
  858. u16 w_index = le16_to_cpu(ctrl->wIndex);
  859. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  860. pipe_stall(r8a66597, ep->pipenum);
  861. control_end(r8a66597, 1);
  862. }
  863. break;
  864. default:
  865. pipe_stall(r8a66597, 0);
  866. break;
  867. }
  868. }
  869. /* if return value is true, call class driver's setup() */
  870. static int setup_packet(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  871. {
  872. u16 *p = (u16 *)ctrl;
  873. unsigned long offset = USBREQ;
  874. int i, ret = 0;
  875. /* read fifo */
  876. r8a66597_write(r8a66597, ~VALID, INTSTS0);
  877. for (i = 0; i < 4; i++)
  878. p[i] = r8a66597_read(r8a66597, offset + i*2);
  879. /* check request */
  880. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  881. switch (ctrl->bRequest) {
  882. case USB_REQ_GET_STATUS:
  883. get_status(r8a66597, ctrl);
  884. break;
  885. case USB_REQ_CLEAR_FEATURE:
  886. clear_feature(r8a66597, ctrl);
  887. break;
  888. case USB_REQ_SET_FEATURE:
  889. set_feature(r8a66597, ctrl);
  890. break;
  891. default:
  892. ret = 1;
  893. break;
  894. }
  895. } else
  896. ret = 1;
  897. return ret;
  898. }
  899. static void r8a66597_update_usb_speed(struct r8a66597 *r8a66597)
  900. {
  901. u16 speed = get_usb_speed(r8a66597);
  902. switch (speed) {
  903. case HSMODE:
  904. r8a66597->gadget.speed = USB_SPEED_HIGH;
  905. break;
  906. case FSMODE:
  907. r8a66597->gadget.speed = USB_SPEED_FULL;
  908. break;
  909. default:
  910. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  911. printk(KERN_ERR "USB speed unknown\n");
  912. }
  913. }
  914. static void irq_device_state(struct r8a66597 *r8a66597)
  915. {
  916. u16 dvsq;
  917. dvsq = r8a66597_read(r8a66597, INTSTS0) & DVSQ;
  918. r8a66597_write(r8a66597, ~DVST, INTSTS0);
  919. if (dvsq == DS_DFLT) {
  920. /* bus reset */
  921. r8a66597->driver->disconnect(&r8a66597->gadget);
  922. r8a66597_update_usb_speed(r8a66597);
  923. }
  924. if (r8a66597->old_dvsq == DS_CNFG && dvsq != DS_CNFG)
  925. r8a66597_update_usb_speed(r8a66597);
  926. if ((dvsq == DS_CNFG || dvsq == DS_ADDS)
  927. && r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  928. r8a66597_update_usb_speed(r8a66597);
  929. r8a66597->old_dvsq = dvsq;
  930. }
  931. static void irq_control_stage(struct r8a66597 *r8a66597)
  932. __releases(r8a66597->lock)
  933. __acquires(r8a66597->lock)
  934. {
  935. struct usb_ctrlrequest ctrl;
  936. u16 ctsq;
  937. ctsq = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
  938. r8a66597_write(r8a66597, ~CTRT, INTSTS0);
  939. switch (ctsq) {
  940. case CS_IDST: {
  941. struct r8a66597_ep *ep;
  942. struct r8a66597_request *req;
  943. ep = &r8a66597->ep[0];
  944. req = get_request_from_ep(ep);
  945. transfer_complete(ep, req, 0);
  946. }
  947. break;
  948. case CS_RDDS:
  949. case CS_WRDS:
  950. case CS_WRND:
  951. if (setup_packet(r8a66597, &ctrl)) {
  952. spin_unlock(&r8a66597->lock);
  953. if (r8a66597->driver->setup(&r8a66597->gadget, &ctrl)
  954. < 0)
  955. pipe_stall(r8a66597, 0);
  956. spin_lock(&r8a66597->lock);
  957. }
  958. break;
  959. case CS_RDSS:
  960. case CS_WRSS:
  961. control_end(r8a66597, 0);
  962. break;
  963. default:
  964. printk(KERN_ERR "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  965. break;
  966. }
  967. }
  968. static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
  969. {
  970. struct r8a66597 *r8a66597 = _r8a66597;
  971. u16 intsts0;
  972. u16 intenb0;
  973. u16 brdysts, nrdysts, bempsts;
  974. u16 brdyenb, nrdyenb, bempenb;
  975. u16 savepipe;
  976. u16 mask0;
  977. spin_lock(&r8a66597->lock);
  978. intsts0 = r8a66597_read(r8a66597, INTSTS0);
  979. intenb0 = r8a66597_read(r8a66597, INTENB0);
  980. savepipe = r8a66597_read(r8a66597, CFIFOSEL);
  981. mask0 = intsts0 & intenb0;
  982. if (mask0) {
  983. brdysts = r8a66597_read(r8a66597, BRDYSTS);
  984. nrdysts = r8a66597_read(r8a66597, NRDYSTS);
  985. bempsts = r8a66597_read(r8a66597, BEMPSTS);
  986. brdyenb = r8a66597_read(r8a66597, BRDYENB);
  987. nrdyenb = r8a66597_read(r8a66597, NRDYENB);
  988. bempenb = r8a66597_read(r8a66597, BEMPENB);
  989. if (mask0 & VBINT) {
  990. r8a66597_write(r8a66597, 0xffff & ~VBINT,
  991. INTSTS0);
  992. r8a66597_start_xclock(r8a66597);
  993. /* start vbus sampling */
  994. r8a66597->old_vbus = r8a66597_read(r8a66597, INTSTS0)
  995. & VBSTS;
  996. r8a66597->scount = R8A66597_MAX_SAMPLING;
  997. mod_timer(&r8a66597->timer,
  998. jiffies + msecs_to_jiffies(50));
  999. }
  1000. if (intsts0 & DVSQ)
  1001. irq_device_state(r8a66597);
  1002. if ((intsts0 & BRDY) && (intenb0 & BRDYE)
  1003. && (brdysts & brdyenb))
  1004. irq_pipe_ready(r8a66597, brdysts, brdyenb);
  1005. if ((intsts0 & BEMP) && (intenb0 & BEMPE)
  1006. && (bempsts & bempenb))
  1007. irq_pipe_empty(r8a66597, bempsts, bempenb);
  1008. if (intsts0 & CTRT)
  1009. irq_control_stage(r8a66597);
  1010. }
  1011. r8a66597_write(r8a66597, savepipe, CFIFOSEL);
  1012. spin_unlock(&r8a66597->lock);
  1013. return IRQ_HANDLED;
  1014. }
  1015. static void r8a66597_timer(unsigned long _r8a66597)
  1016. {
  1017. struct r8a66597 *r8a66597 = (struct r8a66597 *)_r8a66597;
  1018. unsigned long flags;
  1019. u16 tmp;
  1020. spin_lock_irqsave(&r8a66597->lock, flags);
  1021. tmp = r8a66597_read(r8a66597, SYSCFG0);
  1022. if (r8a66597->scount > 0) {
  1023. tmp = r8a66597_read(r8a66597, INTSTS0) & VBSTS;
  1024. if (tmp == r8a66597->old_vbus) {
  1025. r8a66597->scount--;
  1026. if (r8a66597->scount == 0) {
  1027. if (tmp == VBSTS)
  1028. r8a66597_usb_connect(r8a66597);
  1029. else
  1030. r8a66597_usb_disconnect(r8a66597);
  1031. } else {
  1032. mod_timer(&r8a66597->timer,
  1033. jiffies + msecs_to_jiffies(50));
  1034. }
  1035. } else {
  1036. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1037. r8a66597->old_vbus = tmp;
  1038. mod_timer(&r8a66597->timer,
  1039. jiffies + msecs_to_jiffies(50));
  1040. }
  1041. }
  1042. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1043. }
  1044. /*-------------------------------------------------------------------------*/
  1045. static int r8a66597_enable(struct usb_ep *_ep,
  1046. const struct usb_endpoint_descriptor *desc)
  1047. {
  1048. struct r8a66597_ep *ep;
  1049. ep = container_of(_ep, struct r8a66597_ep, ep);
  1050. return alloc_pipe_config(ep, desc);
  1051. }
  1052. static int r8a66597_disable(struct usb_ep *_ep)
  1053. {
  1054. struct r8a66597_ep *ep;
  1055. struct r8a66597_request *req;
  1056. unsigned long flags;
  1057. ep = container_of(_ep, struct r8a66597_ep, ep);
  1058. BUG_ON(!ep);
  1059. while (!list_empty(&ep->queue)) {
  1060. req = get_request_from_ep(ep);
  1061. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1062. transfer_complete(ep, req, -ECONNRESET);
  1063. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1064. }
  1065. pipe_irq_disable(ep->r8a66597, ep->pipenum);
  1066. return free_pipe_config(ep);
  1067. }
  1068. static struct usb_request *r8a66597_alloc_request(struct usb_ep *_ep,
  1069. gfp_t gfp_flags)
  1070. {
  1071. struct r8a66597_request *req;
  1072. req = kzalloc(sizeof(struct r8a66597_request), gfp_flags);
  1073. if (!req)
  1074. return NULL;
  1075. INIT_LIST_HEAD(&req->queue);
  1076. return &req->req;
  1077. }
  1078. static void r8a66597_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1079. {
  1080. struct r8a66597_request *req;
  1081. req = container_of(_req, struct r8a66597_request, req);
  1082. kfree(req);
  1083. }
  1084. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  1085. gfp_t gfp_flags)
  1086. {
  1087. struct r8a66597_ep *ep;
  1088. struct r8a66597_request *req;
  1089. unsigned long flags;
  1090. int request = 0;
  1091. ep = container_of(_ep, struct r8a66597_ep, ep);
  1092. req = container_of(_req, struct r8a66597_request, req);
  1093. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  1094. return -ESHUTDOWN;
  1095. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1096. if (list_empty(&ep->queue))
  1097. request = 1;
  1098. list_add_tail(&req->queue, &ep->queue);
  1099. req->req.actual = 0;
  1100. req->req.status = -EINPROGRESS;
  1101. if (ep->desc == NULL) /* control */
  1102. start_ep0(ep, req);
  1103. else {
  1104. if (request && !ep->busy)
  1105. start_packet(ep, req);
  1106. }
  1107. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1108. return 0;
  1109. }
  1110. static int r8a66597_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1111. {
  1112. struct r8a66597_ep *ep;
  1113. struct r8a66597_request *req;
  1114. unsigned long flags;
  1115. ep = container_of(_ep, struct r8a66597_ep, ep);
  1116. req = container_of(_req, struct r8a66597_request, req);
  1117. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1118. if (!list_empty(&ep->queue))
  1119. transfer_complete(ep, req, -ECONNRESET);
  1120. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1121. return 0;
  1122. }
  1123. static int r8a66597_set_halt(struct usb_ep *_ep, int value)
  1124. {
  1125. struct r8a66597_ep *ep;
  1126. struct r8a66597_request *req;
  1127. unsigned long flags;
  1128. int ret = 0;
  1129. ep = container_of(_ep, struct r8a66597_ep, ep);
  1130. req = get_request_from_ep(ep);
  1131. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1132. if (!list_empty(&ep->queue)) {
  1133. ret = -EAGAIN;
  1134. goto out;
  1135. }
  1136. if (value) {
  1137. ep->busy = 1;
  1138. pipe_stall(ep->r8a66597, ep->pipenum);
  1139. } else {
  1140. ep->busy = 0;
  1141. ep->wedge = 0;
  1142. pipe_stop(ep->r8a66597, ep->pipenum);
  1143. }
  1144. out:
  1145. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1146. return ret;
  1147. }
  1148. static int r8a66597_set_wedge(struct usb_ep *_ep)
  1149. {
  1150. struct r8a66597_ep *ep;
  1151. unsigned long flags;
  1152. ep = container_of(_ep, struct r8a66597_ep, ep);
  1153. if (!ep || !ep->desc)
  1154. return -EINVAL;
  1155. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1156. ep->wedge = 1;
  1157. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1158. return usb_ep_set_halt(_ep);
  1159. }
  1160. static void r8a66597_fifo_flush(struct usb_ep *_ep)
  1161. {
  1162. struct r8a66597_ep *ep;
  1163. unsigned long flags;
  1164. ep = container_of(_ep, struct r8a66597_ep, ep);
  1165. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1166. if (list_empty(&ep->queue) && !ep->busy) {
  1167. pipe_stop(ep->r8a66597, ep->pipenum);
  1168. r8a66597_bclr(ep->r8a66597, BCLR, ep->fifoctr);
  1169. }
  1170. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1171. }
  1172. static struct usb_ep_ops r8a66597_ep_ops = {
  1173. .enable = r8a66597_enable,
  1174. .disable = r8a66597_disable,
  1175. .alloc_request = r8a66597_alloc_request,
  1176. .free_request = r8a66597_free_request,
  1177. .queue = r8a66597_queue,
  1178. .dequeue = r8a66597_dequeue,
  1179. .set_halt = r8a66597_set_halt,
  1180. .set_wedge = r8a66597_set_wedge,
  1181. .fifo_flush = r8a66597_fifo_flush,
  1182. };
  1183. /*-------------------------------------------------------------------------*/
  1184. static struct r8a66597 *the_controller;
  1185. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1186. {
  1187. struct r8a66597 *r8a66597 = the_controller;
  1188. int retval;
  1189. if (!driver
  1190. || driver->speed != USB_SPEED_HIGH
  1191. || !driver->bind
  1192. || !driver->setup)
  1193. return -EINVAL;
  1194. if (!r8a66597)
  1195. return -ENODEV;
  1196. if (r8a66597->driver)
  1197. return -EBUSY;
  1198. /* hook up the driver */
  1199. driver->driver.bus = NULL;
  1200. r8a66597->driver = driver;
  1201. r8a66597->gadget.dev.driver = &driver->driver;
  1202. retval = device_add(&r8a66597->gadget.dev);
  1203. if (retval) {
  1204. printk(KERN_ERR "device_add error (%d)\n", retval);
  1205. goto error;
  1206. }
  1207. retval = driver->bind(&r8a66597->gadget);
  1208. if (retval) {
  1209. printk(KERN_ERR "bind to driver error (%d)\n", retval);
  1210. device_del(&r8a66597->gadget.dev);
  1211. goto error;
  1212. }
  1213. r8a66597_bset(r8a66597, VBSE, INTENB0);
  1214. if (r8a66597_read(r8a66597, INTSTS0) & VBSTS) {
  1215. r8a66597_start_xclock(r8a66597);
  1216. /* start vbus sampling */
  1217. r8a66597->old_vbus = r8a66597_read(r8a66597,
  1218. INTSTS0) & VBSTS;
  1219. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1220. mod_timer(&r8a66597->timer, jiffies + msecs_to_jiffies(50));
  1221. }
  1222. return 0;
  1223. error:
  1224. r8a66597->driver = NULL;
  1225. r8a66597->gadget.dev.driver = NULL;
  1226. return retval;
  1227. }
  1228. EXPORT_SYMBOL(usb_gadget_register_driver);
  1229. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1230. {
  1231. struct r8a66597 *r8a66597 = the_controller;
  1232. unsigned long flags;
  1233. if (driver != r8a66597->driver || !driver->unbind)
  1234. return -EINVAL;
  1235. spin_lock_irqsave(&r8a66597->lock, flags);
  1236. if (r8a66597->gadget.speed != USB_SPEED_UNKNOWN)
  1237. r8a66597_usb_disconnect(r8a66597);
  1238. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1239. r8a66597_bclr(r8a66597, VBSE, INTENB0);
  1240. driver->unbind(&r8a66597->gadget);
  1241. init_controller(r8a66597);
  1242. disable_controller(r8a66597);
  1243. device_del(&r8a66597->gadget.dev);
  1244. r8a66597->driver = NULL;
  1245. return 0;
  1246. }
  1247. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1248. /*-------------------------------------------------------------------------*/
  1249. static int r8a66597_get_frame(struct usb_gadget *_gadget)
  1250. {
  1251. struct r8a66597 *r8a66597 = gadget_to_r8a66597(_gadget);
  1252. return r8a66597_read(r8a66597, FRMNUM) & 0x03FF;
  1253. }
  1254. static struct usb_gadget_ops r8a66597_gadget_ops = {
  1255. .get_frame = r8a66597_get_frame,
  1256. };
  1257. static int __exit r8a66597_remove(struct platform_device *pdev)
  1258. {
  1259. struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
  1260. del_timer_sync(&r8a66597->timer);
  1261. iounmap((void *)r8a66597->reg);
  1262. free_irq(platform_get_irq(pdev, 0), r8a66597);
  1263. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1264. #ifdef CONFIG_HAVE_CLK
  1265. if (r8a66597->pdata->on_chip) {
  1266. clk_disable(r8a66597->clk);
  1267. clk_put(r8a66597->clk);
  1268. }
  1269. #endif
  1270. kfree(r8a66597);
  1271. return 0;
  1272. }
  1273. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1274. {
  1275. }
  1276. static int __init r8a66597_probe(struct platform_device *pdev)
  1277. {
  1278. #ifdef CONFIG_HAVE_CLK
  1279. char clk_name[8];
  1280. #endif
  1281. struct resource *res, *ires;
  1282. int irq;
  1283. void __iomem *reg = NULL;
  1284. struct r8a66597 *r8a66597 = NULL;
  1285. int ret = 0;
  1286. int i;
  1287. unsigned long irq_trigger;
  1288. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1289. if (!res) {
  1290. ret = -ENODEV;
  1291. printk(KERN_ERR "platform_get_resource error.\n");
  1292. goto clean_up;
  1293. }
  1294. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1295. irq = ires->start;
  1296. irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1297. if (irq < 0) {
  1298. ret = -ENODEV;
  1299. printk(KERN_ERR "platform_get_irq error.\n");
  1300. goto clean_up;
  1301. }
  1302. reg = ioremap(res->start, resource_size(res));
  1303. if (reg == NULL) {
  1304. ret = -ENOMEM;
  1305. printk(KERN_ERR "ioremap error.\n");
  1306. goto clean_up;
  1307. }
  1308. /* initialize ucd */
  1309. r8a66597 = kzalloc(sizeof(struct r8a66597), GFP_KERNEL);
  1310. if (r8a66597 == NULL) {
  1311. printk(KERN_ERR "kzalloc error\n");
  1312. goto clean_up;
  1313. }
  1314. spin_lock_init(&r8a66597->lock);
  1315. dev_set_drvdata(&pdev->dev, r8a66597);
  1316. r8a66597->pdata = pdev->dev.platform_data;
  1317. r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
  1318. r8a66597->gadget.ops = &r8a66597_gadget_ops;
  1319. device_initialize(&r8a66597->gadget.dev);
  1320. dev_set_name(&r8a66597->gadget.dev, "gadget");
  1321. r8a66597->gadget.is_dualspeed = 1;
  1322. r8a66597->gadget.dev.parent = &pdev->dev;
  1323. r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1324. r8a66597->gadget.dev.release = pdev->dev.release;
  1325. r8a66597->gadget.name = udc_name;
  1326. init_timer(&r8a66597->timer);
  1327. r8a66597->timer.function = r8a66597_timer;
  1328. r8a66597->timer.data = (unsigned long)r8a66597;
  1329. r8a66597->reg = (unsigned long)reg;
  1330. #ifdef CONFIG_HAVE_CLK
  1331. if (r8a66597->pdata->on_chip) {
  1332. snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id);
  1333. r8a66597->clk = clk_get(&pdev->dev, clk_name);
  1334. if (IS_ERR(r8a66597->clk)) {
  1335. dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
  1336. clk_name);
  1337. ret = PTR_ERR(r8a66597->clk);
  1338. goto clean_up;
  1339. }
  1340. clk_enable(r8a66597->clk);
  1341. }
  1342. #endif
  1343. disable_controller(r8a66597); /* make sure controller is disabled */
  1344. ret = request_irq(irq, r8a66597_irq, IRQF_DISABLED | IRQF_SHARED,
  1345. udc_name, r8a66597);
  1346. if (ret < 0) {
  1347. printk(KERN_ERR "request_irq error (%d)\n", ret);
  1348. goto clean_up2;
  1349. }
  1350. INIT_LIST_HEAD(&r8a66597->gadget.ep_list);
  1351. r8a66597->gadget.ep0 = &r8a66597->ep[0].ep;
  1352. INIT_LIST_HEAD(&r8a66597->gadget.ep0->ep_list);
  1353. for (i = 0; i < R8A66597_MAX_NUM_PIPE; i++) {
  1354. struct r8a66597_ep *ep = &r8a66597->ep[i];
  1355. if (i != 0) {
  1356. INIT_LIST_HEAD(&r8a66597->ep[i].ep.ep_list);
  1357. list_add_tail(&r8a66597->ep[i].ep.ep_list,
  1358. &r8a66597->gadget.ep_list);
  1359. }
  1360. ep->r8a66597 = r8a66597;
  1361. INIT_LIST_HEAD(&ep->queue);
  1362. ep->ep.name = r8a66597_ep_name[i];
  1363. ep->ep.ops = &r8a66597_ep_ops;
  1364. ep->ep.maxpacket = 512;
  1365. }
  1366. r8a66597->ep[0].ep.maxpacket = 64;
  1367. r8a66597->ep[0].pipenum = 0;
  1368. r8a66597->ep[0].fifoaddr = CFIFO;
  1369. r8a66597->ep[0].fifosel = CFIFOSEL;
  1370. r8a66597->ep[0].fifoctr = CFIFOCTR;
  1371. r8a66597->ep[0].fifotrn = 0;
  1372. r8a66597->ep[0].pipectr = get_pipectr_addr(0);
  1373. r8a66597->pipenum2ep[0] = &r8a66597->ep[0];
  1374. r8a66597->epaddr2ep[0] = &r8a66597->ep[0];
  1375. the_controller = r8a66597;
  1376. r8a66597->ep0_req = r8a66597_alloc_request(&r8a66597->ep[0].ep,
  1377. GFP_KERNEL);
  1378. if (r8a66597->ep0_req == NULL)
  1379. goto clean_up3;
  1380. r8a66597->ep0_req->complete = nop_completion;
  1381. init_controller(r8a66597);
  1382. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1383. return 0;
  1384. clean_up3:
  1385. free_irq(irq, r8a66597);
  1386. clean_up2:
  1387. #ifdef CONFIG_HAVE_CLK
  1388. if (r8a66597->pdata->on_chip) {
  1389. clk_disable(r8a66597->clk);
  1390. clk_put(r8a66597->clk);
  1391. }
  1392. #endif
  1393. clean_up:
  1394. if (r8a66597) {
  1395. if (r8a66597->ep0_req)
  1396. r8a66597_free_request(&r8a66597->ep[0].ep,
  1397. r8a66597->ep0_req);
  1398. kfree(r8a66597);
  1399. }
  1400. if (reg)
  1401. iounmap(reg);
  1402. return ret;
  1403. }
  1404. /*-------------------------------------------------------------------------*/
  1405. static struct platform_driver r8a66597_driver = {
  1406. .remove = __exit_p(r8a66597_remove),
  1407. .driver = {
  1408. .name = (char *) udc_name,
  1409. },
  1410. };
  1411. static int __init r8a66597_udc_init(void)
  1412. {
  1413. return platform_driver_probe(&r8a66597_driver, r8a66597_probe);
  1414. }
  1415. module_init(r8a66597_udc_init);
  1416. static void __exit r8a66597_udc_cleanup(void)
  1417. {
  1418. platform_driver_unregister(&r8a66597_driver);
  1419. }
  1420. module_exit(r8a66597_udc_cleanup);
  1421. MODULE_DESCRIPTION("R8A66597 USB gadget driver");
  1422. MODULE_LICENSE("GPL");
  1423. MODULE_AUTHOR("Yoshihiro Shimoda");