langwell_udc.c 80 KB

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  1. /*
  2. * Intel Langwell USB Device Controller driver
  3. * Copyright (C) 2008-2009, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. *
  18. */
  19. /* #undef DEBUG */
  20. /* #undef VERBOSE */
  21. #if defined(CONFIG_USB_LANGWELL_OTG)
  22. #define OTG_TRANSCEIVER
  23. #endif
  24. #include <linux/module.h>
  25. #include <linux/pci.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/kernel.h>
  28. #include <linux/delay.h>
  29. #include <linux/ioport.h>
  30. #include <linux/sched.h>
  31. #include <linux/slab.h>
  32. #include <linux/errno.h>
  33. #include <linux/init.h>
  34. #include <linux/timer.h>
  35. #include <linux/list.h>
  36. #include <linux/interrupt.h>
  37. #include <linux/moduleparam.h>
  38. #include <linux/device.h>
  39. #include <linux/usb/ch9.h>
  40. #include <linux/usb/gadget.h>
  41. #include <linux/usb/otg.h>
  42. #include <linux/pm.h>
  43. #include <linux/io.h>
  44. #include <linux/irq.h>
  45. #include <asm/system.h>
  46. #include <asm/unaligned.h>
  47. #include "langwell_udc.h"
  48. #define DRIVER_DESC "Intel Langwell USB Device Controller driver"
  49. #define DRIVER_VERSION "16 May 2009"
  50. static const char driver_name[] = "langwell_udc";
  51. static const char driver_desc[] = DRIVER_DESC;
  52. /* controller device global variable */
  53. static struct langwell_udc *the_controller;
  54. /* for endpoint 0 operations */
  55. static const struct usb_endpoint_descriptor
  56. langwell_ep0_desc = {
  57. .bLength = USB_DT_ENDPOINT_SIZE,
  58. .bDescriptorType = USB_DT_ENDPOINT,
  59. .bEndpointAddress = 0,
  60. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  61. .wMaxPacketSize = EP0_MAX_PKT_SIZE,
  62. };
  63. /*-------------------------------------------------------------------------*/
  64. /* debugging */
  65. #ifdef DEBUG
  66. #define DBG(dev, fmt, args...) \
  67. pr_debug("%s %s: " fmt , driver_name, \
  68. pci_name(dev->pdev), ## args)
  69. #else
  70. #define DBG(dev, fmt, args...) \
  71. do { } while (0)
  72. #endif /* DEBUG */
  73. #ifdef VERBOSE
  74. #define VDBG DBG
  75. #else
  76. #define VDBG(dev, fmt, args...) \
  77. do { } while (0)
  78. #endif /* VERBOSE */
  79. #define ERROR(dev, fmt, args...) \
  80. pr_err("%s %s: " fmt , driver_name, \
  81. pci_name(dev->pdev), ## args)
  82. #define WARNING(dev, fmt, args...) \
  83. pr_warning("%s %s: " fmt , driver_name, \
  84. pci_name(dev->pdev), ## args)
  85. #define INFO(dev, fmt, args...) \
  86. pr_info("%s %s: " fmt , driver_name, \
  87. pci_name(dev->pdev), ## args)
  88. #ifdef VERBOSE
  89. static inline void print_all_registers(struct langwell_udc *dev)
  90. {
  91. int i;
  92. /* Capability Registers */
  93. printk(KERN_DEBUG "Capability Registers (offset: "
  94. "0x%04x, length: 0x%08x)\n",
  95. CAP_REG_OFFSET,
  96. (u32)sizeof(struct langwell_cap_regs));
  97. printk(KERN_DEBUG "caplength=0x%02x\n",
  98. readb(&dev->cap_regs->caplength));
  99. printk(KERN_DEBUG "hciversion=0x%04x\n",
  100. readw(&dev->cap_regs->hciversion));
  101. printk(KERN_DEBUG "hcsparams=0x%08x\n",
  102. readl(&dev->cap_regs->hcsparams));
  103. printk(KERN_DEBUG "hccparams=0x%08x\n",
  104. readl(&dev->cap_regs->hccparams));
  105. printk(KERN_DEBUG "dciversion=0x%04x\n",
  106. readw(&dev->cap_regs->dciversion));
  107. printk(KERN_DEBUG "dccparams=0x%08x\n",
  108. readl(&dev->cap_regs->dccparams));
  109. /* Operational Registers */
  110. printk(KERN_DEBUG "Operational Registers (offset: "
  111. "0x%04x, length: 0x%08x)\n",
  112. OP_REG_OFFSET,
  113. (u32)sizeof(struct langwell_op_regs));
  114. printk(KERN_DEBUG "extsts=0x%08x\n",
  115. readl(&dev->op_regs->extsts));
  116. printk(KERN_DEBUG "extintr=0x%08x\n",
  117. readl(&dev->op_regs->extintr));
  118. printk(KERN_DEBUG "usbcmd=0x%08x\n",
  119. readl(&dev->op_regs->usbcmd));
  120. printk(KERN_DEBUG "usbsts=0x%08x\n",
  121. readl(&dev->op_regs->usbsts));
  122. printk(KERN_DEBUG "usbintr=0x%08x\n",
  123. readl(&dev->op_regs->usbintr));
  124. printk(KERN_DEBUG "frindex=0x%08x\n",
  125. readl(&dev->op_regs->frindex));
  126. printk(KERN_DEBUG "ctrldssegment=0x%08x\n",
  127. readl(&dev->op_regs->ctrldssegment));
  128. printk(KERN_DEBUG "deviceaddr=0x%08x\n",
  129. readl(&dev->op_regs->deviceaddr));
  130. printk(KERN_DEBUG "endpointlistaddr=0x%08x\n",
  131. readl(&dev->op_regs->endpointlistaddr));
  132. printk(KERN_DEBUG "ttctrl=0x%08x\n",
  133. readl(&dev->op_regs->ttctrl));
  134. printk(KERN_DEBUG "burstsize=0x%08x\n",
  135. readl(&dev->op_regs->burstsize));
  136. printk(KERN_DEBUG "txfilltuning=0x%08x\n",
  137. readl(&dev->op_regs->txfilltuning));
  138. printk(KERN_DEBUG "txttfilltuning=0x%08x\n",
  139. readl(&dev->op_regs->txttfilltuning));
  140. printk(KERN_DEBUG "ic_usb=0x%08x\n",
  141. readl(&dev->op_regs->ic_usb));
  142. printk(KERN_DEBUG "ulpi_viewport=0x%08x\n",
  143. readl(&dev->op_regs->ulpi_viewport));
  144. printk(KERN_DEBUG "configflag=0x%08x\n",
  145. readl(&dev->op_regs->configflag));
  146. printk(KERN_DEBUG "portsc1=0x%08x\n",
  147. readl(&dev->op_regs->portsc1));
  148. printk(KERN_DEBUG "devlc=0x%08x\n",
  149. readl(&dev->op_regs->devlc));
  150. printk(KERN_DEBUG "otgsc=0x%08x\n",
  151. readl(&dev->op_regs->otgsc));
  152. printk(KERN_DEBUG "usbmode=0x%08x\n",
  153. readl(&dev->op_regs->usbmode));
  154. printk(KERN_DEBUG "endptnak=0x%08x\n",
  155. readl(&dev->op_regs->endptnak));
  156. printk(KERN_DEBUG "endptnaken=0x%08x\n",
  157. readl(&dev->op_regs->endptnaken));
  158. printk(KERN_DEBUG "endptsetupstat=0x%08x\n",
  159. readl(&dev->op_regs->endptsetupstat));
  160. printk(KERN_DEBUG "endptprime=0x%08x\n",
  161. readl(&dev->op_regs->endptprime));
  162. printk(KERN_DEBUG "endptflush=0x%08x\n",
  163. readl(&dev->op_regs->endptflush));
  164. printk(KERN_DEBUG "endptstat=0x%08x\n",
  165. readl(&dev->op_regs->endptstat));
  166. printk(KERN_DEBUG "endptcomplete=0x%08x\n",
  167. readl(&dev->op_regs->endptcomplete));
  168. for (i = 0; i < dev->ep_max / 2; i++) {
  169. printk(KERN_DEBUG "endptctrl[%d]=0x%08x\n",
  170. i, readl(&dev->op_regs->endptctrl[i]));
  171. }
  172. }
  173. #endif /* VERBOSE */
  174. /*-------------------------------------------------------------------------*/
  175. #define DIR_STRING(bAddress) (((bAddress) & USB_DIR_IN) ? "in" : "out")
  176. #define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \
  177. USB_DIR_IN) : ((ep)->desc->bEndpointAddress \
  178. & USB_DIR_IN) == USB_DIR_IN)
  179. #ifdef DEBUG
  180. static char *type_string(u8 bmAttributes)
  181. {
  182. switch ((bmAttributes) & USB_ENDPOINT_XFERTYPE_MASK) {
  183. case USB_ENDPOINT_XFER_BULK:
  184. return "bulk";
  185. case USB_ENDPOINT_XFER_ISOC:
  186. return "iso";
  187. case USB_ENDPOINT_XFER_INT:
  188. return "int";
  189. };
  190. return "control";
  191. }
  192. #endif
  193. /* configure endpoint control registers */
  194. static void ep_reset(struct langwell_ep *ep, unsigned char ep_num,
  195. unsigned char is_in, unsigned char ep_type)
  196. {
  197. struct langwell_udc *dev;
  198. u32 endptctrl;
  199. dev = ep->dev;
  200. VDBG(dev, "---> %s()\n", __func__);
  201. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  202. if (is_in) { /* TX */
  203. if (ep_num)
  204. endptctrl |= EPCTRL_TXR;
  205. endptctrl |= EPCTRL_TXE;
  206. endptctrl |= ep_type << EPCTRL_TXT_SHIFT;
  207. } else { /* RX */
  208. if (ep_num)
  209. endptctrl |= EPCTRL_RXR;
  210. endptctrl |= EPCTRL_RXE;
  211. endptctrl |= ep_type << EPCTRL_RXT_SHIFT;
  212. }
  213. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  214. VDBG(dev, "<--- %s()\n", __func__);
  215. }
  216. /* reset ep0 dQH and endptctrl */
  217. static void ep0_reset(struct langwell_udc *dev)
  218. {
  219. struct langwell_ep *ep;
  220. int i;
  221. VDBG(dev, "---> %s()\n", __func__);
  222. /* ep0 in and out */
  223. for (i = 0; i < 2; i++) {
  224. ep = &dev->ep[i];
  225. ep->dev = dev;
  226. /* ep0 dQH */
  227. ep->dqh = &dev->ep_dqh[i];
  228. /* configure ep0 endpoint capabilities in dQH */
  229. ep->dqh->dqh_ios = 1;
  230. ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE;
  231. /* FIXME: enable ep0-in HW zero length termination select */
  232. if (is_in(ep))
  233. ep->dqh->dqh_zlt = 0;
  234. ep->dqh->dqh_mult = 0;
  235. /* configure ep0 control registers */
  236. ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL);
  237. }
  238. VDBG(dev, "<--- %s()\n", __func__);
  239. return;
  240. }
  241. /*-------------------------------------------------------------------------*/
  242. /* endpoints operations */
  243. /* configure endpoint, making it usable */
  244. static int langwell_ep_enable(struct usb_ep *_ep,
  245. const struct usb_endpoint_descriptor *desc)
  246. {
  247. struct langwell_udc *dev;
  248. struct langwell_ep *ep;
  249. u16 max = 0;
  250. unsigned long flags;
  251. int retval = 0;
  252. unsigned char zlt, ios = 0, mult = 0;
  253. ep = container_of(_ep, struct langwell_ep, ep);
  254. dev = ep->dev;
  255. VDBG(dev, "---> %s()\n", __func__);
  256. if (!_ep || !desc || ep->desc
  257. || desc->bDescriptorType != USB_DT_ENDPOINT)
  258. return -EINVAL;
  259. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  260. return -ESHUTDOWN;
  261. max = le16_to_cpu(desc->wMaxPacketSize);
  262. /*
  263. * disable HW zero length termination select
  264. * driver handles zero length packet through req->req.zero
  265. */
  266. zlt = 1;
  267. /*
  268. * sanity check type, direction, address, and then
  269. * initialize the endpoint capabilities fields in dQH
  270. */
  271. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  272. case USB_ENDPOINT_XFER_CONTROL:
  273. ios = 1;
  274. break;
  275. case USB_ENDPOINT_XFER_BULK:
  276. if ((dev->gadget.speed == USB_SPEED_HIGH
  277. && max != 512)
  278. || (dev->gadget.speed == USB_SPEED_FULL
  279. && max > 64)) {
  280. goto done;
  281. }
  282. break;
  283. case USB_ENDPOINT_XFER_INT:
  284. if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
  285. goto done;
  286. switch (dev->gadget.speed) {
  287. case USB_SPEED_HIGH:
  288. if (max <= 1024)
  289. break;
  290. case USB_SPEED_FULL:
  291. if (max <= 64)
  292. break;
  293. default:
  294. if (max <= 8)
  295. break;
  296. goto done;
  297. }
  298. break;
  299. case USB_ENDPOINT_XFER_ISOC:
  300. if (strstr(ep->ep.name, "-bulk")
  301. || strstr(ep->ep.name, "-int"))
  302. goto done;
  303. switch (dev->gadget.speed) {
  304. case USB_SPEED_HIGH:
  305. if (max <= 1024)
  306. break;
  307. case USB_SPEED_FULL:
  308. if (max <= 1023)
  309. break;
  310. default:
  311. goto done;
  312. }
  313. /*
  314. * FIXME:
  315. * calculate transactions needed for high bandwidth iso
  316. */
  317. mult = (unsigned char)(1 + ((max >> 11) & 0x03));
  318. max = max & 0x8ff; /* bit 0~10 */
  319. /* 3 transactions at most */
  320. if (mult > 3)
  321. goto done;
  322. break;
  323. default:
  324. goto done;
  325. }
  326. spin_lock_irqsave(&dev->lock, flags);
  327. /* configure endpoint capabilities in dQH */
  328. ep->dqh->dqh_ios = ios;
  329. ep->dqh->dqh_mpl = cpu_to_le16(max);
  330. ep->dqh->dqh_zlt = zlt;
  331. ep->dqh->dqh_mult = mult;
  332. ep->ep.maxpacket = max;
  333. ep->desc = desc;
  334. ep->stopped = 0;
  335. ep->ep_num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  336. /* ep_type */
  337. ep->ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  338. /* configure endpoint control registers */
  339. ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type);
  340. DBG(dev, "enabled %s (ep%d%s-%s), max %04x\n",
  341. _ep->name,
  342. ep->ep_num,
  343. DIR_STRING(desc->bEndpointAddress),
  344. type_string(desc->bmAttributes),
  345. max);
  346. spin_unlock_irqrestore(&dev->lock, flags);
  347. done:
  348. VDBG(dev, "<--- %s()\n", __func__);
  349. return retval;
  350. }
  351. /*-------------------------------------------------------------------------*/
  352. /* retire a request */
  353. static void done(struct langwell_ep *ep, struct langwell_request *req,
  354. int status)
  355. {
  356. struct langwell_udc *dev = ep->dev;
  357. unsigned stopped = ep->stopped;
  358. struct langwell_dtd *curr_dtd, *next_dtd;
  359. int i;
  360. VDBG(dev, "---> %s()\n", __func__);
  361. /* remove the req from ep->queue */
  362. list_del_init(&req->queue);
  363. if (req->req.status == -EINPROGRESS)
  364. req->req.status = status;
  365. else
  366. status = req->req.status;
  367. /* free dTD for the request */
  368. next_dtd = req->head;
  369. for (i = 0; i < req->dtd_count; i++) {
  370. curr_dtd = next_dtd;
  371. if (i != req->dtd_count - 1)
  372. next_dtd = curr_dtd->next_dtd_virt;
  373. dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma);
  374. }
  375. if (req->mapped) {
  376. dma_unmap_single(&dev->pdev->dev, req->req.dma, req->req.length,
  377. is_in(ep) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  378. req->req.dma = DMA_ADDR_INVALID;
  379. req->mapped = 0;
  380. } else
  381. dma_sync_single_for_cpu(&dev->pdev->dev, req->req.dma,
  382. req->req.length,
  383. is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  384. if (status != -ESHUTDOWN)
  385. DBG(dev, "complete %s, req %p, stat %d, len %u/%u\n",
  386. ep->ep.name, &req->req, status,
  387. req->req.actual, req->req.length);
  388. /* don't modify queue heads during completion callback */
  389. ep->stopped = 1;
  390. spin_unlock(&dev->lock);
  391. /* complete routine from gadget driver */
  392. if (req->req.complete)
  393. req->req.complete(&ep->ep, &req->req);
  394. spin_lock(&dev->lock);
  395. ep->stopped = stopped;
  396. VDBG(dev, "<--- %s()\n", __func__);
  397. }
  398. static void langwell_ep_fifo_flush(struct usb_ep *_ep);
  399. /* delete all endpoint requests, called with spinlock held */
  400. static void nuke(struct langwell_ep *ep, int status)
  401. {
  402. /* called with spinlock held */
  403. ep->stopped = 1;
  404. /* endpoint fifo flush */
  405. if (&ep->ep && ep->desc)
  406. langwell_ep_fifo_flush(&ep->ep);
  407. while (!list_empty(&ep->queue)) {
  408. struct langwell_request *req = NULL;
  409. req = list_entry(ep->queue.next, struct langwell_request,
  410. queue);
  411. done(ep, req, status);
  412. }
  413. }
  414. /*-------------------------------------------------------------------------*/
  415. /* endpoint is no longer usable */
  416. static int langwell_ep_disable(struct usb_ep *_ep)
  417. {
  418. struct langwell_ep *ep;
  419. unsigned long flags;
  420. struct langwell_udc *dev;
  421. int ep_num;
  422. u32 endptctrl;
  423. ep = container_of(_ep, struct langwell_ep, ep);
  424. dev = ep->dev;
  425. VDBG(dev, "---> %s()\n", __func__);
  426. if (!_ep || !ep->desc)
  427. return -EINVAL;
  428. spin_lock_irqsave(&dev->lock, flags);
  429. /* disable endpoint control register */
  430. ep_num = ep->ep_num;
  431. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  432. if (is_in(ep))
  433. endptctrl &= ~EPCTRL_TXE;
  434. else
  435. endptctrl &= ~EPCTRL_RXE;
  436. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  437. /* nuke all pending requests (does flush) */
  438. nuke(ep, -ESHUTDOWN);
  439. ep->desc = NULL;
  440. ep->stopped = 1;
  441. spin_unlock_irqrestore(&dev->lock, flags);
  442. DBG(dev, "disabled %s\n", _ep->name);
  443. VDBG(dev, "<--- %s()\n", __func__);
  444. return 0;
  445. }
  446. /* allocate a request object to use with this endpoint */
  447. static struct usb_request *langwell_alloc_request(struct usb_ep *_ep,
  448. gfp_t gfp_flags)
  449. {
  450. struct langwell_ep *ep;
  451. struct langwell_udc *dev;
  452. struct langwell_request *req = NULL;
  453. if (!_ep)
  454. return NULL;
  455. ep = container_of(_ep, struct langwell_ep, ep);
  456. dev = ep->dev;
  457. VDBG(dev, "---> %s()\n", __func__);
  458. req = kzalloc(sizeof(*req), gfp_flags);
  459. if (!req)
  460. return NULL;
  461. req->req.dma = DMA_ADDR_INVALID;
  462. INIT_LIST_HEAD(&req->queue);
  463. VDBG(dev, "alloc request for %s\n", _ep->name);
  464. VDBG(dev, "<--- %s()\n", __func__);
  465. return &req->req;
  466. }
  467. /* free a request object */
  468. static void langwell_free_request(struct usb_ep *_ep,
  469. struct usb_request *_req)
  470. {
  471. struct langwell_ep *ep;
  472. struct langwell_udc *dev;
  473. struct langwell_request *req = NULL;
  474. ep = container_of(_ep, struct langwell_ep, ep);
  475. dev = ep->dev;
  476. VDBG(dev, "---> %s()\n", __func__);
  477. if (!_ep || !_req)
  478. return;
  479. req = container_of(_req, struct langwell_request, req);
  480. WARN_ON(!list_empty(&req->queue));
  481. if (_req)
  482. kfree(req);
  483. VDBG(dev, "free request for %s\n", _ep->name);
  484. VDBG(dev, "<--- %s()\n", __func__);
  485. }
  486. /*-------------------------------------------------------------------------*/
  487. /* queue dTD and PRIME endpoint */
  488. static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req)
  489. {
  490. u32 bit_mask, usbcmd, endptstat, dtd_dma;
  491. u8 dtd_status;
  492. int i;
  493. struct langwell_dqh *dqh;
  494. struct langwell_udc *dev;
  495. dev = ep->dev;
  496. VDBG(dev, "---> %s()\n", __func__);
  497. i = ep->ep_num * 2 + is_in(ep);
  498. dqh = &dev->ep_dqh[i];
  499. if (ep->ep_num)
  500. VDBG(dev, "%s\n", ep->name);
  501. else
  502. /* ep0 */
  503. VDBG(dev, "%s-%s\n", ep->name, is_in(ep) ? "in" : "out");
  504. VDBG(dev, "ep_dqh[%d] addr: 0x%08x\n", i, (u32)&(dev->ep_dqh[i]));
  505. bit_mask = is_in(ep) ?
  506. (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num));
  507. VDBG(dev, "bit_mask = 0x%08x\n", bit_mask);
  508. /* check if the pipe is empty */
  509. if (!(list_empty(&ep->queue))) {
  510. /* add dTD to the end of linked list */
  511. struct langwell_request *lastreq;
  512. lastreq = list_entry(ep->queue.prev,
  513. struct langwell_request, queue);
  514. lastreq->tail->dtd_next =
  515. cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK);
  516. /* read prime bit, if 1 goto out */
  517. if (readl(&dev->op_regs->endptprime) & bit_mask)
  518. goto out;
  519. do {
  520. /* set ATDTW bit in USBCMD */
  521. usbcmd = readl(&dev->op_regs->usbcmd);
  522. writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd);
  523. /* read correct status bit */
  524. endptstat = readl(&dev->op_regs->endptstat) & bit_mask;
  525. } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW));
  526. /* write ATDTW bit to 0 */
  527. usbcmd = readl(&dev->op_regs->usbcmd);
  528. writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd);
  529. if (endptstat)
  530. goto out;
  531. }
  532. /* write dQH next pointer and terminate bit to 0 */
  533. dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK;
  534. dqh->dtd_next = cpu_to_le32(dtd_dma);
  535. /* clear active and halt bit */
  536. dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED);
  537. dqh->dtd_status &= dtd_status;
  538. VDBG(dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status);
  539. /* write 1 to endptprime register to PRIME endpoint */
  540. bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num);
  541. VDBG(dev, "endprime bit_mask = 0x%08x\n", bit_mask);
  542. writel(bit_mask, &dev->op_regs->endptprime);
  543. out:
  544. VDBG(dev, "<--- %s()\n", __func__);
  545. return 0;
  546. }
  547. /* fill in the dTD structure to build a transfer descriptor */
  548. static struct langwell_dtd *build_dtd(struct langwell_request *req,
  549. unsigned *length, dma_addr_t *dma, int *is_last)
  550. {
  551. u32 buf_ptr;
  552. struct langwell_dtd *dtd;
  553. struct langwell_udc *dev;
  554. int i;
  555. dev = req->ep->dev;
  556. VDBG(dev, "---> %s()\n", __func__);
  557. /* the maximum transfer length, up to 16k bytes */
  558. *length = min(req->req.length - req->req.actual,
  559. (unsigned)DTD_MAX_TRANSFER_LENGTH);
  560. /* create dTD dma_pool resource */
  561. dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma);
  562. if (dtd == NULL)
  563. return dtd;
  564. dtd->dtd_dma = *dma;
  565. /* initialize buffer page pointers */
  566. buf_ptr = (u32)(req->req.dma + req->req.actual);
  567. for (i = 0; i < 5; i++)
  568. dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE);
  569. req->req.actual += *length;
  570. /* fill in total bytes with transfer size */
  571. dtd->dtd_total = cpu_to_le16(*length);
  572. VDBG(dev, "dtd->dtd_total = %d\n", dtd->dtd_total);
  573. /* set is_last flag if req->req.zero is set or not */
  574. if (req->req.zero) {
  575. if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
  576. *is_last = 1;
  577. else
  578. *is_last = 0;
  579. } else if (req->req.length == req->req.actual) {
  580. *is_last = 1;
  581. } else
  582. *is_last = 0;
  583. if (*is_last == 0)
  584. VDBG(dev, "multi-dtd request!\n");
  585. /* set interrupt on complete bit for the last dTD */
  586. if (*is_last && !req->req.no_interrupt)
  587. dtd->dtd_ioc = 1;
  588. /* set multiplier override 0 for non-ISO and non-TX endpoint */
  589. dtd->dtd_multo = 0;
  590. /* set the active bit of status field to 1 */
  591. dtd->dtd_status = DTD_STS_ACTIVE;
  592. VDBG(dev, "dtd->dtd_status = 0x%02x\n", dtd->dtd_status);
  593. VDBG(dev, "length = %d, dma addr= 0x%08x\n", *length, (int)*dma);
  594. VDBG(dev, "<--- %s()\n", __func__);
  595. return dtd;
  596. }
  597. /* generate dTD linked list for a request */
  598. static int req_to_dtd(struct langwell_request *req)
  599. {
  600. unsigned count;
  601. int is_last, is_first = 1;
  602. struct langwell_dtd *dtd, *last_dtd = NULL;
  603. struct langwell_udc *dev;
  604. dma_addr_t dma;
  605. dev = req->ep->dev;
  606. VDBG(dev, "---> %s()\n", __func__);
  607. do {
  608. dtd = build_dtd(req, &count, &dma, &is_last);
  609. if (dtd == NULL)
  610. return -ENOMEM;
  611. if (is_first) {
  612. is_first = 0;
  613. req->head = dtd;
  614. } else {
  615. last_dtd->dtd_next = cpu_to_le32(dma);
  616. last_dtd->next_dtd_virt = dtd;
  617. }
  618. last_dtd = dtd;
  619. req->dtd_count++;
  620. } while (!is_last);
  621. /* set terminate bit to 1 for the last dTD */
  622. dtd->dtd_next = DTD_TERM;
  623. req->tail = dtd;
  624. VDBG(dev, "<--- %s()\n", __func__);
  625. return 0;
  626. }
  627. /*-------------------------------------------------------------------------*/
  628. /* queue (submits) an I/O requests to an endpoint */
  629. static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
  630. gfp_t gfp_flags)
  631. {
  632. struct langwell_request *req;
  633. struct langwell_ep *ep;
  634. struct langwell_udc *dev;
  635. unsigned long flags;
  636. int is_iso = 0, zlflag = 0;
  637. /* always require a cpu-view buffer */
  638. req = container_of(_req, struct langwell_request, req);
  639. ep = container_of(_ep, struct langwell_ep, ep);
  640. if (!_req || !_req->complete || !_req->buf
  641. || !list_empty(&req->queue)) {
  642. return -EINVAL;
  643. }
  644. if (unlikely(!_ep || !ep->desc))
  645. return -EINVAL;
  646. dev = ep->dev;
  647. req->ep = ep;
  648. VDBG(dev, "---> %s()\n", __func__);
  649. if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
  650. if (req->req.length > ep->ep.maxpacket)
  651. return -EMSGSIZE;
  652. is_iso = 1;
  653. }
  654. if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN))
  655. return -ESHUTDOWN;
  656. /* set up dma mapping in case the caller didn't */
  657. if (_req->dma == DMA_ADDR_INVALID) {
  658. /* WORKAROUND: WARN_ON(size == 0) */
  659. if (_req->length == 0) {
  660. VDBG(dev, "req->length: 0->1\n");
  661. zlflag = 1;
  662. _req->length++;
  663. }
  664. _req->dma = dma_map_single(&dev->pdev->dev,
  665. _req->buf, _req->length,
  666. is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  667. if (zlflag && (_req->length == 1)) {
  668. VDBG(dev, "req->length: 1->0\n");
  669. zlflag = 0;
  670. _req->length = 0;
  671. }
  672. req->mapped = 1;
  673. VDBG(dev, "req->mapped = 1\n");
  674. } else {
  675. dma_sync_single_for_device(&dev->pdev->dev,
  676. _req->dma, _req->length,
  677. is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  678. req->mapped = 0;
  679. VDBG(dev, "req->mapped = 0\n");
  680. }
  681. DBG(dev, "%s queue req %p, len %u, buf %p, dma 0x%08x\n",
  682. _ep->name,
  683. _req, _req->length, _req->buf, _req->dma);
  684. _req->status = -EINPROGRESS;
  685. _req->actual = 0;
  686. req->dtd_count = 0;
  687. spin_lock_irqsave(&dev->lock, flags);
  688. /* build and put dTDs to endpoint queue */
  689. if (!req_to_dtd(req)) {
  690. queue_dtd(ep, req);
  691. } else {
  692. spin_unlock_irqrestore(&dev->lock, flags);
  693. return -ENOMEM;
  694. }
  695. /* update ep0 state */
  696. if (ep->ep_num == 0)
  697. dev->ep0_state = DATA_STATE_XMIT;
  698. if (likely(req != NULL)) {
  699. list_add_tail(&req->queue, &ep->queue);
  700. VDBG(dev, "list_add_tail() \n");
  701. }
  702. spin_unlock_irqrestore(&dev->lock, flags);
  703. VDBG(dev, "<--- %s()\n", __func__);
  704. return 0;
  705. }
  706. /* dequeue (cancels, unlinks) an I/O request from an endpoint */
  707. static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  708. {
  709. struct langwell_ep *ep;
  710. struct langwell_udc *dev;
  711. struct langwell_request *req;
  712. unsigned long flags;
  713. int stopped, ep_num, retval = 0;
  714. u32 endptctrl;
  715. ep = container_of(_ep, struct langwell_ep, ep);
  716. dev = ep->dev;
  717. VDBG(dev, "---> %s()\n", __func__);
  718. if (!_ep || !ep->desc || !_req)
  719. return -EINVAL;
  720. if (!dev->driver)
  721. return -ESHUTDOWN;
  722. spin_lock_irqsave(&dev->lock, flags);
  723. stopped = ep->stopped;
  724. /* quiesce dma while we patch the queue */
  725. ep->stopped = 1;
  726. ep_num = ep->ep_num;
  727. /* disable endpoint control register */
  728. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  729. if (is_in(ep))
  730. endptctrl &= ~EPCTRL_TXE;
  731. else
  732. endptctrl &= ~EPCTRL_RXE;
  733. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  734. /* make sure it's still queued on this endpoint */
  735. list_for_each_entry(req, &ep->queue, queue) {
  736. if (&req->req == _req)
  737. break;
  738. }
  739. if (&req->req != _req) {
  740. retval = -EINVAL;
  741. goto done;
  742. }
  743. /* queue head may be partially complete. */
  744. if (ep->queue.next == &req->queue) {
  745. DBG(dev, "unlink (%s) dma\n", _ep->name);
  746. _req->status = -ECONNRESET;
  747. langwell_ep_fifo_flush(&ep->ep);
  748. /* not the last request in endpoint queue */
  749. if (likely(ep->queue.next == &req->queue)) {
  750. struct langwell_dqh *dqh;
  751. struct langwell_request *next_req;
  752. dqh = ep->dqh;
  753. next_req = list_entry(req->queue.next,
  754. struct langwell_request, queue);
  755. /* point the dQH to the first dTD of next request */
  756. writel((u32) next_req->head, &dqh->dqh_current);
  757. }
  758. } else {
  759. struct langwell_request *prev_req;
  760. prev_req = list_entry(req->queue.prev,
  761. struct langwell_request, queue);
  762. writel(readl(&req->tail->dtd_next),
  763. &prev_req->tail->dtd_next);
  764. }
  765. done(ep, req, -ECONNRESET);
  766. done:
  767. /* enable endpoint again */
  768. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  769. if (is_in(ep))
  770. endptctrl |= EPCTRL_TXE;
  771. else
  772. endptctrl |= EPCTRL_RXE;
  773. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  774. ep->stopped = stopped;
  775. spin_unlock_irqrestore(&dev->lock, flags);
  776. VDBG(dev, "<--- %s()\n", __func__);
  777. return retval;
  778. }
  779. /*-------------------------------------------------------------------------*/
  780. /* endpoint set/clear halt */
  781. static void ep_set_halt(struct langwell_ep *ep, int value)
  782. {
  783. u32 endptctrl = 0;
  784. int ep_num;
  785. struct langwell_udc *dev = ep->dev;
  786. VDBG(dev, "---> %s()\n", __func__);
  787. ep_num = ep->ep_num;
  788. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  789. /* value: 1 - set halt, 0 - clear halt */
  790. if (value) {
  791. /* set the stall bit */
  792. if (is_in(ep))
  793. endptctrl |= EPCTRL_TXS;
  794. else
  795. endptctrl |= EPCTRL_RXS;
  796. } else {
  797. /* clear the stall bit and reset data toggle */
  798. if (is_in(ep)) {
  799. endptctrl &= ~EPCTRL_TXS;
  800. endptctrl |= EPCTRL_TXR;
  801. } else {
  802. endptctrl &= ~EPCTRL_RXS;
  803. endptctrl |= EPCTRL_RXR;
  804. }
  805. }
  806. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  807. VDBG(dev, "<--- %s()\n", __func__);
  808. }
  809. /* set the endpoint halt feature */
  810. static int langwell_ep_set_halt(struct usb_ep *_ep, int value)
  811. {
  812. struct langwell_ep *ep;
  813. struct langwell_udc *dev;
  814. unsigned long flags;
  815. int retval = 0;
  816. ep = container_of(_ep, struct langwell_ep, ep);
  817. dev = ep->dev;
  818. VDBG(dev, "---> %s()\n", __func__);
  819. if (!_ep || !ep->desc)
  820. return -EINVAL;
  821. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  822. return -ESHUTDOWN;
  823. if (ep->desc && (ep->desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
  824. == USB_ENDPOINT_XFER_ISOC)
  825. return -EOPNOTSUPP;
  826. spin_lock_irqsave(&dev->lock, flags);
  827. /*
  828. * attempt to halt IN ep will fail if any transfer requests
  829. * are still queue
  830. */
  831. if (!list_empty(&ep->queue) && is_in(ep) && value) {
  832. /* IN endpoint FIFO holds bytes */
  833. DBG(dev, "%s FIFO holds bytes\n", _ep->name);
  834. retval = -EAGAIN;
  835. goto done;
  836. }
  837. /* endpoint set/clear halt */
  838. if (ep->ep_num) {
  839. ep_set_halt(ep, value);
  840. } else { /* endpoint 0 */
  841. dev->ep0_state = WAIT_FOR_SETUP;
  842. dev->ep0_dir = USB_DIR_OUT;
  843. }
  844. done:
  845. spin_unlock_irqrestore(&dev->lock, flags);
  846. DBG(dev, "%s %s halt\n", _ep->name, value ? "set" : "clear");
  847. VDBG(dev, "<--- %s()\n", __func__);
  848. return retval;
  849. }
  850. /* set the halt feature and ignores clear requests */
  851. static int langwell_ep_set_wedge(struct usb_ep *_ep)
  852. {
  853. struct langwell_ep *ep;
  854. struct langwell_udc *dev;
  855. ep = container_of(_ep, struct langwell_ep, ep);
  856. dev = ep->dev;
  857. VDBG(dev, "---> %s()\n", __func__);
  858. if (!_ep || !ep->desc)
  859. return -EINVAL;
  860. VDBG(dev, "<--- %s()\n", __func__);
  861. return usb_ep_set_halt(_ep);
  862. }
  863. /* flush contents of a fifo */
  864. static void langwell_ep_fifo_flush(struct usb_ep *_ep)
  865. {
  866. struct langwell_ep *ep;
  867. struct langwell_udc *dev;
  868. u32 flush_bit;
  869. unsigned long timeout;
  870. ep = container_of(_ep, struct langwell_ep, ep);
  871. dev = ep->dev;
  872. VDBG(dev, "---> %s()\n", __func__);
  873. if (!_ep || !ep->desc) {
  874. VDBG(dev, "ep or ep->desc is NULL\n");
  875. VDBG(dev, "<--- %s()\n", __func__);
  876. return;
  877. }
  878. VDBG(dev, "%s-%s fifo flush\n", _ep->name, is_in(ep) ? "in" : "out");
  879. /* flush endpoint buffer */
  880. if (ep->ep_num == 0)
  881. flush_bit = (1 << 16) | 1;
  882. else if (is_in(ep))
  883. flush_bit = 1 << (ep->ep_num + 16); /* TX */
  884. else
  885. flush_bit = 1 << ep->ep_num; /* RX */
  886. /* wait until flush complete */
  887. timeout = jiffies + FLUSH_TIMEOUT;
  888. do {
  889. writel(flush_bit, &dev->op_regs->endptflush);
  890. while (readl(&dev->op_regs->endptflush)) {
  891. if (time_after(jiffies, timeout)) {
  892. ERROR(dev, "ep flush timeout\n");
  893. goto done;
  894. }
  895. cpu_relax();
  896. }
  897. } while (readl(&dev->op_regs->endptstat) & flush_bit);
  898. done:
  899. VDBG(dev, "<--- %s()\n", __func__);
  900. }
  901. /* endpoints operations structure */
  902. static const struct usb_ep_ops langwell_ep_ops = {
  903. /* configure endpoint, making it usable */
  904. .enable = langwell_ep_enable,
  905. /* endpoint is no longer usable */
  906. .disable = langwell_ep_disable,
  907. /* allocate a request object to use with this endpoint */
  908. .alloc_request = langwell_alloc_request,
  909. /* free a request object */
  910. .free_request = langwell_free_request,
  911. /* queue (submits) an I/O requests to an endpoint */
  912. .queue = langwell_ep_queue,
  913. /* dequeue (cancels, unlinks) an I/O request from an endpoint */
  914. .dequeue = langwell_ep_dequeue,
  915. /* set the endpoint halt feature */
  916. .set_halt = langwell_ep_set_halt,
  917. /* set the halt feature and ignores clear requests */
  918. .set_wedge = langwell_ep_set_wedge,
  919. /* flush contents of a fifo */
  920. .fifo_flush = langwell_ep_fifo_flush,
  921. };
  922. /*-------------------------------------------------------------------------*/
  923. /* device controller usb_gadget_ops structure */
  924. /* returns the current frame number */
  925. static int langwell_get_frame(struct usb_gadget *_gadget)
  926. {
  927. struct langwell_udc *dev;
  928. u16 retval;
  929. if (!_gadget)
  930. return -ENODEV;
  931. dev = container_of(_gadget, struct langwell_udc, gadget);
  932. VDBG(dev, "---> %s()\n", __func__);
  933. retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK;
  934. VDBG(dev, "<--- %s()\n", __func__);
  935. return retval;
  936. }
  937. /* tries to wake up the host connected to this gadget */
  938. static int langwell_wakeup(struct usb_gadget *_gadget)
  939. {
  940. struct langwell_udc *dev;
  941. u32 portsc1, devlc;
  942. unsigned long flags;
  943. if (!_gadget)
  944. return 0;
  945. dev = container_of(_gadget, struct langwell_udc, gadget);
  946. VDBG(dev, "---> %s()\n", __func__);
  947. /* Remote Wakeup feature not enabled by host */
  948. if (!dev->remote_wakeup)
  949. return -ENOTSUPP;
  950. spin_lock_irqsave(&dev->lock, flags);
  951. portsc1 = readl(&dev->op_regs->portsc1);
  952. if (!(portsc1 & PORTS_SUSP)) {
  953. spin_unlock_irqrestore(&dev->lock, flags);
  954. return 0;
  955. }
  956. /* LPM L1 to L0, remote wakeup */
  957. if (dev->lpm && dev->lpm_state == LPM_L1) {
  958. portsc1 |= PORTS_SLP;
  959. writel(portsc1, &dev->op_regs->portsc1);
  960. }
  961. /* force port resume */
  962. if (dev->usb_state == USB_STATE_SUSPENDED) {
  963. portsc1 |= PORTS_FPR;
  964. writel(portsc1, &dev->op_regs->portsc1);
  965. }
  966. /* exit PHY low power suspend */
  967. devlc = readl(&dev->op_regs->devlc);
  968. VDBG(dev, "devlc = 0x%08x\n", devlc);
  969. devlc &= ~LPM_PHCD;
  970. writel(devlc, &dev->op_regs->devlc);
  971. spin_unlock_irqrestore(&dev->lock, flags);
  972. VDBG(dev, "<--- %s()\n", __func__);
  973. return 0;
  974. }
  975. /* notify controller that VBUS is powered or not */
  976. static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active)
  977. {
  978. struct langwell_udc *dev;
  979. unsigned long flags;
  980. u32 usbcmd;
  981. if (!_gadget)
  982. return -ENODEV;
  983. dev = container_of(_gadget, struct langwell_udc, gadget);
  984. VDBG(dev, "---> %s()\n", __func__);
  985. spin_lock_irqsave(&dev->lock, flags);
  986. VDBG(dev, "VBUS status: %s\n", is_active ? "on" : "off");
  987. dev->vbus_active = (is_active != 0);
  988. if (dev->driver && dev->softconnected && dev->vbus_active) {
  989. usbcmd = readl(&dev->op_regs->usbcmd);
  990. usbcmd |= CMD_RUNSTOP;
  991. writel(usbcmd, &dev->op_regs->usbcmd);
  992. } else {
  993. usbcmd = readl(&dev->op_regs->usbcmd);
  994. usbcmd &= ~CMD_RUNSTOP;
  995. writel(usbcmd, &dev->op_regs->usbcmd);
  996. }
  997. spin_unlock_irqrestore(&dev->lock, flags);
  998. VDBG(dev, "<--- %s()\n", __func__);
  999. return 0;
  1000. }
  1001. /* constrain controller's VBUS power usage */
  1002. static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  1003. {
  1004. struct langwell_udc *dev;
  1005. if (!_gadget)
  1006. return -ENODEV;
  1007. dev = container_of(_gadget, struct langwell_udc, gadget);
  1008. VDBG(dev, "---> %s()\n", __func__);
  1009. if (dev->transceiver) {
  1010. VDBG(dev, "otg_set_power\n");
  1011. VDBG(dev, "<--- %s()\n", __func__);
  1012. return otg_set_power(dev->transceiver, mA);
  1013. }
  1014. VDBG(dev, "<--- %s()\n", __func__);
  1015. return -ENOTSUPP;
  1016. }
  1017. /* D+ pullup, software-controlled connect/disconnect to USB host */
  1018. static int langwell_pullup(struct usb_gadget *_gadget, int is_on)
  1019. {
  1020. struct langwell_udc *dev;
  1021. u32 usbcmd;
  1022. unsigned long flags;
  1023. if (!_gadget)
  1024. return -ENODEV;
  1025. dev = container_of(_gadget, struct langwell_udc, gadget);
  1026. VDBG(dev, "---> %s()\n", __func__);
  1027. spin_lock_irqsave(&dev->lock, flags);
  1028. dev->softconnected = (is_on != 0);
  1029. if (dev->driver && dev->softconnected && dev->vbus_active) {
  1030. usbcmd = readl(&dev->op_regs->usbcmd);
  1031. usbcmd |= CMD_RUNSTOP;
  1032. writel(usbcmd, &dev->op_regs->usbcmd);
  1033. } else {
  1034. usbcmd = readl(&dev->op_regs->usbcmd);
  1035. usbcmd &= ~CMD_RUNSTOP;
  1036. writel(usbcmd, &dev->op_regs->usbcmd);
  1037. }
  1038. spin_unlock_irqrestore(&dev->lock, flags);
  1039. VDBG(dev, "<--- %s()\n", __func__);
  1040. return 0;
  1041. }
  1042. /* device controller usb_gadget_ops structure */
  1043. static const struct usb_gadget_ops langwell_ops = {
  1044. /* returns the current frame number */
  1045. .get_frame = langwell_get_frame,
  1046. /* tries to wake up the host connected to this gadget */
  1047. .wakeup = langwell_wakeup,
  1048. /* set the device selfpowered feature, always selfpowered */
  1049. /* .set_selfpowered = langwell_set_selfpowered, */
  1050. /* notify controller that VBUS is powered or not */
  1051. .vbus_session = langwell_vbus_session,
  1052. /* constrain controller's VBUS power usage */
  1053. .vbus_draw = langwell_vbus_draw,
  1054. /* D+ pullup, software-controlled connect/disconnect to USB host */
  1055. .pullup = langwell_pullup,
  1056. };
  1057. /*-------------------------------------------------------------------------*/
  1058. /* device controller operations */
  1059. /* reset device controller */
  1060. static int langwell_udc_reset(struct langwell_udc *dev)
  1061. {
  1062. u32 usbcmd, usbmode, devlc, endpointlistaddr;
  1063. unsigned long timeout;
  1064. if (!dev)
  1065. return -EINVAL;
  1066. DBG(dev, "---> %s()\n", __func__);
  1067. /* set controller to stop state */
  1068. usbcmd = readl(&dev->op_regs->usbcmd);
  1069. usbcmd &= ~CMD_RUNSTOP;
  1070. writel(usbcmd, &dev->op_regs->usbcmd);
  1071. /* reset device controller */
  1072. usbcmd = readl(&dev->op_regs->usbcmd);
  1073. usbcmd |= CMD_RST;
  1074. writel(usbcmd, &dev->op_regs->usbcmd);
  1075. /* wait for reset to complete */
  1076. timeout = jiffies + RESET_TIMEOUT;
  1077. while (readl(&dev->op_regs->usbcmd) & CMD_RST) {
  1078. if (time_after(jiffies, timeout)) {
  1079. ERROR(dev, "device reset timeout\n");
  1080. return -ETIMEDOUT;
  1081. }
  1082. cpu_relax();
  1083. }
  1084. /* set controller to device mode */
  1085. usbmode = readl(&dev->op_regs->usbmode);
  1086. usbmode |= MODE_DEVICE;
  1087. /* turn setup lockout off, require setup tripwire in usbcmd */
  1088. usbmode |= MODE_SLOM;
  1089. writel(usbmode, &dev->op_regs->usbmode);
  1090. usbmode = readl(&dev->op_regs->usbmode);
  1091. VDBG(dev, "usbmode=0x%08x\n", usbmode);
  1092. /* Write-Clear setup status */
  1093. writel(0, &dev->op_regs->usbsts);
  1094. /* if support USB LPM, ACK all LPM token */
  1095. if (dev->lpm) {
  1096. devlc = readl(&dev->op_regs->devlc);
  1097. devlc &= ~LPM_STL; /* don't STALL LPM token */
  1098. devlc &= ~LPM_NYT_ACK; /* ACK LPM token */
  1099. writel(devlc, &dev->op_regs->devlc);
  1100. }
  1101. /* fill endpointlistaddr register */
  1102. endpointlistaddr = dev->ep_dqh_dma;
  1103. endpointlistaddr &= ENDPOINTLISTADDR_MASK;
  1104. writel(endpointlistaddr, &dev->op_regs->endpointlistaddr);
  1105. VDBG(dev, "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n",
  1106. dev->ep_dqh, endpointlistaddr,
  1107. readl(&dev->op_regs->endpointlistaddr));
  1108. DBG(dev, "<--- %s()\n", __func__);
  1109. return 0;
  1110. }
  1111. /* reinitialize device controller endpoints */
  1112. static int eps_reinit(struct langwell_udc *dev)
  1113. {
  1114. struct langwell_ep *ep;
  1115. char name[14];
  1116. int i;
  1117. VDBG(dev, "---> %s()\n", __func__);
  1118. /* initialize ep0 */
  1119. ep = &dev->ep[0];
  1120. ep->dev = dev;
  1121. strncpy(ep->name, "ep0", sizeof(ep->name));
  1122. ep->ep.name = ep->name;
  1123. ep->ep.ops = &langwell_ep_ops;
  1124. ep->stopped = 0;
  1125. ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
  1126. ep->ep_num = 0;
  1127. ep->desc = &langwell_ep0_desc;
  1128. INIT_LIST_HEAD(&ep->queue);
  1129. ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
  1130. /* initialize other endpoints */
  1131. for (i = 2; i < dev->ep_max; i++) {
  1132. ep = &dev->ep[i];
  1133. if (i % 2)
  1134. snprintf(name, sizeof(name), "ep%din", i / 2);
  1135. else
  1136. snprintf(name, sizeof(name), "ep%dout", i / 2);
  1137. ep->dev = dev;
  1138. strncpy(ep->name, name, sizeof(ep->name));
  1139. ep->ep.name = ep->name;
  1140. ep->ep.ops = &langwell_ep_ops;
  1141. ep->stopped = 0;
  1142. ep->ep.maxpacket = (unsigned short) ~0;
  1143. ep->ep_num = i / 2;
  1144. INIT_LIST_HEAD(&ep->queue);
  1145. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  1146. ep->dqh = &dev->ep_dqh[i];
  1147. }
  1148. VDBG(dev, "<--- %s()\n", __func__);
  1149. return 0;
  1150. }
  1151. /* enable interrupt and set controller to run state */
  1152. static void langwell_udc_start(struct langwell_udc *dev)
  1153. {
  1154. u32 usbintr, usbcmd;
  1155. DBG(dev, "---> %s()\n", __func__);
  1156. /* enable interrupts */
  1157. usbintr = INTR_ULPIE /* ULPI */
  1158. | INTR_SLE /* suspend */
  1159. /* | INTR_SRE SOF received */
  1160. | INTR_URE /* USB reset */
  1161. | INTR_AAE /* async advance */
  1162. | INTR_SEE /* system error */
  1163. | INTR_FRE /* frame list rollover */
  1164. | INTR_PCE /* port change detect */
  1165. | INTR_UEE /* USB error interrupt */
  1166. | INTR_UE; /* USB interrupt */
  1167. writel(usbintr, &dev->op_regs->usbintr);
  1168. /* clear stopped bit */
  1169. dev->stopped = 0;
  1170. /* set controller to run */
  1171. usbcmd = readl(&dev->op_regs->usbcmd);
  1172. usbcmd |= CMD_RUNSTOP;
  1173. writel(usbcmd, &dev->op_regs->usbcmd);
  1174. DBG(dev, "<--- %s()\n", __func__);
  1175. return;
  1176. }
  1177. /* disable interrupt and set controller to stop state */
  1178. static void langwell_udc_stop(struct langwell_udc *dev)
  1179. {
  1180. u32 usbcmd;
  1181. DBG(dev, "---> %s()\n", __func__);
  1182. /* disable all interrupts */
  1183. writel(0, &dev->op_regs->usbintr);
  1184. /* set stopped bit */
  1185. dev->stopped = 1;
  1186. /* set controller to stop state */
  1187. usbcmd = readl(&dev->op_regs->usbcmd);
  1188. usbcmd &= ~CMD_RUNSTOP;
  1189. writel(usbcmd, &dev->op_regs->usbcmd);
  1190. DBG(dev, "<--- %s()\n", __func__);
  1191. return;
  1192. }
  1193. /* stop all USB activities */
  1194. static void stop_activity(struct langwell_udc *dev,
  1195. struct usb_gadget_driver *driver)
  1196. {
  1197. struct langwell_ep *ep;
  1198. DBG(dev, "---> %s()\n", __func__);
  1199. nuke(&dev->ep[0], -ESHUTDOWN);
  1200. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1201. nuke(ep, -ESHUTDOWN);
  1202. }
  1203. /* report disconnect; the driver is already quiesced */
  1204. if (driver) {
  1205. spin_unlock(&dev->lock);
  1206. driver->disconnect(&dev->gadget);
  1207. spin_lock(&dev->lock);
  1208. }
  1209. DBG(dev, "<--- %s()\n", __func__);
  1210. }
  1211. /*-------------------------------------------------------------------------*/
  1212. /* device "function" sysfs attribute file */
  1213. static ssize_t show_function(struct device *_dev,
  1214. struct device_attribute *attr, char *buf)
  1215. {
  1216. struct langwell_udc *dev = the_controller;
  1217. if (!dev->driver || !dev->driver->function
  1218. || strlen(dev->driver->function) > PAGE_SIZE)
  1219. return 0;
  1220. return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
  1221. }
  1222. static DEVICE_ATTR(function, S_IRUGO, show_function, NULL);
  1223. /* device "langwell_udc" sysfs attribute file */
  1224. static ssize_t show_langwell_udc(struct device *_dev,
  1225. struct device_attribute *attr, char *buf)
  1226. {
  1227. struct langwell_udc *dev = the_controller;
  1228. struct langwell_request *req;
  1229. struct langwell_ep *ep = NULL;
  1230. char *next;
  1231. unsigned size;
  1232. unsigned t;
  1233. unsigned i;
  1234. unsigned long flags;
  1235. u32 tmp_reg;
  1236. next = buf;
  1237. size = PAGE_SIZE;
  1238. spin_lock_irqsave(&dev->lock, flags);
  1239. /* driver basic information */
  1240. t = scnprintf(next, size,
  1241. DRIVER_DESC "\n"
  1242. "%s version: %s\n"
  1243. "Gadget driver: %s\n\n",
  1244. driver_name, DRIVER_VERSION,
  1245. dev->driver ? dev->driver->driver.name : "(none)");
  1246. size -= t;
  1247. next += t;
  1248. /* device registers */
  1249. tmp_reg = readl(&dev->op_regs->usbcmd);
  1250. t = scnprintf(next, size,
  1251. "USBCMD reg:\n"
  1252. "SetupTW: %d\n"
  1253. "Run/Stop: %s\n\n",
  1254. (tmp_reg & CMD_SUTW) ? 1 : 0,
  1255. (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop");
  1256. size -= t;
  1257. next += t;
  1258. tmp_reg = readl(&dev->op_regs->usbsts);
  1259. t = scnprintf(next, size,
  1260. "USB Status Reg:\n"
  1261. "Device Suspend: %d\n"
  1262. "Reset Received: %d\n"
  1263. "System Error: %s\n"
  1264. "USB Error Interrupt: %s\n\n",
  1265. (tmp_reg & STS_SLI) ? 1 : 0,
  1266. (tmp_reg & STS_URI) ? 1 : 0,
  1267. (tmp_reg & STS_SEI) ? "Error" : "No error",
  1268. (tmp_reg & STS_UEI) ? "Error detected" : "No error");
  1269. size -= t;
  1270. next += t;
  1271. tmp_reg = readl(&dev->op_regs->usbintr);
  1272. t = scnprintf(next, size,
  1273. "USB Intrrupt Enable Reg:\n"
  1274. "Sleep Enable: %d\n"
  1275. "SOF Received Enable: %d\n"
  1276. "Reset Enable: %d\n"
  1277. "System Error Enable: %d\n"
  1278. "Port Change Dectected Enable: %d\n"
  1279. "USB Error Intr Enable: %d\n"
  1280. "USB Intr Enable: %d\n\n",
  1281. (tmp_reg & INTR_SLE) ? 1 : 0,
  1282. (tmp_reg & INTR_SRE) ? 1 : 0,
  1283. (tmp_reg & INTR_URE) ? 1 : 0,
  1284. (tmp_reg & INTR_SEE) ? 1 : 0,
  1285. (tmp_reg & INTR_PCE) ? 1 : 0,
  1286. (tmp_reg & INTR_UEE) ? 1 : 0,
  1287. (tmp_reg & INTR_UE) ? 1 : 0);
  1288. size -= t;
  1289. next += t;
  1290. tmp_reg = readl(&dev->op_regs->frindex);
  1291. t = scnprintf(next, size,
  1292. "USB Frame Index Reg:\n"
  1293. "Frame Number is 0x%08x\n\n",
  1294. (tmp_reg & FRINDEX_MASK));
  1295. size -= t;
  1296. next += t;
  1297. tmp_reg = readl(&dev->op_regs->deviceaddr);
  1298. t = scnprintf(next, size,
  1299. "USB Device Address Reg:\n"
  1300. "Device Addr is 0x%x\n\n",
  1301. USBADR(tmp_reg));
  1302. size -= t;
  1303. next += t;
  1304. tmp_reg = readl(&dev->op_regs->endpointlistaddr);
  1305. t = scnprintf(next, size,
  1306. "USB Endpoint List Address Reg:\n"
  1307. "Endpoint List Pointer is 0x%x\n\n",
  1308. EPBASE(tmp_reg));
  1309. size -= t;
  1310. next += t;
  1311. tmp_reg = readl(&dev->op_regs->portsc1);
  1312. t = scnprintf(next, size,
  1313. "USB Port Status & Control Reg:\n"
  1314. "Port Reset: %s\n"
  1315. "Port Suspend Mode: %s\n"
  1316. "Over-current Change: %s\n"
  1317. "Port Enable/Disable Change: %s\n"
  1318. "Port Enabled/Disabled: %s\n"
  1319. "Current Connect Status: %s\n\n",
  1320. (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset",
  1321. (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend",
  1322. (tmp_reg & PORTS_OCC) ? "Detected" : "No",
  1323. (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed",
  1324. (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct",
  1325. (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached");
  1326. size -= t;
  1327. next += t;
  1328. tmp_reg = readl(&dev->op_regs->devlc);
  1329. t = scnprintf(next, size,
  1330. "Device LPM Control Reg:\n"
  1331. "Parallel Transceiver : %d\n"
  1332. "Serial Transceiver : %d\n"
  1333. "Port Speed: %s\n"
  1334. "Port Force Full Speed Connenct: %s\n"
  1335. "PHY Low Power Suspend Clock Disable: %s\n"
  1336. "BmAttributes: %d\n\n",
  1337. LPM_PTS(tmp_reg),
  1338. (tmp_reg & LPM_STS) ? 1 : 0,
  1339. ({
  1340. char *s;
  1341. switch (LPM_PSPD(tmp_reg)) {
  1342. case LPM_SPEED_FULL:
  1343. s = "Full Speed"; break;
  1344. case LPM_SPEED_LOW:
  1345. s = "Low Speed"; break;
  1346. case LPM_SPEED_HIGH:
  1347. s = "High Speed"; break;
  1348. default:
  1349. s = "Unknown Speed"; break;
  1350. }
  1351. s;
  1352. }),
  1353. (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force",
  1354. (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled",
  1355. LPM_BA(tmp_reg));
  1356. size -= t;
  1357. next += t;
  1358. tmp_reg = readl(&dev->op_regs->usbmode);
  1359. t = scnprintf(next, size,
  1360. "USB Mode Reg:\n"
  1361. "Controller Mode is : %s\n\n", ({
  1362. char *s;
  1363. switch (MODE_CM(tmp_reg)) {
  1364. case MODE_IDLE:
  1365. s = "Idle"; break;
  1366. case MODE_DEVICE:
  1367. s = "Device Controller"; break;
  1368. case MODE_HOST:
  1369. s = "Host Controller"; break;
  1370. default:
  1371. s = "None"; break;
  1372. }
  1373. s;
  1374. }));
  1375. size -= t;
  1376. next += t;
  1377. tmp_reg = readl(&dev->op_regs->endptsetupstat);
  1378. t = scnprintf(next, size,
  1379. "Endpoint Setup Status Reg:\n"
  1380. "SETUP on ep 0x%04x\n\n",
  1381. tmp_reg & SETUPSTAT_MASK);
  1382. size -= t;
  1383. next += t;
  1384. for (i = 0; i < dev->ep_max / 2; i++) {
  1385. tmp_reg = readl(&dev->op_regs->endptctrl[i]);
  1386. t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n",
  1387. i, tmp_reg);
  1388. size -= t;
  1389. next += t;
  1390. }
  1391. tmp_reg = readl(&dev->op_regs->endptprime);
  1392. t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg);
  1393. size -= t;
  1394. next += t;
  1395. /* langwell_udc, langwell_ep, langwell_request structure information */
  1396. ep = &dev->ep[0];
  1397. t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n",
  1398. ep->ep.name, ep->ep.maxpacket, ep->ep_num);
  1399. size -= t;
  1400. next += t;
  1401. if (list_empty(&ep->queue)) {
  1402. t = scnprintf(next, size, "its req queue is empty\n\n");
  1403. size -= t;
  1404. next += t;
  1405. } else {
  1406. list_for_each_entry(req, &ep->queue, queue) {
  1407. t = scnprintf(next, size,
  1408. "req %p actual 0x%x length 0x%x buf %p\n",
  1409. &req->req, req->req.actual,
  1410. req->req.length, req->req.buf);
  1411. size -= t;
  1412. next += t;
  1413. }
  1414. }
  1415. /* other gadget->eplist ep */
  1416. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1417. if (ep->desc) {
  1418. t = scnprintf(next, size,
  1419. "\n%s MaxPacketSize: 0x%x, "
  1420. "ep_num: %d\n",
  1421. ep->ep.name, ep->ep.maxpacket,
  1422. ep->ep_num);
  1423. size -= t;
  1424. next += t;
  1425. if (list_empty(&ep->queue)) {
  1426. t = scnprintf(next, size,
  1427. "its req queue is empty\n\n");
  1428. size -= t;
  1429. next += t;
  1430. } else {
  1431. list_for_each_entry(req, &ep->queue, queue) {
  1432. t = scnprintf(next, size,
  1433. "req %p actual 0x%x length "
  1434. "0x%x buf %p\n",
  1435. &req->req, req->req.actual,
  1436. req->req.length, req->req.buf);
  1437. size -= t;
  1438. next += t;
  1439. }
  1440. }
  1441. }
  1442. }
  1443. spin_unlock_irqrestore(&dev->lock, flags);
  1444. return PAGE_SIZE - size;
  1445. }
  1446. static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL);
  1447. /*-------------------------------------------------------------------------*/
  1448. /*
  1449. * when a driver is successfully registered, it will receive
  1450. * control requests including set_configuration(), which enables
  1451. * non-control requests. then usb traffic follows until a
  1452. * disconnect is reported. then a host may connect again, or
  1453. * the driver might get unbound.
  1454. */
  1455. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1456. {
  1457. struct langwell_udc *dev = the_controller;
  1458. unsigned long flags;
  1459. int retval;
  1460. if (!dev)
  1461. return -ENODEV;
  1462. DBG(dev, "---> %s()\n", __func__);
  1463. if (dev->driver)
  1464. return -EBUSY;
  1465. spin_lock_irqsave(&dev->lock, flags);
  1466. /* hook up the driver ... */
  1467. driver->driver.bus = NULL;
  1468. dev->driver = driver;
  1469. dev->gadget.dev.driver = &driver->driver;
  1470. spin_unlock_irqrestore(&dev->lock, flags);
  1471. retval = driver->bind(&dev->gadget);
  1472. if (retval) {
  1473. DBG(dev, "bind to driver %s --> %d\n",
  1474. driver->driver.name, retval);
  1475. dev->driver = NULL;
  1476. dev->gadget.dev.driver = NULL;
  1477. return retval;
  1478. }
  1479. retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
  1480. if (retval)
  1481. goto err_unbind;
  1482. dev->usb_state = USB_STATE_ATTACHED;
  1483. dev->ep0_state = WAIT_FOR_SETUP;
  1484. dev->ep0_dir = USB_DIR_OUT;
  1485. /* enable interrupt and set controller to run state */
  1486. if (dev->got_irq)
  1487. langwell_udc_start(dev);
  1488. VDBG(dev, "After langwell_udc_start(), print all registers:\n");
  1489. #ifdef VERBOSE
  1490. print_all_registers(dev);
  1491. #endif
  1492. INFO(dev, "register driver: %s\n", driver->driver.name);
  1493. VDBG(dev, "<--- %s()\n", __func__);
  1494. return 0;
  1495. err_unbind:
  1496. driver->unbind(&dev->gadget);
  1497. dev->gadget.dev.driver = NULL;
  1498. dev->driver = NULL;
  1499. DBG(dev, "<--- %s()\n", __func__);
  1500. return retval;
  1501. }
  1502. EXPORT_SYMBOL(usb_gadget_register_driver);
  1503. /* unregister gadget driver */
  1504. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1505. {
  1506. struct langwell_udc *dev = the_controller;
  1507. unsigned long flags;
  1508. if (!dev)
  1509. return -ENODEV;
  1510. DBG(dev, "---> %s()\n", __func__);
  1511. if (unlikely(!driver || !driver->bind || !driver->unbind))
  1512. return -EINVAL;
  1513. /* unbind OTG transceiver */
  1514. if (dev->transceiver)
  1515. (void)otg_set_peripheral(dev->transceiver, 0);
  1516. /* disable interrupt and set controller to stop state */
  1517. langwell_udc_stop(dev);
  1518. dev->usb_state = USB_STATE_ATTACHED;
  1519. dev->ep0_state = WAIT_FOR_SETUP;
  1520. dev->ep0_dir = USB_DIR_OUT;
  1521. spin_lock_irqsave(&dev->lock, flags);
  1522. /* stop all usb activities */
  1523. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1524. stop_activity(dev, driver);
  1525. spin_unlock_irqrestore(&dev->lock, flags);
  1526. /* unbind gadget driver */
  1527. driver->unbind(&dev->gadget);
  1528. dev->gadget.dev.driver = NULL;
  1529. dev->driver = NULL;
  1530. device_remove_file(&dev->pdev->dev, &dev_attr_function);
  1531. INFO(dev, "unregistered driver '%s'\n", driver->driver.name);
  1532. DBG(dev, "<--- %s()\n", __func__);
  1533. return 0;
  1534. }
  1535. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1536. /*-------------------------------------------------------------------------*/
  1537. /*
  1538. * setup tripwire is used as a semaphore to ensure that the setup data
  1539. * payload is extracted from a dQH without being corrupted
  1540. */
  1541. static void setup_tripwire(struct langwell_udc *dev)
  1542. {
  1543. u32 usbcmd,
  1544. endptsetupstat;
  1545. unsigned long timeout;
  1546. struct langwell_dqh *dqh;
  1547. VDBG(dev, "---> %s()\n", __func__);
  1548. /* ep0 OUT dQH */
  1549. dqh = &dev->ep_dqh[EP_DIR_OUT];
  1550. /* Write-Clear endptsetupstat */
  1551. endptsetupstat = readl(&dev->op_regs->endptsetupstat);
  1552. writel(endptsetupstat, &dev->op_regs->endptsetupstat);
  1553. /* wait until endptsetupstat is cleared */
  1554. timeout = jiffies + SETUPSTAT_TIMEOUT;
  1555. while (readl(&dev->op_regs->endptsetupstat)) {
  1556. if (time_after(jiffies, timeout)) {
  1557. ERROR(dev, "setup_tripwire timeout\n");
  1558. break;
  1559. }
  1560. cpu_relax();
  1561. }
  1562. /* while a hazard exists when setup packet arrives */
  1563. do {
  1564. /* set setup tripwire bit */
  1565. usbcmd = readl(&dev->op_regs->usbcmd);
  1566. writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd);
  1567. /* copy the setup packet to local buffer */
  1568. memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8);
  1569. } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW));
  1570. /* Write-Clear setup tripwire bit */
  1571. usbcmd = readl(&dev->op_regs->usbcmd);
  1572. writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd);
  1573. VDBG(dev, "<--- %s()\n", __func__);
  1574. }
  1575. /* protocol ep0 stall, will automatically be cleared on new transaction */
  1576. static void ep0_stall(struct langwell_udc *dev)
  1577. {
  1578. u32 endptctrl;
  1579. VDBG(dev, "---> %s()\n", __func__);
  1580. /* set TX and RX to stall */
  1581. endptctrl = readl(&dev->op_regs->endptctrl[0]);
  1582. endptctrl |= EPCTRL_TXS | EPCTRL_RXS;
  1583. writel(endptctrl, &dev->op_regs->endptctrl[0]);
  1584. /* update ep0 state */
  1585. dev->ep0_state = WAIT_FOR_SETUP;
  1586. dev->ep0_dir = USB_DIR_OUT;
  1587. VDBG(dev, "<--- %s()\n", __func__);
  1588. }
  1589. /* PRIME a status phase for ep0 */
  1590. static int prime_status_phase(struct langwell_udc *dev, int dir)
  1591. {
  1592. struct langwell_request *req;
  1593. struct langwell_ep *ep;
  1594. int status = 0;
  1595. VDBG(dev, "---> %s()\n", __func__);
  1596. if (dir == EP_DIR_IN)
  1597. dev->ep0_dir = USB_DIR_IN;
  1598. else
  1599. dev->ep0_dir = USB_DIR_OUT;
  1600. ep = &dev->ep[0];
  1601. dev->ep0_state = WAIT_FOR_OUT_STATUS;
  1602. req = dev->status_req;
  1603. req->ep = ep;
  1604. req->req.length = 0;
  1605. req->req.status = -EINPROGRESS;
  1606. req->req.actual = 0;
  1607. req->req.complete = NULL;
  1608. req->dtd_count = 0;
  1609. if (!req_to_dtd(req))
  1610. status = queue_dtd(ep, req);
  1611. else
  1612. return -ENOMEM;
  1613. if (status)
  1614. ERROR(dev, "can't queue ep0 status request\n");
  1615. list_add_tail(&req->queue, &ep->queue);
  1616. VDBG(dev, "<--- %s()\n", __func__);
  1617. return status;
  1618. }
  1619. /* SET_ADDRESS request routine */
  1620. static void set_address(struct langwell_udc *dev, u16 value,
  1621. u16 index, u16 length)
  1622. {
  1623. VDBG(dev, "---> %s()\n", __func__);
  1624. /* save the new address to device struct */
  1625. dev->dev_addr = (u8) value;
  1626. VDBG(dev, "dev->dev_addr = %d\n", dev->dev_addr);
  1627. /* update usb state */
  1628. dev->usb_state = USB_STATE_ADDRESS;
  1629. /* STATUS phase */
  1630. if (prime_status_phase(dev, EP_DIR_IN))
  1631. ep0_stall(dev);
  1632. VDBG(dev, "<--- %s()\n", __func__);
  1633. }
  1634. /* return endpoint by windex */
  1635. static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev,
  1636. u16 wIndex)
  1637. {
  1638. struct langwell_ep *ep;
  1639. VDBG(dev, "---> %s()\n", __func__);
  1640. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  1641. return &dev->ep[0];
  1642. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1643. u8 bEndpointAddress;
  1644. if (!ep->desc)
  1645. continue;
  1646. bEndpointAddress = ep->desc->bEndpointAddress;
  1647. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  1648. continue;
  1649. if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
  1650. == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
  1651. return ep;
  1652. }
  1653. VDBG(dev, "<--- %s()\n", __func__);
  1654. return NULL;
  1655. }
  1656. /* return whether endpoint is stalled, 0: not stalled; 1: stalled */
  1657. static int ep_is_stall(struct langwell_ep *ep)
  1658. {
  1659. struct langwell_udc *dev = ep->dev;
  1660. u32 endptctrl;
  1661. int retval;
  1662. VDBG(dev, "---> %s()\n", __func__);
  1663. endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]);
  1664. if (is_in(ep))
  1665. retval = endptctrl & EPCTRL_TXS ? 1 : 0;
  1666. else
  1667. retval = endptctrl & EPCTRL_RXS ? 1 : 0;
  1668. VDBG(dev, "<--- %s()\n", __func__);
  1669. return retval;
  1670. }
  1671. /* GET_STATUS request routine */
  1672. static void get_status(struct langwell_udc *dev, u8 request_type, u16 value,
  1673. u16 index, u16 length)
  1674. {
  1675. struct langwell_request *req;
  1676. struct langwell_ep *ep;
  1677. u16 status_data = 0; /* 16 bits cpu view status data */
  1678. int status = 0;
  1679. VDBG(dev, "---> %s()\n", __func__);
  1680. ep = &dev->ep[0];
  1681. if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1682. /* get device status */
  1683. status_data = 1 << USB_DEVICE_SELF_POWERED;
  1684. status_data |= dev->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
  1685. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
  1686. /* get interface status */
  1687. status_data = 0;
  1688. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
  1689. /* get endpoint status */
  1690. struct langwell_ep *epn;
  1691. epn = get_ep_by_windex(dev, index);
  1692. /* stall if endpoint doesn't exist */
  1693. if (!epn)
  1694. goto stall;
  1695. status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT;
  1696. }
  1697. dev->ep0_dir = USB_DIR_IN;
  1698. /* borrow the per device status_req */
  1699. req = dev->status_req;
  1700. /* fill in the reqest structure */
  1701. *((u16 *) req->req.buf) = cpu_to_le16(status_data);
  1702. req->ep = ep;
  1703. req->req.length = 2;
  1704. req->req.status = -EINPROGRESS;
  1705. req->req.actual = 0;
  1706. req->req.complete = NULL;
  1707. req->dtd_count = 0;
  1708. /* prime the data phase */
  1709. if (!req_to_dtd(req))
  1710. status = queue_dtd(ep, req);
  1711. else /* no mem */
  1712. goto stall;
  1713. if (status) {
  1714. ERROR(dev, "response error on GET_STATUS request\n");
  1715. goto stall;
  1716. }
  1717. list_add_tail(&req->queue, &ep->queue);
  1718. dev->ep0_state = DATA_STATE_XMIT;
  1719. VDBG(dev, "<--- %s()\n", __func__);
  1720. return;
  1721. stall:
  1722. ep0_stall(dev);
  1723. VDBG(dev, "<--- %s()\n", __func__);
  1724. }
  1725. /* setup packet interrupt handler */
  1726. static void handle_setup_packet(struct langwell_udc *dev,
  1727. struct usb_ctrlrequest *setup)
  1728. {
  1729. u16 wValue = le16_to_cpu(setup->wValue);
  1730. u16 wIndex = le16_to_cpu(setup->wIndex);
  1731. u16 wLength = le16_to_cpu(setup->wLength);
  1732. VDBG(dev, "---> %s()\n", __func__);
  1733. /* ep0 fifo flush */
  1734. nuke(&dev->ep[0], -ESHUTDOWN);
  1735. DBG(dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
  1736. setup->bRequestType, setup->bRequest,
  1737. wValue, wIndex, wLength);
  1738. /* RNDIS gadget delegate */
  1739. if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) {
  1740. /* USB_CDC_SEND_ENCAPSULATED_COMMAND */
  1741. goto delegate;
  1742. }
  1743. /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
  1744. if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) {
  1745. /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
  1746. goto delegate;
  1747. }
  1748. /* We process some stardard setup requests here */
  1749. switch (setup->bRequest) {
  1750. case USB_REQ_GET_STATUS:
  1751. DBG(dev, "SETUP: USB_REQ_GET_STATUS\n");
  1752. /* get status, DATA and STATUS phase */
  1753. if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
  1754. != (USB_DIR_IN | USB_TYPE_STANDARD))
  1755. break;
  1756. get_status(dev, setup->bRequestType, wValue, wIndex, wLength);
  1757. goto end;
  1758. case USB_REQ_SET_ADDRESS:
  1759. DBG(dev, "SETUP: USB_REQ_SET_ADDRESS\n");
  1760. /* STATUS phase */
  1761. if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
  1762. | USB_RECIP_DEVICE))
  1763. break;
  1764. set_address(dev, wValue, wIndex, wLength);
  1765. goto end;
  1766. case USB_REQ_CLEAR_FEATURE:
  1767. case USB_REQ_SET_FEATURE:
  1768. /* STATUS phase */
  1769. {
  1770. int rc = -EOPNOTSUPP;
  1771. if (setup->bRequest == USB_REQ_SET_FEATURE)
  1772. DBG(dev, "SETUP: USB_REQ_SET_FEATURE\n");
  1773. else if (setup->bRequest == USB_REQ_CLEAR_FEATURE)
  1774. DBG(dev, "SETUP: USB_REQ_CLEAR_FEATURE\n");
  1775. if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
  1776. == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
  1777. struct langwell_ep *epn;
  1778. epn = get_ep_by_windex(dev, wIndex);
  1779. /* stall if endpoint doesn't exist */
  1780. if (!epn) {
  1781. ep0_stall(dev);
  1782. goto end;
  1783. }
  1784. if (wValue != 0 || wLength != 0
  1785. || epn->ep_num > dev->ep_max)
  1786. break;
  1787. spin_unlock(&dev->lock);
  1788. rc = langwell_ep_set_halt(&epn->ep,
  1789. (setup->bRequest == USB_REQ_SET_FEATURE)
  1790. ? 1 : 0);
  1791. spin_lock(&dev->lock);
  1792. } else if ((setup->bRequestType & (USB_RECIP_MASK
  1793. | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
  1794. | USB_TYPE_STANDARD)) {
  1795. if (!gadget_is_otg(&dev->gadget))
  1796. break;
  1797. else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) {
  1798. dev->gadget.b_hnp_enable = 1;
  1799. #ifdef OTG_TRANSCEIVER
  1800. if (!dev->lotg->otg.default_a)
  1801. dev->lotg->hsm.b_hnp_enable = 1;
  1802. #endif
  1803. } else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
  1804. dev->gadget.a_hnp_support = 1;
  1805. else if (setup->bRequest ==
  1806. USB_DEVICE_A_ALT_HNP_SUPPORT)
  1807. dev->gadget.a_alt_hnp_support = 1;
  1808. else
  1809. break;
  1810. rc = 0;
  1811. } else
  1812. break;
  1813. if (rc == 0) {
  1814. if (prime_status_phase(dev, EP_DIR_IN))
  1815. ep0_stall(dev);
  1816. }
  1817. goto end;
  1818. }
  1819. case USB_REQ_GET_DESCRIPTOR:
  1820. DBG(dev, "SETUP: USB_REQ_GET_DESCRIPTOR\n");
  1821. goto delegate;
  1822. case USB_REQ_SET_DESCRIPTOR:
  1823. DBG(dev, "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n");
  1824. goto delegate;
  1825. case USB_REQ_GET_CONFIGURATION:
  1826. DBG(dev, "SETUP: USB_REQ_GET_CONFIGURATION\n");
  1827. goto delegate;
  1828. case USB_REQ_SET_CONFIGURATION:
  1829. DBG(dev, "SETUP: USB_REQ_SET_CONFIGURATION\n");
  1830. goto delegate;
  1831. case USB_REQ_GET_INTERFACE:
  1832. DBG(dev, "SETUP: USB_REQ_GET_INTERFACE\n");
  1833. goto delegate;
  1834. case USB_REQ_SET_INTERFACE:
  1835. DBG(dev, "SETUP: USB_REQ_SET_INTERFACE\n");
  1836. goto delegate;
  1837. case USB_REQ_SYNCH_FRAME:
  1838. DBG(dev, "SETUP: USB_REQ_SYNCH_FRAME unsupported\n");
  1839. goto delegate;
  1840. default:
  1841. /* delegate USB standard requests to the gadget driver */
  1842. goto delegate;
  1843. delegate:
  1844. /* USB requests handled by gadget */
  1845. if (wLength) {
  1846. /* DATA phase from gadget, STATUS phase from udc */
  1847. dev->ep0_dir = (setup->bRequestType & USB_DIR_IN)
  1848. ? USB_DIR_IN : USB_DIR_OUT;
  1849. VDBG(dev, "dev->ep0_dir = 0x%x, wLength = %d\n",
  1850. dev->ep0_dir, wLength);
  1851. spin_unlock(&dev->lock);
  1852. if (dev->driver->setup(&dev->gadget,
  1853. &dev->local_setup_buff) < 0)
  1854. ep0_stall(dev);
  1855. spin_lock(&dev->lock);
  1856. dev->ep0_state = (setup->bRequestType & USB_DIR_IN)
  1857. ? DATA_STATE_XMIT : DATA_STATE_RECV;
  1858. } else {
  1859. /* no DATA phase, IN STATUS phase from gadget */
  1860. dev->ep0_dir = USB_DIR_IN;
  1861. VDBG(dev, "dev->ep0_dir = 0x%x, wLength = %d\n",
  1862. dev->ep0_dir, wLength);
  1863. spin_unlock(&dev->lock);
  1864. if (dev->driver->setup(&dev->gadget,
  1865. &dev->local_setup_buff) < 0)
  1866. ep0_stall(dev);
  1867. spin_lock(&dev->lock);
  1868. dev->ep0_state = WAIT_FOR_OUT_STATUS;
  1869. }
  1870. break;
  1871. }
  1872. end:
  1873. VDBG(dev, "<--- %s()\n", __func__);
  1874. return;
  1875. }
  1876. /* transfer completion, process endpoint request and free the completed dTDs
  1877. * for this request
  1878. */
  1879. static int process_ep_req(struct langwell_udc *dev, int index,
  1880. struct langwell_request *curr_req)
  1881. {
  1882. struct langwell_dtd *curr_dtd;
  1883. struct langwell_dqh *curr_dqh;
  1884. int td_complete, actual, remaining_length;
  1885. int i, dir;
  1886. u8 dtd_status = 0;
  1887. int retval = 0;
  1888. curr_dqh = &dev->ep_dqh[index];
  1889. dir = index % 2;
  1890. curr_dtd = curr_req->head;
  1891. td_complete = 0;
  1892. actual = curr_req->req.length;
  1893. VDBG(dev, "---> %s()\n", __func__);
  1894. for (i = 0; i < curr_req->dtd_count; i++) {
  1895. remaining_length = le16_to_cpu(curr_dtd->dtd_total);
  1896. actual -= remaining_length;
  1897. /* command execution states by dTD */
  1898. dtd_status = curr_dtd->dtd_status;
  1899. if (!dtd_status) {
  1900. /* transfers completed successfully */
  1901. if (!remaining_length) {
  1902. td_complete++;
  1903. VDBG(dev, "dTD transmitted successfully\n");
  1904. } else {
  1905. if (dir) {
  1906. VDBG(dev, "TX dTD remains data\n");
  1907. retval = -EPROTO;
  1908. break;
  1909. } else {
  1910. td_complete++;
  1911. break;
  1912. }
  1913. }
  1914. } else {
  1915. /* transfers completed with errors */
  1916. if (dtd_status & DTD_STS_ACTIVE) {
  1917. DBG(dev, "request not completed\n");
  1918. retval = 1;
  1919. return retval;
  1920. } else if (dtd_status & DTD_STS_HALTED) {
  1921. ERROR(dev, "dTD error %08x dQH[%d]\n",
  1922. dtd_status, index);
  1923. /* clear the errors and halt condition */
  1924. curr_dqh->dtd_status = 0;
  1925. retval = -EPIPE;
  1926. break;
  1927. } else if (dtd_status & DTD_STS_DBE) {
  1928. DBG(dev, "data buffer (overflow) error\n");
  1929. retval = -EPROTO;
  1930. break;
  1931. } else if (dtd_status & DTD_STS_TRE) {
  1932. DBG(dev, "transaction(ISO) error\n");
  1933. retval = -EILSEQ;
  1934. break;
  1935. } else
  1936. ERROR(dev, "unknown error (0x%x)!\n",
  1937. dtd_status);
  1938. }
  1939. if (i != curr_req->dtd_count - 1)
  1940. curr_dtd = (struct langwell_dtd *)
  1941. curr_dtd->next_dtd_virt;
  1942. }
  1943. if (retval)
  1944. return retval;
  1945. curr_req->req.actual = actual;
  1946. VDBG(dev, "<--- %s()\n", __func__);
  1947. return 0;
  1948. }
  1949. /* complete DATA or STATUS phase of ep0 prime status phase if needed */
  1950. static void ep0_req_complete(struct langwell_udc *dev,
  1951. struct langwell_ep *ep0, struct langwell_request *req)
  1952. {
  1953. u32 new_addr;
  1954. VDBG(dev, "---> %s()\n", __func__);
  1955. if (dev->usb_state == USB_STATE_ADDRESS) {
  1956. /* set the new address */
  1957. new_addr = (u32)dev->dev_addr;
  1958. writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr);
  1959. new_addr = USBADR(readl(&dev->op_regs->deviceaddr));
  1960. VDBG(dev, "new_addr = %d\n", new_addr);
  1961. }
  1962. done(ep0, req, 0);
  1963. switch (dev->ep0_state) {
  1964. case DATA_STATE_XMIT:
  1965. /* receive status phase */
  1966. if (prime_status_phase(dev, EP_DIR_OUT))
  1967. ep0_stall(dev);
  1968. break;
  1969. case DATA_STATE_RECV:
  1970. /* send status phase */
  1971. if (prime_status_phase(dev, EP_DIR_IN))
  1972. ep0_stall(dev);
  1973. break;
  1974. case WAIT_FOR_OUT_STATUS:
  1975. dev->ep0_state = WAIT_FOR_SETUP;
  1976. break;
  1977. case WAIT_FOR_SETUP:
  1978. ERROR(dev, "unexpect ep0 packets\n");
  1979. break;
  1980. default:
  1981. ep0_stall(dev);
  1982. break;
  1983. }
  1984. VDBG(dev, "<--- %s()\n", __func__);
  1985. }
  1986. /* USB transfer completion interrupt */
  1987. static void handle_trans_complete(struct langwell_udc *dev)
  1988. {
  1989. u32 complete_bits;
  1990. int i, ep_num, dir, bit_mask, status;
  1991. struct langwell_ep *epn;
  1992. struct langwell_request *curr_req, *temp_req;
  1993. VDBG(dev, "---> %s()\n", __func__);
  1994. complete_bits = readl(&dev->op_regs->endptcomplete);
  1995. VDBG(dev, "endptcomplete register: 0x%08x\n", complete_bits);
  1996. /* Write-Clear the bits in endptcomplete register */
  1997. writel(complete_bits, &dev->op_regs->endptcomplete);
  1998. if (!complete_bits) {
  1999. DBG(dev, "complete_bits = 0\n");
  2000. goto done;
  2001. }
  2002. for (i = 0; i < dev->ep_max; i++) {
  2003. ep_num = i / 2;
  2004. dir = i % 2;
  2005. bit_mask = 1 << (ep_num + 16 * dir);
  2006. if (!(complete_bits & bit_mask))
  2007. continue;
  2008. /* ep0 */
  2009. if (i == 1)
  2010. epn = &dev->ep[0];
  2011. else
  2012. epn = &dev->ep[i];
  2013. if (epn->name == NULL) {
  2014. WARNING(dev, "invalid endpoint\n");
  2015. continue;
  2016. }
  2017. if (i < 2)
  2018. /* ep0 in and out */
  2019. DBG(dev, "%s-%s transfer completed\n",
  2020. epn->name,
  2021. is_in(epn) ? "in" : "out");
  2022. else
  2023. DBG(dev, "%s transfer completed\n", epn->name);
  2024. /* process the req queue until an uncomplete request */
  2025. list_for_each_entry_safe(curr_req, temp_req,
  2026. &epn->queue, queue) {
  2027. status = process_ep_req(dev, i, curr_req);
  2028. VDBG(dev, "%s req status: %d\n", epn->name, status);
  2029. if (status)
  2030. break;
  2031. /* write back status to req */
  2032. curr_req->req.status = status;
  2033. /* ep0 request completion */
  2034. if (ep_num == 0) {
  2035. ep0_req_complete(dev, epn, curr_req);
  2036. break;
  2037. } else {
  2038. done(epn, curr_req, status);
  2039. }
  2040. }
  2041. }
  2042. done:
  2043. VDBG(dev, "<--- %s()\n", __func__);
  2044. return;
  2045. }
  2046. /* port change detect interrupt handler */
  2047. static void handle_port_change(struct langwell_udc *dev)
  2048. {
  2049. u32 portsc1, devlc;
  2050. u32 speed;
  2051. VDBG(dev, "---> %s()\n", __func__);
  2052. if (dev->bus_reset)
  2053. dev->bus_reset = 0;
  2054. portsc1 = readl(&dev->op_regs->portsc1);
  2055. devlc = readl(&dev->op_regs->devlc);
  2056. VDBG(dev, "portsc1 = 0x%08x, devlc = 0x%08x\n",
  2057. portsc1, devlc);
  2058. /* bus reset is finished */
  2059. if (!(portsc1 & PORTS_PR)) {
  2060. /* get the speed */
  2061. speed = LPM_PSPD(devlc);
  2062. switch (speed) {
  2063. case LPM_SPEED_HIGH:
  2064. dev->gadget.speed = USB_SPEED_HIGH;
  2065. break;
  2066. case LPM_SPEED_FULL:
  2067. dev->gadget.speed = USB_SPEED_FULL;
  2068. break;
  2069. case LPM_SPEED_LOW:
  2070. dev->gadget.speed = USB_SPEED_LOW;
  2071. break;
  2072. default:
  2073. dev->gadget.speed = USB_SPEED_UNKNOWN;
  2074. break;
  2075. }
  2076. VDBG(dev, "speed = %d, dev->gadget.speed = %d\n",
  2077. speed, dev->gadget.speed);
  2078. }
  2079. /* LPM L0 to L1 */
  2080. if (dev->lpm && dev->lpm_state == LPM_L0)
  2081. if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) {
  2082. INFO(dev, "LPM L0 to L1\n");
  2083. dev->lpm_state = LPM_L1;
  2084. }
  2085. /* LPM L1 to L0, force resume or remote wakeup finished */
  2086. if (dev->lpm && dev->lpm_state == LPM_L1)
  2087. if (!(portsc1 & PORTS_SUSP)) {
  2088. if (portsc1 & PORTS_SLP)
  2089. INFO(dev, "LPM L1 to L0, force resume\n");
  2090. else
  2091. INFO(dev, "LPM L1 to L0, remote wakeup\n");
  2092. dev->lpm_state = LPM_L0;
  2093. }
  2094. /* update USB state */
  2095. if (!dev->resume_state)
  2096. dev->usb_state = USB_STATE_DEFAULT;
  2097. VDBG(dev, "<--- %s()\n", __func__);
  2098. }
  2099. /* USB reset interrupt handler */
  2100. static void handle_usb_reset(struct langwell_udc *dev)
  2101. {
  2102. u32 deviceaddr,
  2103. endptsetupstat,
  2104. endptcomplete;
  2105. unsigned long timeout;
  2106. VDBG(dev, "---> %s()\n", __func__);
  2107. /* Write-Clear the device address */
  2108. deviceaddr = readl(&dev->op_regs->deviceaddr);
  2109. writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr);
  2110. dev->dev_addr = 0;
  2111. /* clear usb state */
  2112. dev->resume_state = 0;
  2113. /* LPM L1 to L0, reset */
  2114. if (dev->lpm)
  2115. dev->lpm_state = LPM_L0;
  2116. dev->ep0_dir = USB_DIR_OUT;
  2117. dev->ep0_state = WAIT_FOR_SETUP;
  2118. dev->remote_wakeup = 0; /* default to 0 on reset */
  2119. dev->gadget.b_hnp_enable = 0;
  2120. dev->gadget.a_hnp_support = 0;
  2121. dev->gadget.a_alt_hnp_support = 0;
  2122. /* Write-Clear all the setup token semaphores */
  2123. endptsetupstat = readl(&dev->op_regs->endptsetupstat);
  2124. writel(endptsetupstat, &dev->op_regs->endptsetupstat);
  2125. /* Write-Clear all the endpoint complete status bits */
  2126. endptcomplete = readl(&dev->op_regs->endptcomplete);
  2127. writel(endptcomplete, &dev->op_regs->endptcomplete);
  2128. /* wait until all endptprime bits cleared */
  2129. timeout = jiffies + PRIME_TIMEOUT;
  2130. while (readl(&dev->op_regs->endptprime)) {
  2131. if (time_after(jiffies, timeout)) {
  2132. ERROR(dev, "USB reset timeout\n");
  2133. break;
  2134. }
  2135. cpu_relax();
  2136. }
  2137. /* write 1s to endptflush register to clear any primed buffers */
  2138. writel((u32) ~0, &dev->op_regs->endptflush);
  2139. if (readl(&dev->op_regs->portsc1) & PORTS_PR) {
  2140. VDBG(dev, "USB bus reset\n");
  2141. /* bus is reseting */
  2142. dev->bus_reset = 1;
  2143. /* reset all the queues, stop all USB activities */
  2144. stop_activity(dev, dev->driver);
  2145. dev->usb_state = USB_STATE_DEFAULT;
  2146. } else {
  2147. VDBG(dev, "device controller reset\n");
  2148. /* controller reset */
  2149. langwell_udc_reset(dev);
  2150. /* reset all the queues, stop all USB activities */
  2151. stop_activity(dev, dev->driver);
  2152. /* reset ep0 dQH and endptctrl */
  2153. ep0_reset(dev);
  2154. /* enable interrupt and set controller to run state */
  2155. langwell_udc_start(dev);
  2156. dev->usb_state = USB_STATE_ATTACHED;
  2157. }
  2158. #ifdef OTG_TRANSCEIVER
  2159. /* refer to USB OTG 6.6.2.3 b_hnp_en is cleared */
  2160. if (!dev->lotg->otg.default_a)
  2161. dev->lotg->hsm.b_hnp_enable = 0;
  2162. #endif
  2163. VDBG(dev, "<--- %s()\n", __func__);
  2164. }
  2165. /* USB bus suspend/resume interrupt */
  2166. static void handle_bus_suspend(struct langwell_udc *dev)
  2167. {
  2168. u32 devlc;
  2169. DBG(dev, "---> %s()\n", __func__);
  2170. dev->resume_state = dev->usb_state;
  2171. dev->usb_state = USB_STATE_SUSPENDED;
  2172. #ifdef OTG_TRANSCEIVER
  2173. if (dev->lotg->otg.default_a) {
  2174. if (dev->lotg->hsm.b_bus_suspend_vld == 1) {
  2175. dev->lotg->hsm.b_bus_suspend = 1;
  2176. /* notify transceiver the state changes */
  2177. if (spin_trylock(&dev->lotg->wq_lock)) {
  2178. langwell_update_transceiver();
  2179. spin_unlock(&dev->lotg->wq_lock);
  2180. }
  2181. }
  2182. dev->lotg->hsm.b_bus_suspend_vld++;
  2183. } else {
  2184. if (!dev->lotg->hsm.a_bus_suspend) {
  2185. dev->lotg->hsm.a_bus_suspend = 1;
  2186. /* notify transceiver the state changes */
  2187. if (spin_trylock(&dev->lotg->wq_lock)) {
  2188. langwell_update_transceiver();
  2189. spin_unlock(&dev->lotg->wq_lock);
  2190. }
  2191. }
  2192. }
  2193. #endif
  2194. /* report suspend to the driver */
  2195. if (dev->driver) {
  2196. if (dev->driver->suspend) {
  2197. spin_unlock(&dev->lock);
  2198. dev->driver->suspend(&dev->gadget);
  2199. spin_lock(&dev->lock);
  2200. DBG(dev, "suspend %s\n", dev->driver->driver.name);
  2201. }
  2202. }
  2203. /* enter PHY low power suspend */
  2204. devlc = readl(&dev->op_regs->devlc);
  2205. VDBG(dev, "devlc = 0x%08x\n", devlc);
  2206. devlc |= LPM_PHCD;
  2207. writel(devlc, &dev->op_regs->devlc);
  2208. DBG(dev, "<--- %s()\n", __func__);
  2209. }
  2210. static void handle_bus_resume(struct langwell_udc *dev)
  2211. {
  2212. u32 devlc;
  2213. DBG(dev, "---> %s()\n", __func__);
  2214. dev->usb_state = dev->resume_state;
  2215. dev->resume_state = 0;
  2216. /* exit PHY low power suspend */
  2217. devlc = readl(&dev->op_regs->devlc);
  2218. VDBG(dev, "devlc = 0x%08x\n", devlc);
  2219. devlc &= ~LPM_PHCD;
  2220. writel(devlc, &dev->op_regs->devlc);
  2221. #ifdef OTG_TRANSCEIVER
  2222. if (dev->lotg->otg.default_a == 0)
  2223. dev->lotg->hsm.a_bus_suspend = 0;
  2224. #endif
  2225. /* report resume to the driver */
  2226. if (dev->driver) {
  2227. if (dev->driver->resume) {
  2228. spin_unlock(&dev->lock);
  2229. dev->driver->resume(&dev->gadget);
  2230. spin_lock(&dev->lock);
  2231. DBG(dev, "resume %s\n", dev->driver->driver.name);
  2232. }
  2233. }
  2234. DBG(dev, "<--- %s()\n", __func__);
  2235. }
  2236. /* USB device controller interrupt handler */
  2237. static irqreturn_t langwell_irq(int irq, void *_dev)
  2238. {
  2239. struct langwell_udc *dev = _dev;
  2240. u32 usbsts,
  2241. usbintr,
  2242. irq_sts,
  2243. portsc1;
  2244. VDBG(dev, "---> %s()\n", __func__);
  2245. if (dev->stopped) {
  2246. VDBG(dev, "handle IRQ_NONE\n");
  2247. VDBG(dev, "<--- %s()\n", __func__);
  2248. return IRQ_NONE;
  2249. }
  2250. spin_lock(&dev->lock);
  2251. /* USB status */
  2252. usbsts = readl(&dev->op_regs->usbsts);
  2253. /* USB interrupt enable */
  2254. usbintr = readl(&dev->op_regs->usbintr);
  2255. irq_sts = usbsts & usbintr;
  2256. VDBG(dev, "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n",
  2257. usbsts, usbintr, irq_sts);
  2258. if (!irq_sts) {
  2259. VDBG(dev, "handle IRQ_NONE\n");
  2260. VDBG(dev, "<--- %s()\n", __func__);
  2261. spin_unlock(&dev->lock);
  2262. return IRQ_NONE;
  2263. }
  2264. /* Write-Clear interrupt status bits */
  2265. writel(irq_sts, &dev->op_regs->usbsts);
  2266. /* resume from suspend */
  2267. portsc1 = readl(&dev->op_regs->portsc1);
  2268. if (dev->usb_state == USB_STATE_SUSPENDED)
  2269. if (!(portsc1 & PORTS_SUSP))
  2270. handle_bus_resume(dev);
  2271. /* USB interrupt */
  2272. if (irq_sts & STS_UI) {
  2273. VDBG(dev, "USB interrupt\n");
  2274. /* setup packet received from ep0 */
  2275. if (readl(&dev->op_regs->endptsetupstat)
  2276. & EP0SETUPSTAT_MASK) {
  2277. VDBG(dev, "USB SETUP packet received interrupt\n");
  2278. /* setup tripwire semaphone */
  2279. setup_tripwire(dev);
  2280. handle_setup_packet(dev, &dev->local_setup_buff);
  2281. }
  2282. /* USB transfer completion */
  2283. if (readl(&dev->op_regs->endptcomplete)) {
  2284. VDBG(dev, "USB transfer completion interrupt\n");
  2285. handle_trans_complete(dev);
  2286. }
  2287. }
  2288. /* SOF received interrupt (for ISO transfer) */
  2289. if (irq_sts & STS_SRI) {
  2290. /* FIXME */
  2291. /* VDBG(dev, "SOF received interrupt\n"); */
  2292. }
  2293. /* port change detect interrupt */
  2294. if (irq_sts & STS_PCI) {
  2295. VDBG(dev, "port change detect interrupt\n");
  2296. handle_port_change(dev);
  2297. }
  2298. /* suspend interrrupt */
  2299. if (irq_sts & STS_SLI) {
  2300. VDBG(dev, "suspend interrupt\n");
  2301. handle_bus_suspend(dev);
  2302. }
  2303. /* USB reset interrupt */
  2304. if (irq_sts & STS_URI) {
  2305. VDBG(dev, "USB reset interrupt\n");
  2306. handle_usb_reset(dev);
  2307. }
  2308. /* USB error or system error interrupt */
  2309. if (irq_sts & (STS_UEI | STS_SEI)) {
  2310. /* FIXME */
  2311. WARNING(dev, "error IRQ, irq_sts: %x\n", irq_sts);
  2312. }
  2313. spin_unlock(&dev->lock);
  2314. VDBG(dev, "<--- %s()\n", __func__);
  2315. return IRQ_HANDLED;
  2316. }
  2317. /*-------------------------------------------------------------------------*/
  2318. /* release device structure */
  2319. static void gadget_release(struct device *_dev)
  2320. {
  2321. struct langwell_udc *dev = the_controller;
  2322. DBG(dev, "---> %s()\n", __func__);
  2323. complete(dev->done);
  2324. DBG(dev, "<--- %s()\n", __func__);
  2325. kfree(dev);
  2326. }
  2327. /* tear down the binding between this driver and the pci device */
  2328. static void langwell_udc_remove(struct pci_dev *pdev)
  2329. {
  2330. struct langwell_udc *dev = the_controller;
  2331. DECLARE_COMPLETION(done);
  2332. BUG_ON(dev->driver);
  2333. DBG(dev, "---> %s()\n", __func__);
  2334. dev->done = &done;
  2335. /* free memory allocated in probe */
  2336. if (dev->dtd_pool)
  2337. dma_pool_destroy(dev->dtd_pool);
  2338. if (dev->status_req) {
  2339. kfree(dev->status_req->req.buf);
  2340. kfree(dev->status_req);
  2341. }
  2342. if (dev->ep_dqh)
  2343. dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
  2344. dev->ep_dqh, dev->ep_dqh_dma);
  2345. kfree(dev->ep);
  2346. /* diable IRQ handler */
  2347. if (dev->got_irq)
  2348. free_irq(pdev->irq, dev);
  2349. #ifndef OTG_TRANSCEIVER
  2350. if (dev->cap_regs)
  2351. iounmap(dev->cap_regs);
  2352. if (dev->region)
  2353. release_mem_region(pci_resource_start(pdev, 0),
  2354. pci_resource_len(pdev, 0));
  2355. if (dev->enabled)
  2356. pci_disable_device(pdev);
  2357. #else
  2358. if (dev->transceiver) {
  2359. otg_put_transceiver(dev->transceiver);
  2360. dev->transceiver = NULL;
  2361. dev->lotg = NULL;
  2362. }
  2363. #endif
  2364. dev->cap_regs = NULL;
  2365. INFO(dev, "unbind\n");
  2366. DBG(dev, "<--- %s()\n", __func__);
  2367. device_unregister(&dev->gadget.dev);
  2368. device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
  2369. #ifndef OTG_TRANSCEIVER
  2370. pci_set_drvdata(pdev, NULL);
  2371. #endif
  2372. /* free dev, wait for the release() finished */
  2373. wait_for_completion(&done);
  2374. the_controller = NULL;
  2375. }
  2376. /*
  2377. * wrap this driver around the specified device, but
  2378. * don't respond over USB until a gadget driver binds to us.
  2379. */
  2380. static int langwell_udc_probe(struct pci_dev *pdev,
  2381. const struct pci_device_id *id)
  2382. {
  2383. struct langwell_udc *dev;
  2384. #ifndef OTG_TRANSCEIVER
  2385. unsigned long resource, len;
  2386. #endif
  2387. void __iomem *base = NULL;
  2388. size_t size;
  2389. int retval;
  2390. if (the_controller) {
  2391. dev_warn(&pdev->dev, "ignoring\n");
  2392. return -EBUSY;
  2393. }
  2394. /* alloc, and start init */
  2395. dev = kzalloc(sizeof *dev, GFP_KERNEL);
  2396. if (dev == NULL) {
  2397. retval = -ENOMEM;
  2398. goto error;
  2399. }
  2400. /* initialize device spinlock */
  2401. spin_lock_init(&dev->lock);
  2402. dev->pdev = pdev;
  2403. DBG(dev, "---> %s()\n", __func__);
  2404. #ifdef OTG_TRANSCEIVER
  2405. /* PCI device is already enabled by otg_transceiver driver */
  2406. dev->enabled = 1;
  2407. /* mem region and register base */
  2408. dev->region = 1;
  2409. dev->transceiver = otg_get_transceiver();
  2410. dev->lotg = otg_to_langwell(dev->transceiver);
  2411. base = dev->lotg->regs;
  2412. #else
  2413. pci_set_drvdata(pdev, dev);
  2414. /* now all the pci goodies ... */
  2415. if (pci_enable_device(pdev) < 0) {
  2416. retval = -ENODEV;
  2417. goto error;
  2418. }
  2419. dev->enabled = 1;
  2420. /* control register: BAR 0 */
  2421. resource = pci_resource_start(pdev, 0);
  2422. len = pci_resource_len(pdev, 0);
  2423. if (!request_mem_region(resource, len, driver_name)) {
  2424. ERROR(dev, "controller already in use\n");
  2425. retval = -EBUSY;
  2426. goto error;
  2427. }
  2428. dev->region = 1;
  2429. base = ioremap_nocache(resource, len);
  2430. #endif
  2431. if (base == NULL) {
  2432. ERROR(dev, "can't map memory\n");
  2433. retval = -EFAULT;
  2434. goto error;
  2435. }
  2436. dev->cap_regs = (struct langwell_cap_regs __iomem *) base;
  2437. VDBG(dev, "dev->cap_regs: %p\n", dev->cap_regs);
  2438. dev->op_regs = (struct langwell_op_regs __iomem *)
  2439. (base + OP_REG_OFFSET);
  2440. VDBG(dev, "dev->op_regs: %p\n", dev->op_regs);
  2441. /* irq setup after old hardware is cleaned up */
  2442. if (!pdev->irq) {
  2443. ERROR(dev, "No IRQ. Check PCI setup!\n");
  2444. retval = -ENODEV;
  2445. goto error;
  2446. }
  2447. #ifndef OTG_TRANSCEIVER
  2448. INFO(dev, "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n",
  2449. pdev->irq, resource, len, base);
  2450. /* enables bus-mastering for device dev */
  2451. pci_set_master(pdev);
  2452. if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
  2453. driver_name, dev) != 0) {
  2454. ERROR(dev, "request interrupt %d failed\n", pdev->irq);
  2455. retval = -EBUSY;
  2456. goto error;
  2457. }
  2458. dev->got_irq = 1;
  2459. #endif
  2460. /* set stopped bit */
  2461. dev->stopped = 1;
  2462. /* capabilities and endpoint number */
  2463. dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0;
  2464. dev->dciversion = readw(&dev->cap_regs->dciversion);
  2465. dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0;
  2466. VDBG(dev, "dev->lpm: %d\n", dev->lpm);
  2467. VDBG(dev, "dev->dciversion: 0x%04x\n", dev->dciversion);
  2468. VDBG(dev, "dccparams: 0x%08x\n", readl(&dev->cap_regs->dccparams));
  2469. VDBG(dev, "dev->devcap: %d\n", dev->devcap);
  2470. if (!dev->devcap) {
  2471. ERROR(dev, "can't support device mode\n");
  2472. retval = -ENODEV;
  2473. goto error;
  2474. }
  2475. /* a pair of endpoints (out/in) for each address */
  2476. dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2;
  2477. VDBG(dev, "dev->ep_max: %d\n", dev->ep_max);
  2478. /* allocate endpoints memory */
  2479. dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max,
  2480. GFP_KERNEL);
  2481. if (!dev->ep) {
  2482. ERROR(dev, "allocate endpoints memory failed\n");
  2483. retval = -ENOMEM;
  2484. goto error;
  2485. }
  2486. /* allocate device dQH memory */
  2487. size = dev->ep_max * sizeof(struct langwell_dqh);
  2488. VDBG(dev, "orig size = %d\n", size);
  2489. if (size < DQH_ALIGNMENT)
  2490. size = DQH_ALIGNMENT;
  2491. else if ((size % DQH_ALIGNMENT) != 0) {
  2492. size += DQH_ALIGNMENT + 1;
  2493. size &= ~(DQH_ALIGNMENT - 1);
  2494. }
  2495. dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
  2496. &dev->ep_dqh_dma, GFP_KERNEL);
  2497. if (!dev->ep_dqh) {
  2498. ERROR(dev, "allocate dQH memory failed\n");
  2499. retval = -ENOMEM;
  2500. goto error;
  2501. }
  2502. dev->ep_dqh_size = size;
  2503. VDBG(dev, "ep_dqh_size = %d\n", dev->ep_dqh_size);
  2504. /* initialize ep0 status request structure */
  2505. dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL);
  2506. if (!dev->status_req) {
  2507. ERROR(dev, "allocate status_req memory failed\n");
  2508. retval = -ENOMEM;
  2509. goto error;
  2510. }
  2511. INIT_LIST_HEAD(&dev->status_req->queue);
  2512. /* allocate a small amount of memory to get valid address */
  2513. dev->status_req->req.buf = kmalloc(8, GFP_KERNEL);
  2514. dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf);
  2515. dev->resume_state = USB_STATE_NOTATTACHED;
  2516. dev->usb_state = USB_STATE_POWERED;
  2517. dev->ep0_dir = USB_DIR_OUT;
  2518. dev->remote_wakeup = 0; /* default to 0 on reset */
  2519. #ifndef OTG_TRANSCEIVER
  2520. /* reset device controller */
  2521. langwell_udc_reset(dev);
  2522. #endif
  2523. /* initialize gadget structure */
  2524. dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */
  2525. dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */
  2526. INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */
  2527. dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
  2528. dev->gadget.is_dualspeed = 1; /* support dual speed */
  2529. #ifdef OTG_TRANSCEIVER
  2530. dev->gadget.is_otg = 1; /* support otg mode */
  2531. #endif
  2532. /* the "gadget" abstracts/virtualizes the controller */
  2533. dev_set_name(&dev->gadget.dev, "gadget");
  2534. dev->gadget.dev.parent = &pdev->dev;
  2535. dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
  2536. dev->gadget.dev.release = gadget_release;
  2537. dev->gadget.name = driver_name; /* gadget name */
  2538. /* controller endpoints reinit */
  2539. eps_reinit(dev);
  2540. #ifndef OTG_TRANSCEIVER
  2541. /* reset ep0 dQH and endptctrl */
  2542. ep0_reset(dev);
  2543. #endif
  2544. /* create dTD dma_pool resource */
  2545. dev->dtd_pool = dma_pool_create("langwell_dtd",
  2546. &dev->pdev->dev,
  2547. sizeof(struct langwell_dtd),
  2548. DTD_ALIGNMENT,
  2549. DMA_BOUNDARY);
  2550. if (!dev->dtd_pool) {
  2551. retval = -ENOMEM;
  2552. goto error;
  2553. }
  2554. /* done */
  2555. INFO(dev, "%s\n", driver_desc);
  2556. INFO(dev, "irq %d, pci mem %p\n", pdev->irq, base);
  2557. INFO(dev, "Driver version: " DRIVER_VERSION "\n");
  2558. INFO(dev, "Support (max) %d endpoints\n", dev->ep_max);
  2559. INFO(dev, "Device interface version: 0x%04x\n", dev->dciversion);
  2560. INFO(dev, "Controller mode: %s\n", dev->devcap ? "Device" : "Host");
  2561. INFO(dev, "Support USB LPM: %s\n", dev->lpm ? "Yes" : "No");
  2562. VDBG(dev, "After langwell_udc_probe(), print all registers:\n");
  2563. #ifdef VERBOSE
  2564. print_all_registers(dev);
  2565. #endif
  2566. the_controller = dev;
  2567. retval = device_register(&dev->gadget.dev);
  2568. if (retval)
  2569. goto error;
  2570. retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc);
  2571. if (retval)
  2572. goto error;
  2573. VDBG(dev, "<--- %s()\n", __func__);
  2574. return 0;
  2575. error:
  2576. if (dev) {
  2577. DBG(dev, "<--- %s()\n", __func__);
  2578. langwell_udc_remove(pdev);
  2579. }
  2580. return retval;
  2581. }
  2582. /* device controller suspend */
  2583. static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
  2584. {
  2585. struct langwell_udc *dev = the_controller;
  2586. u32 devlc;
  2587. DBG(dev, "---> %s()\n", __func__);
  2588. /* disable interrupt and set controller to stop state */
  2589. langwell_udc_stop(dev);
  2590. /* diable IRQ handler */
  2591. if (dev->got_irq)
  2592. free_irq(pdev->irq, dev);
  2593. dev->got_irq = 0;
  2594. /* save PCI state */
  2595. pci_save_state(pdev);
  2596. /* set device power state */
  2597. pci_set_power_state(pdev, PCI_D3hot);
  2598. /* enter PHY low power suspend */
  2599. devlc = readl(&dev->op_regs->devlc);
  2600. VDBG(dev, "devlc = 0x%08x\n", devlc);
  2601. devlc |= LPM_PHCD;
  2602. writel(devlc, &dev->op_regs->devlc);
  2603. DBG(dev, "<--- %s()\n", __func__);
  2604. return 0;
  2605. }
  2606. /* device controller resume */
  2607. static int langwell_udc_resume(struct pci_dev *pdev)
  2608. {
  2609. struct langwell_udc *dev = the_controller;
  2610. u32 devlc;
  2611. DBG(dev, "---> %s()\n", __func__);
  2612. /* exit PHY low power suspend */
  2613. devlc = readl(&dev->op_regs->devlc);
  2614. VDBG(dev, "devlc = 0x%08x\n", devlc);
  2615. devlc &= ~LPM_PHCD;
  2616. writel(devlc, &dev->op_regs->devlc);
  2617. /* set device D0 power state */
  2618. pci_set_power_state(pdev, PCI_D0);
  2619. /* restore PCI state */
  2620. pci_restore_state(pdev);
  2621. /* enable IRQ handler */
  2622. if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED, driver_name, dev)
  2623. != 0) {
  2624. ERROR(dev, "request interrupt %d failed\n", pdev->irq);
  2625. return -1;
  2626. }
  2627. dev->got_irq = 1;
  2628. /* reset and start controller to run state */
  2629. if (dev->stopped) {
  2630. /* reset device controller */
  2631. langwell_udc_reset(dev);
  2632. /* reset ep0 dQH and endptctrl */
  2633. ep0_reset(dev);
  2634. /* start device if gadget is loaded */
  2635. if (dev->driver)
  2636. langwell_udc_start(dev);
  2637. }
  2638. /* reset USB status */
  2639. dev->usb_state = USB_STATE_ATTACHED;
  2640. dev->ep0_state = WAIT_FOR_SETUP;
  2641. dev->ep0_dir = USB_DIR_OUT;
  2642. DBG(dev, "<--- %s()\n", __func__);
  2643. return 0;
  2644. }
  2645. /* pci driver shutdown */
  2646. static void langwell_udc_shutdown(struct pci_dev *pdev)
  2647. {
  2648. struct langwell_udc *dev = the_controller;
  2649. u32 usbmode;
  2650. DBG(dev, "---> %s()\n", __func__);
  2651. /* reset controller mode to IDLE */
  2652. usbmode = readl(&dev->op_regs->usbmode);
  2653. DBG(dev, "usbmode = 0x%08x\n", usbmode);
  2654. usbmode &= (~3 | MODE_IDLE);
  2655. writel(usbmode, &dev->op_regs->usbmode);
  2656. DBG(dev, "<--- %s()\n", __func__);
  2657. }
  2658. /*-------------------------------------------------------------------------*/
  2659. static const struct pci_device_id pci_ids[] = { {
  2660. .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
  2661. .class_mask = ~0,
  2662. .vendor = 0x8086,
  2663. .device = 0x0811,
  2664. .subvendor = PCI_ANY_ID,
  2665. .subdevice = PCI_ANY_ID,
  2666. }, { /* end: all zeroes */ }
  2667. };
  2668. MODULE_DEVICE_TABLE(pci, pci_ids);
  2669. static struct pci_driver langwell_pci_driver = {
  2670. .name = (char *) driver_name,
  2671. .id_table = pci_ids,
  2672. .probe = langwell_udc_probe,
  2673. .remove = langwell_udc_remove,
  2674. /* device controller suspend/resume */
  2675. .suspend = langwell_udc_suspend,
  2676. .resume = langwell_udc_resume,
  2677. .shutdown = langwell_udc_shutdown,
  2678. };
  2679. MODULE_DESCRIPTION(DRIVER_DESC);
  2680. MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>");
  2681. MODULE_VERSION(DRIVER_VERSION);
  2682. MODULE_LICENSE("GPL");
  2683. static int __init init(void)
  2684. {
  2685. #ifdef OTG_TRANSCEIVER
  2686. return langwell_register_peripheral(&langwell_pci_driver);
  2687. #else
  2688. return pci_register_driver(&langwell_pci_driver);
  2689. #endif
  2690. }
  2691. module_init(init);
  2692. static void __exit cleanup(void)
  2693. {
  2694. #ifdef OTG_TRANSCEIVER
  2695. return langwell_unregister_peripheral(&langwell_pci_driver);
  2696. #else
  2697. pci_unregister_driver(&langwell_pci_driver);
  2698. #endif
  2699. }
  2700. module_exit(cleanup);