pci.c 26 KB

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  1. /*
  2. * Sonics Silicon Backplane PCI-Hostbus related functions.
  3. *
  4. * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
  5. * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
  6. * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
  7. * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
  8. * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  9. *
  10. * Derived from the Broadcom 4400 device driver.
  11. * Copyright (C) 2002 David S. Miller (davem@redhat.com)
  12. * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
  13. * Copyright (C) 2006 Broadcom Corporation.
  14. *
  15. * Licensed under the GNU/GPL. See COPYING for details.
  16. */
  17. #include <linux/ssb/ssb.h>
  18. #include <linux/ssb/ssb_regs.h>
  19. #include <linux/pci.h>
  20. #include <linux/delay.h>
  21. #include "ssb_private.h"
  22. /* Define the following to 1 to enable a printk on each coreswitch. */
  23. #define SSB_VERBOSE_PCICORESWITCH_DEBUG 0
  24. /* Lowlevel coreswitching */
  25. int ssb_pci_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
  26. {
  27. int err;
  28. int attempts = 0;
  29. u32 cur_core;
  30. while (1) {
  31. err = pci_write_config_dword(bus->host_pci, SSB_BAR0_WIN,
  32. (coreidx * SSB_CORE_SIZE)
  33. + SSB_ENUM_BASE);
  34. if (err)
  35. goto error;
  36. err = pci_read_config_dword(bus->host_pci, SSB_BAR0_WIN,
  37. &cur_core);
  38. if (err)
  39. goto error;
  40. cur_core = (cur_core - SSB_ENUM_BASE)
  41. / SSB_CORE_SIZE;
  42. if (cur_core == coreidx)
  43. break;
  44. if (attempts++ > SSB_BAR0_MAX_RETRIES)
  45. goto error;
  46. udelay(10);
  47. }
  48. return 0;
  49. error:
  50. ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
  51. return -ENODEV;
  52. }
  53. int ssb_pci_switch_core(struct ssb_bus *bus,
  54. struct ssb_device *dev)
  55. {
  56. int err;
  57. unsigned long flags;
  58. #if SSB_VERBOSE_PCICORESWITCH_DEBUG
  59. ssb_printk(KERN_INFO PFX
  60. "Switching to %s core, index %d\n",
  61. ssb_core_name(dev->id.coreid),
  62. dev->core_index);
  63. #endif
  64. spin_lock_irqsave(&bus->bar_lock, flags);
  65. err = ssb_pci_switch_coreidx(bus, dev->core_index);
  66. if (!err)
  67. bus->mapped_device = dev;
  68. spin_unlock_irqrestore(&bus->bar_lock, flags);
  69. return err;
  70. }
  71. /* Enable/disable the on board crystal oscillator and/or PLL. */
  72. int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on)
  73. {
  74. int err;
  75. u32 in, out, outenable;
  76. u16 pci_status;
  77. if (bus->bustype != SSB_BUSTYPE_PCI)
  78. return 0;
  79. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_IN, &in);
  80. if (err)
  81. goto err_pci;
  82. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &out);
  83. if (err)
  84. goto err_pci;
  85. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, &outenable);
  86. if (err)
  87. goto err_pci;
  88. outenable |= what;
  89. if (turn_on) {
  90. /* Avoid glitching the clock if GPRS is already using it.
  91. * We can't actually read the state of the PLLPD so we infer it
  92. * by the value of XTAL_PU which *is* readable via gpioin.
  93. */
  94. if (!(in & SSB_GPIO_XTAL)) {
  95. if (what & SSB_GPIO_XTAL) {
  96. /* Turn the crystal on */
  97. out |= SSB_GPIO_XTAL;
  98. if (what & SSB_GPIO_PLL)
  99. out |= SSB_GPIO_PLL;
  100. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  101. if (err)
  102. goto err_pci;
  103. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE,
  104. outenable);
  105. if (err)
  106. goto err_pci;
  107. msleep(1);
  108. }
  109. if (what & SSB_GPIO_PLL) {
  110. /* Turn the PLL on */
  111. out &= ~SSB_GPIO_PLL;
  112. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  113. if (err)
  114. goto err_pci;
  115. msleep(5);
  116. }
  117. }
  118. err = pci_read_config_word(bus->host_pci, PCI_STATUS, &pci_status);
  119. if (err)
  120. goto err_pci;
  121. pci_status &= ~PCI_STATUS_SIG_TARGET_ABORT;
  122. err = pci_write_config_word(bus->host_pci, PCI_STATUS, pci_status);
  123. if (err)
  124. goto err_pci;
  125. } else {
  126. if (what & SSB_GPIO_XTAL) {
  127. /* Turn the crystal off */
  128. out &= ~SSB_GPIO_XTAL;
  129. }
  130. if (what & SSB_GPIO_PLL) {
  131. /* Turn the PLL off */
  132. out |= SSB_GPIO_PLL;
  133. }
  134. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  135. if (err)
  136. goto err_pci;
  137. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, outenable);
  138. if (err)
  139. goto err_pci;
  140. }
  141. out:
  142. return err;
  143. err_pci:
  144. printk(KERN_ERR PFX "Error: ssb_pci_xtal() could not access PCI config space!\n");
  145. err = -EBUSY;
  146. goto out;
  147. }
  148. /* Get the word-offset for a SSB_SPROM_XXX define. */
  149. #define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
  150. /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
  151. #define SPEX16(_outvar, _offset, _mask, _shift) \
  152. out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
  153. #define SPEX32(_outvar, _offset, _mask, _shift) \
  154. out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
  155. in[SPOFF(_offset)]) & (_mask)) >> (_shift))
  156. #define SPEX(_outvar, _offset, _mask, _shift) \
  157. SPEX16(_outvar, _offset, _mask, _shift)
  158. static inline u8 ssb_crc8(u8 crc, u8 data)
  159. {
  160. /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */
  161. static const u8 t[] = {
  162. 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
  163. 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
  164. 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
  165. 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
  166. 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
  167. 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
  168. 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
  169. 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
  170. 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
  171. 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
  172. 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
  173. 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
  174. 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
  175. 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
  176. 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
  177. 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
  178. 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
  179. 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
  180. 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
  181. 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
  182. 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
  183. 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
  184. 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
  185. 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
  186. 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
  187. 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
  188. 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
  189. 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
  190. 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
  191. 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
  192. 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
  193. 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
  194. };
  195. return t[crc ^ data];
  196. }
  197. static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
  198. {
  199. int word;
  200. u8 crc = 0xFF;
  201. for (word = 0; word < size - 1; word++) {
  202. crc = ssb_crc8(crc, sprom[word] & 0x00FF);
  203. crc = ssb_crc8(crc, (sprom[word] & 0xFF00) >> 8);
  204. }
  205. crc = ssb_crc8(crc, sprom[size - 1] & 0x00FF);
  206. crc ^= 0xFF;
  207. return crc;
  208. }
  209. static int sprom_check_crc(const u16 *sprom, size_t size)
  210. {
  211. u8 crc;
  212. u8 expected_crc;
  213. u16 tmp;
  214. crc = ssb_sprom_crc(sprom, size);
  215. tmp = sprom[size - 1] & SSB_SPROM_REVISION_CRC;
  216. expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
  217. if (crc != expected_crc)
  218. return -EPROTO;
  219. return 0;
  220. }
  221. static int sprom_do_read(struct ssb_bus *bus, u16 *sprom)
  222. {
  223. int i;
  224. for (i = 0; i < bus->sprom_size; i++)
  225. sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
  226. return 0;
  227. }
  228. static int sprom_do_write(struct ssb_bus *bus, const u16 *sprom)
  229. {
  230. struct pci_dev *pdev = bus->host_pci;
  231. int i, err;
  232. u32 spromctl;
  233. u16 size = bus->sprom_size;
  234. ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
  235. err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
  236. if (err)
  237. goto err_ctlreg;
  238. spromctl |= SSB_SPROMCTL_WE;
  239. err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
  240. if (err)
  241. goto err_ctlreg;
  242. ssb_printk(KERN_NOTICE PFX "[ 0%%");
  243. msleep(500);
  244. for (i = 0; i < size; i++) {
  245. if (i == size / 4)
  246. ssb_printk("25%%");
  247. else if (i == size / 2)
  248. ssb_printk("50%%");
  249. else if (i == (size * 3) / 4)
  250. ssb_printk("75%%");
  251. else if (i % 2)
  252. ssb_printk(".");
  253. writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
  254. mmiowb();
  255. msleep(20);
  256. }
  257. err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
  258. if (err)
  259. goto err_ctlreg;
  260. spromctl &= ~SSB_SPROMCTL_WE;
  261. err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
  262. if (err)
  263. goto err_ctlreg;
  264. msleep(500);
  265. ssb_printk("100%% ]\n");
  266. ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
  267. return 0;
  268. err_ctlreg:
  269. ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n");
  270. return err;
  271. }
  272. static s8 r123_extract_antgain(u8 sprom_revision, const u16 *in,
  273. u16 mask, u16 shift)
  274. {
  275. u16 v;
  276. u8 gain;
  277. v = in[SPOFF(SSB_SPROM1_AGAIN)];
  278. gain = (v & mask) >> shift;
  279. if (gain == 0xFF)
  280. gain = 2; /* If unset use 2dBm */
  281. if (sprom_revision == 1) {
  282. /* Convert to Q5.2 */
  283. gain <<= 2;
  284. } else {
  285. /* Q5.2 Fractional part is stored in 0xC0 */
  286. gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
  287. }
  288. return (s8)gain;
  289. }
  290. static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
  291. {
  292. int i;
  293. u16 v;
  294. s8 gain;
  295. u16 loc[3];
  296. if (out->revision == 3) /* rev 3 moved MAC */
  297. loc[0] = SSB_SPROM3_IL0MAC;
  298. else {
  299. loc[0] = SSB_SPROM1_IL0MAC;
  300. loc[1] = SSB_SPROM1_ET0MAC;
  301. loc[2] = SSB_SPROM1_ET1MAC;
  302. }
  303. for (i = 0; i < 3; i++) {
  304. v = in[SPOFF(loc[0]) + i];
  305. *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
  306. }
  307. if (out->revision < 3) { /* only rev 1-2 have et0, et1 */
  308. for (i = 0; i < 3; i++) {
  309. v = in[SPOFF(loc[1]) + i];
  310. *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
  311. }
  312. for (i = 0; i < 3; i++) {
  313. v = in[SPOFF(loc[2]) + i];
  314. *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
  315. }
  316. }
  317. SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
  318. SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
  319. SSB_SPROM1_ETHPHY_ET1A_SHIFT);
  320. SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
  321. SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
  322. SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
  323. SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
  324. SSB_SPROM1_BINF_CCODE_SHIFT);
  325. SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
  326. SSB_SPROM1_BINF_ANTA_SHIFT);
  327. SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
  328. SSB_SPROM1_BINF_ANTBG_SHIFT);
  329. SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
  330. SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
  331. SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
  332. SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
  333. SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
  334. SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
  335. SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
  336. SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
  337. SSB_SPROM1_GPIOA_P1_SHIFT);
  338. SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
  339. SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
  340. SSB_SPROM1_GPIOB_P3_SHIFT);
  341. SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A,
  342. SSB_SPROM1_MAXPWR_A_SHIFT);
  343. SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0);
  344. SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A,
  345. SSB_SPROM1_ITSSI_A_SHIFT);
  346. SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
  347. SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
  348. if (out->revision >= 2)
  349. SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
  350. /* Extract the antenna gain values. */
  351. gain = r123_extract_antgain(out->revision, in,
  352. SSB_SPROM1_AGAIN_BG,
  353. SSB_SPROM1_AGAIN_BG_SHIFT);
  354. out->antenna_gain.ghz24.a0 = gain;
  355. out->antenna_gain.ghz24.a1 = gain;
  356. out->antenna_gain.ghz24.a2 = gain;
  357. out->antenna_gain.ghz24.a3 = gain;
  358. gain = r123_extract_antgain(out->revision, in,
  359. SSB_SPROM1_AGAIN_A,
  360. SSB_SPROM1_AGAIN_A_SHIFT);
  361. out->antenna_gain.ghz5.a0 = gain;
  362. out->antenna_gain.ghz5.a1 = gain;
  363. out->antenna_gain.ghz5.a2 = gain;
  364. out->antenna_gain.ghz5.a3 = gain;
  365. }
  366. static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
  367. {
  368. int i;
  369. u16 v;
  370. u16 il0mac_offset;
  371. if (out->revision == 4)
  372. il0mac_offset = SSB_SPROM4_IL0MAC;
  373. else
  374. il0mac_offset = SSB_SPROM5_IL0MAC;
  375. /* extract the MAC address */
  376. for (i = 0; i < 3; i++) {
  377. v = in[SPOFF(il0mac_offset) + i];
  378. *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
  379. }
  380. SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
  381. SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
  382. SSB_SPROM4_ETHPHY_ET1A_SHIFT);
  383. if (out->revision == 4) {
  384. SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
  385. SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
  386. SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
  387. } else {
  388. SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
  389. SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
  390. SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
  391. }
  392. SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
  393. SSB_SPROM4_ANTAVAIL_A_SHIFT);
  394. SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG,
  395. SSB_SPROM4_ANTAVAIL_BG_SHIFT);
  396. SPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0);
  397. SPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG,
  398. SSB_SPROM4_ITSSI_BG_SHIFT);
  399. SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0);
  400. SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A,
  401. SSB_SPROM4_ITSSI_A_SHIFT);
  402. if (out->revision == 4) {
  403. SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);
  404. SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,
  405. SSB_SPROM4_GPIOA_P1_SHIFT);
  406. SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);
  407. SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,
  408. SSB_SPROM4_GPIOB_P3_SHIFT);
  409. } else {
  410. SPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0);
  411. SPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1,
  412. SSB_SPROM5_GPIOA_P1_SHIFT);
  413. SPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0);
  414. SPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3,
  415. SSB_SPROM5_GPIOB_P3_SHIFT);
  416. }
  417. /* Extract the antenna gain values. */
  418. SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
  419. SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
  420. SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
  421. SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
  422. SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
  423. SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
  424. SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
  425. SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
  426. memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
  427. sizeof(out->antenna_gain.ghz5));
  428. /* TODO - get remaining rev 4 stuff needed */
  429. }
  430. static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
  431. {
  432. int i;
  433. u16 v;
  434. /* extract the MAC address */
  435. for (i = 0; i < 3; i++) {
  436. v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
  437. *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
  438. }
  439. SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
  440. SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
  441. SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
  442. SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
  443. SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
  444. SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
  445. SSB_SPROM8_ANTAVAIL_A_SHIFT);
  446. SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
  447. SSB_SPROM8_ANTAVAIL_BG_SHIFT);
  448. SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
  449. SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
  450. SSB_SPROM8_ITSSI_BG_SHIFT);
  451. SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
  452. SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
  453. SSB_SPROM8_ITSSI_A_SHIFT);
  454. SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
  455. SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
  456. SSB_SPROM8_MAXP_AL_SHIFT);
  457. SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
  458. SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
  459. SSB_SPROM8_GPIOA_P1_SHIFT);
  460. SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
  461. SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
  462. SSB_SPROM8_GPIOB_P3_SHIFT);
  463. SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
  464. SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
  465. SSB_SPROM8_TRI5G_SHIFT);
  466. SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
  467. SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
  468. SSB_SPROM8_TRI5GH_SHIFT);
  469. SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
  470. SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
  471. SSB_SPROM8_RXPO5G_SHIFT);
  472. SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
  473. SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
  474. SSB_SPROM8_RSSISMC2G_SHIFT);
  475. SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
  476. SSB_SPROM8_RSSISAV2G_SHIFT);
  477. SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
  478. SSB_SPROM8_BXA2G_SHIFT);
  479. SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
  480. SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
  481. SSB_SPROM8_RSSISMC5G_SHIFT);
  482. SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
  483. SSB_SPROM8_RSSISAV5G_SHIFT);
  484. SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
  485. SSB_SPROM8_BXA5G_SHIFT);
  486. SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
  487. SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
  488. SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
  489. SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
  490. SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
  491. SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
  492. SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
  493. SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
  494. SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
  495. SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
  496. SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
  497. SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
  498. SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
  499. SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
  500. SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
  501. SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
  502. SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
  503. /* Extract the antenna gain values. */
  504. SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
  505. SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
  506. SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
  507. SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
  508. SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
  509. SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
  510. SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
  511. SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
  512. memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
  513. sizeof(out->antenna_gain.ghz5));
  514. /* TODO - get remaining rev 8 stuff needed */
  515. }
  516. static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out,
  517. const u16 *in, u16 size)
  518. {
  519. memset(out, 0, sizeof(*out));
  520. out->revision = in[size - 1] & 0x00FF;
  521. ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
  522. memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
  523. memset(out->et1mac, 0xFF, 6);
  524. if ((bus->chip_id & 0xFF00) == 0x4400) {
  525. /* Workaround: The BCM44XX chip has a stupid revision
  526. * number stored in the SPROM.
  527. * Always extract r1. */
  528. out->revision = 1;
  529. sprom_extract_r123(out, in);
  530. } else if (bus->chip_id == 0x4321) {
  531. /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
  532. out->revision = 4;
  533. sprom_extract_r45(out, in);
  534. } else {
  535. switch (out->revision) {
  536. case 1:
  537. case 2:
  538. case 3:
  539. sprom_extract_r123(out, in);
  540. break;
  541. case 4:
  542. case 5:
  543. sprom_extract_r45(out, in);
  544. break;
  545. case 8:
  546. sprom_extract_r8(out, in);
  547. break;
  548. default:
  549. ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
  550. " revision %d detected. Will extract"
  551. " v1\n", out->revision);
  552. out->revision = 1;
  553. sprom_extract_r123(out, in);
  554. }
  555. }
  556. if (out->boardflags_lo == 0xFFFF)
  557. out->boardflags_lo = 0; /* per specs */
  558. if (out->boardflags_hi == 0xFFFF)
  559. out->boardflags_hi = 0; /* per specs */
  560. return 0;
  561. }
  562. static int ssb_pci_sprom_get(struct ssb_bus *bus,
  563. struct ssb_sprom *sprom)
  564. {
  565. const struct ssb_sprom *fallback;
  566. int err = -ENOMEM;
  567. u16 *buf;
  568. buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
  569. if (!buf)
  570. goto out;
  571. bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
  572. sprom_do_read(bus, buf);
  573. err = sprom_check_crc(buf, bus->sprom_size);
  574. if (err) {
  575. /* try for a 440 byte SPROM - revision 4 and higher */
  576. kfree(buf);
  577. buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
  578. GFP_KERNEL);
  579. if (!buf)
  580. goto out;
  581. bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
  582. sprom_do_read(bus, buf);
  583. err = sprom_check_crc(buf, bus->sprom_size);
  584. if (err) {
  585. /* All CRC attempts failed.
  586. * Maybe there is no SPROM on the device?
  587. * If we have a fallback, use that. */
  588. fallback = ssb_get_fallback_sprom();
  589. if (fallback) {
  590. memcpy(sprom, fallback, sizeof(*sprom));
  591. err = 0;
  592. goto out_free;
  593. }
  594. ssb_printk(KERN_WARNING PFX "WARNING: Invalid"
  595. " SPROM CRC (corrupt SPROM)\n");
  596. }
  597. }
  598. err = sprom_extract(bus, sprom, buf, bus->sprom_size);
  599. out_free:
  600. kfree(buf);
  601. out:
  602. return err;
  603. }
  604. static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
  605. struct ssb_boardinfo *bi)
  606. {
  607. pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
  608. &bi->vendor);
  609. pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
  610. &bi->type);
  611. pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
  612. &bi->rev);
  613. }
  614. int ssb_pci_get_invariants(struct ssb_bus *bus,
  615. struct ssb_init_invariants *iv)
  616. {
  617. int err;
  618. err = ssb_pci_sprom_get(bus, &iv->sprom);
  619. if (err)
  620. goto out;
  621. ssb_pci_get_boardinfo(bus, &iv->boardinfo);
  622. out:
  623. return err;
  624. }
  625. #ifdef CONFIG_SSB_DEBUG
  626. static int ssb_pci_assert_buspower(struct ssb_bus *bus)
  627. {
  628. if (likely(bus->powered_up))
  629. return 0;
  630. printk(KERN_ERR PFX "FATAL ERROR: Bus powered down "
  631. "while accessing PCI MMIO space\n");
  632. if (bus->power_warn_count <= 10) {
  633. bus->power_warn_count++;
  634. dump_stack();
  635. }
  636. return -ENODEV;
  637. }
  638. #else /* DEBUG */
  639. static inline int ssb_pci_assert_buspower(struct ssb_bus *bus)
  640. {
  641. return 0;
  642. }
  643. #endif /* DEBUG */
  644. static u8 ssb_pci_read8(struct ssb_device *dev, u16 offset)
  645. {
  646. struct ssb_bus *bus = dev->bus;
  647. if (unlikely(ssb_pci_assert_buspower(bus)))
  648. return 0xFF;
  649. if (unlikely(bus->mapped_device != dev)) {
  650. if (unlikely(ssb_pci_switch_core(bus, dev)))
  651. return 0xFF;
  652. }
  653. return ioread8(bus->mmio + offset);
  654. }
  655. static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
  656. {
  657. struct ssb_bus *bus = dev->bus;
  658. if (unlikely(ssb_pci_assert_buspower(bus)))
  659. return 0xFFFF;
  660. if (unlikely(bus->mapped_device != dev)) {
  661. if (unlikely(ssb_pci_switch_core(bus, dev)))
  662. return 0xFFFF;
  663. }
  664. return ioread16(bus->mmio + offset);
  665. }
  666. static u32 ssb_pci_read32(struct ssb_device *dev, u16 offset)
  667. {
  668. struct ssb_bus *bus = dev->bus;
  669. if (unlikely(ssb_pci_assert_buspower(bus)))
  670. return 0xFFFFFFFF;
  671. if (unlikely(bus->mapped_device != dev)) {
  672. if (unlikely(ssb_pci_switch_core(bus, dev)))
  673. return 0xFFFFFFFF;
  674. }
  675. return ioread32(bus->mmio + offset);
  676. }
  677. #ifdef CONFIG_SSB_BLOCKIO
  678. static void ssb_pci_block_read(struct ssb_device *dev, void *buffer,
  679. size_t count, u16 offset, u8 reg_width)
  680. {
  681. struct ssb_bus *bus = dev->bus;
  682. void __iomem *addr = bus->mmio + offset;
  683. if (unlikely(ssb_pci_assert_buspower(bus)))
  684. goto error;
  685. if (unlikely(bus->mapped_device != dev)) {
  686. if (unlikely(ssb_pci_switch_core(bus, dev)))
  687. goto error;
  688. }
  689. switch (reg_width) {
  690. case sizeof(u8):
  691. ioread8_rep(addr, buffer, count);
  692. break;
  693. case sizeof(u16):
  694. SSB_WARN_ON(count & 1);
  695. ioread16_rep(addr, buffer, count >> 1);
  696. break;
  697. case sizeof(u32):
  698. SSB_WARN_ON(count & 3);
  699. ioread32_rep(addr, buffer, count >> 2);
  700. break;
  701. default:
  702. SSB_WARN_ON(1);
  703. }
  704. return;
  705. error:
  706. memset(buffer, 0xFF, count);
  707. }
  708. #endif /* CONFIG_SSB_BLOCKIO */
  709. static void ssb_pci_write8(struct ssb_device *dev, u16 offset, u8 value)
  710. {
  711. struct ssb_bus *bus = dev->bus;
  712. if (unlikely(ssb_pci_assert_buspower(bus)))
  713. return;
  714. if (unlikely(bus->mapped_device != dev)) {
  715. if (unlikely(ssb_pci_switch_core(bus, dev)))
  716. return;
  717. }
  718. iowrite8(value, bus->mmio + offset);
  719. }
  720. static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
  721. {
  722. struct ssb_bus *bus = dev->bus;
  723. if (unlikely(ssb_pci_assert_buspower(bus)))
  724. return;
  725. if (unlikely(bus->mapped_device != dev)) {
  726. if (unlikely(ssb_pci_switch_core(bus, dev)))
  727. return;
  728. }
  729. iowrite16(value, bus->mmio + offset);
  730. }
  731. static void ssb_pci_write32(struct ssb_device *dev, u16 offset, u32 value)
  732. {
  733. struct ssb_bus *bus = dev->bus;
  734. if (unlikely(ssb_pci_assert_buspower(bus)))
  735. return;
  736. if (unlikely(bus->mapped_device != dev)) {
  737. if (unlikely(ssb_pci_switch_core(bus, dev)))
  738. return;
  739. }
  740. iowrite32(value, bus->mmio + offset);
  741. }
  742. #ifdef CONFIG_SSB_BLOCKIO
  743. static void ssb_pci_block_write(struct ssb_device *dev, const void *buffer,
  744. size_t count, u16 offset, u8 reg_width)
  745. {
  746. struct ssb_bus *bus = dev->bus;
  747. void __iomem *addr = bus->mmio + offset;
  748. if (unlikely(ssb_pci_assert_buspower(bus)))
  749. return;
  750. if (unlikely(bus->mapped_device != dev)) {
  751. if (unlikely(ssb_pci_switch_core(bus, dev)))
  752. return;
  753. }
  754. switch (reg_width) {
  755. case sizeof(u8):
  756. iowrite8_rep(addr, buffer, count);
  757. break;
  758. case sizeof(u16):
  759. SSB_WARN_ON(count & 1);
  760. iowrite16_rep(addr, buffer, count >> 1);
  761. break;
  762. case sizeof(u32):
  763. SSB_WARN_ON(count & 3);
  764. iowrite32_rep(addr, buffer, count >> 2);
  765. break;
  766. default:
  767. SSB_WARN_ON(1);
  768. }
  769. }
  770. #endif /* CONFIG_SSB_BLOCKIO */
  771. /* Not "static", as it's used in main.c */
  772. const struct ssb_bus_ops ssb_pci_ops = {
  773. .read8 = ssb_pci_read8,
  774. .read16 = ssb_pci_read16,
  775. .read32 = ssb_pci_read32,
  776. .write8 = ssb_pci_write8,
  777. .write16 = ssb_pci_write16,
  778. .write32 = ssb_pci_write32,
  779. #ifdef CONFIG_SSB_BLOCKIO
  780. .block_read = ssb_pci_block_read,
  781. .block_write = ssb_pci_block_write,
  782. #endif
  783. };
  784. static ssize_t ssb_pci_attr_sprom_show(struct device *pcidev,
  785. struct device_attribute *attr,
  786. char *buf)
  787. {
  788. struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
  789. struct ssb_bus *bus;
  790. bus = ssb_pci_dev_to_bus(pdev);
  791. if (!bus)
  792. return -ENODEV;
  793. return ssb_attr_sprom_show(bus, buf, sprom_do_read);
  794. }
  795. static ssize_t ssb_pci_attr_sprom_store(struct device *pcidev,
  796. struct device_attribute *attr,
  797. const char *buf, size_t count)
  798. {
  799. struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
  800. struct ssb_bus *bus;
  801. bus = ssb_pci_dev_to_bus(pdev);
  802. if (!bus)
  803. return -ENODEV;
  804. return ssb_attr_sprom_store(bus, buf, count,
  805. sprom_check_crc, sprom_do_write);
  806. }
  807. static DEVICE_ATTR(ssb_sprom, 0600,
  808. ssb_pci_attr_sprom_show,
  809. ssb_pci_attr_sprom_store);
  810. void ssb_pci_exit(struct ssb_bus *bus)
  811. {
  812. struct pci_dev *pdev;
  813. if (bus->bustype != SSB_BUSTYPE_PCI)
  814. return;
  815. pdev = bus->host_pci;
  816. device_remove_file(&pdev->dev, &dev_attr_ssb_sprom);
  817. }
  818. int ssb_pci_init(struct ssb_bus *bus)
  819. {
  820. struct pci_dev *pdev;
  821. int err;
  822. if (bus->bustype != SSB_BUSTYPE_PCI)
  823. return 0;
  824. pdev = bus->host_pci;
  825. mutex_init(&bus->sprom_mutex);
  826. err = device_create_file(&pdev->dev, &dev_attr_ssb_sprom);
  827. if (err)
  828. goto out;
  829. out:
  830. return err;
  831. }