main.c 32 KB

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  1. /*
  2. * Sonics Silicon Backplane
  3. * Subsystem core
  4. *
  5. * Copyright 2005, Broadcom Corporation
  6. * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
  7. *
  8. * Licensed under the GNU/GPL. See COPYING for details.
  9. */
  10. #include "ssb_private.h"
  11. #include <linux/delay.h>
  12. #include <linux/io.h>
  13. #include <linux/ssb/ssb.h>
  14. #include <linux/ssb/ssb_regs.h>
  15. #include <linux/ssb/ssb_driver_gige.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/pci.h>
  18. #include <linux/mmc/sdio_func.h>
  19. #include <pcmcia/cs_types.h>
  20. #include <pcmcia/cs.h>
  21. #include <pcmcia/cistpl.h>
  22. #include <pcmcia/ds.h>
  23. MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
  24. MODULE_LICENSE("GPL");
  25. /* Temporary list of yet-to-be-attached buses */
  26. static LIST_HEAD(attach_queue);
  27. /* List if running buses */
  28. static LIST_HEAD(buses);
  29. /* Software ID counter */
  30. static unsigned int next_busnumber;
  31. /* buses_mutes locks the two buslists and the next_busnumber.
  32. * Don't lock this directly, but use ssb_buses_[un]lock() below. */
  33. static DEFINE_MUTEX(buses_mutex);
  34. /* There are differences in the codeflow, if the bus is
  35. * initialized from early boot, as various needed services
  36. * are not available early. This is a mechanism to delay
  37. * these initializations to after early boot has finished.
  38. * It's also used to avoid mutex locking, as that's not
  39. * available and needed early. */
  40. static bool ssb_is_early_boot = 1;
  41. static void ssb_buses_lock(void);
  42. static void ssb_buses_unlock(void);
  43. #ifdef CONFIG_SSB_PCIHOST
  44. struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
  45. {
  46. struct ssb_bus *bus;
  47. ssb_buses_lock();
  48. list_for_each_entry(bus, &buses, list) {
  49. if (bus->bustype == SSB_BUSTYPE_PCI &&
  50. bus->host_pci == pdev)
  51. goto found;
  52. }
  53. bus = NULL;
  54. found:
  55. ssb_buses_unlock();
  56. return bus;
  57. }
  58. #endif /* CONFIG_SSB_PCIHOST */
  59. #ifdef CONFIG_SSB_PCMCIAHOST
  60. struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
  61. {
  62. struct ssb_bus *bus;
  63. ssb_buses_lock();
  64. list_for_each_entry(bus, &buses, list) {
  65. if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
  66. bus->host_pcmcia == pdev)
  67. goto found;
  68. }
  69. bus = NULL;
  70. found:
  71. ssb_buses_unlock();
  72. return bus;
  73. }
  74. #endif /* CONFIG_SSB_PCMCIAHOST */
  75. #ifdef CONFIG_SSB_SDIOHOST
  76. struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
  77. {
  78. struct ssb_bus *bus;
  79. ssb_buses_lock();
  80. list_for_each_entry(bus, &buses, list) {
  81. if (bus->bustype == SSB_BUSTYPE_SDIO &&
  82. bus->host_sdio == func)
  83. goto found;
  84. }
  85. bus = NULL;
  86. found:
  87. ssb_buses_unlock();
  88. return bus;
  89. }
  90. #endif /* CONFIG_SSB_SDIOHOST */
  91. int ssb_for_each_bus_call(unsigned long data,
  92. int (*func)(struct ssb_bus *bus, unsigned long data))
  93. {
  94. struct ssb_bus *bus;
  95. int res;
  96. ssb_buses_lock();
  97. list_for_each_entry(bus, &buses, list) {
  98. res = func(bus, data);
  99. if (res >= 0) {
  100. ssb_buses_unlock();
  101. return res;
  102. }
  103. }
  104. ssb_buses_unlock();
  105. return -ENODEV;
  106. }
  107. static struct ssb_device *ssb_device_get(struct ssb_device *dev)
  108. {
  109. if (dev)
  110. get_device(dev->dev);
  111. return dev;
  112. }
  113. static void ssb_device_put(struct ssb_device *dev)
  114. {
  115. if (dev)
  116. put_device(dev->dev);
  117. }
  118. static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
  119. {
  120. if (drv)
  121. get_driver(&drv->drv);
  122. return drv;
  123. }
  124. static inline void ssb_driver_put(struct ssb_driver *drv)
  125. {
  126. if (drv)
  127. put_driver(&drv->drv);
  128. }
  129. static int ssb_device_resume(struct device *dev)
  130. {
  131. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  132. struct ssb_driver *ssb_drv;
  133. int err = 0;
  134. if (dev->driver) {
  135. ssb_drv = drv_to_ssb_drv(dev->driver);
  136. if (ssb_drv && ssb_drv->resume)
  137. err = ssb_drv->resume(ssb_dev);
  138. if (err)
  139. goto out;
  140. }
  141. out:
  142. return err;
  143. }
  144. static int ssb_device_suspend(struct device *dev, pm_message_t state)
  145. {
  146. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  147. struct ssb_driver *ssb_drv;
  148. int err = 0;
  149. if (dev->driver) {
  150. ssb_drv = drv_to_ssb_drv(dev->driver);
  151. if (ssb_drv && ssb_drv->suspend)
  152. err = ssb_drv->suspend(ssb_dev, state);
  153. if (err)
  154. goto out;
  155. }
  156. out:
  157. return err;
  158. }
  159. int ssb_bus_resume(struct ssb_bus *bus)
  160. {
  161. int err;
  162. /* Reset HW state information in memory, so that HW is
  163. * completely reinitialized. */
  164. bus->mapped_device = NULL;
  165. #ifdef CONFIG_SSB_DRIVER_PCICORE
  166. bus->pcicore.setup_done = 0;
  167. #endif
  168. err = ssb_bus_powerup(bus, 0);
  169. if (err)
  170. return err;
  171. err = ssb_pcmcia_hardware_setup(bus);
  172. if (err) {
  173. ssb_bus_may_powerdown(bus);
  174. return err;
  175. }
  176. ssb_chipco_resume(&bus->chipco);
  177. ssb_bus_may_powerdown(bus);
  178. return 0;
  179. }
  180. EXPORT_SYMBOL(ssb_bus_resume);
  181. int ssb_bus_suspend(struct ssb_bus *bus)
  182. {
  183. ssb_chipco_suspend(&bus->chipco);
  184. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  185. return 0;
  186. }
  187. EXPORT_SYMBOL(ssb_bus_suspend);
  188. #ifdef CONFIG_SSB_SPROM
  189. /** ssb_devices_freeze - Freeze all devices on the bus.
  190. *
  191. * After freezing no device driver will be handling a device
  192. * on this bus anymore. ssb_devices_thaw() must be called after
  193. * a successful freeze to reactivate the devices.
  194. *
  195. * @bus: The bus.
  196. * @ctx: Context structure. Pass this to ssb_devices_thaw().
  197. */
  198. int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
  199. {
  200. struct ssb_device *sdev;
  201. struct ssb_driver *sdrv;
  202. unsigned int i;
  203. memset(ctx, 0, sizeof(*ctx));
  204. ctx->bus = bus;
  205. SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
  206. for (i = 0; i < bus->nr_devices; i++) {
  207. sdev = ssb_device_get(&bus->devices[i]);
  208. if (!sdev->dev || !sdev->dev->driver ||
  209. !device_is_registered(sdev->dev)) {
  210. ssb_device_put(sdev);
  211. continue;
  212. }
  213. sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
  214. if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
  215. ssb_device_put(sdev);
  216. continue;
  217. }
  218. sdrv->remove(sdev);
  219. ctx->device_frozen[i] = 1;
  220. }
  221. return 0;
  222. }
  223. /** ssb_devices_thaw - Unfreeze all devices on the bus.
  224. *
  225. * This will re-attach the device drivers and re-init the devices.
  226. *
  227. * @ctx: The context structure from ssb_devices_freeze()
  228. */
  229. int ssb_devices_thaw(struct ssb_freeze_context *ctx)
  230. {
  231. struct ssb_bus *bus = ctx->bus;
  232. struct ssb_device *sdev;
  233. struct ssb_driver *sdrv;
  234. unsigned int i;
  235. int err, result = 0;
  236. for (i = 0; i < bus->nr_devices; i++) {
  237. if (!ctx->device_frozen[i])
  238. continue;
  239. sdev = &bus->devices[i];
  240. if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
  241. continue;
  242. sdrv = drv_to_ssb_drv(sdev->dev->driver);
  243. if (SSB_WARN_ON(!sdrv || !sdrv->probe))
  244. continue;
  245. err = sdrv->probe(sdev, &sdev->id);
  246. if (err) {
  247. ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
  248. dev_name(sdev->dev));
  249. result = err;
  250. }
  251. ssb_driver_put(sdrv);
  252. ssb_device_put(sdev);
  253. }
  254. return result;
  255. }
  256. #endif /* CONFIG_SSB_SPROM */
  257. static void ssb_device_shutdown(struct device *dev)
  258. {
  259. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  260. struct ssb_driver *ssb_drv;
  261. if (!dev->driver)
  262. return;
  263. ssb_drv = drv_to_ssb_drv(dev->driver);
  264. if (ssb_drv && ssb_drv->shutdown)
  265. ssb_drv->shutdown(ssb_dev);
  266. }
  267. static int ssb_device_remove(struct device *dev)
  268. {
  269. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  270. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  271. if (ssb_drv && ssb_drv->remove)
  272. ssb_drv->remove(ssb_dev);
  273. ssb_device_put(ssb_dev);
  274. return 0;
  275. }
  276. static int ssb_device_probe(struct device *dev)
  277. {
  278. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  279. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  280. int err = 0;
  281. ssb_device_get(ssb_dev);
  282. if (ssb_drv && ssb_drv->probe)
  283. err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
  284. if (err)
  285. ssb_device_put(ssb_dev);
  286. return err;
  287. }
  288. static int ssb_match_devid(const struct ssb_device_id *tabid,
  289. const struct ssb_device_id *devid)
  290. {
  291. if ((tabid->vendor != devid->vendor) &&
  292. tabid->vendor != SSB_ANY_VENDOR)
  293. return 0;
  294. if ((tabid->coreid != devid->coreid) &&
  295. tabid->coreid != SSB_ANY_ID)
  296. return 0;
  297. if ((tabid->revision != devid->revision) &&
  298. tabid->revision != SSB_ANY_REV)
  299. return 0;
  300. return 1;
  301. }
  302. static int ssb_bus_match(struct device *dev, struct device_driver *drv)
  303. {
  304. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  305. struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
  306. const struct ssb_device_id *id;
  307. for (id = ssb_drv->id_table;
  308. id->vendor || id->coreid || id->revision;
  309. id++) {
  310. if (ssb_match_devid(id, &ssb_dev->id))
  311. return 1; /* found */
  312. }
  313. return 0;
  314. }
  315. static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
  316. {
  317. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  318. if (!dev)
  319. return -ENODEV;
  320. return add_uevent_var(env,
  321. "MODALIAS=ssb:v%04Xid%04Xrev%02X",
  322. ssb_dev->id.vendor, ssb_dev->id.coreid,
  323. ssb_dev->id.revision);
  324. }
  325. static struct bus_type ssb_bustype = {
  326. .name = "ssb",
  327. .match = ssb_bus_match,
  328. .probe = ssb_device_probe,
  329. .remove = ssb_device_remove,
  330. .shutdown = ssb_device_shutdown,
  331. .suspend = ssb_device_suspend,
  332. .resume = ssb_device_resume,
  333. .uevent = ssb_device_uevent,
  334. };
  335. static void ssb_buses_lock(void)
  336. {
  337. /* See the comment at the ssb_is_early_boot definition */
  338. if (!ssb_is_early_boot)
  339. mutex_lock(&buses_mutex);
  340. }
  341. static void ssb_buses_unlock(void)
  342. {
  343. /* See the comment at the ssb_is_early_boot definition */
  344. if (!ssb_is_early_boot)
  345. mutex_unlock(&buses_mutex);
  346. }
  347. static void ssb_devices_unregister(struct ssb_bus *bus)
  348. {
  349. struct ssb_device *sdev;
  350. int i;
  351. for (i = bus->nr_devices - 1; i >= 0; i--) {
  352. sdev = &(bus->devices[i]);
  353. if (sdev->dev)
  354. device_unregister(sdev->dev);
  355. }
  356. }
  357. void ssb_bus_unregister(struct ssb_bus *bus)
  358. {
  359. ssb_buses_lock();
  360. ssb_devices_unregister(bus);
  361. list_del(&bus->list);
  362. ssb_buses_unlock();
  363. ssb_pcmcia_exit(bus);
  364. ssb_pci_exit(bus);
  365. ssb_iounmap(bus);
  366. }
  367. EXPORT_SYMBOL(ssb_bus_unregister);
  368. static void ssb_release_dev(struct device *dev)
  369. {
  370. struct __ssb_dev_wrapper *devwrap;
  371. devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
  372. kfree(devwrap);
  373. }
  374. static int ssb_devices_register(struct ssb_bus *bus)
  375. {
  376. struct ssb_device *sdev;
  377. struct device *dev;
  378. struct __ssb_dev_wrapper *devwrap;
  379. int i, err = 0;
  380. int dev_idx = 0;
  381. for (i = 0; i < bus->nr_devices; i++) {
  382. sdev = &(bus->devices[i]);
  383. /* We don't register SSB-system devices to the kernel,
  384. * as the drivers for them are built into SSB. */
  385. switch (sdev->id.coreid) {
  386. case SSB_DEV_CHIPCOMMON:
  387. case SSB_DEV_PCI:
  388. case SSB_DEV_PCIE:
  389. case SSB_DEV_PCMCIA:
  390. case SSB_DEV_MIPS:
  391. case SSB_DEV_MIPS_3302:
  392. case SSB_DEV_EXTIF:
  393. continue;
  394. }
  395. devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
  396. if (!devwrap) {
  397. ssb_printk(KERN_ERR PFX
  398. "Could not allocate device\n");
  399. err = -ENOMEM;
  400. goto error;
  401. }
  402. dev = &devwrap->dev;
  403. devwrap->sdev = sdev;
  404. dev->release = ssb_release_dev;
  405. dev->bus = &ssb_bustype;
  406. dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
  407. switch (bus->bustype) {
  408. case SSB_BUSTYPE_PCI:
  409. #ifdef CONFIG_SSB_PCIHOST
  410. sdev->irq = bus->host_pci->irq;
  411. dev->parent = &bus->host_pci->dev;
  412. #endif
  413. break;
  414. case SSB_BUSTYPE_PCMCIA:
  415. #ifdef CONFIG_SSB_PCMCIAHOST
  416. sdev->irq = bus->host_pcmcia->irq.AssignedIRQ;
  417. dev->parent = &bus->host_pcmcia->dev;
  418. #endif
  419. break;
  420. case SSB_BUSTYPE_SDIO:
  421. #ifdef CONFIG_SSB_SDIO
  422. sdev->irq = bus->host_sdio->dev.irq;
  423. dev->parent = &bus->host_sdio->dev;
  424. #endif
  425. break;
  426. case SSB_BUSTYPE_SSB:
  427. dev->dma_mask = &dev->coherent_dma_mask;
  428. break;
  429. }
  430. sdev->dev = dev;
  431. err = device_register(dev);
  432. if (err) {
  433. ssb_printk(KERN_ERR PFX
  434. "Could not register %s\n",
  435. dev_name(dev));
  436. /* Set dev to NULL to not unregister
  437. * dev on error unwinding. */
  438. sdev->dev = NULL;
  439. kfree(devwrap);
  440. goto error;
  441. }
  442. dev_idx++;
  443. }
  444. return 0;
  445. error:
  446. /* Unwind the already registered devices. */
  447. ssb_devices_unregister(bus);
  448. return err;
  449. }
  450. /* Needs ssb_buses_lock() */
  451. static int ssb_attach_queued_buses(void)
  452. {
  453. struct ssb_bus *bus, *n;
  454. int err = 0;
  455. int drop_them_all = 0;
  456. list_for_each_entry_safe(bus, n, &attach_queue, list) {
  457. if (drop_them_all) {
  458. list_del(&bus->list);
  459. continue;
  460. }
  461. /* Can't init the PCIcore in ssb_bus_register(), as that
  462. * is too early in boot for embedded systems
  463. * (no udelay() available). So do it here in attach stage.
  464. */
  465. err = ssb_bus_powerup(bus, 0);
  466. if (err)
  467. goto error;
  468. ssb_pcicore_init(&bus->pcicore);
  469. ssb_bus_may_powerdown(bus);
  470. err = ssb_devices_register(bus);
  471. error:
  472. if (err) {
  473. drop_them_all = 1;
  474. list_del(&bus->list);
  475. continue;
  476. }
  477. list_move_tail(&bus->list, &buses);
  478. }
  479. return err;
  480. }
  481. static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
  482. {
  483. struct ssb_bus *bus = dev->bus;
  484. offset += dev->core_index * SSB_CORE_SIZE;
  485. return readb(bus->mmio + offset);
  486. }
  487. static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
  488. {
  489. struct ssb_bus *bus = dev->bus;
  490. offset += dev->core_index * SSB_CORE_SIZE;
  491. return readw(bus->mmio + offset);
  492. }
  493. static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
  494. {
  495. struct ssb_bus *bus = dev->bus;
  496. offset += dev->core_index * SSB_CORE_SIZE;
  497. return readl(bus->mmio + offset);
  498. }
  499. #ifdef CONFIG_SSB_BLOCKIO
  500. static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer,
  501. size_t count, u16 offset, u8 reg_width)
  502. {
  503. struct ssb_bus *bus = dev->bus;
  504. void __iomem *addr;
  505. offset += dev->core_index * SSB_CORE_SIZE;
  506. addr = bus->mmio + offset;
  507. switch (reg_width) {
  508. case sizeof(u8): {
  509. u8 *buf = buffer;
  510. while (count) {
  511. *buf = __raw_readb(addr);
  512. buf++;
  513. count--;
  514. }
  515. break;
  516. }
  517. case sizeof(u16): {
  518. __le16 *buf = buffer;
  519. SSB_WARN_ON(count & 1);
  520. while (count) {
  521. *buf = (__force __le16)__raw_readw(addr);
  522. buf++;
  523. count -= 2;
  524. }
  525. break;
  526. }
  527. case sizeof(u32): {
  528. __le32 *buf = buffer;
  529. SSB_WARN_ON(count & 3);
  530. while (count) {
  531. *buf = (__force __le32)__raw_readl(addr);
  532. buf++;
  533. count -= 4;
  534. }
  535. break;
  536. }
  537. default:
  538. SSB_WARN_ON(1);
  539. }
  540. }
  541. #endif /* CONFIG_SSB_BLOCKIO */
  542. static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
  543. {
  544. struct ssb_bus *bus = dev->bus;
  545. offset += dev->core_index * SSB_CORE_SIZE;
  546. writeb(value, bus->mmio + offset);
  547. }
  548. static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
  549. {
  550. struct ssb_bus *bus = dev->bus;
  551. offset += dev->core_index * SSB_CORE_SIZE;
  552. writew(value, bus->mmio + offset);
  553. }
  554. static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
  555. {
  556. struct ssb_bus *bus = dev->bus;
  557. offset += dev->core_index * SSB_CORE_SIZE;
  558. writel(value, bus->mmio + offset);
  559. }
  560. #ifdef CONFIG_SSB_BLOCKIO
  561. static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer,
  562. size_t count, u16 offset, u8 reg_width)
  563. {
  564. struct ssb_bus *bus = dev->bus;
  565. void __iomem *addr;
  566. offset += dev->core_index * SSB_CORE_SIZE;
  567. addr = bus->mmio + offset;
  568. switch (reg_width) {
  569. case sizeof(u8): {
  570. const u8 *buf = buffer;
  571. while (count) {
  572. __raw_writeb(*buf, addr);
  573. buf++;
  574. count--;
  575. }
  576. break;
  577. }
  578. case sizeof(u16): {
  579. const __le16 *buf = buffer;
  580. SSB_WARN_ON(count & 1);
  581. while (count) {
  582. __raw_writew((__force u16)(*buf), addr);
  583. buf++;
  584. count -= 2;
  585. }
  586. break;
  587. }
  588. case sizeof(u32): {
  589. const __le32 *buf = buffer;
  590. SSB_WARN_ON(count & 3);
  591. while (count) {
  592. __raw_writel((__force u32)(*buf), addr);
  593. buf++;
  594. count -= 4;
  595. }
  596. break;
  597. }
  598. default:
  599. SSB_WARN_ON(1);
  600. }
  601. }
  602. #endif /* CONFIG_SSB_BLOCKIO */
  603. /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
  604. static const struct ssb_bus_ops ssb_ssb_ops = {
  605. .read8 = ssb_ssb_read8,
  606. .read16 = ssb_ssb_read16,
  607. .read32 = ssb_ssb_read32,
  608. .write8 = ssb_ssb_write8,
  609. .write16 = ssb_ssb_write16,
  610. .write32 = ssb_ssb_write32,
  611. #ifdef CONFIG_SSB_BLOCKIO
  612. .block_read = ssb_ssb_block_read,
  613. .block_write = ssb_ssb_block_write,
  614. #endif
  615. };
  616. static int ssb_fetch_invariants(struct ssb_bus *bus,
  617. ssb_invariants_func_t get_invariants)
  618. {
  619. struct ssb_init_invariants iv;
  620. int err;
  621. memset(&iv, 0, sizeof(iv));
  622. err = get_invariants(bus, &iv);
  623. if (err)
  624. goto out;
  625. memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
  626. memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
  627. bus->has_cardbus_slot = iv.has_cardbus_slot;
  628. out:
  629. return err;
  630. }
  631. static int ssb_bus_register(struct ssb_bus *bus,
  632. ssb_invariants_func_t get_invariants,
  633. unsigned long baseaddr)
  634. {
  635. int err;
  636. spin_lock_init(&bus->bar_lock);
  637. INIT_LIST_HEAD(&bus->list);
  638. #ifdef CONFIG_SSB_EMBEDDED
  639. spin_lock_init(&bus->gpio_lock);
  640. #endif
  641. /* Powerup the bus */
  642. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  643. if (err)
  644. goto out;
  645. /* Init SDIO-host device (if any), before the scan */
  646. err = ssb_sdio_init(bus);
  647. if (err)
  648. goto err_disable_xtal;
  649. ssb_buses_lock();
  650. bus->busnumber = next_busnumber;
  651. /* Scan for devices (cores) */
  652. err = ssb_bus_scan(bus, baseaddr);
  653. if (err)
  654. goto err_sdio_exit;
  655. /* Init PCI-host device (if any) */
  656. err = ssb_pci_init(bus);
  657. if (err)
  658. goto err_unmap;
  659. /* Init PCMCIA-host device (if any) */
  660. err = ssb_pcmcia_init(bus);
  661. if (err)
  662. goto err_pci_exit;
  663. /* Initialize basic system devices (if available) */
  664. err = ssb_bus_powerup(bus, 0);
  665. if (err)
  666. goto err_pcmcia_exit;
  667. ssb_chipcommon_init(&bus->chipco);
  668. ssb_mipscore_init(&bus->mipscore);
  669. err = ssb_fetch_invariants(bus, get_invariants);
  670. if (err) {
  671. ssb_bus_may_powerdown(bus);
  672. goto err_pcmcia_exit;
  673. }
  674. ssb_bus_may_powerdown(bus);
  675. /* Queue it for attach.
  676. * See the comment at the ssb_is_early_boot definition. */
  677. list_add_tail(&bus->list, &attach_queue);
  678. if (!ssb_is_early_boot) {
  679. /* This is not early boot, so we must attach the bus now */
  680. err = ssb_attach_queued_buses();
  681. if (err)
  682. goto err_dequeue;
  683. }
  684. next_busnumber++;
  685. ssb_buses_unlock();
  686. out:
  687. return err;
  688. err_dequeue:
  689. list_del(&bus->list);
  690. err_pcmcia_exit:
  691. ssb_pcmcia_exit(bus);
  692. err_pci_exit:
  693. ssb_pci_exit(bus);
  694. err_unmap:
  695. ssb_iounmap(bus);
  696. err_sdio_exit:
  697. ssb_sdio_exit(bus);
  698. err_disable_xtal:
  699. ssb_buses_unlock();
  700. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  701. return err;
  702. }
  703. #ifdef CONFIG_SSB_PCIHOST
  704. int ssb_bus_pcibus_register(struct ssb_bus *bus,
  705. struct pci_dev *host_pci)
  706. {
  707. int err;
  708. bus->bustype = SSB_BUSTYPE_PCI;
  709. bus->host_pci = host_pci;
  710. bus->ops = &ssb_pci_ops;
  711. err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
  712. if (!err) {
  713. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  714. "PCI device %s\n", dev_name(&host_pci->dev));
  715. }
  716. return err;
  717. }
  718. EXPORT_SYMBOL(ssb_bus_pcibus_register);
  719. #endif /* CONFIG_SSB_PCIHOST */
  720. #ifdef CONFIG_SSB_PCMCIAHOST
  721. int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
  722. struct pcmcia_device *pcmcia_dev,
  723. unsigned long baseaddr)
  724. {
  725. int err;
  726. bus->bustype = SSB_BUSTYPE_PCMCIA;
  727. bus->host_pcmcia = pcmcia_dev;
  728. bus->ops = &ssb_pcmcia_ops;
  729. err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
  730. if (!err) {
  731. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  732. "PCMCIA device %s\n", pcmcia_dev->devname);
  733. }
  734. return err;
  735. }
  736. EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
  737. #endif /* CONFIG_SSB_PCMCIAHOST */
  738. #ifdef CONFIG_SSB_SDIOHOST
  739. int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
  740. unsigned int quirks)
  741. {
  742. int err;
  743. bus->bustype = SSB_BUSTYPE_SDIO;
  744. bus->host_sdio = func;
  745. bus->ops = &ssb_sdio_ops;
  746. bus->quirks = quirks;
  747. err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
  748. if (!err) {
  749. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  750. "SDIO device %s\n", sdio_func_id(func));
  751. }
  752. return err;
  753. }
  754. EXPORT_SYMBOL(ssb_bus_sdiobus_register);
  755. #endif /* CONFIG_SSB_PCMCIAHOST */
  756. int ssb_bus_ssbbus_register(struct ssb_bus *bus,
  757. unsigned long baseaddr,
  758. ssb_invariants_func_t get_invariants)
  759. {
  760. int err;
  761. bus->bustype = SSB_BUSTYPE_SSB;
  762. bus->ops = &ssb_ssb_ops;
  763. err = ssb_bus_register(bus, get_invariants, baseaddr);
  764. if (!err) {
  765. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
  766. "address 0x%08lX\n", baseaddr);
  767. }
  768. return err;
  769. }
  770. int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
  771. {
  772. drv->drv.name = drv->name;
  773. drv->drv.bus = &ssb_bustype;
  774. drv->drv.owner = owner;
  775. return driver_register(&drv->drv);
  776. }
  777. EXPORT_SYMBOL(__ssb_driver_register);
  778. void ssb_driver_unregister(struct ssb_driver *drv)
  779. {
  780. driver_unregister(&drv->drv);
  781. }
  782. EXPORT_SYMBOL(ssb_driver_unregister);
  783. void ssb_set_devtypedata(struct ssb_device *dev, void *data)
  784. {
  785. struct ssb_bus *bus = dev->bus;
  786. struct ssb_device *ent;
  787. int i;
  788. for (i = 0; i < bus->nr_devices; i++) {
  789. ent = &(bus->devices[i]);
  790. if (ent->id.vendor != dev->id.vendor)
  791. continue;
  792. if (ent->id.coreid != dev->id.coreid)
  793. continue;
  794. ent->devtypedata = data;
  795. }
  796. }
  797. EXPORT_SYMBOL(ssb_set_devtypedata);
  798. static u32 clkfactor_f6_resolve(u32 v)
  799. {
  800. /* map the magic values */
  801. switch (v) {
  802. case SSB_CHIPCO_CLK_F6_2:
  803. return 2;
  804. case SSB_CHIPCO_CLK_F6_3:
  805. return 3;
  806. case SSB_CHIPCO_CLK_F6_4:
  807. return 4;
  808. case SSB_CHIPCO_CLK_F6_5:
  809. return 5;
  810. case SSB_CHIPCO_CLK_F6_6:
  811. return 6;
  812. case SSB_CHIPCO_CLK_F6_7:
  813. return 7;
  814. }
  815. return 0;
  816. }
  817. /* Calculate the speed the backplane would run at a given set of clockcontrol values */
  818. u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
  819. {
  820. u32 n1, n2, clock, m1, m2, m3, mc;
  821. n1 = (n & SSB_CHIPCO_CLK_N1);
  822. n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
  823. switch (plltype) {
  824. case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
  825. if (m & SSB_CHIPCO_CLK_T6_MMASK)
  826. return SSB_CHIPCO_CLK_T6_M0;
  827. return SSB_CHIPCO_CLK_T6_M1;
  828. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  829. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  830. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  831. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  832. n1 = clkfactor_f6_resolve(n1);
  833. n2 += SSB_CHIPCO_CLK_F5_BIAS;
  834. break;
  835. case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
  836. n1 += SSB_CHIPCO_CLK_T2_BIAS;
  837. n2 += SSB_CHIPCO_CLK_T2_BIAS;
  838. SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
  839. SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
  840. break;
  841. case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
  842. return 100000000;
  843. default:
  844. SSB_WARN_ON(1);
  845. }
  846. switch (plltype) {
  847. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  848. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  849. clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
  850. break;
  851. default:
  852. clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
  853. }
  854. if (!clock)
  855. return 0;
  856. m1 = (m & SSB_CHIPCO_CLK_M1);
  857. m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
  858. m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
  859. mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
  860. switch (plltype) {
  861. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  862. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  863. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  864. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  865. m1 = clkfactor_f6_resolve(m1);
  866. if ((plltype == SSB_PLLTYPE_1) ||
  867. (plltype == SSB_PLLTYPE_3))
  868. m2 += SSB_CHIPCO_CLK_F5_BIAS;
  869. else
  870. m2 = clkfactor_f6_resolve(m2);
  871. m3 = clkfactor_f6_resolve(m3);
  872. switch (mc) {
  873. case SSB_CHIPCO_CLK_MC_BYPASS:
  874. return clock;
  875. case SSB_CHIPCO_CLK_MC_M1:
  876. return (clock / m1);
  877. case SSB_CHIPCO_CLK_MC_M1M2:
  878. return (clock / (m1 * m2));
  879. case SSB_CHIPCO_CLK_MC_M1M2M3:
  880. return (clock / (m1 * m2 * m3));
  881. case SSB_CHIPCO_CLK_MC_M1M3:
  882. return (clock / (m1 * m3));
  883. }
  884. return 0;
  885. case SSB_PLLTYPE_2:
  886. m1 += SSB_CHIPCO_CLK_T2_BIAS;
  887. m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
  888. m3 += SSB_CHIPCO_CLK_T2_BIAS;
  889. SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
  890. SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
  891. SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
  892. if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
  893. clock /= m1;
  894. if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
  895. clock /= m2;
  896. if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
  897. clock /= m3;
  898. return clock;
  899. default:
  900. SSB_WARN_ON(1);
  901. }
  902. return 0;
  903. }
  904. /* Get the current speed the backplane is running at */
  905. u32 ssb_clockspeed(struct ssb_bus *bus)
  906. {
  907. u32 rate;
  908. u32 plltype;
  909. u32 clkctl_n, clkctl_m;
  910. if (ssb_extif_available(&bus->extif))
  911. ssb_extif_get_clockcontrol(&bus->extif, &plltype,
  912. &clkctl_n, &clkctl_m);
  913. else if (bus->chipco.dev)
  914. ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
  915. &clkctl_n, &clkctl_m);
  916. else
  917. return 0;
  918. if (bus->chip_id == 0x5365) {
  919. rate = 100000000;
  920. } else {
  921. rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
  922. if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
  923. rate /= 2;
  924. }
  925. return rate;
  926. }
  927. EXPORT_SYMBOL(ssb_clockspeed);
  928. static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
  929. {
  930. u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
  931. /* The REJECT bit changed position in TMSLOW between
  932. * Backplane revisions. */
  933. switch (rev) {
  934. case SSB_IDLOW_SSBREV_22:
  935. return SSB_TMSLOW_REJECT_22;
  936. case SSB_IDLOW_SSBREV_23:
  937. return SSB_TMSLOW_REJECT_23;
  938. case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
  939. case SSB_IDLOW_SSBREV_25: /* same here */
  940. case SSB_IDLOW_SSBREV_26: /* same here */
  941. case SSB_IDLOW_SSBREV_27: /* same here */
  942. return SSB_TMSLOW_REJECT_23; /* this is a guess */
  943. default:
  944. printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
  945. WARN_ON(1);
  946. }
  947. return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
  948. }
  949. int ssb_device_is_enabled(struct ssb_device *dev)
  950. {
  951. u32 val;
  952. u32 reject;
  953. reject = ssb_tmslow_reject_bitmask(dev);
  954. val = ssb_read32(dev, SSB_TMSLOW);
  955. val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
  956. return (val == SSB_TMSLOW_CLOCK);
  957. }
  958. EXPORT_SYMBOL(ssb_device_is_enabled);
  959. static void ssb_flush_tmslow(struct ssb_device *dev)
  960. {
  961. /* Make _really_ sure the device has finished the TMSLOW
  962. * register write transaction, as we risk running into
  963. * a machine check exception otherwise.
  964. * Do this by reading the register back to commit the
  965. * PCI write and delay an additional usec for the device
  966. * to react to the change. */
  967. ssb_read32(dev, SSB_TMSLOW);
  968. udelay(1);
  969. }
  970. void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
  971. {
  972. u32 val;
  973. ssb_device_disable(dev, core_specific_flags);
  974. ssb_write32(dev, SSB_TMSLOW,
  975. SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
  976. SSB_TMSLOW_FGC | core_specific_flags);
  977. ssb_flush_tmslow(dev);
  978. /* Clear SERR if set. This is a hw bug workaround. */
  979. if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
  980. ssb_write32(dev, SSB_TMSHIGH, 0);
  981. val = ssb_read32(dev, SSB_IMSTATE);
  982. if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
  983. val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
  984. ssb_write32(dev, SSB_IMSTATE, val);
  985. }
  986. ssb_write32(dev, SSB_TMSLOW,
  987. SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
  988. core_specific_flags);
  989. ssb_flush_tmslow(dev);
  990. ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
  991. core_specific_flags);
  992. ssb_flush_tmslow(dev);
  993. }
  994. EXPORT_SYMBOL(ssb_device_enable);
  995. /* Wait for a bit in a register to get set or unset.
  996. * timeout is in units of ten-microseconds */
  997. static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
  998. int timeout, int set)
  999. {
  1000. int i;
  1001. u32 val;
  1002. for (i = 0; i < timeout; i++) {
  1003. val = ssb_read32(dev, reg);
  1004. if (set) {
  1005. if (val & bitmask)
  1006. return 0;
  1007. } else {
  1008. if (!(val & bitmask))
  1009. return 0;
  1010. }
  1011. udelay(10);
  1012. }
  1013. printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
  1014. "register %04X to %s.\n",
  1015. bitmask, reg, (set ? "set" : "clear"));
  1016. return -ETIMEDOUT;
  1017. }
  1018. void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
  1019. {
  1020. u32 reject;
  1021. if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
  1022. return;
  1023. reject = ssb_tmslow_reject_bitmask(dev);
  1024. ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
  1025. ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
  1026. ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
  1027. ssb_write32(dev, SSB_TMSLOW,
  1028. SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
  1029. reject | SSB_TMSLOW_RESET |
  1030. core_specific_flags);
  1031. ssb_flush_tmslow(dev);
  1032. ssb_write32(dev, SSB_TMSLOW,
  1033. reject | SSB_TMSLOW_RESET |
  1034. core_specific_flags);
  1035. ssb_flush_tmslow(dev);
  1036. }
  1037. EXPORT_SYMBOL(ssb_device_disable);
  1038. u32 ssb_dma_translation(struct ssb_device *dev)
  1039. {
  1040. switch (dev->bus->bustype) {
  1041. case SSB_BUSTYPE_SSB:
  1042. return 0;
  1043. case SSB_BUSTYPE_PCI:
  1044. return SSB_PCI_DMA;
  1045. default:
  1046. __ssb_dma_not_implemented(dev);
  1047. }
  1048. return 0;
  1049. }
  1050. EXPORT_SYMBOL(ssb_dma_translation);
  1051. int ssb_dma_set_mask(struct ssb_device *dev, u64 mask)
  1052. {
  1053. #ifdef CONFIG_SSB_PCIHOST
  1054. int err;
  1055. #endif
  1056. switch (dev->bus->bustype) {
  1057. case SSB_BUSTYPE_PCI:
  1058. #ifdef CONFIG_SSB_PCIHOST
  1059. err = pci_set_dma_mask(dev->bus->host_pci, mask);
  1060. if (err)
  1061. return err;
  1062. err = pci_set_consistent_dma_mask(dev->bus->host_pci, mask);
  1063. return err;
  1064. #endif
  1065. case SSB_BUSTYPE_SSB:
  1066. return dma_set_mask(dev->dev, mask);
  1067. default:
  1068. __ssb_dma_not_implemented(dev);
  1069. }
  1070. return -ENOSYS;
  1071. }
  1072. EXPORT_SYMBOL(ssb_dma_set_mask);
  1073. void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size,
  1074. dma_addr_t *dma_handle, gfp_t gfp_flags)
  1075. {
  1076. switch (dev->bus->bustype) {
  1077. case SSB_BUSTYPE_PCI:
  1078. #ifdef CONFIG_SSB_PCIHOST
  1079. if (gfp_flags & GFP_DMA) {
  1080. /* Workaround: The PCI API does not support passing
  1081. * a GFP flag. */
  1082. return dma_alloc_coherent(&dev->bus->host_pci->dev,
  1083. size, dma_handle, gfp_flags);
  1084. }
  1085. return pci_alloc_consistent(dev->bus->host_pci, size, dma_handle);
  1086. #endif
  1087. case SSB_BUSTYPE_SSB:
  1088. return dma_alloc_coherent(dev->dev, size, dma_handle, gfp_flags);
  1089. default:
  1090. __ssb_dma_not_implemented(dev);
  1091. }
  1092. return NULL;
  1093. }
  1094. EXPORT_SYMBOL(ssb_dma_alloc_consistent);
  1095. void ssb_dma_free_consistent(struct ssb_device *dev, size_t size,
  1096. void *vaddr, dma_addr_t dma_handle,
  1097. gfp_t gfp_flags)
  1098. {
  1099. switch (dev->bus->bustype) {
  1100. case SSB_BUSTYPE_PCI:
  1101. #ifdef CONFIG_SSB_PCIHOST
  1102. if (gfp_flags & GFP_DMA) {
  1103. /* Workaround: The PCI API does not support passing
  1104. * a GFP flag. */
  1105. dma_free_coherent(&dev->bus->host_pci->dev,
  1106. size, vaddr, dma_handle);
  1107. return;
  1108. }
  1109. pci_free_consistent(dev->bus->host_pci, size,
  1110. vaddr, dma_handle);
  1111. return;
  1112. #endif
  1113. case SSB_BUSTYPE_SSB:
  1114. dma_free_coherent(dev->dev, size, vaddr, dma_handle);
  1115. return;
  1116. default:
  1117. __ssb_dma_not_implemented(dev);
  1118. }
  1119. }
  1120. EXPORT_SYMBOL(ssb_dma_free_consistent);
  1121. int ssb_bus_may_powerdown(struct ssb_bus *bus)
  1122. {
  1123. struct ssb_chipcommon *cc;
  1124. int err = 0;
  1125. /* On buses where more than one core may be working
  1126. * at a time, we must not powerdown stuff if there are
  1127. * still cores that may want to run. */
  1128. if (bus->bustype == SSB_BUSTYPE_SSB)
  1129. goto out;
  1130. cc = &bus->chipco;
  1131. if (!cc->dev)
  1132. goto out;
  1133. if (cc->dev->id.revision < 5)
  1134. goto out;
  1135. ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
  1136. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  1137. if (err)
  1138. goto error;
  1139. out:
  1140. #ifdef CONFIG_SSB_DEBUG
  1141. bus->powered_up = 0;
  1142. #endif
  1143. return err;
  1144. error:
  1145. ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
  1146. goto out;
  1147. }
  1148. EXPORT_SYMBOL(ssb_bus_may_powerdown);
  1149. int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
  1150. {
  1151. struct ssb_chipcommon *cc;
  1152. int err;
  1153. enum ssb_clkmode mode;
  1154. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  1155. if (err)
  1156. goto error;
  1157. cc = &bus->chipco;
  1158. mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
  1159. ssb_chipco_set_clockmode(cc, mode);
  1160. #ifdef CONFIG_SSB_DEBUG
  1161. bus->powered_up = 1;
  1162. #endif
  1163. return 0;
  1164. error:
  1165. ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
  1166. return err;
  1167. }
  1168. EXPORT_SYMBOL(ssb_bus_powerup);
  1169. u32 ssb_admatch_base(u32 adm)
  1170. {
  1171. u32 base = 0;
  1172. switch (adm & SSB_ADM_TYPE) {
  1173. case SSB_ADM_TYPE0:
  1174. base = (adm & SSB_ADM_BASE0);
  1175. break;
  1176. case SSB_ADM_TYPE1:
  1177. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1178. base = (adm & SSB_ADM_BASE1);
  1179. break;
  1180. case SSB_ADM_TYPE2:
  1181. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1182. base = (adm & SSB_ADM_BASE2);
  1183. break;
  1184. default:
  1185. SSB_WARN_ON(1);
  1186. }
  1187. return base;
  1188. }
  1189. EXPORT_SYMBOL(ssb_admatch_base);
  1190. u32 ssb_admatch_size(u32 adm)
  1191. {
  1192. u32 size = 0;
  1193. switch (adm & SSB_ADM_TYPE) {
  1194. case SSB_ADM_TYPE0:
  1195. size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
  1196. break;
  1197. case SSB_ADM_TYPE1:
  1198. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1199. size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
  1200. break;
  1201. case SSB_ADM_TYPE2:
  1202. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1203. size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
  1204. break;
  1205. default:
  1206. SSB_WARN_ON(1);
  1207. }
  1208. size = (1 << (size + 1));
  1209. return size;
  1210. }
  1211. EXPORT_SYMBOL(ssb_admatch_size);
  1212. static int __init ssb_modinit(void)
  1213. {
  1214. int err;
  1215. /* See the comment at the ssb_is_early_boot definition */
  1216. ssb_is_early_boot = 0;
  1217. err = bus_register(&ssb_bustype);
  1218. if (err)
  1219. return err;
  1220. /* Maybe we already registered some buses at early boot.
  1221. * Check for this and attach them
  1222. */
  1223. ssb_buses_lock();
  1224. err = ssb_attach_queued_buses();
  1225. ssb_buses_unlock();
  1226. if (err) {
  1227. bus_unregister(&ssb_bustype);
  1228. goto out;
  1229. }
  1230. err = b43_pci_ssb_bridge_init();
  1231. if (err) {
  1232. ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
  1233. "initialization failed\n");
  1234. /* don't fail SSB init because of this */
  1235. err = 0;
  1236. }
  1237. err = ssb_gige_init();
  1238. if (err) {
  1239. ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
  1240. "driver initialization failed\n");
  1241. /* don't fail SSB init because of this */
  1242. err = 0;
  1243. }
  1244. out:
  1245. return err;
  1246. }
  1247. /* ssb must be initialized after PCI but before the ssb drivers.
  1248. * That means we must use some initcall between subsys_initcall
  1249. * and device_initcall. */
  1250. fs_initcall(ssb_modinit);
  1251. static void __exit ssb_modexit(void)
  1252. {
  1253. ssb_gige_exit();
  1254. b43_pci_ssb_bridge_exit();
  1255. bus_unregister(&ssb_bustype);
  1256. }
  1257. module_exit(ssb_modexit)