au1550_spi.c 26 KB

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  1. /*
  2. * au1550_spi.c - au1550 psc spi controller driver
  3. * may work also with au1200, au1210, au1250
  4. * will not work on au1000, au1100 and au1500 (no full spi controller there)
  5. *
  6. * Copyright (c) 2006 ATRON electronic GmbH
  7. * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/errno.h>
  26. #include <linux/device.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/resource.h>
  29. #include <linux/spi/spi.h>
  30. #include <linux/spi/spi_bitbang.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/completion.h>
  33. #include <asm/mach-au1x00/au1000.h>
  34. #include <asm/mach-au1x00/au1xxx_psc.h>
  35. #include <asm/mach-au1x00/au1xxx_dbdma.h>
  36. #include <asm/mach-au1x00/au1550_spi.h>
  37. static unsigned usedma = 1;
  38. module_param(usedma, uint, 0644);
  39. /*
  40. #define AU1550_SPI_DEBUG_LOOPBACK
  41. */
  42. #define AU1550_SPI_DBDMA_DESCRIPTORS 1
  43. #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
  44. struct au1550_spi {
  45. struct spi_bitbang bitbang;
  46. volatile psc_spi_t __iomem *regs;
  47. int irq;
  48. unsigned freq_max;
  49. unsigned freq_min;
  50. unsigned len;
  51. unsigned tx_count;
  52. unsigned rx_count;
  53. const u8 *tx;
  54. u8 *rx;
  55. void (*rx_word)(struct au1550_spi *hw);
  56. void (*tx_word)(struct au1550_spi *hw);
  57. int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
  58. irqreturn_t (*irq_callback)(struct au1550_spi *hw);
  59. struct completion master_done;
  60. unsigned usedma;
  61. u32 dma_tx_id;
  62. u32 dma_rx_id;
  63. u32 dma_tx_ch;
  64. u32 dma_rx_ch;
  65. u8 *dma_rx_tmpbuf;
  66. unsigned dma_rx_tmpbuf_size;
  67. u32 dma_rx_tmpbuf_addr;
  68. struct spi_master *master;
  69. struct device *dev;
  70. struct au1550_spi_info *pdata;
  71. struct resource *ioarea;
  72. };
  73. /* we use an 8-bit memory device for dma transfers to/from spi fifo */
  74. static dbdev_tab_t au1550_spi_mem_dbdev =
  75. {
  76. .dev_id = DBDMA_MEM_CHAN,
  77. .dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
  78. .dev_tsize = 0,
  79. .dev_devwidth = 8,
  80. .dev_physaddr = 0x00000000,
  81. .dev_intlevel = 0,
  82. .dev_intpolarity = 0
  83. };
  84. static int ddma_memid; /* id to above mem dma device */
  85. static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
  86. /*
  87. * compute BRG and DIV bits to setup spi clock based on main input clock rate
  88. * that was specified in platform data structure
  89. * according to au1550 datasheet:
  90. * psc_tempclk = psc_mainclk / (2 << DIV)
  91. * spiclk = psc_tempclk / (2 * (BRG + 1))
  92. * BRG valid range is 4..63
  93. * DIV valid range is 0..3
  94. */
  95. static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
  96. {
  97. u32 mainclk_hz = hw->pdata->mainclk_hz;
  98. u32 div, brg;
  99. for (div = 0; div < 4; div++) {
  100. brg = mainclk_hz / speed_hz / (4 << div);
  101. /* now we have BRG+1 in brg, so count with that */
  102. if (brg < (4 + 1)) {
  103. brg = (4 + 1); /* speed_hz too big */
  104. break; /* set lowest brg (div is == 0) */
  105. }
  106. if (brg <= (63 + 1))
  107. break; /* we have valid brg and div */
  108. }
  109. if (div == 4) {
  110. div = 3; /* speed_hz too small */
  111. brg = (63 + 1); /* set highest brg and div */
  112. }
  113. brg--;
  114. return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
  115. }
  116. static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
  117. {
  118. hw->regs->psc_spimsk =
  119. PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
  120. | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
  121. | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
  122. au_sync();
  123. hw->regs->psc_spievent =
  124. PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
  125. | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
  126. | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
  127. au_sync();
  128. }
  129. static void au1550_spi_reset_fifos(struct au1550_spi *hw)
  130. {
  131. u32 pcr;
  132. hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
  133. au_sync();
  134. do {
  135. pcr = hw->regs->psc_spipcr;
  136. au_sync();
  137. } while (pcr != 0);
  138. }
  139. /*
  140. * dma transfers are used for the most common spi word size of 8-bits
  141. * we cannot easily change already set up dma channels' width, so if we wanted
  142. * dma support for more than 8-bit words (up to 24 bits), we would need to
  143. * setup dma channels from scratch on each spi transfer, based on bits_per_word
  144. * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
  145. * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
  146. * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
  147. */
  148. static void au1550_spi_chipsel(struct spi_device *spi, int value)
  149. {
  150. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  151. unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
  152. u32 cfg, stat;
  153. switch (value) {
  154. case BITBANG_CS_INACTIVE:
  155. if (hw->pdata->deactivate_cs)
  156. hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
  157. cspol);
  158. break;
  159. case BITBANG_CS_ACTIVE:
  160. au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
  161. cfg = hw->regs->psc_spicfg;
  162. au_sync();
  163. hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
  164. au_sync();
  165. if (spi->mode & SPI_CPOL)
  166. cfg |= PSC_SPICFG_BI;
  167. else
  168. cfg &= ~PSC_SPICFG_BI;
  169. if (spi->mode & SPI_CPHA)
  170. cfg &= ~PSC_SPICFG_CDE;
  171. else
  172. cfg |= PSC_SPICFG_CDE;
  173. if (spi->mode & SPI_LSB_FIRST)
  174. cfg |= PSC_SPICFG_MLF;
  175. else
  176. cfg &= ~PSC_SPICFG_MLF;
  177. if (hw->usedma && spi->bits_per_word <= 8)
  178. cfg &= ~PSC_SPICFG_DD_DISABLE;
  179. else
  180. cfg |= PSC_SPICFG_DD_DISABLE;
  181. cfg = PSC_SPICFG_CLR_LEN(cfg);
  182. cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
  183. cfg = PSC_SPICFG_CLR_BAUD(cfg);
  184. cfg &= ~PSC_SPICFG_SET_DIV(3);
  185. cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
  186. hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
  187. au_sync();
  188. do {
  189. stat = hw->regs->psc_spistat;
  190. au_sync();
  191. } while ((stat & PSC_SPISTAT_DR) == 0);
  192. if (hw->pdata->activate_cs)
  193. hw->pdata->activate_cs(hw->pdata, spi->chip_select,
  194. cspol);
  195. break;
  196. }
  197. }
  198. static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
  199. {
  200. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  201. unsigned bpw, hz;
  202. u32 cfg, stat;
  203. bpw = spi->bits_per_word;
  204. hz = spi->max_speed_hz;
  205. if (t) {
  206. if (t->bits_per_word)
  207. bpw = t->bits_per_word;
  208. if (t->speed_hz)
  209. hz = t->speed_hz;
  210. }
  211. if (bpw < 4 || bpw > 24) {
  212. dev_err(&spi->dev, "setupxfer: invalid bits_per_word=%d\n",
  213. bpw);
  214. return -EINVAL;
  215. }
  216. if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
  217. dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
  218. hz);
  219. return -EINVAL;
  220. }
  221. au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
  222. cfg = hw->regs->psc_spicfg;
  223. au_sync();
  224. hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
  225. au_sync();
  226. if (hw->usedma && bpw <= 8)
  227. cfg &= ~PSC_SPICFG_DD_DISABLE;
  228. else
  229. cfg |= PSC_SPICFG_DD_DISABLE;
  230. cfg = PSC_SPICFG_CLR_LEN(cfg);
  231. cfg |= PSC_SPICFG_SET_LEN(bpw);
  232. cfg = PSC_SPICFG_CLR_BAUD(cfg);
  233. cfg &= ~PSC_SPICFG_SET_DIV(3);
  234. cfg |= au1550_spi_baudcfg(hw, hz);
  235. hw->regs->psc_spicfg = cfg;
  236. au_sync();
  237. if (cfg & PSC_SPICFG_DE_ENABLE) {
  238. do {
  239. stat = hw->regs->psc_spistat;
  240. au_sync();
  241. } while ((stat & PSC_SPISTAT_DR) == 0);
  242. }
  243. au1550_spi_reset_fifos(hw);
  244. au1550_spi_mask_ack_all(hw);
  245. return 0;
  246. }
  247. static int au1550_spi_setup(struct spi_device *spi)
  248. {
  249. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  250. if (spi->bits_per_word < 4 || spi->bits_per_word > 24) {
  251. dev_err(&spi->dev, "setup: invalid bits_per_word=%d\n",
  252. spi->bits_per_word);
  253. return -EINVAL;
  254. }
  255. if (spi->max_speed_hz == 0)
  256. spi->max_speed_hz = hw->freq_max;
  257. if (spi->max_speed_hz > hw->freq_max
  258. || spi->max_speed_hz < hw->freq_min)
  259. return -EINVAL;
  260. /*
  261. * NOTE: cannot change speed and other hw settings immediately,
  262. * otherwise sharing of spi bus is not possible,
  263. * so do not call setupxfer(spi, NULL) here
  264. */
  265. return 0;
  266. }
  267. /*
  268. * for dma spi transfers, we have to setup rx channel, otherwise there is
  269. * no reliable way how to recognize that spi transfer is done
  270. * dma complete callbacks are called before real spi transfer is finished
  271. * and if only tx dma channel is set up (and rx fifo overflow event masked)
  272. * spi master done event irq is not generated unless rx fifo is empty (emptied)
  273. * so we need rx tmp buffer to use for rx dma if user does not provide one
  274. */
  275. static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
  276. {
  277. hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
  278. if (!hw->dma_rx_tmpbuf)
  279. return -ENOMEM;
  280. hw->dma_rx_tmpbuf_size = size;
  281. hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
  282. size, DMA_FROM_DEVICE);
  283. if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
  284. kfree(hw->dma_rx_tmpbuf);
  285. hw->dma_rx_tmpbuf = 0;
  286. hw->dma_rx_tmpbuf_size = 0;
  287. return -EFAULT;
  288. }
  289. return 0;
  290. }
  291. static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
  292. {
  293. dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
  294. hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
  295. kfree(hw->dma_rx_tmpbuf);
  296. hw->dma_rx_tmpbuf = 0;
  297. hw->dma_rx_tmpbuf_size = 0;
  298. }
  299. static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
  300. {
  301. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  302. dma_addr_t dma_tx_addr;
  303. dma_addr_t dma_rx_addr;
  304. u32 res;
  305. hw->len = t->len;
  306. hw->tx_count = 0;
  307. hw->rx_count = 0;
  308. hw->tx = t->tx_buf;
  309. hw->rx = t->rx_buf;
  310. dma_tx_addr = t->tx_dma;
  311. dma_rx_addr = t->rx_dma;
  312. /*
  313. * check if buffers are already dma mapped, map them otherwise:
  314. * - first map the TX buffer, so cache data gets written to memory
  315. * - then map the RX buffer, so that cache entries (with
  316. * soon-to-be-stale data) get removed
  317. * use rx buffer in place of tx if tx buffer was not provided
  318. * use temp rx buffer (preallocated or realloc to fit) for rx dma
  319. */
  320. if (t->tx_buf) {
  321. if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
  322. dma_tx_addr = dma_map_single(hw->dev,
  323. (void *)t->tx_buf,
  324. t->len, DMA_TO_DEVICE);
  325. if (dma_mapping_error(hw->dev, dma_tx_addr))
  326. dev_err(hw->dev, "tx dma map error\n");
  327. }
  328. }
  329. if (t->rx_buf) {
  330. if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
  331. dma_rx_addr = dma_map_single(hw->dev,
  332. (void *)t->rx_buf,
  333. t->len, DMA_FROM_DEVICE);
  334. if (dma_mapping_error(hw->dev, dma_rx_addr))
  335. dev_err(hw->dev, "rx dma map error\n");
  336. }
  337. } else {
  338. if (t->len > hw->dma_rx_tmpbuf_size) {
  339. int ret;
  340. au1550_spi_dma_rxtmp_free(hw);
  341. ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
  342. AU1550_SPI_DMA_RXTMP_MINSIZE));
  343. if (ret < 0)
  344. return ret;
  345. }
  346. hw->rx = hw->dma_rx_tmpbuf;
  347. dma_rx_addr = hw->dma_rx_tmpbuf_addr;
  348. dma_sync_single_for_device(hw->dev, dma_rx_addr,
  349. t->len, DMA_FROM_DEVICE);
  350. }
  351. if (!t->tx_buf) {
  352. dma_sync_single_for_device(hw->dev, dma_rx_addr,
  353. t->len, DMA_BIDIRECTIONAL);
  354. hw->tx = hw->rx;
  355. }
  356. /* put buffers on the ring */
  357. res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, hw->rx, t->len);
  358. if (!res)
  359. dev_err(hw->dev, "rx dma put dest error\n");
  360. res = au1xxx_dbdma_put_source(hw->dma_tx_ch, (void *)hw->tx, t->len);
  361. if (!res)
  362. dev_err(hw->dev, "tx dma put source error\n");
  363. au1xxx_dbdma_start(hw->dma_rx_ch);
  364. au1xxx_dbdma_start(hw->dma_tx_ch);
  365. /* by default enable nearly all events interrupt */
  366. hw->regs->psc_spimsk = PSC_SPIMSK_SD;
  367. au_sync();
  368. /* start the transfer */
  369. hw->regs->psc_spipcr = PSC_SPIPCR_MS;
  370. au_sync();
  371. wait_for_completion(&hw->master_done);
  372. au1xxx_dbdma_stop(hw->dma_tx_ch);
  373. au1xxx_dbdma_stop(hw->dma_rx_ch);
  374. if (!t->rx_buf) {
  375. /* using the temporal preallocated and premapped buffer */
  376. dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
  377. DMA_FROM_DEVICE);
  378. }
  379. /* unmap buffers if mapped above */
  380. if (t->rx_buf && t->rx_dma == 0 )
  381. dma_unmap_single(hw->dev, dma_rx_addr, t->len,
  382. DMA_FROM_DEVICE);
  383. if (t->tx_buf && t->tx_dma == 0 )
  384. dma_unmap_single(hw->dev, dma_tx_addr, t->len,
  385. DMA_TO_DEVICE);
  386. return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
  387. }
  388. static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
  389. {
  390. u32 stat, evnt;
  391. stat = hw->regs->psc_spistat;
  392. evnt = hw->regs->psc_spievent;
  393. au_sync();
  394. if ((stat & PSC_SPISTAT_DI) == 0) {
  395. dev_err(hw->dev, "Unexpected IRQ!\n");
  396. return IRQ_NONE;
  397. }
  398. if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
  399. | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
  400. | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
  401. != 0) {
  402. /*
  403. * due to an spi error we consider transfer as done,
  404. * so mask all events until before next transfer start
  405. * and stop the possibly running dma immediatelly
  406. */
  407. au1550_spi_mask_ack_all(hw);
  408. au1xxx_dbdma_stop(hw->dma_rx_ch);
  409. au1xxx_dbdma_stop(hw->dma_tx_ch);
  410. /* get number of transfered bytes */
  411. hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
  412. hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
  413. au1xxx_dbdma_reset(hw->dma_rx_ch);
  414. au1xxx_dbdma_reset(hw->dma_tx_ch);
  415. au1550_spi_reset_fifos(hw);
  416. if (evnt == PSC_SPIEVNT_RO)
  417. dev_err(hw->dev,
  418. "dma transfer: receive FIFO overflow!\n");
  419. else
  420. dev_err(hw->dev,
  421. "dma transfer: unexpected SPI error "
  422. "(event=0x%x stat=0x%x)!\n", evnt, stat);
  423. complete(&hw->master_done);
  424. return IRQ_HANDLED;
  425. }
  426. if ((evnt & PSC_SPIEVNT_MD) != 0) {
  427. /* transfer completed successfully */
  428. au1550_spi_mask_ack_all(hw);
  429. hw->rx_count = hw->len;
  430. hw->tx_count = hw->len;
  431. complete(&hw->master_done);
  432. }
  433. return IRQ_HANDLED;
  434. }
  435. /* routines to handle different word sizes in pio mode */
  436. #define AU1550_SPI_RX_WORD(size, mask) \
  437. static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
  438. { \
  439. u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
  440. au_sync(); \
  441. if (hw->rx) { \
  442. *(u##size *)hw->rx = (u##size)fifoword; \
  443. hw->rx += (size) / 8; \
  444. } \
  445. hw->rx_count += (size) / 8; \
  446. }
  447. #define AU1550_SPI_TX_WORD(size, mask) \
  448. static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
  449. { \
  450. u32 fifoword = 0; \
  451. if (hw->tx) { \
  452. fifoword = *(u##size *)hw->tx & (u32)(mask); \
  453. hw->tx += (size) / 8; \
  454. } \
  455. hw->tx_count += (size) / 8; \
  456. if (hw->tx_count >= hw->len) \
  457. fifoword |= PSC_SPITXRX_LC; \
  458. hw->regs->psc_spitxrx = fifoword; \
  459. au_sync(); \
  460. }
  461. AU1550_SPI_RX_WORD(8,0xff)
  462. AU1550_SPI_RX_WORD(16,0xffff)
  463. AU1550_SPI_RX_WORD(32,0xffffff)
  464. AU1550_SPI_TX_WORD(8,0xff)
  465. AU1550_SPI_TX_WORD(16,0xffff)
  466. AU1550_SPI_TX_WORD(32,0xffffff)
  467. static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
  468. {
  469. u32 stat, mask;
  470. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  471. hw->tx = t->tx_buf;
  472. hw->rx = t->rx_buf;
  473. hw->len = t->len;
  474. hw->tx_count = 0;
  475. hw->rx_count = 0;
  476. /* by default enable nearly all events after filling tx fifo */
  477. mask = PSC_SPIMSK_SD;
  478. /* fill the transmit FIFO */
  479. while (hw->tx_count < hw->len) {
  480. hw->tx_word(hw);
  481. if (hw->tx_count >= hw->len) {
  482. /* mask tx fifo request interrupt as we are done */
  483. mask |= PSC_SPIMSK_TR;
  484. }
  485. stat = hw->regs->psc_spistat;
  486. au_sync();
  487. if (stat & PSC_SPISTAT_TF)
  488. break;
  489. }
  490. /* enable event interrupts */
  491. hw->regs->psc_spimsk = mask;
  492. au_sync();
  493. /* start the transfer */
  494. hw->regs->psc_spipcr = PSC_SPIPCR_MS;
  495. au_sync();
  496. wait_for_completion(&hw->master_done);
  497. return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
  498. }
  499. static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
  500. {
  501. int busy;
  502. u32 stat, evnt;
  503. stat = hw->regs->psc_spistat;
  504. evnt = hw->regs->psc_spievent;
  505. au_sync();
  506. if ((stat & PSC_SPISTAT_DI) == 0) {
  507. dev_err(hw->dev, "Unexpected IRQ!\n");
  508. return IRQ_NONE;
  509. }
  510. if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
  511. | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
  512. | PSC_SPIEVNT_SD))
  513. != 0) {
  514. /*
  515. * due to an error we consider transfer as done,
  516. * so mask all events until before next transfer start
  517. */
  518. au1550_spi_mask_ack_all(hw);
  519. au1550_spi_reset_fifos(hw);
  520. dev_err(hw->dev,
  521. "pio transfer: unexpected SPI error "
  522. "(event=0x%x stat=0x%x)!\n", evnt, stat);
  523. complete(&hw->master_done);
  524. return IRQ_HANDLED;
  525. }
  526. /*
  527. * while there is something to read from rx fifo
  528. * or there is a space to write to tx fifo:
  529. */
  530. do {
  531. busy = 0;
  532. stat = hw->regs->psc_spistat;
  533. au_sync();
  534. /*
  535. * Take care to not let the Rx FIFO overflow.
  536. *
  537. * We only write a byte if we have read one at least. Initially,
  538. * the write fifo is full, so we should read from the read fifo
  539. * first.
  540. * In case we miss a word from the read fifo, we should get a
  541. * RO event and should back out.
  542. */
  543. if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
  544. hw->rx_word(hw);
  545. busy = 1;
  546. if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
  547. hw->tx_word(hw);
  548. }
  549. } while (busy);
  550. hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
  551. au_sync();
  552. /*
  553. * Restart the SPI transmission in case of a transmit underflow.
  554. * This seems to work despite the notes in the Au1550 data book
  555. * of Figure 8-4 with flowchart for SPI master operation:
  556. *
  557. * """Note 1: An XFR Error Interrupt occurs, unless masked,
  558. * for any of the following events: Tx FIFO Underflow,
  559. * Rx FIFO Overflow, or Multiple-master Error
  560. * Note 2: In case of a Tx Underflow Error, all zeroes are
  561. * transmitted."""
  562. *
  563. * By simply restarting the spi transfer on Tx Underflow Error,
  564. * we assume that spi transfer was paused instead of zeroes
  565. * transmittion mentioned in the Note 2 of Au1550 data book.
  566. */
  567. if (evnt & PSC_SPIEVNT_TU) {
  568. hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
  569. au_sync();
  570. hw->regs->psc_spipcr = PSC_SPIPCR_MS;
  571. au_sync();
  572. }
  573. if (hw->rx_count >= hw->len) {
  574. /* transfer completed successfully */
  575. au1550_spi_mask_ack_all(hw);
  576. complete(&hw->master_done);
  577. }
  578. return IRQ_HANDLED;
  579. }
  580. static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
  581. {
  582. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  583. return hw->txrx_bufs(spi, t);
  584. }
  585. static irqreturn_t au1550_spi_irq(int irq, void *dev)
  586. {
  587. struct au1550_spi *hw = dev;
  588. return hw->irq_callback(hw);
  589. }
  590. static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
  591. {
  592. if (bpw <= 8) {
  593. if (hw->usedma) {
  594. hw->txrx_bufs = &au1550_spi_dma_txrxb;
  595. hw->irq_callback = &au1550_spi_dma_irq_callback;
  596. } else {
  597. hw->rx_word = &au1550_spi_rx_word_8;
  598. hw->tx_word = &au1550_spi_tx_word_8;
  599. hw->txrx_bufs = &au1550_spi_pio_txrxb;
  600. hw->irq_callback = &au1550_spi_pio_irq_callback;
  601. }
  602. } else if (bpw <= 16) {
  603. hw->rx_word = &au1550_spi_rx_word_16;
  604. hw->tx_word = &au1550_spi_tx_word_16;
  605. hw->txrx_bufs = &au1550_spi_pio_txrxb;
  606. hw->irq_callback = &au1550_spi_pio_irq_callback;
  607. } else {
  608. hw->rx_word = &au1550_spi_rx_word_32;
  609. hw->tx_word = &au1550_spi_tx_word_32;
  610. hw->txrx_bufs = &au1550_spi_pio_txrxb;
  611. hw->irq_callback = &au1550_spi_pio_irq_callback;
  612. }
  613. }
  614. static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
  615. {
  616. u32 stat, cfg;
  617. /* set up the PSC for SPI mode */
  618. hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
  619. au_sync();
  620. hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
  621. au_sync();
  622. hw->regs->psc_spicfg = 0;
  623. au_sync();
  624. hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
  625. au_sync();
  626. do {
  627. stat = hw->regs->psc_spistat;
  628. au_sync();
  629. } while ((stat & PSC_SPISTAT_SR) == 0);
  630. cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
  631. cfg |= PSC_SPICFG_SET_LEN(8);
  632. cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
  633. /* use minimal allowed brg and div values as initial setting: */
  634. cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
  635. #ifdef AU1550_SPI_DEBUG_LOOPBACK
  636. cfg |= PSC_SPICFG_LB;
  637. #endif
  638. hw->regs->psc_spicfg = cfg;
  639. au_sync();
  640. au1550_spi_mask_ack_all(hw);
  641. hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
  642. au_sync();
  643. do {
  644. stat = hw->regs->psc_spistat;
  645. au_sync();
  646. } while ((stat & PSC_SPISTAT_DR) == 0);
  647. au1550_spi_reset_fifos(hw);
  648. }
  649. static int __init au1550_spi_probe(struct platform_device *pdev)
  650. {
  651. struct au1550_spi *hw;
  652. struct spi_master *master;
  653. struct resource *r;
  654. int err = 0;
  655. master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
  656. if (master == NULL) {
  657. dev_err(&pdev->dev, "No memory for spi_master\n");
  658. err = -ENOMEM;
  659. goto err_nomem;
  660. }
  661. /* the spi->mode bits understood by this driver: */
  662. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
  663. hw = spi_master_get_devdata(master);
  664. hw->master = spi_master_get(master);
  665. hw->pdata = pdev->dev.platform_data;
  666. hw->dev = &pdev->dev;
  667. if (hw->pdata == NULL) {
  668. dev_err(&pdev->dev, "No platform data supplied\n");
  669. err = -ENOENT;
  670. goto err_no_pdata;
  671. }
  672. r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  673. if (!r) {
  674. dev_err(&pdev->dev, "no IRQ\n");
  675. err = -ENODEV;
  676. goto err_no_iores;
  677. }
  678. hw->irq = r->start;
  679. hw->usedma = 0;
  680. r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  681. if (r) {
  682. hw->dma_tx_id = r->start;
  683. r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  684. if (r) {
  685. hw->dma_rx_id = r->start;
  686. if (usedma && ddma_memid) {
  687. if (pdev->dev.dma_mask == NULL)
  688. dev_warn(&pdev->dev, "no dma mask\n");
  689. else
  690. hw->usedma = 1;
  691. }
  692. }
  693. }
  694. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  695. if (!r) {
  696. dev_err(&pdev->dev, "no mmio resource\n");
  697. err = -ENODEV;
  698. goto err_no_iores;
  699. }
  700. hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
  701. pdev->name);
  702. if (!hw->ioarea) {
  703. dev_err(&pdev->dev, "Cannot reserve iomem region\n");
  704. err = -ENXIO;
  705. goto err_no_iores;
  706. }
  707. hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
  708. if (!hw->regs) {
  709. dev_err(&pdev->dev, "cannot ioremap\n");
  710. err = -ENXIO;
  711. goto err_ioremap;
  712. }
  713. platform_set_drvdata(pdev, hw);
  714. init_completion(&hw->master_done);
  715. hw->bitbang.master = hw->master;
  716. hw->bitbang.setup_transfer = au1550_spi_setupxfer;
  717. hw->bitbang.chipselect = au1550_spi_chipsel;
  718. hw->bitbang.master->setup = au1550_spi_setup;
  719. hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
  720. if (hw->usedma) {
  721. hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
  722. hw->dma_tx_id, NULL, (void *)hw);
  723. if (hw->dma_tx_ch == 0) {
  724. dev_err(&pdev->dev,
  725. "Cannot allocate tx dma channel\n");
  726. err = -ENXIO;
  727. goto err_no_txdma;
  728. }
  729. au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
  730. if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
  731. AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
  732. dev_err(&pdev->dev,
  733. "Cannot allocate tx dma descriptors\n");
  734. err = -ENXIO;
  735. goto err_no_txdma_descr;
  736. }
  737. hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
  738. ddma_memid, NULL, (void *)hw);
  739. if (hw->dma_rx_ch == 0) {
  740. dev_err(&pdev->dev,
  741. "Cannot allocate rx dma channel\n");
  742. err = -ENXIO;
  743. goto err_no_rxdma;
  744. }
  745. au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
  746. if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
  747. AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
  748. dev_err(&pdev->dev,
  749. "Cannot allocate rx dma descriptors\n");
  750. err = -ENXIO;
  751. goto err_no_rxdma_descr;
  752. }
  753. err = au1550_spi_dma_rxtmp_alloc(hw,
  754. AU1550_SPI_DMA_RXTMP_MINSIZE);
  755. if (err < 0) {
  756. dev_err(&pdev->dev,
  757. "Cannot allocate initial rx dma tmp buffer\n");
  758. goto err_dma_rxtmp_alloc;
  759. }
  760. }
  761. au1550_spi_bits_handlers_set(hw, 8);
  762. err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
  763. if (err) {
  764. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  765. goto err_no_irq;
  766. }
  767. master->bus_num = pdev->id;
  768. master->num_chipselect = hw->pdata->num_chipselect;
  769. /*
  770. * precompute valid range for spi freq - from au1550 datasheet:
  771. * psc_tempclk = psc_mainclk / (2 << DIV)
  772. * spiclk = psc_tempclk / (2 * (BRG + 1))
  773. * BRG valid range is 4..63
  774. * DIV valid range is 0..3
  775. * round the min and max frequencies to values that would still
  776. * produce valid brg and div
  777. */
  778. {
  779. int min_div = (2 << 0) * (2 * (4 + 1));
  780. int max_div = (2 << 3) * (2 * (63 + 1));
  781. hw->freq_max = hw->pdata->mainclk_hz / min_div;
  782. hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1;
  783. }
  784. au1550_spi_setup_psc_as_spi(hw);
  785. err = spi_bitbang_start(&hw->bitbang);
  786. if (err) {
  787. dev_err(&pdev->dev, "Failed to register SPI master\n");
  788. goto err_register;
  789. }
  790. dev_info(&pdev->dev,
  791. "spi master registered: bus_num=%d num_chipselect=%d\n",
  792. master->bus_num, master->num_chipselect);
  793. return 0;
  794. err_register:
  795. free_irq(hw->irq, hw);
  796. err_no_irq:
  797. au1550_spi_dma_rxtmp_free(hw);
  798. err_dma_rxtmp_alloc:
  799. err_no_rxdma_descr:
  800. if (hw->usedma)
  801. au1xxx_dbdma_chan_free(hw->dma_rx_ch);
  802. err_no_rxdma:
  803. err_no_txdma_descr:
  804. if (hw->usedma)
  805. au1xxx_dbdma_chan_free(hw->dma_tx_ch);
  806. err_no_txdma:
  807. iounmap((void __iomem *)hw->regs);
  808. err_ioremap:
  809. release_resource(hw->ioarea);
  810. kfree(hw->ioarea);
  811. err_no_iores:
  812. err_no_pdata:
  813. spi_master_put(hw->master);
  814. err_nomem:
  815. return err;
  816. }
  817. static int __exit au1550_spi_remove(struct platform_device *pdev)
  818. {
  819. struct au1550_spi *hw = platform_get_drvdata(pdev);
  820. dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
  821. hw->master->bus_num);
  822. spi_bitbang_stop(&hw->bitbang);
  823. free_irq(hw->irq, hw);
  824. iounmap((void __iomem *)hw->regs);
  825. release_resource(hw->ioarea);
  826. kfree(hw->ioarea);
  827. if (hw->usedma) {
  828. au1550_spi_dma_rxtmp_free(hw);
  829. au1xxx_dbdma_chan_free(hw->dma_rx_ch);
  830. au1xxx_dbdma_chan_free(hw->dma_tx_ch);
  831. }
  832. platform_set_drvdata(pdev, NULL);
  833. spi_master_put(hw->master);
  834. return 0;
  835. }
  836. /* work with hotplug and coldplug */
  837. MODULE_ALIAS("platform:au1550-spi");
  838. static struct platform_driver au1550_spi_drv = {
  839. .remove = __exit_p(au1550_spi_remove),
  840. .driver = {
  841. .name = "au1550-spi",
  842. .owner = THIS_MODULE,
  843. },
  844. };
  845. static int __init au1550_spi_init(void)
  846. {
  847. /*
  848. * create memory device with 8 bits dev_devwidth
  849. * needed for proper byte ordering to spi fifo
  850. */
  851. if (usedma) {
  852. ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
  853. if (!ddma_memid)
  854. printk(KERN_ERR "au1550-spi: cannot add memory"
  855. "dbdma device\n");
  856. }
  857. return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe);
  858. }
  859. module_init(au1550_spi_init);
  860. static void __exit au1550_spi_exit(void)
  861. {
  862. if (usedma && ddma_memid)
  863. au1xxx_ddma_del_device(ddma_memid);
  864. platform_driver_unregister(&au1550_spi_drv);
  865. }
  866. module_exit(au1550_spi_exit);
  867. MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
  868. MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
  869. MODULE_LICENSE("GPL");