mv_sas.c 55 KB

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  1. /*
  2. * Marvell 88SE64xx/88SE94xx main function
  3. *
  4. * Copyright 2007 Red Hat, Inc.
  5. * Copyright 2008 Marvell. <kewei@marvell.com>
  6. *
  7. * This file is licensed under GPLv2.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; version 2 of the
  12. * License.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17. * General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  22. * USA
  23. */
  24. #include "mv_sas.h"
  25. static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
  26. {
  27. if (task->lldd_task) {
  28. struct mvs_slot_info *slot;
  29. slot = task->lldd_task;
  30. *tag = slot->slot_tag;
  31. return 1;
  32. }
  33. return 0;
  34. }
  35. void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
  36. {
  37. void *bitmap = &mvi->tags;
  38. clear_bit(tag, bitmap);
  39. }
  40. void mvs_tag_free(struct mvs_info *mvi, u32 tag)
  41. {
  42. mvs_tag_clear(mvi, tag);
  43. }
  44. void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
  45. {
  46. void *bitmap = &mvi->tags;
  47. set_bit(tag, bitmap);
  48. }
  49. inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
  50. {
  51. unsigned int index, tag;
  52. void *bitmap = &mvi->tags;
  53. index = find_first_zero_bit(bitmap, mvi->tags_num);
  54. tag = index;
  55. if (tag >= mvi->tags_num)
  56. return -SAS_QUEUE_FULL;
  57. mvs_tag_set(mvi, tag);
  58. *tag_out = tag;
  59. return 0;
  60. }
  61. void mvs_tag_init(struct mvs_info *mvi)
  62. {
  63. int i;
  64. for (i = 0; i < mvi->tags_num; ++i)
  65. mvs_tag_clear(mvi, i);
  66. }
  67. void mvs_hexdump(u32 size, u8 *data, u32 baseaddr)
  68. {
  69. u32 i;
  70. u32 run;
  71. u32 offset;
  72. offset = 0;
  73. while (size) {
  74. printk(KERN_DEBUG"%08X : ", baseaddr + offset);
  75. if (size >= 16)
  76. run = 16;
  77. else
  78. run = size;
  79. size -= run;
  80. for (i = 0; i < 16; i++) {
  81. if (i < run)
  82. printk(KERN_DEBUG"%02X ", (u32)data[i]);
  83. else
  84. printk(KERN_DEBUG" ");
  85. }
  86. printk(KERN_DEBUG": ");
  87. for (i = 0; i < run; i++)
  88. printk(KERN_DEBUG"%c",
  89. isalnum(data[i]) ? data[i] : '.');
  90. printk(KERN_DEBUG"\n");
  91. data = &data[16];
  92. offset += run;
  93. }
  94. printk(KERN_DEBUG"\n");
  95. }
  96. #if (_MV_DUMP > 1)
  97. static void mvs_hba_sb_dump(struct mvs_info *mvi, u32 tag,
  98. enum sas_protocol proto)
  99. {
  100. u32 offset;
  101. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  102. offset = slot->cmd_size + MVS_OAF_SZ +
  103. MVS_CHIP_DISP->prd_size() * slot->n_elem;
  104. dev_printk(KERN_DEBUG, mvi->dev, "+---->Status buffer[%d] :\n",
  105. tag);
  106. mvs_hexdump(32, (u8 *) slot->response,
  107. (u32) slot->buf_dma + offset);
  108. }
  109. #endif
  110. static void mvs_hba_memory_dump(struct mvs_info *mvi, u32 tag,
  111. enum sas_protocol proto)
  112. {
  113. #if (_MV_DUMP > 1)
  114. u32 sz, w_ptr;
  115. u64 addr;
  116. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  117. /*Delivery Queue */
  118. sz = MVS_CHIP_SLOT_SZ;
  119. w_ptr = slot->tx;
  120. addr = mvi->tx_dma;
  121. dev_printk(KERN_DEBUG, mvi->dev,
  122. "Delivery Queue Size=%04d , WRT_PTR=%04X\n", sz, w_ptr);
  123. dev_printk(KERN_DEBUG, mvi->dev,
  124. "Delivery Queue Base Address=0x%llX (PA)"
  125. "(tx_dma=0x%llX), Entry=%04d\n",
  126. addr, (unsigned long long)mvi->tx_dma, w_ptr);
  127. mvs_hexdump(sizeof(u32), (u8 *)(&mvi->tx[mvi->tx_prod]),
  128. (u32) mvi->tx_dma + sizeof(u32) * w_ptr);
  129. /*Command List */
  130. addr = mvi->slot_dma;
  131. dev_printk(KERN_DEBUG, mvi->dev,
  132. "Command List Base Address=0x%llX (PA)"
  133. "(slot_dma=0x%llX), Header=%03d\n",
  134. addr, (unsigned long long)slot->buf_dma, tag);
  135. dev_printk(KERN_DEBUG, mvi->dev, "Command Header[%03d]:\n", tag);
  136. /*mvs_cmd_hdr */
  137. mvs_hexdump(sizeof(struct mvs_cmd_hdr), (u8 *)(&mvi->slot[tag]),
  138. (u32) mvi->slot_dma + tag * sizeof(struct mvs_cmd_hdr));
  139. /*1.command table area */
  140. dev_printk(KERN_DEBUG, mvi->dev, "+---->Command Table :\n");
  141. mvs_hexdump(slot->cmd_size, (u8 *) slot->buf, (u32) slot->buf_dma);
  142. /*2.open address frame area */
  143. dev_printk(KERN_DEBUG, mvi->dev, "+---->Open Address Frame :\n");
  144. mvs_hexdump(MVS_OAF_SZ, (u8 *) slot->buf + slot->cmd_size,
  145. (u32) slot->buf_dma + slot->cmd_size);
  146. /*3.status buffer */
  147. mvs_hba_sb_dump(mvi, tag, proto);
  148. /*4.PRD table */
  149. dev_printk(KERN_DEBUG, mvi->dev, "+---->PRD table :\n");
  150. mvs_hexdump(MVS_CHIP_DISP->prd_size() * slot->n_elem,
  151. (u8 *) slot->buf + slot->cmd_size + MVS_OAF_SZ,
  152. (u32) slot->buf_dma + slot->cmd_size + MVS_OAF_SZ);
  153. #endif
  154. }
  155. static void mvs_hba_cq_dump(struct mvs_info *mvi)
  156. {
  157. #if (_MV_DUMP > 2)
  158. u64 addr;
  159. void __iomem *regs = mvi->regs;
  160. u32 entry = mvi->rx_cons + 1;
  161. u32 rx_desc = le32_to_cpu(mvi->rx[entry]);
  162. /*Completion Queue */
  163. addr = mr32(RX_HI) << 16 << 16 | mr32(RX_LO);
  164. dev_printk(KERN_DEBUG, mvi->dev, "Completion Task = 0x%p\n",
  165. mvi->slot_info[rx_desc & RXQ_SLOT_MASK].task);
  166. dev_printk(KERN_DEBUG, mvi->dev,
  167. "Completion List Base Address=0x%llX (PA), "
  168. "CQ_Entry=%04d, CQ_WP=0x%08X\n",
  169. addr, entry - 1, mvi->rx[0]);
  170. mvs_hexdump(sizeof(u32), (u8 *)(&rx_desc),
  171. mvi->rx_dma + sizeof(u32) * entry);
  172. #endif
  173. }
  174. void mvs_get_sas_addr(void *buf, u32 buflen)
  175. {
  176. /*memcpy(buf, "\x50\x05\x04\x30\x11\xab\x64\x40", 8);*/
  177. }
  178. struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
  179. {
  180. unsigned long i = 0, j = 0, hi = 0;
  181. struct sas_ha_struct *sha = dev->port->ha;
  182. struct mvs_info *mvi = NULL;
  183. struct asd_sas_phy *phy;
  184. while (sha->sas_port[i]) {
  185. if (sha->sas_port[i] == dev->port) {
  186. phy = container_of(sha->sas_port[i]->phy_list.next,
  187. struct asd_sas_phy, port_phy_el);
  188. j = 0;
  189. while (sha->sas_phy[j]) {
  190. if (sha->sas_phy[j] == phy)
  191. break;
  192. j++;
  193. }
  194. break;
  195. }
  196. i++;
  197. }
  198. hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  199. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  200. return mvi;
  201. }
  202. /* FIXME */
  203. int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
  204. {
  205. unsigned long i = 0, j = 0, n = 0, num = 0;
  206. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  207. struct mvs_info *mvi = mvi_dev->mvi_info;
  208. struct sas_ha_struct *sha = dev->port->ha;
  209. while (sha->sas_port[i]) {
  210. if (sha->sas_port[i] == dev->port) {
  211. struct asd_sas_phy *phy;
  212. list_for_each_entry(phy,
  213. &sha->sas_port[i]->phy_list, port_phy_el) {
  214. j = 0;
  215. while (sha->sas_phy[j]) {
  216. if (sha->sas_phy[j] == phy)
  217. break;
  218. j++;
  219. }
  220. phyno[n] = (j >= mvi->chip->n_phy) ?
  221. (j - mvi->chip->n_phy) : j;
  222. num++;
  223. n++;
  224. }
  225. break;
  226. }
  227. i++;
  228. }
  229. return num;
  230. }
  231. static inline void mvs_free_reg_set(struct mvs_info *mvi,
  232. struct mvs_device *dev)
  233. {
  234. if (!dev) {
  235. mv_printk("device has been free.\n");
  236. return;
  237. }
  238. if (dev->runing_req != 0)
  239. return;
  240. if (dev->taskfileset == MVS_ID_NOT_MAPPED)
  241. return;
  242. MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
  243. }
  244. static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
  245. struct mvs_device *dev)
  246. {
  247. if (dev->taskfileset != MVS_ID_NOT_MAPPED)
  248. return 0;
  249. return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
  250. }
  251. void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
  252. {
  253. u32 no;
  254. for_each_phy(phy_mask, phy_mask, no) {
  255. if (!(phy_mask & 1))
  256. continue;
  257. MVS_CHIP_DISP->phy_reset(mvi, no, hard);
  258. }
  259. }
  260. /* FIXME: locking? */
  261. int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
  262. void *funcdata)
  263. {
  264. int rc = 0, phy_id = sas_phy->id;
  265. u32 tmp, i = 0, hi;
  266. struct sas_ha_struct *sha = sas_phy->ha;
  267. struct mvs_info *mvi = NULL;
  268. while (sha->sas_phy[i]) {
  269. if (sha->sas_phy[i] == sas_phy)
  270. break;
  271. i++;
  272. }
  273. hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  274. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  275. switch (func) {
  276. case PHY_FUNC_SET_LINK_RATE:
  277. MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
  278. break;
  279. case PHY_FUNC_HARD_RESET:
  280. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
  281. if (tmp & PHY_RST_HARD)
  282. break;
  283. MVS_CHIP_DISP->phy_reset(mvi, phy_id, 1);
  284. break;
  285. case PHY_FUNC_LINK_RESET:
  286. MVS_CHIP_DISP->phy_enable(mvi, phy_id);
  287. MVS_CHIP_DISP->phy_reset(mvi, phy_id, 0);
  288. break;
  289. case PHY_FUNC_DISABLE:
  290. MVS_CHIP_DISP->phy_disable(mvi, phy_id);
  291. break;
  292. case PHY_FUNC_RELEASE_SPINUP_HOLD:
  293. default:
  294. rc = -EOPNOTSUPP;
  295. }
  296. msleep(200);
  297. return rc;
  298. }
  299. void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
  300. u32 off_lo, u32 off_hi, u64 sas_addr)
  301. {
  302. u32 lo = (u32)sas_addr;
  303. u32 hi = (u32)(sas_addr>>32);
  304. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
  305. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
  306. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
  307. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
  308. }
  309. static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
  310. {
  311. struct mvs_phy *phy = &mvi->phy[i];
  312. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  313. struct sas_ha_struct *sas_ha;
  314. if (!phy->phy_attached)
  315. return;
  316. if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
  317. && phy->phy_type & PORT_TYPE_SAS) {
  318. return;
  319. }
  320. sas_ha = mvi->sas;
  321. sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
  322. if (sas_phy->phy) {
  323. struct sas_phy *sphy = sas_phy->phy;
  324. sphy->negotiated_linkrate = sas_phy->linkrate;
  325. sphy->minimum_linkrate = phy->minimum_linkrate;
  326. sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  327. sphy->maximum_linkrate = phy->maximum_linkrate;
  328. sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
  329. }
  330. if (phy->phy_type & PORT_TYPE_SAS) {
  331. struct sas_identify_frame *id;
  332. id = (struct sas_identify_frame *)phy->frame_rcvd;
  333. id->dev_type = phy->identify.device_type;
  334. id->initiator_bits = SAS_PROTOCOL_ALL;
  335. id->target_bits = phy->identify.target_port_protocols;
  336. } else if (phy->phy_type & PORT_TYPE_SATA) {
  337. /*Nothing*/
  338. }
  339. mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
  340. sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
  341. mvi->sas->notify_port_event(sas_phy,
  342. PORTE_BYTES_DMAED);
  343. }
  344. int mvs_slave_alloc(struct scsi_device *scsi_dev)
  345. {
  346. struct domain_device *dev = sdev_to_domain_dev(scsi_dev);
  347. if (dev_is_sata(dev)) {
  348. /* We don't need to rescan targets
  349. * if REPORT_LUNS request is failed
  350. */
  351. if (scsi_dev->lun > 0)
  352. return -ENXIO;
  353. scsi_dev->tagged_supported = 1;
  354. }
  355. return sas_slave_alloc(scsi_dev);
  356. }
  357. int mvs_slave_configure(struct scsi_device *sdev)
  358. {
  359. struct domain_device *dev = sdev_to_domain_dev(sdev);
  360. int ret = sas_slave_configure(sdev);
  361. if (ret)
  362. return ret;
  363. if (dev_is_sata(dev)) {
  364. /* may set PIO mode */
  365. #if MV_DISABLE_NCQ
  366. struct ata_port *ap = dev->sata_dev.ap;
  367. struct ata_device *adev = ap->link.device;
  368. adev->flags |= ATA_DFLAG_NCQ_OFF;
  369. scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, 1);
  370. #endif
  371. }
  372. return 0;
  373. }
  374. void mvs_scan_start(struct Scsi_Host *shost)
  375. {
  376. int i, j;
  377. unsigned short core_nr;
  378. struct mvs_info *mvi;
  379. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  380. core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
  381. for (j = 0; j < core_nr; j++) {
  382. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
  383. for (i = 0; i < mvi->chip->n_phy; ++i)
  384. mvs_bytes_dmaed(mvi, i);
  385. }
  386. }
  387. int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
  388. {
  389. /* give the phy enabling interrupt event time to come in (1s
  390. * is empirically about all it takes) */
  391. if (time < HZ)
  392. return 0;
  393. /* Wait for discovery to finish */
  394. scsi_flush_work(shost);
  395. return 1;
  396. }
  397. static int mvs_task_prep_smp(struct mvs_info *mvi,
  398. struct mvs_task_exec_info *tei)
  399. {
  400. int elem, rc, i;
  401. struct sas_task *task = tei->task;
  402. struct mvs_cmd_hdr *hdr = tei->hdr;
  403. struct domain_device *dev = task->dev;
  404. struct asd_sas_port *sas_port = dev->port;
  405. struct scatterlist *sg_req, *sg_resp;
  406. u32 req_len, resp_len, tag = tei->tag;
  407. void *buf_tmp;
  408. u8 *buf_oaf;
  409. dma_addr_t buf_tmp_dma;
  410. void *buf_prd;
  411. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  412. u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  413. #if _MV_DUMP
  414. u8 *buf_cmd;
  415. void *from;
  416. #endif
  417. /*
  418. * DMA-map SMP request, response buffers
  419. */
  420. sg_req = &task->smp_task.smp_req;
  421. elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
  422. if (!elem)
  423. return -ENOMEM;
  424. req_len = sg_dma_len(sg_req);
  425. sg_resp = &task->smp_task.smp_resp;
  426. elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
  427. if (!elem) {
  428. rc = -ENOMEM;
  429. goto err_out;
  430. }
  431. resp_len = SB_RFB_MAX;
  432. /* must be in dwords */
  433. if ((req_len & 0x3) || (resp_len & 0x3)) {
  434. rc = -EINVAL;
  435. goto err_out_2;
  436. }
  437. /*
  438. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  439. */
  440. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
  441. buf_tmp = slot->buf;
  442. buf_tmp_dma = slot->buf_dma;
  443. #if _MV_DUMP
  444. buf_cmd = buf_tmp;
  445. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  446. buf_tmp += req_len;
  447. buf_tmp_dma += req_len;
  448. slot->cmd_size = req_len;
  449. #else
  450. hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
  451. #endif
  452. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  453. buf_oaf = buf_tmp;
  454. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  455. buf_tmp += MVS_OAF_SZ;
  456. buf_tmp_dma += MVS_OAF_SZ;
  457. /* region 3: PRD table *********************************** */
  458. buf_prd = buf_tmp;
  459. if (tei->n_elem)
  460. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  461. else
  462. hdr->prd_tbl = 0;
  463. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  464. buf_tmp += i;
  465. buf_tmp_dma += i;
  466. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  467. slot->response = buf_tmp;
  468. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  469. if (mvi->flags & MVF_FLAG_SOC)
  470. hdr->reserved[0] = 0;
  471. /*
  472. * Fill in TX ring and command slot header
  473. */
  474. slot->tx = mvi->tx_prod;
  475. mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
  476. TXQ_MODE_I | tag |
  477. (sas_port->phy_mask << TXQ_PHY_SHIFT));
  478. hdr->flags |= flags;
  479. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
  480. hdr->tags = cpu_to_le32(tag);
  481. hdr->data_len = 0;
  482. /* generate open address frame hdr (first 12 bytes) */
  483. /* initiator, SMP, ftype 1h */
  484. buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
  485. buf_oaf[1] = dev->linkrate & 0xf;
  486. *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
  487. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  488. /* fill in PRD (scatter/gather) table, if any */
  489. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  490. #if _MV_DUMP
  491. /* copy cmd table */
  492. from = kmap_atomic(sg_page(sg_req), KM_IRQ0);
  493. memcpy(buf_cmd, from + sg_req->offset, req_len);
  494. kunmap_atomic(from, KM_IRQ0);
  495. #endif
  496. return 0;
  497. err_out_2:
  498. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
  499. PCI_DMA_FROMDEVICE);
  500. err_out:
  501. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
  502. PCI_DMA_TODEVICE);
  503. return rc;
  504. }
  505. static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
  506. {
  507. struct ata_queued_cmd *qc = task->uldd_task;
  508. if (qc) {
  509. if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
  510. qc->tf.command == ATA_CMD_FPDMA_READ) {
  511. *tag = qc->tag;
  512. return 1;
  513. }
  514. }
  515. return 0;
  516. }
  517. static int mvs_task_prep_ata(struct mvs_info *mvi,
  518. struct mvs_task_exec_info *tei)
  519. {
  520. struct sas_task *task = tei->task;
  521. struct domain_device *dev = task->dev;
  522. struct mvs_device *mvi_dev = dev->lldd_dev;
  523. struct mvs_cmd_hdr *hdr = tei->hdr;
  524. struct asd_sas_port *sas_port = dev->port;
  525. struct mvs_slot_info *slot;
  526. void *buf_prd;
  527. u32 tag = tei->tag, hdr_tag;
  528. u32 flags, del_q;
  529. void *buf_tmp;
  530. u8 *buf_cmd, *buf_oaf;
  531. dma_addr_t buf_tmp_dma;
  532. u32 i, req_len, resp_len;
  533. const u32 max_resp_len = SB_RFB_MAX;
  534. if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
  535. mv_dprintk("Have not enough regiset for dev %d.\n",
  536. mvi_dev->device_id);
  537. return -EBUSY;
  538. }
  539. slot = &mvi->slot_info[tag];
  540. slot->tx = mvi->tx_prod;
  541. del_q = TXQ_MODE_I | tag |
  542. (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
  543. (sas_port->phy_mask << TXQ_PHY_SHIFT) |
  544. (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
  545. mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
  546. #ifndef DISABLE_HOTPLUG_DMA_FIX
  547. if (task->data_dir == DMA_FROM_DEVICE)
  548. flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
  549. else
  550. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  551. #else
  552. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  553. #endif
  554. if (task->ata_task.use_ncq)
  555. flags |= MCH_FPDMA;
  556. if (dev->sata_dev.command_set == ATAPI_COMMAND_SET) {
  557. if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
  558. flags |= MCH_ATAPI;
  559. }
  560. /* FIXME: fill in port multiplier number */
  561. hdr->flags = cpu_to_le32(flags);
  562. /* FIXME: the low order order 5 bits for the TAG if enable NCQ */
  563. if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
  564. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  565. else
  566. hdr_tag = tag;
  567. hdr->tags = cpu_to_le32(hdr_tag);
  568. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  569. /*
  570. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  571. */
  572. /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
  573. buf_cmd = buf_tmp = slot->buf;
  574. buf_tmp_dma = slot->buf_dma;
  575. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  576. buf_tmp += MVS_ATA_CMD_SZ;
  577. buf_tmp_dma += MVS_ATA_CMD_SZ;
  578. #if _MV_DUMP
  579. slot->cmd_size = MVS_ATA_CMD_SZ;
  580. #endif
  581. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  582. /* used for STP. unused for SATA? */
  583. buf_oaf = buf_tmp;
  584. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  585. buf_tmp += MVS_OAF_SZ;
  586. buf_tmp_dma += MVS_OAF_SZ;
  587. /* region 3: PRD table ********************************************* */
  588. buf_prd = buf_tmp;
  589. if (tei->n_elem)
  590. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  591. else
  592. hdr->prd_tbl = 0;
  593. i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
  594. buf_tmp += i;
  595. buf_tmp_dma += i;
  596. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  597. /* FIXME: probably unused, for SATA. kept here just in case
  598. * we get a STP/SATA error information record
  599. */
  600. slot->response = buf_tmp;
  601. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  602. if (mvi->flags & MVF_FLAG_SOC)
  603. hdr->reserved[0] = 0;
  604. req_len = sizeof(struct host_to_dev_fis);
  605. resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
  606. sizeof(struct mvs_err_info) - i;
  607. /* request, response lengths */
  608. resp_len = min(resp_len, max_resp_len);
  609. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  610. if (likely(!task->ata_task.device_control_reg_update))
  611. task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
  612. /* fill in command FIS and ATAPI CDB */
  613. memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
  614. if (dev->sata_dev.command_set == ATAPI_COMMAND_SET)
  615. memcpy(buf_cmd + STP_ATAPI_CMD,
  616. task->ata_task.atapi_packet, 16);
  617. /* generate open address frame hdr (first 12 bytes) */
  618. /* initiator, STP, ftype 1h */
  619. buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
  620. buf_oaf[1] = dev->linkrate & 0xf;
  621. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  622. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  623. /* fill in PRD (scatter/gather) table, if any */
  624. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  625. #ifndef DISABLE_HOTPLUG_DMA_FIX
  626. if (task->data_dir == DMA_FROM_DEVICE)
  627. MVS_CHIP_DISP->dma_fix(mvi->bulk_buffer_dma,
  628. TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
  629. #endif
  630. return 0;
  631. }
  632. static int mvs_task_prep_ssp(struct mvs_info *mvi,
  633. struct mvs_task_exec_info *tei, int is_tmf,
  634. struct mvs_tmf_task *tmf)
  635. {
  636. struct sas_task *task = tei->task;
  637. struct mvs_cmd_hdr *hdr = tei->hdr;
  638. struct mvs_port *port = tei->port;
  639. struct domain_device *dev = task->dev;
  640. struct mvs_device *mvi_dev = dev->lldd_dev;
  641. struct asd_sas_port *sas_port = dev->port;
  642. struct mvs_slot_info *slot;
  643. void *buf_prd;
  644. struct ssp_frame_hdr *ssp_hdr;
  645. void *buf_tmp;
  646. u8 *buf_cmd, *buf_oaf, fburst = 0;
  647. dma_addr_t buf_tmp_dma;
  648. u32 flags;
  649. u32 resp_len, req_len, i, tag = tei->tag;
  650. const u32 max_resp_len = SB_RFB_MAX;
  651. u32 phy_mask;
  652. slot = &mvi->slot_info[tag];
  653. phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
  654. sas_port->phy_mask) & TXQ_PHY_MASK;
  655. slot->tx = mvi->tx_prod;
  656. mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
  657. (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
  658. (phy_mask << TXQ_PHY_SHIFT));
  659. flags = MCH_RETRY;
  660. if (task->ssp_task.enable_first_burst) {
  661. flags |= MCH_FBURST;
  662. fburst = (1 << 7);
  663. }
  664. if (is_tmf)
  665. flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
  666. else
  667. flags |= (MCH_SSP_FR_CMD << MCH_SSP_FR_TYPE_SHIFT);
  668. hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
  669. hdr->tags = cpu_to_le32(tag);
  670. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  671. /*
  672. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  673. */
  674. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
  675. buf_cmd = buf_tmp = slot->buf;
  676. buf_tmp_dma = slot->buf_dma;
  677. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  678. buf_tmp += MVS_SSP_CMD_SZ;
  679. buf_tmp_dma += MVS_SSP_CMD_SZ;
  680. #if _MV_DUMP
  681. slot->cmd_size = MVS_SSP_CMD_SZ;
  682. #endif
  683. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  684. buf_oaf = buf_tmp;
  685. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  686. buf_tmp += MVS_OAF_SZ;
  687. buf_tmp_dma += MVS_OAF_SZ;
  688. /* region 3: PRD table ********************************************* */
  689. buf_prd = buf_tmp;
  690. if (tei->n_elem)
  691. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  692. else
  693. hdr->prd_tbl = 0;
  694. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  695. buf_tmp += i;
  696. buf_tmp_dma += i;
  697. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  698. slot->response = buf_tmp;
  699. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  700. if (mvi->flags & MVF_FLAG_SOC)
  701. hdr->reserved[0] = 0;
  702. resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
  703. sizeof(struct mvs_err_info) - i;
  704. resp_len = min(resp_len, max_resp_len);
  705. req_len = sizeof(struct ssp_frame_hdr) + 28;
  706. /* request, response lengths */
  707. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  708. /* generate open address frame hdr (first 12 bytes) */
  709. /* initiator, SSP, ftype 1h */
  710. buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
  711. buf_oaf[1] = dev->linkrate & 0xf;
  712. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  713. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  714. /* fill in SSP frame header (Command Table.SSP frame header) */
  715. ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
  716. if (is_tmf)
  717. ssp_hdr->frame_type = SSP_TASK;
  718. else
  719. ssp_hdr->frame_type = SSP_COMMAND;
  720. memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
  721. HASHED_SAS_ADDR_SIZE);
  722. memcpy(ssp_hdr->hashed_src_addr,
  723. dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
  724. ssp_hdr->tag = cpu_to_be16(tag);
  725. /* fill in IU for TASK and Command Frame */
  726. buf_cmd += sizeof(*ssp_hdr);
  727. memcpy(buf_cmd, &task->ssp_task.LUN, 8);
  728. if (ssp_hdr->frame_type != SSP_TASK) {
  729. buf_cmd[9] = fburst | task->ssp_task.task_attr |
  730. (task->ssp_task.task_prio << 3);
  731. memcpy(buf_cmd + 12, &task->ssp_task.cdb, 16);
  732. } else{
  733. buf_cmd[10] = tmf->tmf;
  734. switch (tmf->tmf) {
  735. case TMF_ABORT_TASK:
  736. case TMF_QUERY_TASK:
  737. buf_cmd[12] =
  738. (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
  739. buf_cmd[13] =
  740. tmf->tag_of_task_to_be_managed & 0xff;
  741. break;
  742. default:
  743. break;
  744. }
  745. }
  746. /* fill in PRD (scatter/gather) table, if any */
  747. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  748. return 0;
  749. }
  750. #define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == NO_DEVICE)))
  751. static int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
  752. struct completion *completion,int is_tmf,
  753. struct mvs_tmf_task *tmf)
  754. {
  755. struct domain_device *dev = task->dev;
  756. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  757. struct mvs_info *mvi = mvi_dev->mvi_info;
  758. struct mvs_task_exec_info tei;
  759. struct sas_task *t = task;
  760. struct mvs_slot_info *slot;
  761. u32 tag = 0xdeadbeef, rc, n_elem = 0;
  762. u32 n = num, pass = 0;
  763. unsigned long flags = 0;
  764. if (!dev->port) {
  765. struct task_status_struct *tsm = &t->task_status;
  766. tsm->resp = SAS_TASK_UNDELIVERED;
  767. tsm->stat = SAS_PHY_DOWN;
  768. t->task_done(t);
  769. return 0;
  770. }
  771. spin_lock_irqsave(&mvi->lock, flags);
  772. do {
  773. dev = t->dev;
  774. mvi_dev = dev->lldd_dev;
  775. if (DEV_IS_GONE(mvi_dev)) {
  776. if (mvi_dev)
  777. mv_dprintk("device %d not ready.\n",
  778. mvi_dev->device_id);
  779. else
  780. mv_dprintk("device %016llx not ready.\n",
  781. SAS_ADDR(dev->sas_addr));
  782. rc = SAS_PHY_DOWN;
  783. goto out_done;
  784. }
  785. if (dev->port->id >= mvi->chip->n_phy)
  786. tei.port = &mvi->port[dev->port->id - mvi->chip->n_phy];
  787. else
  788. tei.port = &mvi->port[dev->port->id];
  789. if (!tei.port->port_attached) {
  790. if (sas_protocol_ata(t->task_proto)) {
  791. mv_dprintk("port %d does not"
  792. "attached device.\n", dev->port->id);
  793. rc = SAS_PHY_DOWN;
  794. goto out_done;
  795. } else {
  796. struct task_status_struct *ts = &t->task_status;
  797. ts->resp = SAS_TASK_UNDELIVERED;
  798. ts->stat = SAS_PHY_DOWN;
  799. t->task_done(t);
  800. if (n > 1)
  801. t = list_entry(t->list.next,
  802. struct sas_task, list);
  803. continue;
  804. }
  805. }
  806. if (!sas_protocol_ata(t->task_proto)) {
  807. if (t->num_scatter) {
  808. n_elem = dma_map_sg(mvi->dev,
  809. t->scatter,
  810. t->num_scatter,
  811. t->data_dir);
  812. if (!n_elem) {
  813. rc = -ENOMEM;
  814. goto err_out;
  815. }
  816. }
  817. } else {
  818. n_elem = t->num_scatter;
  819. }
  820. rc = mvs_tag_alloc(mvi, &tag);
  821. if (rc)
  822. goto err_out;
  823. slot = &mvi->slot_info[tag];
  824. t->lldd_task = NULL;
  825. slot->n_elem = n_elem;
  826. slot->slot_tag = tag;
  827. memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
  828. tei.task = t;
  829. tei.hdr = &mvi->slot[tag];
  830. tei.tag = tag;
  831. tei.n_elem = n_elem;
  832. switch (t->task_proto) {
  833. case SAS_PROTOCOL_SMP:
  834. rc = mvs_task_prep_smp(mvi, &tei);
  835. break;
  836. case SAS_PROTOCOL_SSP:
  837. rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
  838. break;
  839. case SAS_PROTOCOL_SATA:
  840. case SAS_PROTOCOL_STP:
  841. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  842. rc = mvs_task_prep_ata(mvi, &tei);
  843. break;
  844. default:
  845. dev_printk(KERN_ERR, mvi->dev,
  846. "unknown sas_task proto: 0x%x\n",
  847. t->task_proto);
  848. rc = -EINVAL;
  849. break;
  850. }
  851. if (rc) {
  852. mv_dprintk("rc is %x\n", rc);
  853. goto err_out_tag;
  854. }
  855. slot->task = t;
  856. slot->port = tei.port;
  857. t->lldd_task = slot;
  858. list_add_tail(&slot->entry, &tei.port->list);
  859. /* TODO: select normal or high priority */
  860. spin_lock(&t->task_state_lock);
  861. t->task_state_flags |= SAS_TASK_AT_INITIATOR;
  862. spin_unlock(&t->task_state_lock);
  863. mvs_hba_memory_dump(mvi, tag, t->task_proto);
  864. mvi_dev->runing_req++;
  865. ++pass;
  866. mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
  867. if (n > 1)
  868. t = list_entry(t->list.next, struct sas_task, list);
  869. } while (--n);
  870. rc = 0;
  871. goto out_done;
  872. err_out_tag:
  873. mvs_tag_free(mvi, tag);
  874. err_out:
  875. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  876. if (!sas_protocol_ata(t->task_proto))
  877. if (n_elem)
  878. dma_unmap_sg(mvi->dev, t->scatter, n_elem,
  879. t->data_dir);
  880. out_done:
  881. if (likely(pass)) {
  882. MVS_CHIP_DISP->start_delivery(mvi,
  883. (mvi->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
  884. }
  885. spin_unlock_irqrestore(&mvi->lock, flags);
  886. return rc;
  887. }
  888. int mvs_queue_command(struct sas_task *task, const int num,
  889. gfp_t gfp_flags)
  890. {
  891. return mvs_task_exec(task, num, gfp_flags, NULL, 0, NULL);
  892. }
  893. static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
  894. {
  895. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  896. mvs_tag_clear(mvi, slot_idx);
  897. }
  898. static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
  899. struct mvs_slot_info *slot, u32 slot_idx)
  900. {
  901. if (!slot->task)
  902. return;
  903. if (!sas_protocol_ata(task->task_proto))
  904. if (slot->n_elem)
  905. dma_unmap_sg(mvi->dev, task->scatter,
  906. slot->n_elem, task->data_dir);
  907. switch (task->task_proto) {
  908. case SAS_PROTOCOL_SMP:
  909. dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
  910. PCI_DMA_FROMDEVICE);
  911. dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
  912. PCI_DMA_TODEVICE);
  913. break;
  914. case SAS_PROTOCOL_SATA:
  915. case SAS_PROTOCOL_STP:
  916. case SAS_PROTOCOL_SSP:
  917. default:
  918. /* do nothing */
  919. break;
  920. }
  921. list_del_init(&slot->entry);
  922. task->lldd_task = NULL;
  923. slot->task = NULL;
  924. slot->port = NULL;
  925. slot->slot_tag = 0xFFFFFFFF;
  926. mvs_slot_free(mvi, slot_idx);
  927. }
  928. static void mvs_update_wideport(struct mvs_info *mvi, int i)
  929. {
  930. struct mvs_phy *phy = &mvi->phy[i];
  931. struct mvs_port *port = phy->port;
  932. int j, no;
  933. for_each_phy(port->wide_port_phymap, j, no) {
  934. if (j & 1) {
  935. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  936. PHYR_WIDE_PORT);
  937. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  938. port->wide_port_phymap);
  939. } else {
  940. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  941. PHYR_WIDE_PORT);
  942. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  943. 0);
  944. }
  945. }
  946. }
  947. static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
  948. {
  949. u32 tmp;
  950. struct mvs_phy *phy = &mvi->phy[i];
  951. struct mvs_port *port = phy->port;
  952. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
  953. if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
  954. if (!port)
  955. phy->phy_attached = 1;
  956. return tmp;
  957. }
  958. if (port) {
  959. if (phy->phy_type & PORT_TYPE_SAS) {
  960. port->wide_port_phymap &= ~(1U << i);
  961. if (!port->wide_port_phymap)
  962. port->port_attached = 0;
  963. mvs_update_wideport(mvi, i);
  964. } else if (phy->phy_type & PORT_TYPE_SATA)
  965. port->port_attached = 0;
  966. phy->port = NULL;
  967. phy->phy_attached = 0;
  968. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  969. }
  970. return 0;
  971. }
  972. static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
  973. {
  974. u32 *s = (u32 *) buf;
  975. if (!s)
  976. return NULL;
  977. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
  978. s[3] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  979. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
  980. s[2] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  981. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
  982. s[1] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  983. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
  984. s[0] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  985. /* Workaround: take some ATAPI devices for ATA */
  986. if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
  987. s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
  988. return s;
  989. }
  990. static u32 mvs_is_sig_fis_received(u32 irq_status)
  991. {
  992. return irq_status & PHYEV_SIG_FIS;
  993. }
  994. void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
  995. {
  996. struct mvs_phy *phy = &mvi->phy[i];
  997. struct sas_identify_frame *id;
  998. id = (struct sas_identify_frame *)phy->frame_rcvd;
  999. if (get_st) {
  1000. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
  1001. phy->phy_status = mvs_is_phy_ready(mvi, i);
  1002. }
  1003. if (phy->phy_status) {
  1004. int oob_done = 0;
  1005. struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
  1006. oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
  1007. MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
  1008. if (phy->phy_type & PORT_TYPE_SATA) {
  1009. phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
  1010. if (mvs_is_sig_fis_received(phy->irq_status)) {
  1011. phy->phy_attached = 1;
  1012. phy->att_dev_sas_addr =
  1013. i + mvi->id * mvi->chip->n_phy;
  1014. if (oob_done)
  1015. sas_phy->oob_mode = SATA_OOB_MODE;
  1016. phy->frame_rcvd_size =
  1017. sizeof(struct dev_to_host_fis);
  1018. mvs_get_d2h_reg(mvi, i, id);
  1019. } else {
  1020. u32 tmp;
  1021. dev_printk(KERN_DEBUG, mvi->dev,
  1022. "Phy%d : No sig fis\n", i);
  1023. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
  1024. MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
  1025. tmp | PHYEV_SIG_FIS);
  1026. phy->phy_attached = 0;
  1027. phy->phy_type &= ~PORT_TYPE_SATA;
  1028. MVS_CHIP_DISP->phy_reset(mvi, i, 0);
  1029. goto out_done;
  1030. }
  1031. } else if (phy->phy_type & PORT_TYPE_SAS
  1032. || phy->att_dev_info & PORT_SSP_INIT_MASK) {
  1033. phy->phy_attached = 1;
  1034. phy->identify.device_type =
  1035. phy->att_dev_info & PORT_DEV_TYPE_MASK;
  1036. if (phy->identify.device_type == SAS_END_DEV)
  1037. phy->identify.target_port_protocols =
  1038. SAS_PROTOCOL_SSP;
  1039. else if (phy->identify.device_type != NO_DEVICE)
  1040. phy->identify.target_port_protocols =
  1041. SAS_PROTOCOL_SMP;
  1042. if (oob_done)
  1043. sas_phy->oob_mode = SAS_OOB_MODE;
  1044. phy->frame_rcvd_size =
  1045. sizeof(struct sas_identify_frame);
  1046. }
  1047. memcpy(sas_phy->attached_sas_addr,
  1048. &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
  1049. if (MVS_CHIP_DISP->phy_work_around)
  1050. MVS_CHIP_DISP->phy_work_around(mvi, i);
  1051. }
  1052. mv_dprintk("port %d attach dev info is %x\n",
  1053. i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
  1054. mv_dprintk("port %d attach sas addr is %llx\n",
  1055. i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
  1056. out_done:
  1057. if (get_st)
  1058. MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
  1059. }
  1060. static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
  1061. {
  1062. struct sas_ha_struct *sas_ha = sas_phy->ha;
  1063. struct mvs_info *mvi = NULL; int i = 0, hi;
  1064. struct mvs_phy *phy = sas_phy->lldd_phy;
  1065. struct asd_sas_port *sas_port = sas_phy->port;
  1066. struct mvs_port *port;
  1067. unsigned long flags = 0;
  1068. if (!sas_port)
  1069. return;
  1070. while (sas_ha->sas_phy[i]) {
  1071. if (sas_ha->sas_phy[i] == sas_phy)
  1072. break;
  1073. i++;
  1074. }
  1075. hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
  1076. mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
  1077. if (sas_port->id >= mvi->chip->n_phy)
  1078. port = &mvi->port[sas_port->id - mvi->chip->n_phy];
  1079. else
  1080. port = &mvi->port[sas_port->id];
  1081. if (lock)
  1082. spin_lock_irqsave(&mvi->lock, flags);
  1083. port->port_attached = 1;
  1084. phy->port = port;
  1085. if (phy->phy_type & PORT_TYPE_SAS) {
  1086. port->wide_port_phymap = sas_port->phy_mask;
  1087. mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
  1088. mvs_update_wideport(mvi, sas_phy->id);
  1089. }
  1090. if (lock)
  1091. spin_unlock_irqrestore(&mvi->lock, flags);
  1092. }
  1093. static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
  1094. {
  1095. /*Nothing*/
  1096. }
  1097. void mvs_port_formed(struct asd_sas_phy *sas_phy)
  1098. {
  1099. mvs_port_notify_formed(sas_phy, 1);
  1100. }
  1101. void mvs_port_deformed(struct asd_sas_phy *sas_phy)
  1102. {
  1103. mvs_port_notify_deformed(sas_phy, 1);
  1104. }
  1105. struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
  1106. {
  1107. u32 dev;
  1108. for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
  1109. if (mvi->devices[dev].dev_type == NO_DEVICE) {
  1110. mvi->devices[dev].device_id = dev;
  1111. return &mvi->devices[dev];
  1112. }
  1113. }
  1114. if (dev == MVS_MAX_DEVICES)
  1115. mv_printk("max support %d devices, ignore ..\n",
  1116. MVS_MAX_DEVICES);
  1117. return NULL;
  1118. }
  1119. void mvs_free_dev(struct mvs_device *mvi_dev)
  1120. {
  1121. u32 id = mvi_dev->device_id;
  1122. memset(mvi_dev, 0, sizeof(*mvi_dev));
  1123. mvi_dev->device_id = id;
  1124. mvi_dev->dev_type = NO_DEVICE;
  1125. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1126. mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
  1127. }
  1128. int mvs_dev_found_notify(struct domain_device *dev, int lock)
  1129. {
  1130. unsigned long flags = 0;
  1131. int res = 0;
  1132. struct mvs_info *mvi = NULL;
  1133. struct domain_device *parent_dev = dev->parent;
  1134. struct mvs_device *mvi_device;
  1135. mvi = mvs_find_dev_mvi(dev);
  1136. if (lock)
  1137. spin_lock_irqsave(&mvi->lock, flags);
  1138. mvi_device = mvs_alloc_dev(mvi);
  1139. if (!mvi_device) {
  1140. res = -1;
  1141. goto found_out;
  1142. }
  1143. dev->lldd_dev = mvi_device;
  1144. mvi_device->dev_type = dev->dev_type;
  1145. mvi_device->mvi_info = mvi;
  1146. if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
  1147. int phy_id;
  1148. u8 phy_num = parent_dev->ex_dev.num_phys;
  1149. struct ex_phy *phy;
  1150. for (phy_id = 0; phy_id < phy_num; phy_id++) {
  1151. phy = &parent_dev->ex_dev.ex_phy[phy_id];
  1152. if (SAS_ADDR(phy->attached_sas_addr) ==
  1153. SAS_ADDR(dev->sas_addr)) {
  1154. mvi_device->attached_phy = phy_id;
  1155. break;
  1156. }
  1157. }
  1158. if (phy_id == phy_num) {
  1159. mv_printk("Error: no attached dev:%016llx"
  1160. "at ex:%016llx.\n",
  1161. SAS_ADDR(dev->sas_addr),
  1162. SAS_ADDR(parent_dev->sas_addr));
  1163. res = -1;
  1164. }
  1165. }
  1166. found_out:
  1167. if (lock)
  1168. spin_unlock_irqrestore(&mvi->lock, flags);
  1169. return res;
  1170. }
  1171. int mvs_dev_found(struct domain_device *dev)
  1172. {
  1173. return mvs_dev_found_notify(dev, 1);
  1174. }
  1175. void mvs_dev_gone_notify(struct domain_device *dev, int lock)
  1176. {
  1177. unsigned long flags = 0;
  1178. struct mvs_device *mvi_dev = dev->lldd_dev;
  1179. struct mvs_info *mvi = mvi_dev->mvi_info;
  1180. if (lock)
  1181. spin_lock_irqsave(&mvi->lock, flags);
  1182. if (mvi_dev) {
  1183. mv_dprintk("found dev[%d:%x] is gone.\n",
  1184. mvi_dev->device_id, mvi_dev->dev_type);
  1185. mvs_free_reg_set(mvi, mvi_dev);
  1186. mvs_free_dev(mvi_dev);
  1187. } else {
  1188. mv_dprintk("found dev has gone.\n");
  1189. }
  1190. dev->lldd_dev = NULL;
  1191. if (lock)
  1192. spin_unlock_irqrestore(&mvi->lock, flags);
  1193. }
  1194. void mvs_dev_gone(struct domain_device *dev)
  1195. {
  1196. mvs_dev_gone_notify(dev, 1);
  1197. }
  1198. static struct sas_task *mvs_alloc_task(void)
  1199. {
  1200. struct sas_task *task = kzalloc(sizeof(struct sas_task), GFP_KERNEL);
  1201. if (task) {
  1202. INIT_LIST_HEAD(&task->list);
  1203. spin_lock_init(&task->task_state_lock);
  1204. task->task_state_flags = SAS_TASK_STATE_PENDING;
  1205. init_timer(&task->timer);
  1206. init_completion(&task->completion);
  1207. }
  1208. return task;
  1209. }
  1210. static void mvs_free_task(struct sas_task *task)
  1211. {
  1212. if (task) {
  1213. BUG_ON(!list_empty(&task->list));
  1214. kfree(task);
  1215. }
  1216. }
  1217. static void mvs_task_done(struct sas_task *task)
  1218. {
  1219. if (!del_timer(&task->timer))
  1220. return;
  1221. complete(&task->completion);
  1222. }
  1223. static void mvs_tmf_timedout(unsigned long data)
  1224. {
  1225. struct sas_task *task = (struct sas_task *)data;
  1226. task->task_state_flags |= SAS_TASK_STATE_ABORTED;
  1227. complete(&task->completion);
  1228. }
  1229. /* XXX */
  1230. #define MVS_TASK_TIMEOUT 20
  1231. static int mvs_exec_internal_tmf_task(struct domain_device *dev,
  1232. void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
  1233. {
  1234. int res, retry;
  1235. struct sas_task *task = NULL;
  1236. for (retry = 0; retry < 3; retry++) {
  1237. task = mvs_alloc_task();
  1238. if (!task)
  1239. return -ENOMEM;
  1240. task->dev = dev;
  1241. task->task_proto = dev->tproto;
  1242. memcpy(&task->ssp_task, parameter, para_len);
  1243. task->task_done = mvs_task_done;
  1244. task->timer.data = (unsigned long) task;
  1245. task->timer.function = mvs_tmf_timedout;
  1246. task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
  1247. add_timer(&task->timer);
  1248. res = mvs_task_exec(task, 1, GFP_KERNEL, NULL, 1, tmf);
  1249. if (res) {
  1250. del_timer(&task->timer);
  1251. mv_printk("executing internel task failed:%d\n", res);
  1252. goto ex_err;
  1253. }
  1254. wait_for_completion(&task->completion);
  1255. res = -TMF_RESP_FUNC_FAILED;
  1256. /* Even TMF timed out, return direct. */
  1257. if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
  1258. if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
  1259. mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
  1260. goto ex_err;
  1261. }
  1262. }
  1263. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1264. task->task_status.stat == SAM_GOOD) {
  1265. res = TMF_RESP_FUNC_COMPLETE;
  1266. break;
  1267. }
  1268. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1269. task->task_status.stat == SAS_DATA_UNDERRUN) {
  1270. /* no error, but return the number of bytes of
  1271. * underrun */
  1272. res = task->task_status.residual;
  1273. break;
  1274. }
  1275. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1276. task->task_status.stat == SAS_DATA_OVERRUN) {
  1277. mv_dprintk("blocked task error.\n");
  1278. res = -EMSGSIZE;
  1279. break;
  1280. } else {
  1281. mv_dprintk(" task to dev %016llx response: 0x%x "
  1282. "status 0x%x\n",
  1283. SAS_ADDR(dev->sas_addr),
  1284. task->task_status.resp,
  1285. task->task_status.stat);
  1286. mvs_free_task(task);
  1287. task = NULL;
  1288. }
  1289. }
  1290. ex_err:
  1291. BUG_ON(retry == 3 && task != NULL);
  1292. if (task != NULL)
  1293. mvs_free_task(task);
  1294. return res;
  1295. }
  1296. static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
  1297. u8 *lun, struct mvs_tmf_task *tmf)
  1298. {
  1299. struct sas_ssp_task ssp_task;
  1300. DECLARE_COMPLETION_ONSTACK(completion);
  1301. if (!(dev->tproto & SAS_PROTOCOL_SSP))
  1302. return TMF_RESP_FUNC_ESUPP;
  1303. strncpy((u8 *)&ssp_task.LUN, lun, 8);
  1304. return mvs_exec_internal_tmf_task(dev, &ssp_task,
  1305. sizeof(ssp_task), tmf);
  1306. }
  1307. /* Standard mandates link reset for ATA (type 0)
  1308. and hard reset for SSP (type 1) , only for RECOVERY */
  1309. static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
  1310. {
  1311. int rc;
  1312. struct sas_phy *phy = sas_find_local_phy(dev);
  1313. int reset_type = (dev->dev_type == SATA_DEV ||
  1314. (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
  1315. rc = sas_phy_reset(phy, reset_type);
  1316. msleep(2000);
  1317. return rc;
  1318. }
  1319. /* mandatory SAM-3 */
  1320. int mvs_lu_reset(struct domain_device *dev, u8 *lun)
  1321. {
  1322. unsigned long flags;
  1323. int i, phyno[WIDE_PORT_MAX_PHY], num , rc = TMF_RESP_FUNC_FAILED;
  1324. struct mvs_tmf_task tmf_task;
  1325. struct mvs_device * mvi_dev = dev->lldd_dev;
  1326. struct mvs_info *mvi = mvi_dev->mvi_info;
  1327. tmf_task.tmf = TMF_LU_RESET;
  1328. mvi_dev->dev_status = MVS_DEV_EH;
  1329. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1330. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1331. num = mvs_find_dev_phyno(dev, phyno);
  1332. spin_lock_irqsave(&mvi->lock, flags);
  1333. for (i = 0; i < num; i++)
  1334. mvs_release_task(mvi, phyno[i], dev);
  1335. spin_unlock_irqrestore(&mvi->lock, flags);
  1336. }
  1337. /* If failed, fall-through I_T_Nexus reset */
  1338. mv_printk("%s for device[%x]:rc= %d\n", __func__,
  1339. mvi_dev->device_id, rc);
  1340. return rc;
  1341. }
  1342. int mvs_I_T_nexus_reset(struct domain_device *dev)
  1343. {
  1344. unsigned long flags;
  1345. int i, phyno[WIDE_PORT_MAX_PHY], num , rc = TMF_RESP_FUNC_FAILED;
  1346. struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1347. struct mvs_info *mvi = mvi_dev->mvi_info;
  1348. if (mvi_dev->dev_status != MVS_DEV_EH)
  1349. return TMF_RESP_FUNC_COMPLETE;
  1350. rc = mvs_debug_I_T_nexus_reset(dev);
  1351. mv_printk("%s for device[%x]:rc= %d\n",
  1352. __func__, mvi_dev->device_id, rc);
  1353. /* housekeeper */
  1354. num = mvs_find_dev_phyno(dev, phyno);
  1355. spin_lock_irqsave(&mvi->lock, flags);
  1356. for (i = 0; i < num; i++)
  1357. mvs_release_task(mvi, phyno[i], dev);
  1358. spin_unlock_irqrestore(&mvi->lock, flags);
  1359. return rc;
  1360. }
  1361. /* optional SAM-3 */
  1362. int mvs_query_task(struct sas_task *task)
  1363. {
  1364. u32 tag;
  1365. struct scsi_lun lun;
  1366. struct mvs_tmf_task tmf_task;
  1367. int rc = TMF_RESP_FUNC_FAILED;
  1368. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1369. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1370. struct domain_device *dev = task->dev;
  1371. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1372. struct mvs_info *mvi = mvi_dev->mvi_info;
  1373. int_to_scsilun(cmnd->device->lun, &lun);
  1374. rc = mvs_find_tag(mvi, task, &tag);
  1375. if (rc == 0) {
  1376. rc = TMF_RESP_FUNC_FAILED;
  1377. return rc;
  1378. }
  1379. tmf_task.tmf = TMF_QUERY_TASK;
  1380. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1381. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1382. switch (rc) {
  1383. /* The task is still in Lun, release it then */
  1384. case TMF_RESP_FUNC_SUCC:
  1385. /* The task is not in Lun or failed, reset the phy */
  1386. case TMF_RESP_FUNC_FAILED:
  1387. case TMF_RESP_FUNC_COMPLETE:
  1388. break;
  1389. }
  1390. }
  1391. mv_printk("%s:rc= %d\n", __func__, rc);
  1392. return rc;
  1393. }
  1394. /* mandatory SAM-3, still need free task/slot info */
  1395. int mvs_abort_task(struct sas_task *task)
  1396. {
  1397. struct scsi_lun lun;
  1398. struct mvs_tmf_task tmf_task;
  1399. struct domain_device *dev = task->dev;
  1400. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1401. struct mvs_info *mvi = mvi_dev->mvi_info;
  1402. int rc = TMF_RESP_FUNC_FAILED;
  1403. unsigned long flags;
  1404. u32 tag;
  1405. if (mvi->exp_req)
  1406. mvi->exp_req--;
  1407. spin_lock_irqsave(&task->task_state_lock, flags);
  1408. if (task->task_state_flags & SAS_TASK_STATE_DONE) {
  1409. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1410. rc = TMF_RESP_FUNC_COMPLETE;
  1411. goto out;
  1412. }
  1413. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1414. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1415. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1416. int_to_scsilun(cmnd->device->lun, &lun);
  1417. rc = mvs_find_tag(mvi, task, &tag);
  1418. if (rc == 0) {
  1419. mv_printk("No such tag in %s\n", __func__);
  1420. rc = TMF_RESP_FUNC_FAILED;
  1421. return rc;
  1422. }
  1423. tmf_task.tmf = TMF_ABORT_TASK;
  1424. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1425. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1426. /* if successful, clear the task and callback forwards.*/
  1427. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1428. u32 slot_no;
  1429. struct mvs_slot_info *slot;
  1430. if (task->lldd_task) {
  1431. slot = task->lldd_task;
  1432. slot_no = (u32) (slot - mvi->slot_info);
  1433. mvs_slot_complete(mvi, slot_no, 1);
  1434. }
  1435. }
  1436. } else if (task->task_proto & SAS_PROTOCOL_SATA ||
  1437. task->task_proto & SAS_PROTOCOL_STP) {
  1438. /* to do free register_set */
  1439. } else {
  1440. /* SMP */
  1441. }
  1442. out:
  1443. if (rc != TMF_RESP_FUNC_COMPLETE)
  1444. mv_printk("%s:rc= %d\n", __func__, rc);
  1445. return rc;
  1446. }
  1447. int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
  1448. {
  1449. int rc = TMF_RESP_FUNC_FAILED;
  1450. struct mvs_tmf_task tmf_task;
  1451. tmf_task.tmf = TMF_ABORT_TASK_SET;
  1452. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1453. return rc;
  1454. }
  1455. int mvs_clear_aca(struct domain_device *dev, u8 *lun)
  1456. {
  1457. int rc = TMF_RESP_FUNC_FAILED;
  1458. struct mvs_tmf_task tmf_task;
  1459. tmf_task.tmf = TMF_CLEAR_ACA;
  1460. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1461. return rc;
  1462. }
  1463. int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
  1464. {
  1465. int rc = TMF_RESP_FUNC_FAILED;
  1466. struct mvs_tmf_task tmf_task;
  1467. tmf_task.tmf = TMF_CLEAR_TASK_SET;
  1468. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1469. return rc;
  1470. }
  1471. static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
  1472. u32 slot_idx, int err)
  1473. {
  1474. struct mvs_device *mvi_dev = task->dev->lldd_dev;
  1475. struct task_status_struct *tstat = &task->task_status;
  1476. struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
  1477. int stat = SAM_GOOD;
  1478. resp->frame_len = sizeof(struct dev_to_host_fis);
  1479. memcpy(&resp->ending_fis[0],
  1480. SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
  1481. sizeof(struct dev_to_host_fis));
  1482. tstat->buf_valid_size = sizeof(*resp);
  1483. if (unlikely(err))
  1484. stat = SAS_PROTO_RESPONSE;
  1485. return stat;
  1486. }
  1487. static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
  1488. u32 slot_idx)
  1489. {
  1490. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1491. int stat;
  1492. u32 err_dw0 = le32_to_cpu(*(u32 *) (slot->response));
  1493. u32 tfs = 0;
  1494. enum mvs_port_type type = PORT_TYPE_SAS;
  1495. if (err_dw0 & CMD_ISS_STPD)
  1496. MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
  1497. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1498. stat = SAM_CHECK_COND;
  1499. switch (task->task_proto) {
  1500. case SAS_PROTOCOL_SSP:
  1501. stat = SAS_ABORTED_TASK;
  1502. break;
  1503. case SAS_PROTOCOL_SMP:
  1504. stat = SAM_CHECK_COND;
  1505. break;
  1506. case SAS_PROTOCOL_SATA:
  1507. case SAS_PROTOCOL_STP:
  1508. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1509. {
  1510. if (err_dw0 == 0x80400002)
  1511. mv_printk("find reserved error, why?\n");
  1512. task->ata_task.use_ncq = 0;
  1513. stat = SAS_PROTO_RESPONSE;
  1514. mvs_sata_done(mvi, task, slot_idx, 1);
  1515. }
  1516. break;
  1517. default:
  1518. break;
  1519. }
  1520. return stat;
  1521. }
  1522. int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
  1523. {
  1524. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  1525. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1526. struct sas_task *task = slot->task;
  1527. struct mvs_device *mvi_dev = NULL;
  1528. struct task_status_struct *tstat;
  1529. bool aborted;
  1530. void *to;
  1531. enum exec_status sts;
  1532. if (mvi->exp_req)
  1533. mvi->exp_req--;
  1534. if (unlikely(!task || !task->lldd_task))
  1535. return -1;
  1536. tstat = &task->task_status;
  1537. mvi_dev = task->dev->lldd_dev;
  1538. mvs_hba_cq_dump(mvi);
  1539. spin_lock(&task->task_state_lock);
  1540. task->task_state_flags &=
  1541. ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
  1542. task->task_state_flags |= SAS_TASK_STATE_DONE;
  1543. /* race condition*/
  1544. aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
  1545. spin_unlock(&task->task_state_lock);
  1546. memset(tstat, 0, sizeof(*tstat));
  1547. tstat->resp = SAS_TASK_COMPLETE;
  1548. if (unlikely(aborted)) {
  1549. tstat->stat = SAS_ABORTED_TASK;
  1550. if (mvi_dev)
  1551. mvi_dev->runing_req--;
  1552. if (sas_protocol_ata(task->task_proto))
  1553. mvs_free_reg_set(mvi, mvi_dev);
  1554. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1555. return -1;
  1556. }
  1557. if (unlikely(!mvi_dev || !slot->port->port_attached || flags)) {
  1558. mv_dprintk("port has not device.\n");
  1559. tstat->stat = SAS_PHY_DOWN;
  1560. goto out;
  1561. }
  1562. /*
  1563. if (unlikely((rx_desc & RXQ_ERR) || (*(u64 *) slot->response))) {
  1564. mv_dprintk("Find device[%016llx] RXQ_ERR %X,
  1565. err info:%016llx\n",
  1566. SAS_ADDR(task->dev->sas_addr),
  1567. rx_desc, (u64)(*(u64 *) slot->response));
  1568. }
  1569. */
  1570. /* error info record present */
  1571. if (unlikely((rx_desc & RXQ_ERR) && (*(u64 *) slot->response))) {
  1572. tstat->stat = mvs_slot_err(mvi, task, slot_idx);
  1573. goto out;
  1574. }
  1575. switch (task->task_proto) {
  1576. case SAS_PROTOCOL_SSP:
  1577. /* hw says status == 0, datapres == 0 */
  1578. if (rx_desc & RXQ_GOOD) {
  1579. tstat->stat = SAM_GOOD;
  1580. tstat->resp = SAS_TASK_COMPLETE;
  1581. }
  1582. /* response frame present */
  1583. else if (rx_desc & RXQ_RSP) {
  1584. struct ssp_response_iu *iu = slot->response +
  1585. sizeof(struct mvs_err_info);
  1586. sas_ssp_task_response(mvi->dev, task, iu);
  1587. } else
  1588. tstat->stat = SAM_CHECK_COND;
  1589. break;
  1590. case SAS_PROTOCOL_SMP: {
  1591. struct scatterlist *sg_resp = &task->smp_task.smp_resp;
  1592. tstat->stat = SAM_GOOD;
  1593. to = kmap_atomic(sg_page(sg_resp), KM_IRQ0);
  1594. memcpy(to + sg_resp->offset,
  1595. slot->response + sizeof(struct mvs_err_info),
  1596. sg_dma_len(sg_resp));
  1597. kunmap_atomic(to, KM_IRQ0);
  1598. break;
  1599. }
  1600. case SAS_PROTOCOL_SATA:
  1601. case SAS_PROTOCOL_STP:
  1602. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
  1603. tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
  1604. break;
  1605. }
  1606. default:
  1607. tstat->stat = SAM_CHECK_COND;
  1608. break;
  1609. }
  1610. out:
  1611. if (mvi_dev) {
  1612. mvi_dev->runing_req--;
  1613. if (sas_protocol_ata(task->task_proto))
  1614. mvs_free_reg_set(mvi, mvi_dev);
  1615. }
  1616. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1617. sts = tstat->stat;
  1618. spin_unlock(&mvi->lock);
  1619. if (task->task_done)
  1620. task->task_done(task);
  1621. else
  1622. mv_dprintk("why has not task_done.\n");
  1623. spin_lock(&mvi->lock);
  1624. return sts;
  1625. }
  1626. void mvs_release_task(struct mvs_info *mvi,
  1627. int phy_no, struct domain_device *dev)
  1628. {
  1629. int i = 0; u32 slot_idx;
  1630. struct mvs_phy *phy;
  1631. struct mvs_port *port;
  1632. struct mvs_slot_info *slot, *slot2;
  1633. phy = &mvi->phy[phy_no];
  1634. port = phy->port;
  1635. if (!port)
  1636. return;
  1637. list_for_each_entry_safe(slot, slot2, &port->list, entry) {
  1638. struct sas_task *task;
  1639. slot_idx = (u32) (slot - mvi->slot_info);
  1640. task = slot->task;
  1641. if (dev && task->dev != dev)
  1642. continue;
  1643. mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
  1644. slot_idx, slot->slot_tag, task);
  1645. if (task->task_proto & SAS_PROTOCOL_SSP) {
  1646. mv_printk("attached with SSP task CDB[");
  1647. for (i = 0; i < 16; i++)
  1648. mv_printk(" %02x", task->ssp_task.cdb[i]);
  1649. mv_printk(" ]\n");
  1650. }
  1651. mvs_slot_complete(mvi, slot_idx, 1);
  1652. }
  1653. }
  1654. static void mvs_phy_disconnected(struct mvs_phy *phy)
  1655. {
  1656. phy->phy_attached = 0;
  1657. phy->att_dev_info = 0;
  1658. phy->att_dev_sas_addr = 0;
  1659. }
  1660. static void mvs_work_queue(struct work_struct *work)
  1661. {
  1662. struct delayed_work *dw = container_of(work, struct delayed_work, work);
  1663. struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
  1664. struct mvs_info *mvi = mwq->mvi;
  1665. unsigned long flags;
  1666. spin_lock_irqsave(&mvi->lock, flags);
  1667. if (mwq->handler & PHY_PLUG_EVENT) {
  1668. u32 phy_no = (unsigned long) mwq->data;
  1669. struct sas_ha_struct *sas_ha = mvi->sas;
  1670. struct mvs_phy *phy = &mvi->phy[phy_no];
  1671. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1672. if (phy->phy_event & PHY_PLUG_OUT) {
  1673. u32 tmp;
  1674. struct sas_identify_frame *id;
  1675. id = (struct sas_identify_frame *)phy->frame_rcvd;
  1676. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
  1677. phy->phy_event &= ~PHY_PLUG_OUT;
  1678. if (!(tmp & PHY_READY_MASK)) {
  1679. sas_phy_disconnected(sas_phy);
  1680. mvs_phy_disconnected(phy);
  1681. sas_ha->notify_phy_event(sas_phy,
  1682. PHYE_LOSS_OF_SIGNAL);
  1683. mv_dprintk("phy%d Removed Device\n", phy_no);
  1684. } else {
  1685. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1686. mvs_update_phyinfo(mvi, phy_no, 1);
  1687. mvs_bytes_dmaed(mvi, phy_no);
  1688. mvs_port_notify_formed(sas_phy, 0);
  1689. mv_dprintk("phy%d Attached Device\n", phy_no);
  1690. }
  1691. }
  1692. }
  1693. list_del(&mwq->entry);
  1694. spin_unlock_irqrestore(&mvi->lock, flags);
  1695. kfree(mwq);
  1696. }
  1697. static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
  1698. {
  1699. struct mvs_wq *mwq;
  1700. int ret = 0;
  1701. mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
  1702. if (mwq) {
  1703. mwq->mvi = mvi;
  1704. mwq->data = data;
  1705. mwq->handler = handler;
  1706. MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
  1707. list_add_tail(&mwq->entry, &mvi->wq_list);
  1708. schedule_delayed_work(&mwq->work_q, HZ * 2);
  1709. } else
  1710. ret = -ENOMEM;
  1711. return ret;
  1712. }
  1713. static void mvs_sig_time_out(unsigned long tphy)
  1714. {
  1715. struct mvs_phy *phy = (struct mvs_phy *)tphy;
  1716. struct mvs_info *mvi = phy->mvi;
  1717. u8 phy_no;
  1718. for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
  1719. if (&mvi->phy[phy_no] == phy) {
  1720. mv_dprintk("Get signature time out, reset phy %d\n",
  1721. phy_no+mvi->id*mvi->chip->n_phy);
  1722. MVS_CHIP_DISP->phy_reset(mvi, phy_no, 1);
  1723. }
  1724. }
  1725. }
  1726. static void mvs_sig_remove_timer(struct mvs_phy *phy)
  1727. {
  1728. if (phy->timer.function)
  1729. del_timer(&phy->timer);
  1730. phy->timer.function = NULL;
  1731. }
  1732. void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
  1733. {
  1734. u32 tmp;
  1735. struct sas_ha_struct *sas_ha = mvi->sas;
  1736. struct mvs_phy *phy = &mvi->phy[phy_no];
  1737. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1738. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
  1739. mv_dprintk("port %d ctrl sts=0x%X.\n", phy_no+mvi->id*mvi->chip->n_phy,
  1740. MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
  1741. mv_dprintk("Port %d irq sts = 0x%X\n", phy_no+mvi->id*mvi->chip->n_phy,
  1742. phy->irq_status);
  1743. /*
  1744. * events is port event now ,
  1745. * we need check the interrupt status which belongs to per port.
  1746. */
  1747. if (phy->irq_status & PHYEV_DCDR_ERR)
  1748. mv_dprintk("port %d STP decoding error.\n",
  1749. phy_no+mvi->id*mvi->chip->n_phy);
  1750. if (phy->irq_status & PHYEV_POOF) {
  1751. if (!(phy->phy_event & PHY_PLUG_OUT)) {
  1752. int dev_sata = phy->phy_type & PORT_TYPE_SATA;
  1753. int ready;
  1754. mvs_release_task(mvi, phy_no, NULL);
  1755. phy->phy_event |= PHY_PLUG_OUT;
  1756. mvs_handle_event(mvi,
  1757. (void *)(unsigned long)phy_no,
  1758. PHY_PLUG_EVENT);
  1759. ready = mvs_is_phy_ready(mvi, phy_no);
  1760. if (!ready)
  1761. mv_dprintk("phy%d Unplug Notice\n",
  1762. phy_no +
  1763. mvi->id * mvi->chip->n_phy);
  1764. if (ready || dev_sata) {
  1765. if (MVS_CHIP_DISP->stp_reset)
  1766. MVS_CHIP_DISP->stp_reset(mvi,
  1767. phy_no);
  1768. else
  1769. MVS_CHIP_DISP->phy_reset(mvi,
  1770. phy_no, 0);
  1771. return;
  1772. }
  1773. }
  1774. }
  1775. if (phy->irq_status & PHYEV_COMWAKE) {
  1776. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
  1777. MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
  1778. tmp | PHYEV_SIG_FIS);
  1779. if (phy->timer.function == NULL) {
  1780. phy->timer.data = (unsigned long)phy;
  1781. phy->timer.function = mvs_sig_time_out;
  1782. phy->timer.expires = jiffies + 10*HZ;
  1783. add_timer(&phy->timer);
  1784. }
  1785. }
  1786. if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
  1787. phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
  1788. mvs_sig_remove_timer(phy);
  1789. mv_dprintk("notify plug in on phy[%d]\n", phy_no);
  1790. if (phy->phy_status) {
  1791. mdelay(10);
  1792. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1793. if (phy->phy_type & PORT_TYPE_SATA) {
  1794. tmp = MVS_CHIP_DISP->read_port_irq_mask(
  1795. mvi, phy_no);
  1796. tmp &= ~PHYEV_SIG_FIS;
  1797. MVS_CHIP_DISP->write_port_irq_mask(mvi,
  1798. phy_no, tmp);
  1799. }
  1800. mvs_update_phyinfo(mvi, phy_no, 0);
  1801. mvs_bytes_dmaed(mvi, phy_no);
  1802. /* whether driver is going to handle hot plug */
  1803. if (phy->phy_event & PHY_PLUG_OUT) {
  1804. mvs_port_notify_formed(sas_phy, 0);
  1805. phy->phy_event &= ~PHY_PLUG_OUT;
  1806. }
  1807. } else {
  1808. mv_dprintk("plugin interrupt but phy%d is gone\n",
  1809. phy_no + mvi->id*mvi->chip->n_phy);
  1810. }
  1811. } else if (phy->irq_status & PHYEV_BROAD_CH) {
  1812. mv_dprintk("port %d broadcast change.\n",
  1813. phy_no + mvi->id*mvi->chip->n_phy);
  1814. /* exception for Samsung disk drive*/
  1815. mdelay(1000);
  1816. sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  1817. }
  1818. MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
  1819. }
  1820. int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
  1821. {
  1822. u32 rx_prod_idx, rx_desc;
  1823. bool attn = false;
  1824. /* the first dword in the RX ring is special: it contains
  1825. * a mirror of the hardware's RX producer index, so that
  1826. * we don't have to stall the CPU reading that register.
  1827. * The actual RX ring is offset by one dword, due to this.
  1828. */
  1829. rx_prod_idx = mvi->rx_cons;
  1830. mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
  1831. if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
  1832. return 0;
  1833. /* The CMPL_Q may come late, read from register and try again
  1834. * note: if coalescing is enabled,
  1835. * it will need to read from register every time for sure
  1836. */
  1837. if (unlikely(mvi->rx_cons == rx_prod_idx))
  1838. mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
  1839. if (mvi->rx_cons == rx_prod_idx)
  1840. return 0;
  1841. while (mvi->rx_cons != rx_prod_idx) {
  1842. /* increment our internal RX consumer pointer */
  1843. rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
  1844. rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
  1845. if (likely(rx_desc & RXQ_DONE))
  1846. mvs_slot_complete(mvi, rx_desc, 0);
  1847. if (rx_desc & RXQ_ATTN) {
  1848. attn = true;
  1849. } else if (rx_desc & RXQ_ERR) {
  1850. if (!(rx_desc & RXQ_DONE))
  1851. mvs_slot_complete(mvi, rx_desc, 0);
  1852. } else if (rx_desc & RXQ_SLOT_RESET) {
  1853. mvs_slot_free(mvi, rx_desc);
  1854. }
  1855. }
  1856. if (attn && self_clear)
  1857. MVS_CHIP_DISP->int_full(mvi);
  1858. return 0;
  1859. }