bfa_intr.c 4.7 KB

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  1. /*
  2. * Copyright (c) 2005-2009 Brocade Communications Systems, Inc.
  3. * All rights reserved
  4. * www.brocade.com
  5. *
  6. * Linux driver for Brocade Fibre Channel Host Bus Adapter.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License (GPL) Version 2 as
  10. * published by the Free Software Foundation
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. */
  17. #include <bfa.h>
  18. #include <bfi/bfi_cbreg.h>
  19. #include <bfa_port_priv.h>
  20. #include <bfa_intr_priv.h>
  21. #include <cs/bfa_debug.h>
  22. BFA_TRC_FILE(HAL, INTR);
  23. static void
  24. bfa_msix_errint(struct bfa_s *bfa, u32 intr)
  25. {
  26. bfa_ioc_error_isr(&bfa->ioc);
  27. }
  28. static void
  29. bfa_msix_lpu(struct bfa_s *bfa)
  30. {
  31. bfa_ioc_mbox_isr(&bfa->ioc);
  32. }
  33. void
  34. bfa_msix_all(struct bfa_s *bfa, int vec)
  35. {
  36. bfa_intx(bfa);
  37. }
  38. /**
  39. * hal_intr_api
  40. */
  41. bfa_boolean_t
  42. bfa_intx(struct bfa_s *bfa)
  43. {
  44. u32 intr, qintr;
  45. int queue;
  46. intr = bfa_reg_read(bfa->iocfc.bfa_regs.intr_status);
  47. if (!intr)
  48. return BFA_FALSE;
  49. /**
  50. * RME completion queue interrupt
  51. */
  52. qintr = intr & __HFN_INT_RME_MASK;
  53. bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, qintr);
  54. for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) {
  55. if (intr & (__HFN_INT_RME_Q0 << queue))
  56. bfa_msix_rspq(bfa, queue & (BFI_IOC_MAX_CQS - 1));
  57. }
  58. intr &= ~qintr;
  59. if (!intr)
  60. return BFA_TRUE;
  61. /**
  62. * CPE completion queue interrupt
  63. */
  64. qintr = intr & __HFN_INT_CPE_MASK;
  65. bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, qintr);
  66. for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) {
  67. if (intr & (__HFN_INT_CPE_Q0 << queue))
  68. bfa_msix_reqq(bfa, queue & (BFI_IOC_MAX_CQS - 1));
  69. }
  70. intr &= ~qintr;
  71. if (!intr)
  72. return BFA_TRUE;
  73. bfa_msix_lpu_err(bfa, intr);
  74. return BFA_TRUE;
  75. }
  76. void
  77. bfa_isr_enable(struct bfa_s *bfa)
  78. {
  79. u32 intr_unmask;
  80. int pci_func = bfa_ioc_pcifn(&bfa->ioc);
  81. bfa_trc(bfa, pci_func);
  82. bfa_msix_install(bfa);
  83. intr_unmask = (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 |
  84. __HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS);
  85. if (pci_func == 0)
  86. intr_unmask |= (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 |
  87. __HFN_INT_CPE_Q2 | __HFN_INT_CPE_Q3 |
  88. __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 |
  89. __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 |
  90. __HFN_INT_MBOX_LPU0);
  91. else
  92. intr_unmask |= (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 |
  93. __HFN_INT_CPE_Q6 | __HFN_INT_CPE_Q7 |
  94. __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 |
  95. __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 |
  96. __HFN_INT_MBOX_LPU1);
  97. bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, intr_unmask);
  98. bfa_reg_write(bfa->iocfc.bfa_regs.intr_mask, ~intr_unmask);
  99. bfa_isr_mode_set(bfa, bfa->msix.nvecs != 0);
  100. }
  101. void
  102. bfa_isr_disable(struct bfa_s *bfa)
  103. {
  104. bfa_isr_mode_set(bfa, BFA_FALSE);
  105. bfa_reg_write(bfa->iocfc.bfa_regs.intr_mask, -1L);
  106. bfa_msix_uninstall(bfa);
  107. }
  108. void
  109. bfa_msix_reqq(struct bfa_s *bfa, int qid)
  110. {
  111. struct list_head *waitq, *qe, *qen;
  112. struct bfa_reqq_wait_s *wqe;
  113. qid &= (BFI_IOC_MAX_CQS - 1);
  114. waitq = bfa_reqq(bfa, qid);
  115. list_for_each_safe(qe, qen, waitq) {
  116. /**
  117. * Callback only as long as there is room in request queue
  118. */
  119. if (bfa_reqq_full(bfa, qid))
  120. break;
  121. list_del(qe);
  122. wqe = (struct bfa_reqq_wait_s *) qe;
  123. wqe->qresume(wqe->cbarg);
  124. }
  125. }
  126. void
  127. bfa_isr_unhandled(struct bfa_s *bfa, struct bfi_msg_s *m)
  128. {
  129. bfa_trc(bfa, m->mhdr.msg_class);
  130. bfa_trc(bfa, m->mhdr.msg_id);
  131. bfa_trc(bfa, m->mhdr.mtag.i2htok);
  132. bfa_assert(0);
  133. bfa_trc_stop(bfa->trcmod);
  134. }
  135. void
  136. bfa_msix_rspq(struct bfa_s *bfa, int rsp_qid)
  137. {
  138. struct bfi_msg_s *m;
  139. u32 pi, ci;
  140. bfa_trc_fp(bfa, rsp_qid);
  141. rsp_qid &= (BFI_IOC_MAX_CQS - 1);
  142. bfa->iocfc.hwif.hw_rspq_ack(bfa, rsp_qid);
  143. ci = bfa_rspq_ci(bfa, rsp_qid);
  144. pi = bfa_rspq_pi(bfa, rsp_qid);
  145. bfa_trc_fp(bfa, ci);
  146. bfa_trc_fp(bfa, pi);
  147. if (bfa->rme_process) {
  148. while (ci != pi) {
  149. m = bfa_rspq_elem(bfa, rsp_qid, ci);
  150. bfa_assert_fp(m->mhdr.msg_class < BFI_MC_MAX);
  151. bfa_isrs[m->mhdr.msg_class] (bfa, m);
  152. CQ_INCR(ci, bfa->iocfc.cfg.drvcfg.num_rspq_elems);
  153. }
  154. }
  155. /**
  156. * update CI
  157. */
  158. bfa_rspq_ci(bfa, rsp_qid) = pi;
  159. bfa_reg_write(bfa->iocfc.bfa_regs.rme_q_ci[rsp_qid], pi);
  160. bfa_os_mmiowb();
  161. }
  162. void
  163. bfa_msix_lpu_err(struct bfa_s *bfa, int vec)
  164. {
  165. u32 intr;
  166. intr = bfa_reg_read(bfa->iocfc.bfa_regs.intr_status);
  167. if (intr & (__HFN_INT_MBOX_LPU0 | __HFN_INT_MBOX_LPU1))
  168. bfa_msix_lpu(bfa);
  169. if (intr & (__HFN_INT_ERR_EMC |
  170. __HFN_INT_ERR_LPU0 | __HFN_INT_ERR_LPU1 |
  171. __HFN_INT_ERR_PSS))
  172. bfa_msix_errint(bfa, intr);
  173. }
  174. void
  175. bfa_isr_bind(enum bfi_mclass mc, bfa_isr_func_t isr_func)
  176. {
  177. bfa_isrs[mc] = isr_func;
  178. }