qeth_core_main.c 128 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <asm/ebcdic.h>
  22. #include <asm/io.h>
  23. #include "qeth_core.h"
  24. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  25. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  26. /* N P A M L V H */
  27. [QETH_DBF_SETUP] = {"qeth_setup",
  28. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  29. [QETH_DBF_QERR] = {"qeth_qerr",
  30. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  31. [QETH_DBF_TRACE] = {"qeth_trace",
  32. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  33. [QETH_DBF_MSG] = {"qeth_msg",
  34. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  35. [QETH_DBF_SENSE] = {"qeth_sense",
  36. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  37. [QETH_DBF_MISC] = {"qeth_misc",
  38. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  39. [QETH_DBF_CTRL] = {"qeth_control",
  40. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  41. };
  42. EXPORT_SYMBOL_GPL(qeth_dbf);
  43. struct qeth_card_list_struct qeth_core_card_list;
  44. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  45. struct kmem_cache *qeth_core_header_cache;
  46. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  47. static struct device *qeth_core_root_dev;
  48. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  49. static struct lock_class_key qdio_out_skb_queue_key;
  50. static void qeth_send_control_data_cb(struct qeth_channel *,
  51. struct qeth_cmd_buffer *);
  52. static int qeth_issue_next_read(struct qeth_card *);
  53. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  54. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  55. static void qeth_free_buffer_pool(struct qeth_card *);
  56. static int qeth_qdio_establish(struct qeth_card *);
  57. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  58. struct qdio_buffer *buffer, int is_tso,
  59. int *next_element_to_fill)
  60. {
  61. struct skb_frag_struct *frag;
  62. int fragno;
  63. unsigned long addr;
  64. int element, cnt, dlen;
  65. fragno = skb_shinfo(skb)->nr_frags;
  66. element = *next_element_to_fill;
  67. dlen = 0;
  68. if (is_tso)
  69. buffer->element[element].flags =
  70. SBAL_FLAGS_MIDDLE_FRAG;
  71. else
  72. buffer->element[element].flags =
  73. SBAL_FLAGS_FIRST_FRAG;
  74. dlen = skb->len - skb->data_len;
  75. if (dlen) {
  76. buffer->element[element].addr = skb->data;
  77. buffer->element[element].length = dlen;
  78. element++;
  79. }
  80. for (cnt = 0; cnt < fragno; cnt++) {
  81. frag = &skb_shinfo(skb)->frags[cnt];
  82. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  83. frag->page_offset;
  84. buffer->element[element].addr = (char *)addr;
  85. buffer->element[element].length = frag->size;
  86. if (cnt < (fragno - 1))
  87. buffer->element[element].flags =
  88. SBAL_FLAGS_MIDDLE_FRAG;
  89. else
  90. buffer->element[element].flags =
  91. SBAL_FLAGS_LAST_FRAG;
  92. element++;
  93. }
  94. *next_element_to_fill = element;
  95. }
  96. static inline const char *qeth_get_cardname(struct qeth_card *card)
  97. {
  98. if (card->info.guestlan) {
  99. switch (card->info.type) {
  100. case QETH_CARD_TYPE_OSAE:
  101. return " Guest LAN QDIO";
  102. case QETH_CARD_TYPE_IQD:
  103. return " Guest LAN Hiper";
  104. default:
  105. return " unknown";
  106. }
  107. } else {
  108. switch (card->info.type) {
  109. case QETH_CARD_TYPE_OSAE:
  110. return " OSD Express";
  111. case QETH_CARD_TYPE_IQD:
  112. return " HiperSockets";
  113. case QETH_CARD_TYPE_OSN:
  114. return " OSN QDIO";
  115. default:
  116. return " unknown";
  117. }
  118. }
  119. return " n/a";
  120. }
  121. /* max length to be returned: 14 */
  122. const char *qeth_get_cardname_short(struct qeth_card *card)
  123. {
  124. if (card->info.guestlan) {
  125. switch (card->info.type) {
  126. case QETH_CARD_TYPE_OSAE:
  127. return "GuestLAN QDIO";
  128. case QETH_CARD_TYPE_IQD:
  129. return "GuestLAN Hiper";
  130. default:
  131. return "unknown";
  132. }
  133. } else {
  134. switch (card->info.type) {
  135. case QETH_CARD_TYPE_OSAE:
  136. switch (card->info.link_type) {
  137. case QETH_LINK_TYPE_FAST_ETH:
  138. return "OSD_100";
  139. case QETH_LINK_TYPE_HSTR:
  140. return "HSTR";
  141. case QETH_LINK_TYPE_GBIT_ETH:
  142. return "OSD_1000";
  143. case QETH_LINK_TYPE_10GBIT_ETH:
  144. return "OSD_10GIG";
  145. case QETH_LINK_TYPE_LANE_ETH100:
  146. return "OSD_FE_LANE";
  147. case QETH_LINK_TYPE_LANE_TR:
  148. return "OSD_TR_LANE";
  149. case QETH_LINK_TYPE_LANE_ETH1000:
  150. return "OSD_GbE_LANE";
  151. case QETH_LINK_TYPE_LANE:
  152. return "OSD_ATM_LANE";
  153. default:
  154. return "OSD_Express";
  155. }
  156. case QETH_CARD_TYPE_IQD:
  157. return "HiperSockets";
  158. case QETH_CARD_TYPE_OSN:
  159. return "OSN";
  160. default:
  161. return "unknown";
  162. }
  163. }
  164. return "n/a";
  165. }
  166. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  167. int clear_start_mask)
  168. {
  169. unsigned long flags;
  170. spin_lock_irqsave(&card->thread_mask_lock, flags);
  171. card->thread_allowed_mask = threads;
  172. if (clear_start_mask)
  173. card->thread_start_mask &= threads;
  174. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  175. wake_up(&card->wait_q);
  176. }
  177. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  178. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  179. {
  180. unsigned long flags;
  181. int rc = 0;
  182. spin_lock_irqsave(&card->thread_mask_lock, flags);
  183. rc = (card->thread_running_mask & threads);
  184. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  185. return rc;
  186. }
  187. EXPORT_SYMBOL_GPL(qeth_threads_running);
  188. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  189. {
  190. return wait_event_interruptible(card->wait_q,
  191. qeth_threads_running(card, threads) == 0);
  192. }
  193. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  194. void qeth_clear_working_pool_list(struct qeth_card *card)
  195. {
  196. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  197. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  198. list_for_each_entry_safe(pool_entry, tmp,
  199. &card->qdio.in_buf_pool.entry_list, list){
  200. list_del(&pool_entry->list);
  201. }
  202. }
  203. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  204. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  205. {
  206. struct qeth_buffer_pool_entry *pool_entry;
  207. void *ptr;
  208. int i, j;
  209. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  210. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  211. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  212. if (!pool_entry) {
  213. qeth_free_buffer_pool(card);
  214. return -ENOMEM;
  215. }
  216. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  217. ptr = (void *) __get_free_page(GFP_KERNEL);
  218. if (!ptr) {
  219. while (j > 0)
  220. free_page((unsigned long)
  221. pool_entry->elements[--j]);
  222. kfree(pool_entry);
  223. qeth_free_buffer_pool(card);
  224. return -ENOMEM;
  225. }
  226. pool_entry->elements[j] = ptr;
  227. }
  228. list_add(&pool_entry->init_list,
  229. &card->qdio.init_pool.entry_list);
  230. }
  231. return 0;
  232. }
  233. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  234. {
  235. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  236. if ((card->state != CARD_STATE_DOWN) &&
  237. (card->state != CARD_STATE_RECOVER))
  238. return -EPERM;
  239. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  240. qeth_clear_working_pool_list(card);
  241. qeth_free_buffer_pool(card);
  242. card->qdio.in_buf_pool.buf_count = bufcnt;
  243. card->qdio.init_pool.buf_count = bufcnt;
  244. return qeth_alloc_buffer_pool(card);
  245. }
  246. static int qeth_issue_next_read(struct qeth_card *card)
  247. {
  248. int rc;
  249. struct qeth_cmd_buffer *iob;
  250. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  251. if (card->read.state != CH_STATE_UP)
  252. return -EIO;
  253. iob = qeth_get_buffer(&card->read);
  254. if (!iob) {
  255. dev_warn(&card->gdev->dev, "The qeth device driver "
  256. "failed to recover an error on the device\n");
  257. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  258. "available\n", dev_name(&card->gdev->dev));
  259. return -ENOMEM;
  260. }
  261. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  262. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  263. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  264. (addr_t) iob, 0, 0);
  265. if (rc) {
  266. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  267. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  268. atomic_set(&card->read.irq_pending, 0);
  269. qeth_schedule_recovery(card);
  270. wake_up(&card->wait_q);
  271. }
  272. return rc;
  273. }
  274. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  275. {
  276. struct qeth_reply *reply;
  277. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  278. if (reply) {
  279. atomic_set(&reply->refcnt, 1);
  280. atomic_set(&reply->received, 0);
  281. reply->card = card;
  282. };
  283. return reply;
  284. }
  285. static void qeth_get_reply(struct qeth_reply *reply)
  286. {
  287. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  288. atomic_inc(&reply->refcnt);
  289. }
  290. static void qeth_put_reply(struct qeth_reply *reply)
  291. {
  292. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  293. if (atomic_dec_and_test(&reply->refcnt))
  294. kfree(reply);
  295. }
  296. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  297. struct qeth_card *card)
  298. {
  299. char *ipa_name;
  300. int com = cmd->hdr.command;
  301. ipa_name = qeth_get_ipa_cmd_name(com);
  302. if (rc)
  303. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  304. ipa_name, com, QETH_CARD_IFNAME(card),
  305. rc, qeth_get_ipa_msg(rc));
  306. else
  307. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  308. ipa_name, com, QETH_CARD_IFNAME(card));
  309. }
  310. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  311. struct qeth_cmd_buffer *iob)
  312. {
  313. struct qeth_ipa_cmd *cmd = NULL;
  314. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  315. if (IS_IPA(iob->data)) {
  316. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  317. if (IS_IPA_REPLY(cmd)) {
  318. if (cmd->hdr.command < IPA_CMD_SETCCID ||
  319. cmd->hdr.command > IPA_CMD_MODCCID)
  320. qeth_issue_ipa_msg(cmd,
  321. cmd->hdr.return_code, card);
  322. return cmd;
  323. } else {
  324. switch (cmd->hdr.command) {
  325. case IPA_CMD_STOPLAN:
  326. dev_warn(&card->gdev->dev,
  327. "The link for interface %s on CHPID"
  328. " 0x%X failed\n",
  329. QETH_CARD_IFNAME(card),
  330. card->info.chpid);
  331. card->lan_online = 0;
  332. if (card->dev && netif_carrier_ok(card->dev))
  333. netif_carrier_off(card->dev);
  334. return NULL;
  335. case IPA_CMD_STARTLAN:
  336. dev_info(&card->gdev->dev,
  337. "The link for %s on CHPID 0x%X has"
  338. " been restored\n",
  339. QETH_CARD_IFNAME(card),
  340. card->info.chpid);
  341. netif_carrier_on(card->dev);
  342. card->lan_online = 1;
  343. qeth_schedule_recovery(card);
  344. return NULL;
  345. case IPA_CMD_MODCCID:
  346. return cmd;
  347. case IPA_CMD_REGISTER_LOCAL_ADDR:
  348. QETH_DBF_TEXT(TRACE, 3, "irla");
  349. break;
  350. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  351. QETH_DBF_TEXT(TRACE, 3, "urla");
  352. break;
  353. default:
  354. QETH_DBF_MESSAGE(2, "Received data is IPA "
  355. "but not a reply!\n");
  356. break;
  357. }
  358. }
  359. }
  360. return cmd;
  361. }
  362. void qeth_clear_ipacmd_list(struct qeth_card *card)
  363. {
  364. struct qeth_reply *reply, *r;
  365. unsigned long flags;
  366. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  367. spin_lock_irqsave(&card->lock, flags);
  368. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  369. qeth_get_reply(reply);
  370. reply->rc = -EIO;
  371. atomic_inc(&reply->received);
  372. list_del_init(&reply->list);
  373. wake_up(&reply->wait_q);
  374. qeth_put_reply(reply);
  375. }
  376. spin_unlock_irqrestore(&card->lock, flags);
  377. }
  378. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  379. static int qeth_check_idx_response(unsigned char *buffer)
  380. {
  381. if (!buffer)
  382. return 0;
  383. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  384. if ((buffer[2] & 0xc0) == 0xc0) {
  385. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  386. "with cause code 0x%02x%s\n",
  387. buffer[4],
  388. ((buffer[4] == 0x22) ?
  389. " -- try another portname" : ""));
  390. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  391. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  392. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  393. return -EIO;
  394. }
  395. return 0;
  396. }
  397. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  398. __u32 len)
  399. {
  400. struct qeth_card *card;
  401. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  402. card = CARD_FROM_CDEV(channel->ccwdev);
  403. if (channel == &card->read)
  404. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  405. else
  406. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  407. channel->ccw.count = len;
  408. channel->ccw.cda = (__u32) __pa(iob);
  409. }
  410. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  411. {
  412. __u8 index;
  413. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  414. index = channel->io_buf_no;
  415. do {
  416. if (channel->iob[index].state == BUF_STATE_FREE) {
  417. channel->iob[index].state = BUF_STATE_LOCKED;
  418. channel->io_buf_no = (channel->io_buf_no + 1) %
  419. QETH_CMD_BUFFER_NO;
  420. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  421. return channel->iob + index;
  422. }
  423. index = (index + 1) % QETH_CMD_BUFFER_NO;
  424. } while (index != channel->io_buf_no);
  425. return NULL;
  426. }
  427. void qeth_release_buffer(struct qeth_channel *channel,
  428. struct qeth_cmd_buffer *iob)
  429. {
  430. unsigned long flags;
  431. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  432. spin_lock_irqsave(&channel->iob_lock, flags);
  433. memset(iob->data, 0, QETH_BUFSIZE);
  434. iob->state = BUF_STATE_FREE;
  435. iob->callback = qeth_send_control_data_cb;
  436. iob->rc = 0;
  437. spin_unlock_irqrestore(&channel->iob_lock, flags);
  438. }
  439. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  440. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  441. {
  442. struct qeth_cmd_buffer *buffer = NULL;
  443. unsigned long flags;
  444. spin_lock_irqsave(&channel->iob_lock, flags);
  445. buffer = __qeth_get_buffer(channel);
  446. spin_unlock_irqrestore(&channel->iob_lock, flags);
  447. return buffer;
  448. }
  449. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  450. {
  451. struct qeth_cmd_buffer *buffer;
  452. wait_event(channel->wait_q,
  453. ((buffer = qeth_get_buffer(channel)) != NULL));
  454. return buffer;
  455. }
  456. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  457. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  458. {
  459. int cnt;
  460. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  461. qeth_release_buffer(channel, &channel->iob[cnt]);
  462. channel->buf_no = 0;
  463. channel->io_buf_no = 0;
  464. }
  465. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  466. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  467. struct qeth_cmd_buffer *iob)
  468. {
  469. struct qeth_card *card;
  470. struct qeth_reply *reply, *r;
  471. struct qeth_ipa_cmd *cmd;
  472. unsigned long flags;
  473. int keep_reply;
  474. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  475. card = CARD_FROM_CDEV(channel->ccwdev);
  476. if (qeth_check_idx_response(iob->data)) {
  477. qeth_clear_ipacmd_list(card);
  478. if (((iob->data[2] & 0xc0) == 0xc0) && iob->data[4] == 0xf6)
  479. dev_err(&card->gdev->dev,
  480. "The qeth device is not configured "
  481. "for the OSI layer required by z/VM\n");
  482. qeth_schedule_recovery(card);
  483. goto out;
  484. }
  485. cmd = qeth_check_ipa_data(card, iob);
  486. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  487. goto out;
  488. /*in case of OSN : check if cmd is set */
  489. if (card->info.type == QETH_CARD_TYPE_OSN &&
  490. cmd &&
  491. cmd->hdr.command != IPA_CMD_STARTLAN &&
  492. card->osn_info.assist_cb != NULL) {
  493. card->osn_info.assist_cb(card->dev, cmd);
  494. goto out;
  495. }
  496. spin_lock_irqsave(&card->lock, flags);
  497. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  498. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  499. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  500. qeth_get_reply(reply);
  501. list_del_init(&reply->list);
  502. spin_unlock_irqrestore(&card->lock, flags);
  503. keep_reply = 0;
  504. if (reply->callback != NULL) {
  505. if (cmd) {
  506. reply->offset = (__u16)((char *)cmd -
  507. (char *)iob->data);
  508. keep_reply = reply->callback(card,
  509. reply,
  510. (unsigned long)cmd);
  511. } else
  512. keep_reply = reply->callback(card,
  513. reply,
  514. (unsigned long)iob);
  515. }
  516. if (cmd)
  517. reply->rc = (u16) cmd->hdr.return_code;
  518. else if (iob->rc)
  519. reply->rc = iob->rc;
  520. if (keep_reply) {
  521. spin_lock_irqsave(&card->lock, flags);
  522. list_add_tail(&reply->list,
  523. &card->cmd_waiter_list);
  524. spin_unlock_irqrestore(&card->lock, flags);
  525. } else {
  526. atomic_inc(&reply->received);
  527. wake_up(&reply->wait_q);
  528. }
  529. qeth_put_reply(reply);
  530. goto out;
  531. }
  532. }
  533. spin_unlock_irqrestore(&card->lock, flags);
  534. out:
  535. memcpy(&card->seqno.pdu_hdr_ack,
  536. QETH_PDU_HEADER_SEQ_NO(iob->data),
  537. QETH_SEQ_NO_LENGTH);
  538. qeth_release_buffer(channel, iob);
  539. }
  540. static int qeth_setup_channel(struct qeth_channel *channel)
  541. {
  542. int cnt;
  543. QETH_DBF_TEXT(SETUP, 2, "setupch");
  544. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  545. channel->iob[cnt].data = (char *)
  546. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  547. if (channel->iob[cnt].data == NULL)
  548. break;
  549. channel->iob[cnt].state = BUF_STATE_FREE;
  550. channel->iob[cnt].channel = channel;
  551. channel->iob[cnt].callback = qeth_send_control_data_cb;
  552. channel->iob[cnt].rc = 0;
  553. }
  554. if (cnt < QETH_CMD_BUFFER_NO) {
  555. while (cnt-- > 0)
  556. kfree(channel->iob[cnt].data);
  557. return -ENOMEM;
  558. }
  559. channel->buf_no = 0;
  560. channel->io_buf_no = 0;
  561. atomic_set(&channel->irq_pending, 0);
  562. spin_lock_init(&channel->iob_lock);
  563. init_waitqueue_head(&channel->wait_q);
  564. return 0;
  565. }
  566. static int qeth_set_thread_start_bit(struct qeth_card *card,
  567. unsigned long thread)
  568. {
  569. unsigned long flags;
  570. spin_lock_irqsave(&card->thread_mask_lock, flags);
  571. if (!(card->thread_allowed_mask & thread) ||
  572. (card->thread_start_mask & thread)) {
  573. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  574. return -EPERM;
  575. }
  576. card->thread_start_mask |= thread;
  577. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  578. return 0;
  579. }
  580. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  581. {
  582. unsigned long flags;
  583. spin_lock_irqsave(&card->thread_mask_lock, flags);
  584. card->thread_start_mask &= ~thread;
  585. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  586. wake_up(&card->wait_q);
  587. }
  588. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  589. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  590. {
  591. unsigned long flags;
  592. spin_lock_irqsave(&card->thread_mask_lock, flags);
  593. card->thread_running_mask &= ~thread;
  594. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  595. wake_up(&card->wait_q);
  596. }
  597. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  598. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  599. {
  600. unsigned long flags;
  601. int rc = 0;
  602. spin_lock_irqsave(&card->thread_mask_lock, flags);
  603. if (card->thread_start_mask & thread) {
  604. if ((card->thread_allowed_mask & thread) &&
  605. !(card->thread_running_mask & thread)) {
  606. rc = 1;
  607. card->thread_start_mask &= ~thread;
  608. card->thread_running_mask |= thread;
  609. } else
  610. rc = -EPERM;
  611. }
  612. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  613. return rc;
  614. }
  615. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  616. {
  617. int rc = 0;
  618. wait_event(card->wait_q,
  619. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  620. return rc;
  621. }
  622. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  623. void qeth_schedule_recovery(struct qeth_card *card)
  624. {
  625. QETH_DBF_TEXT(TRACE, 2, "startrec");
  626. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  627. schedule_work(&card->kernel_thread_starter);
  628. }
  629. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  630. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  631. {
  632. int dstat, cstat;
  633. char *sense;
  634. sense = (char *) irb->ecw;
  635. cstat = irb->scsw.cmd.cstat;
  636. dstat = irb->scsw.cmd.dstat;
  637. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  638. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  639. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  640. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  641. dev_warn(&cdev->dev, "The qeth device driver "
  642. "failed to recover an error on the device\n");
  643. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x ",
  644. dev_name(&cdev->dev), dstat, cstat);
  645. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  646. 16, 1, irb, 64, 1);
  647. return 1;
  648. }
  649. if (dstat & DEV_STAT_UNIT_CHECK) {
  650. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  651. SENSE_RESETTING_EVENT_FLAG) {
  652. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  653. return 1;
  654. }
  655. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  656. SENSE_COMMAND_REJECT_FLAG) {
  657. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  658. return 1;
  659. }
  660. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  661. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  662. return 1;
  663. }
  664. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  665. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  666. return 0;
  667. }
  668. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  669. return 1;
  670. }
  671. return 0;
  672. }
  673. static long __qeth_check_irb_error(struct ccw_device *cdev,
  674. unsigned long intparm, struct irb *irb)
  675. {
  676. if (!IS_ERR(irb))
  677. return 0;
  678. switch (PTR_ERR(irb)) {
  679. case -EIO:
  680. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  681. dev_name(&cdev->dev));
  682. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  683. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  684. break;
  685. case -ETIMEDOUT:
  686. dev_warn(&cdev->dev, "A hardware operation timed out"
  687. " on the device\n");
  688. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  689. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  690. if (intparm == QETH_RCD_PARM) {
  691. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  692. if (card && (card->data.ccwdev == cdev)) {
  693. card->data.state = CH_STATE_DOWN;
  694. wake_up(&card->wait_q);
  695. }
  696. }
  697. break;
  698. default:
  699. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  700. dev_name(&cdev->dev), PTR_ERR(irb));
  701. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  702. QETH_DBF_TEXT(TRACE, 2, " rc???");
  703. }
  704. return PTR_ERR(irb);
  705. }
  706. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  707. struct irb *irb)
  708. {
  709. int rc;
  710. int cstat, dstat;
  711. struct qeth_cmd_buffer *buffer;
  712. struct qeth_channel *channel;
  713. struct qeth_card *card;
  714. struct qeth_cmd_buffer *iob;
  715. __u8 index;
  716. QETH_DBF_TEXT(TRACE, 5, "irq");
  717. if (__qeth_check_irb_error(cdev, intparm, irb))
  718. return;
  719. cstat = irb->scsw.cmd.cstat;
  720. dstat = irb->scsw.cmd.dstat;
  721. card = CARD_FROM_CDEV(cdev);
  722. if (!card)
  723. return;
  724. if (card->read.ccwdev == cdev) {
  725. channel = &card->read;
  726. QETH_DBF_TEXT(TRACE, 5, "read");
  727. } else if (card->write.ccwdev == cdev) {
  728. channel = &card->write;
  729. QETH_DBF_TEXT(TRACE, 5, "write");
  730. } else {
  731. channel = &card->data;
  732. QETH_DBF_TEXT(TRACE, 5, "data");
  733. }
  734. atomic_set(&channel->irq_pending, 0);
  735. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  736. channel->state = CH_STATE_STOPPED;
  737. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  738. channel->state = CH_STATE_HALTED;
  739. /*let's wake up immediately on data channel*/
  740. if ((channel == &card->data) && (intparm != 0) &&
  741. (intparm != QETH_RCD_PARM))
  742. goto out;
  743. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  744. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  745. /* we don't have to handle this further */
  746. intparm = 0;
  747. }
  748. if (intparm == QETH_HALT_CHANNEL_PARM) {
  749. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  750. /* we don't have to handle this further */
  751. intparm = 0;
  752. }
  753. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  754. (dstat & DEV_STAT_UNIT_CHECK) ||
  755. (cstat)) {
  756. if (irb->esw.esw0.erw.cons) {
  757. dev_warn(&channel->ccwdev->dev,
  758. "The qeth device driver failed to recover "
  759. "an error on the device\n");
  760. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  761. "0x%X dstat 0x%X\n",
  762. dev_name(&channel->ccwdev->dev), cstat, dstat);
  763. print_hex_dump(KERN_WARNING, "qeth: irb ",
  764. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  765. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  766. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  767. }
  768. if (intparm == QETH_RCD_PARM) {
  769. channel->state = CH_STATE_DOWN;
  770. goto out;
  771. }
  772. rc = qeth_get_problem(cdev, irb);
  773. if (rc) {
  774. qeth_clear_ipacmd_list(card);
  775. qeth_schedule_recovery(card);
  776. goto out;
  777. }
  778. }
  779. if (intparm == QETH_RCD_PARM) {
  780. channel->state = CH_STATE_RCD_DONE;
  781. goto out;
  782. }
  783. if (intparm) {
  784. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  785. buffer->state = BUF_STATE_PROCESSED;
  786. }
  787. if (channel == &card->data)
  788. return;
  789. if (channel == &card->read &&
  790. channel->state == CH_STATE_UP)
  791. qeth_issue_next_read(card);
  792. iob = channel->iob;
  793. index = channel->buf_no;
  794. while (iob[index].state == BUF_STATE_PROCESSED) {
  795. if (iob[index].callback != NULL)
  796. iob[index].callback(channel, iob + index);
  797. index = (index + 1) % QETH_CMD_BUFFER_NO;
  798. }
  799. channel->buf_no = index;
  800. out:
  801. wake_up(&card->wait_q);
  802. return;
  803. }
  804. static void __qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  805. struct qeth_qdio_out_buffer *buf, unsigned int qeth_skip_skb)
  806. {
  807. int i;
  808. struct sk_buff *skb;
  809. /* is PCI flag set on buffer? */
  810. if (buf->buffer->element[0].flags & 0x40)
  811. atomic_dec(&queue->set_pci_flags_count);
  812. if (!qeth_skip_skb) {
  813. skb = skb_dequeue(&buf->skb_list);
  814. while (skb) {
  815. atomic_dec(&skb->users);
  816. dev_kfree_skb_any(skb);
  817. skb = skb_dequeue(&buf->skb_list);
  818. }
  819. }
  820. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  821. if (buf->buffer->element[i].addr && buf->is_header[i])
  822. kmem_cache_free(qeth_core_header_cache,
  823. buf->buffer->element[i].addr);
  824. buf->is_header[i] = 0;
  825. buf->buffer->element[i].length = 0;
  826. buf->buffer->element[i].addr = NULL;
  827. buf->buffer->element[i].flags = 0;
  828. }
  829. buf->buffer->element[15].flags = 0;
  830. buf->next_element_to_fill = 0;
  831. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  832. }
  833. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  834. struct qeth_qdio_out_buffer *buf)
  835. {
  836. __qeth_clear_output_buffer(queue, buf, 0);
  837. }
  838. void qeth_clear_qdio_buffers(struct qeth_card *card)
  839. {
  840. int i, j;
  841. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  842. /* clear outbound buffers to free skbs */
  843. for (i = 0; i < card->qdio.no_out_queues; ++i)
  844. if (card->qdio.out_qs[i]) {
  845. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  846. qeth_clear_output_buffer(card->qdio.out_qs[i],
  847. &card->qdio.out_qs[i]->bufs[j]);
  848. }
  849. }
  850. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  851. static void qeth_free_buffer_pool(struct qeth_card *card)
  852. {
  853. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  854. int i = 0;
  855. QETH_DBF_TEXT(TRACE, 5, "freepool");
  856. list_for_each_entry_safe(pool_entry, tmp,
  857. &card->qdio.init_pool.entry_list, init_list){
  858. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  859. free_page((unsigned long)pool_entry->elements[i]);
  860. list_del(&pool_entry->init_list);
  861. kfree(pool_entry);
  862. }
  863. }
  864. static void qeth_free_qdio_buffers(struct qeth_card *card)
  865. {
  866. int i, j;
  867. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  868. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  869. QETH_QDIO_UNINITIALIZED)
  870. return;
  871. kfree(card->qdio.in_q);
  872. card->qdio.in_q = NULL;
  873. /* inbound buffer pool */
  874. qeth_free_buffer_pool(card);
  875. /* free outbound qdio_qs */
  876. if (card->qdio.out_qs) {
  877. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  878. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  879. qeth_clear_output_buffer(card->qdio.out_qs[i],
  880. &card->qdio.out_qs[i]->bufs[j]);
  881. kfree(card->qdio.out_qs[i]);
  882. }
  883. kfree(card->qdio.out_qs);
  884. card->qdio.out_qs = NULL;
  885. }
  886. }
  887. static void qeth_clean_channel(struct qeth_channel *channel)
  888. {
  889. int cnt;
  890. QETH_DBF_TEXT(SETUP, 2, "freech");
  891. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  892. kfree(channel->iob[cnt].data);
  893. }
  894. static int qeth_is_1920_device(struct qeth_card *card)
  895. {
  896. int single_queue = 0;
  897. struct ccw_device *ccwdev;
  898. struct channelPath_dsc {
  899. u8 flags;
  900. u8 lsn;
  901. u8 desc;
  902. u8 chpid;
  903. u8 swla;
  904. u8 zeroes;
  905. u8 chla;
  906. u8 chpp;
  907. } *chp_dsc;
  908. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  909. ccwdev = card->data.ccwdev;
  910. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  911. if (chp_dsc != NULL) {
  912. /* CHPP field bit 6 == 1 -> single queue */
  913. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  914. kfree(chp_dsc);
  915. }
  916. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  917. return single_queue;
  918. }
  919. static void qeth_init_qdio_info(struct qeth_card *card)
  920. {
  921. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  922. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  923. /* inbound */
  924. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  925. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  926. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  927. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  928. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  929. }
  930. static void qeth_set_intial_options(struct qeth_card *card)
  931. {
  932. card->options.route4.type = NO_ROUTER;
  933. card->options.route6.type = NO_ROUTER;
  934. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  935. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  936. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  937. card->options.fake_broadcast = 0;
  938. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  939. card->options.performance_stats = 0;
  940. card->options.rx_sg_cb = QETH_RX_SG_CB;
  941. card->options.isolation = ISOLATION_MODE_NONE;
  942. }
  943. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  944. {
  945. unsigned long flags;
  946. int rc = 0;
  947. spin_lock_irqsave(&card->thread_mask_lock, flags);
  948. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  949. (u8) card->thread_start_mask,
  950. (u8) card->thread_allowed_mask,
  951. (u8) card->thread_running_mask);
  952. rc = (card->thread_start_mask & thread);
  953. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  954. return rc;
  955. }
  956. static void qeth_start_kernel_thread(struct work_struct *work)
  957. {
  958. struct qeth_card *card = container_of(work, struct qeth_card,
  959. kernel_thread_starter);
  960. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  961. if (card->read.state != CH_STATE_UP &&
  962. card->write.state != CH_STATE_UP)
  963. return;
  964. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  965. kthread_run(card->discipline.recover, (void *) card,
  966. "qeth_recover");
  967. }
  968. static int qeth_setup_card(struct qeth_card *card)
  969. {
  970. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  971. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  972. card->read.state = CH_STATE_DOWN;
  973. card->write.state = CH_STATE_DOWN;
  974. card->data.state = CH_STATE_DOWN;
  975. card->state = CARD_STATE_DOWN;
  976. card->lan_online = 0;
  977. card->use_hard_stop = 0;
  978. card->dev = NULL;
  979. spin_lock_init(&card->vlanlock);
  980. spin_lock_init(&card->mclock);
  981. card->vlangrp = NULL;
  982. spin_lock_init(&card->lock);
  983. spin_lock_init(&card->ip_lock);
  984. spin_lock_init(&card->thread_mask_lock);
  985. card->thread_start_mask = 0;
  986. card->thread_allowed_mask = 0;
  987. card->thread_running_mask = 0;
  988. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  989. INIT_LIST_HEAD(&card->ip_list);
  990. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  991. if (!card->ip_tbd_list) {
  992. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  993. return -ENOMEM;
  994. }
  995. INIT_LIST_HEAD(card->ip_tbd_list);
  996. INIT_LIST_HEAD(&card->cmd_waiter_list);
  997. init_waitqueue_head(&card->wait_q);
  998. /* intial options */
  999. qeth_set_intial_options(card);
  1000. /* IP address takeover */
  1001. INIT_LIST_HEAD(&card->ipato.entries);
  1002. card->ipato.enabled = 0;
  1003. card->ipato.invert4 = 0;
  1004. card->ipato.invert6 = 0;
  1005. if (card->info.type == QETH_CARD_TYPE_IQD)
  1006. card->options.checksum_type = NO_CHECKSUMMING;
  1007. /* init QDIO stuff */
  1008. qeth_init_qdio_info(card);
  1009. return 0;
  1010. }
  1011. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1012. {
  1013. struct qeth_card *card = container_of(slr, struct qeth_card,
  1014. qeth_service_level);
  1015. if (card->info.mcl_level[0])
  1016. seq_printf(m, "qeth: %s firmware level %s\n",
  1017. CARD_BUS_ID(card), card->info.mcl_level);
  1018. }
  1019. static struct qeth_card *qeth_alloc_card(void)
  1020. {
  1021. struct qeth_card *card;
  1022. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1023. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1024. if (!card)
  1025. return NULL;
  1026. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1027. if (qeth_setup_channel(&card->read)) {
  1028. kfree(card);
  1029. return NULL;
  1030. }
  1031. if (qeth_setup_channel(&card->write)) {
  1032. qeth_clean_channel(&card->read);
  1033. kfree(card);
  1034. return NULL;
  1035. }
  1036. card->options.layer2 = -1;
  1037. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1038. register_service_level(&card->qeth_service_level);
  1039. return card;
  1040. }
  1041. static int qeth_determine_card_type(struct qeth_card *card)
  1042. {
  1043. int i = 0;
  1044. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1045. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1046. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1047. while (known_devices[i][4]) {
  1048. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1049. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1050. card->info.type = known_devices[i][4];
  1051. card->qdio.no_out_queues = known_devices[i][8];
  1052. card->info.is_multicast_different = known_devices[i][9];
  1053. if (qeth_is_1920_device(card)) {
  1054. dev_info(&card->gdev->dev,
  1055. "Priority Queueing not supported\n");
  1056. card->qdio.no_out_queues = 1;
  1057. card->qdio.default_out_queue = 0;
  1058. }
  1059. return 0;
  1060. }
  1061. i++;
  1062. }
  1063. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1064. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1065. "unknown type\n");
  1066. return -ENOENT;
  1067. }
  1068. static int qeth_clear_channel(struct qeth_channel *channel)
  1069. {
  1070. unsigned long flags;
  1071. struct qeth_card *card;
  1072. int rc;
  1073. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1074. card = CARD_FROM_CDEV(channel->ccwdev);
  1075. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1076. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1077. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1078. if (rc)
  1079. return rc;
  1080. rc = wait_event_interruptible_timeout(card->wait_q,
  1081. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1082. if (rc == -ERESTARTSYS)
  1083. return rc;
  1084. if (channel->state != CH_STATE_STOPPED)
  1085. return -ETIME;
  1086. channel->state = CH_STATE_DOWN;
  1087. return 0;
  1088. }
  1089. static int qeth_halt_channel(struct qeth_channel *channel)
  1090. {
  1091. unsigned long flags;
  1092. struct qeth_card *card;
  1093. int rc;
  1094. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1095. card = CARD_FROM_CDEV(channel->ccwdev);
  1096. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1097. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1098. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1099. if (rc)
  1100. return rc;
  1101. rc = wait_event_interruptible_timeout(card->wait_q,
  1102. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1103. if (rc == -ERESTARTSYS)
  1104. return rc;
  1105. if (channel->state != CH_STATE_HALTED)
  1106. return -ETIME;
  1107. return 0;
  1108. }
  1109. static int qeth_halt_channels(struct qeth_card *card)
  1110. {
  1111. int rc1 = 0, rc2 = 0, rc3 = 0;
  1112. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1113. rc1 = qeth_halt_channel(&card->read);
  1114. rc2 = qeth_halt_channel(&card->write);
  1115. rc3 = qeth_halt_channel(&card->data);
  1116. if (rc1)
  1117. return rc1;
  1118. if (rc2)
  1119. return rc2;
  1120. return rc3;
  1121. }
  1122. static int qeth_clear_channels(struct qeth_card *card)
  1123. {
  1124. int rc1 = 0, rc2 = 0, rc3 = 0;
  1125. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1126. rc1 = qeth_clear_channel(&card->read);
  1127. rc2 = qeth_clear_channel(&card->write);
  1128. rc3 = qeth_clear_channel(&card->data);
  1129. if (rc1)
  1130. return rc1;
  1131. if (rc2)
  1132. return rc2;
  1133. return rc3;
  1134. }
  1135. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1136. {
  1137. int rc = 0;
  1138. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1139. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1140. if (halt)
  1141. rc = qeth_halt_channels(card);
  1142. if (rc)
  1143. return rc;
  1144. return qeth_clear_channels(card);
  1145. }
  1146. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1147. {
  1148. int rc = 0;
  1149. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1150. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1151. QETH_QDIO_CLEANING)) {
  1152. case QETH_QDIO_ESTABLISHED:
  1153. if (card->info.type == QETH_CARD_TYPE_IQD)
  1154. rc = qdio_cleanup(CARD_DDEV(card),
  1155. QDIO_FLAG_CLEANUP_USING_HALT);
  1156. else
  1157. rc = qdio_cleanup(CARD_DDEV(card),
  1158. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1159. if (rc)
  1160. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1161. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1162. break;
  1163. case QETH_QDIO_CLEANING:
  1164. return rc;
  1165. default:
  1166. break;
  1167. }
  1168. rc = qeth_clear_halt_card(card, use_halt);
  1169. if (rc)
  1170. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1171. card->state = CARD_STATE_DOWN;
  1172. return rc;
  1173. }
  1174. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1175. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1176. int *length)
  1177. {
  1178. struct ciw *ciw;
  1179. char *rcd_buf;
  1180. int ret;
  1181. struct qeth_channel *channel = &card->data;
  1182. unsigned long flags;
  1183. /*
  1184. * scan for RCD command in extended SenseID data
  1185. */
  1186. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1187. if (!ciw || ciw->cmd == 0)
  1188. return -EOPNOTSUPP;
  1189. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1190. if (!rcd_buf)
  1191. return -ENOMEM;
  1192. channel->ccw.cmd_code = ciw->cmd;
  1193. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1194. channel->ccw.count = ciw->count;
  1195. channel->ccw.flags = CCW_FLAG_SLI;
  1196. channel->state = CH_STATE_RCD;
  1197. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1198. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1199. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1200. QETH_RCD_TIMEOUT);
  1201. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1202. if (!ret)
  1203. wait_event(card->wait_q,
  1204. (channel->state == CH_STATE_RCD_DONE ||
  1205. channel->state == CH_STATE_DOWN));
  1206. if (channel->state == CH_STATE_DOWN)
  1207. ret = -EIO;
  1208. else
  1209. channel->state = CH_STATE_DOWN;
  1210. if (ret) {
  1211. kfree(rcd_buf);
  1212. *buffer = NULL;
  1213. *length = 0;
  1214. } else {
  1215. *length = ciw->count;
  1216. *buffer = rcd_buf;
  1217. }
  1218. return ret;
  1219. }
  1220. static int qeth_get_unitaddr(struct qeth_card *card)
  1221. {
  1222. int length;
  1223. char *prcd;
  1224. int rc;
  1225. QETH_DBF_TEXT(SETUP, 2, "getunit");
  1226. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1227. if (rc) {
  1228. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  1229. dev_name(&card->gdev->dev), rc);
  1230. return rc;
  1231. }
  1232. card->info.chpid = prcd[30];
  1233. card->info.unit_addr2 = prcd[31];
  1234. card->info.cula = prcd[63];
  1235. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1236. (prcd[0x11] == _ascebc['M']));
  1237. kfree(prcd);
  1238. return 0;
  1239. }
  1240. static void qeth_init_tokens(struct qeth_card *card)
  1241. {
  1242. card->token.issuer_rm_w = 0x00010103UL;
  1243. card->token.cm_filter_w = 0x00010108UL;
  1244. card->token.cm_connection_w = 0x0001010aUL;
  1245. card->token.ulp_filter_w = 0x0001010bUL;
  1246. card->token.ulp_connection_w = 0x0001010dUL;
  1247. }
  1248. static void qeth_init_func_level(struct qeth_card *card)
  1249. {
  1250. if (card->ipato.enabled) {
  1251. if (card->info.type == QETH_CARD_TYPE_IQD)
  1252. card->info.func_level =
  1253. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1254. else
  1255. card->info.func_level =
  1256. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1257. } else {
  1258. if (card->info.type == QETH_CARD_TYPE_IQD)
  1259. /*FIXME:why do we have same values for dis and ena for
  1260. osae??? */
  1261. card->info.func_level =
  1262. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1263. else
  1264. card->info.func_level =
  1265. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1266. }
  1267. }
  1268. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1269. void (*idx_reply_cb)(struct qeth_channel *,
  1270. struct qeth_cmd_buffer *))
  1271. {
  1272. struct qeth_cmd_buffer *iob;
  1273. unsigned long flags;
  1274. int rc;
  1275. struct qeth_card *card;
  1276. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1277. card = CARD_FROM_CDEV(channel->ccwdev);
  1278. iob = qeth_get_buffer(channel);
  1279. iob->callback = idx_reply_cb;
  1280. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1281. channel->ccw.count = QETH_BUFSIZE;
  1282. channel->ccw.cda = (__u32) __pa(iob->data);
  1283. wait_event(card->wait_q,
  1284. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1285. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1286. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1287. rc = ccw_device_start(channel->ccwdev,
  1288. &channel->ccw, (addr_t) iob, 0, 0);
  1289. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1290. if (rc) {
  1291. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1292. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1293. atomic_set(&channel->irq_pending, 0);
  1294. wake_up(&card->wait_q);
  1295. return rc;
  1296. }
  1297. rc = wait_event_interruptible_timeout(card->wait_q,
  1298. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1299. if (rc == -ERESTARTSYS)
  1300. return rc;
  1301. if (channel->state != CH_STATE_UP) {
  1302. rc = -ETIME;
  1303. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1304. qeth_clear_cmd_buffers(channel);
  1305. } else
  1306. rc = 0;
  1307. return rc;
  1308. }
  1309. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1310. void (*idx_reply_cb)(struct qeth_channel *,
  1311. struct qeth_cmd_buffer *))
  1312. {
  1313. struct qeth_card *card;
  1314. struct qeth_cmd_buffer *iob;
  1315. unsigned long flags;
  1316. __u16 temp;
  1317. __u8 tmp;
  1318. int rc;
  1319. struct ccw_dev_id temp_devid;
  1320. card = CARD_FROM_CDEV(channel->ccwdev);
  1321. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1322. iob = qeth_get_buffer(channel);
  1323. iob->callback = idx_reply_cb;
  1324. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1325. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1326. channel->ccw.cda = (__u32) __pa(iob->data);
  1327. if (channel == &card->write) {
  1328. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1329. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1330. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1331. card->seqno.trans_hdr++;
  1332. } else {
  1333. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1334. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1335. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1336. }
  1337. tmp = ((__u8)card->info.portno) | 0x80;
  1338. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1339. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1340. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1341. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1342. &card->info.func_level, sizeof(__u16));
  1343. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1344. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1345. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1346. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1347. wait_event(card->wait_q,
  1348. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1349. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1350. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1351. rc = ccw_device_start(channel->ccwdev,
  1352. &channel->ccw, (addr_t) iob, 0, 0);
  1353. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1354. if (rc) {
  1355. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1356. rc);
  1357. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1358. atomic_set(&channel->irq_pending, 0);
  1359. wake_up(&card->wait_q);
  1360. return rc;
  1361. }
  1362. rc = wait_event_interruptible_timeout(card->wait_q,
  1363. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1364. if (rc == -ERESTARTSYS)
  1365. return rc;
  1366. if (channel->state != CH_STATE_ACTIVATING) {
  1367. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1368. " failed to recover an error on the device\n");
  1369. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1370. dev_name(&channel->ccwdev->dev));
  1371. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1372. qeth_clear_cmd_buffers(channel);
  1373. return -ETIME;
  1374. }
  1375. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1376. }
  1377. static int qeth_peer_func_level(int level)
  1378. {
  1379. if ((level & 0xff) == 8)
  1380. return (level & 0xff) + 0x400;
  1381. if (((level >> 8) & 3) == 1)
  1382. return (level & 0xff) + 0x200;
  1383. return level;
  1384. }
  1385. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1386. struct qeth_cmd_buffer *iob)
  1387. {
  1388. struct qeth_card *card;
  1389. __u16 temp;
  1390. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1391. if (channel->state == CH_STATE_DOWN) {
  1392. channel->state = CH_STATE_ACTIVATING;
  1393. goto out;
  1394. }
  1395. card = CARD_FROM_CDEV(channel->ccwdev);
  1396. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1397. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1398. dev_err(&card->write.ccwdev->dev,
  1399. "The adapter is used exclusively by another "
  1400. "host\n");
  1401. else
  1402. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1403. " negative reply\n",
  1404. dev_name(&card->write.ccwdev->dev));
  1405. goto out;
  1406. }
  1407. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1408. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1409. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1410. "function level mismatch (sent: 0x%x, received: "
  1411. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1412. card->info.func_level, temp);
  1413. goto out;
  1414. }
  1415. channel->state = CH_STATE_UP;
  1416. out:
  1417. qeth_release_buffer(channel, iob);
  1418. }
  1419. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1420. struct qeth_cmd_buffer *iob)
  1421. {
  1422. struct qeth_card *card;
  1423. __u16 temp;
  1424. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1425. if (channel->state == CH_STATE_DOWN) {
  1426. channel->state = CH_STATE_ACTIVATING;
  1427. goto out;
  1428. }
  1429. card = CARD_FROM_CDEV(channel->ccwdev);
  1430. if (qeth_check_idx_response(iob->data))
  1431. goto out;
  1432. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1433. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1434. dev_err(&card->write.ccwdev->dev,
  1435. "The adapter is used exclusively by another "
  1436. "host\n");
  1437. else
  1438. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1439. " negative reply\n",
  1440. dev_name(&card->read.ccwdev->dev));
  1441. goto out;
  1442. }
  1443. /**
  1444. * temporary fix for microcode bug
  1445. * to revert it,replace OR by AND
  1446. */
  1447. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1448. (card->info.type == QETH_CARD_TYPE_OSAE))
  1449. card->info.portname_required = 1;
  1450. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1451. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1452. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1453. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1454. dev_name(&card->read.ccwdev->dev),
  1455. card->info.func_level, temp);
  1456. goto out;
  1457. }
  1458. memcpy(&card->token.issuer_rm_r,
  1459. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1460. QETH_MPC_TOKEN_LENGTH);
  1461. memcpy(&card->info.mcl_level[0],
  1462. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1463. channel->state = CH_STATE_UP;
  1464. out:
  1465. qeth_release_buffer(channel, iob);
  1466. }
  1467. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1468. struct qeth_cmd_buffer *iob)
  1469. {
  1470. qeth_setup_ccw(&card->write, iob->data, len);
  1471. iob->callback = qeth_release_buffer;
  1472. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1473. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1474. card->seqno.trans_hdr++;
  1475. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1476. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1477. card->seqno.pdu_hdr++;
  1478. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1479. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1480. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1481. }
  1482. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1483. int qeth_send_control_data(struct qeth_card *card, int len,
  1484. struct qeth_cmd_buffer *iob,
  1485. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1486. unsigned long),
  1487. void *reply_param)
  1488. {
  1489. int rc;
  1490. unsigned long flags;
  1491. struct qeth_reply *reply = NULL;
  1492. unsigned long timeout, event_timeout;
  1493. struct qeth_ipa_cmd *cmd;
  1494. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1495. reply = qeth_alloc_reply(card);
  1496. if (!reply) {
  1497. return -ENOMEM;
  1498. }
  1499. reply->callback = reply_cb;
  1500. reply->param = reply_param;
  1501. if (card->state == CARD_STATE_DOWN)
  1502. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1503. else
  1504. reply->seqno = card->seqno.ipa++;
  1505. init_waitqueue_head(&reply->wait_q);
  1506. spin_lock_irqsave(&card->lock, flags);
  1507. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1508. spin_unlock_irqrestore(&card->lock, flags);
  1509. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1510. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1511. qeth_prepare_control_data(card, len, iob);
  1512. if (IS_IPA(iob->data))
  1513. event_timeout = QETH_IPA_TIMEOUT;
  1514. else
  1515. event_timeout = QETH_TIMEOUT;
  1516. timeout = jiffies + event_timeout;
  1517. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1518. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1519. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1520. (addr_t) iob, 0, 0);
  1521. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1522. if (rc) {
  1523. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1524. "ccw_device_start rc = %i\n",
  1525. dev_name(&card->write.ccwdev->dev), rc);
  1526. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1527. spin_lock_irqsave(&card->lock, flags);
  1528. list_del_init(&reply->list);
  1529. qeth_put_reply(reply);
  1530. spin_unlock_irqrestore(&card->lock, flags);
  1531. qeth_release_buffer(iob->channel, iob);
  1532. atomic_set(&card->write.irq_pending, 0);
  1533. wake_up(&card->wait_q);
  1534. return rc;
  1535. }
  1536. /* we have only one long running ipassist, since we can ensure
  1537. process context of this command we can sleep */
  1538. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1539. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1540. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1541. if (!wait_event_timeout(reply->wait_q,
  1542. atomic_read(&reply->received), event_timeout))
  1543. goto time_err;
  1544. } else {
  1545. while (!atomic_read(&reply->received)) {
  1546. if (time_after(jiffies, timeout))
  1547. goto time_err;
  1548. cpu_relax();
  1549. };
  1550. }
  1551. rc = reply->rc;
  1552. qeth_put_reply(reply);
  1553. return rc;
  1554. time_err:
  1555. spin_lock_irqsave(&reply->card->lock, flags);
  1556. list_del_init(&reply->list);
  1557. spin_unlock_irqrestore(&reply->card->lock, flags);
  1558. reply->rc = -ETIME;
  1559. atomic_inc(&reply->received);
  1560. wake_up(&reply->wait_q);
  1561. rc = reply->rc;
  1562. qeth_put_reply(reply);
  1563. return rc;
  1564. }
  1565. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1566. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1567. unsigned long data)
  1568. {
  1569. struct qeth_cmd_buffer *iob;
  1570. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1571. iob = (struct qeth_cmd_buffer *) data;
  1572. memcpy(&card->token.cm_filter_r,
  1573. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1574. QETH_MPC_TOKEN_LENGTH);
  1575. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1576. return 0;
  1577. }
  1578. static int qeth_cm_enable(struct qeth_card *card)
  1579. {
  1580. int rc;
  1581. struct qeth_cmd_buffer *iob;
  1582. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1583. iob = qeth_wait_for_buffer(&card->write);
  1584. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1585. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1586. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1587. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1588. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1589. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1590. qeth_cm_enable_cb, NULL);
  1591. return rc;
  1592. }
  1593. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1594. unsigned long data)
  1595. {
  1596. struct qeth_cmd_buffer *iob;
  1597. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1598. iob = (struct qeth_cmd_buffer *) data;
  1599. memcpy(&card->token.cm_connection_r,
  1600. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1601. QETH_MPC_TOKEN_LENGTH);
  1602. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1603. return 0;
  1604. }
  1605. static int qeth_cm_setup(struct qeth_card *card)
  1606. {
  1607. int rc;
  1608. struct qeth_cmd_buffer *iob;
  1609. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1610. iob = qeth_wait_for_buffer(&card->write);
  1611. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1612. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1613. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1614. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1615. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1616. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1617. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1618. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1619. qeth_cm_setup_cb, NULL);
  1620. return rc;
  1621. }
  1622. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1623. {
  1624. switch (card->info.type) {
  1625. case QETH_CARD_TYPE_UNKNOWN:
  1626. return 1500;
  1627. case QETH_CARD_TYPE_IQD:
  1628. return card->info.max_mtu;
  1629. case QETH_CARD_TYPE_OSAE:
  1630. switch (card->info.link_type) {
  1631. case QETH_LINK_TYPE_HSTR:
  1632. case QETH_LINK_TYPE_LANE_TR:
  1633. return 2000;
  1634. default:
  1635. return 1492;
  1636. }
  1637. default:
  1638. return 1500;
  1639. }
  1640. }
  1641. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1642. {
  1643. switch (cardtype) {
  1644. case QETH_CARD_TYPE_UNKNOWN:
  1645. case QETH_CARD_TYPE_OSAE:
  1646. case QETH_CARD_TYPE_OSN:
  1647. return 61440;
  1648. case QETH_CARD_TYPE_IQD:
  1649. return 57344;
  1650. default:
  1651. return 1500;
  1652. }
  1653. }
  1654. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1655. {
  1656. switch (cardtype) {
  1657. case QETH_CARD_TYPE_IQD:
  1658. return 1;
  1659. default:
  1660. return 0;
  1661. }
  1662. }
  1663. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1664. {
  1665. switch (framesize) {
  1666. case 0x4000:
  1667. return 8192;
  1668. case 0x6000:
  1669. return 16384;
  1670. case 0xa000:
  1671. return 32768;
  1672. case 0xffff:
  1673. return 57344;
  1674. default:
  1675. return 0;
  1676. }
  1677. }
  1678. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1679. {
  1680. switch (card->info.type) {
  1681. case QETH_CARD_TYPE_OSAE:
  1682. return ((mtu >= 576) && (mtu <= 61440));
  1683. case QETH_CARD_TYPE_IQD:
  1684. return ((mtu >= 576) &&
  1685. (mtu <= card->info.max_mtu + 4096 - 32));
  1686. case QETH_CARD_TYPE_OSN:
  1687. case QETH_CARD_TYPE_UNKNOWN:
  1688. default:
  1689. return 1;
  1690. }
  1691. }
  1692. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1693. unsigned long data)
  1694. {
  1695. __u16 mtu, framesize;
  1696. __u16 len;
  1697. __u8 link_type;
  1698. struct qeth_cmd_buffer *iob;
  1699. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1700. iob = (struct qeth_cmd_buffer *) data;
  1701. memcpy(&card->token.ulp_filter_r,
  1702. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1703. QETH_MPC_TOKEN_LENGTH);
  1704. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1705. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1706. mtu = qeth_get_mtu_outof_framesize(framesize);
  1707. if (!mtu) {
  1708. iob->rc = -EINVAL;
  1709. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1710. return 0;
  1711. }
  1712. card->info.max_mtu = mtu;
  1713. card->info.initial_mtu = mtu;
  1714. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1715. } else {
  1716. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1717. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1718. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1719. }
  1720. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1721. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1722. memcpy(&link_type,
  1723. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1724. card->info.link_type = link_type;
  1725. } else
  1726. card->info.link_type = 0;
  1727. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1728. return 0;
  1729. }
  1730. static int qeth_ulp_enable(struct qeth_card *card)
  1731. {
  1732. int rc;
  1733. char prot_type;
  1734. struct qeth_cmd_buffer *iob;
  1735. /*FIXME: trace view callbacks*/
  1736. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1737. iob = qeth_wait_for_buffer(&card->write);
  1738. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1739. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1740. (__u8) card->info.portno;
  1741. if (card->options.layer2)
  1742. if (card->info.type == QETH_CARD_TYPE_OSN)
  1743. prot_type = QETH_PROT_OSN2;
  1744. else
  1745. prot_type = QETH_PROT_LAYER2;
  1746. else
  1747. prot_type = QETH_PROT_TCPIP;
  1748. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1749. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1750. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1751. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1752. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1753. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1754. card->info.portname, 9);
  1755. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1756. qeth_ulp_enable_cb, NULL);
  1757. return rc;
  1758. }
  1759. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1760. unsigned long data)
  1761. {
  1762. struct qeth_cmd_buffer *iob;
  1763. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1764. iob = (struct qeth_cmd_buffer *) data;
  1765. memcpy(&card->token.ulp_connection_r,
  1766. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1767. QETH_MPC_TOKEN_LENGTH);
  1768. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1769. return 0;
  1770. }
  1771. static int qeth_ulp_setup(struct qeth_card *card)
  1772. {
  1773. int rc;
  1774. __u16 temp;
  1775. struct qeth_cmd_buffer *iob;
  1776. struct ccw_dev_id dev_id;
  1777. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1778. iob = qeth_wait_for_buffer(&card->write);
  1779. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1780. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1781. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1782. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1783. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1784. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1785. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1786. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1787. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1788. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1789. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1790. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1791. qeth_ulp_setup_cb, NULL);
  1792. return rc;
  1793. }
  1794. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1795. {
  1796. int i, j;
  1797. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1798. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1799. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1800. return 0;
  1801. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1802. GFP_KERNEL);
  1803. if (!card->qdio.in_q)
  1804. goto out_nomem;
  1805. QETH_DBF_TEXT(SETUP, 2, "inq");
  1806. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1807. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1808. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1809. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1810. card->qdio.in_q->bufs[i].buffer =
  1811. &card->qdio.in_q->qdio_bufs[i];
  1812. /* inbound buffer pool */
  1813. if (qeth_alloc_buffer_pool(card))
  1814. goto out_freeinq;
  1815. /* outbound */
  1816. card->qdio.out_qs =
  1817. kmalloc(card->qdio.no_out_queues *
  1818. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1819. if (!card->qdio.out_qs)
  1820. goto out_freepool;
  1821. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1822. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1823. GFP_KERNEL);
  1824. if (!card->qdio.out_qs[i])
  1825. goto out_freeoutq;
  1826. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1827. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1828. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1829. card->qdio.out_qs[i]->queue_no = i;
  1830. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1831. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1832. card->qdio.out_qs[i]->bufs[j].buffer =
  1833. &card->qdio.out_qs[i]->qdio_bufs[j];
  1834. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1835. skb_list);
  1836. lockdep_set_class(
  1837. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1838. &qdio_out_skb_queue_key);
  1839. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1840. }
  1841. }
  1842. return 0;
  1843. out_freeoutq:
  1844. while (i > 0)
  1845. kfree(card->qdio.out_qs[--i]);
  1846. kfree(card->qdio.out_qs);
  1847. card->qdio.out_qs = NULL;
  1848. out_freepool:
  1849. qeth_free_buffer_pool(card);
  1850. out_freeinq:
  1851. kfree(card->qdio.in_q);
  1852. card->qdio.in_q = NULL;
  1853. out_nomem:
  1854. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1855. return -ENOMEM;
  1856. }
  1857. static void qeth_create_qib_param_field(struct qeth_card *card,
  1858. char *param_field)
  1859. {
  1860. param_field[0] = _ascebc['P'];
  1861. param_field[1] = _ascebc['C'];
  1862. param_field[2] = _ascebc['I'];
  1863. param_field[3] = _ascebc['T'];
  1864. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1865. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1866. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1867. }
  1868. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1869. char *param_field)
  1870. {
  1871. param_field[16] = _ascebc['B'];
  1872. param_field[17] = _ascebc['L'];
  1873. param_field[18] = _ascebc['K'];
  1874. param_field[19] = _ascebc['T'];
  1875. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1876. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1877. *((unsigned int *) (&param_field[28])) =
  1878. card->info.blkt.inter_packet_jumbo;
  1879. }
  1880. static int qeth_qdio_activate(struct qeth_card *card)
  1881. {
  1882. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1883. return qdio_activate(CARD_DDEV(card));
  1884. }
  1885. static int qeth_dm_act(struct qeth_card *card)
  1886. {
  1887. int rc;
  1888. struct qeth_cmd_buffer *iob;
  1889. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1890. iob = qeth_wait_for_buffer(&card->write);
  1891. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1892. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1893. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1894. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1895. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1896. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1897. return rc;
  1898. }
  1899. static int qeth_mpc_initialize(struct qeth_card *card)
  1900. {
  1901. int rc;
  1902. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1903. rc = qeth_issue_next_read(card);
  1904. if (rc) {
  1905. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1906. return rc;
  1907. }
  1908. rc = qeth_cm_enable(card);
  1909. if (rc) {
  1910. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1911. goto out_qdio;
  1912. }
  1913. rc = qeth_cm_setup(card);
  1914. if (rc) {
  1915. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1916. goto out_qdio;
  1917. }
  1918. rc = qeth_ulp_enable(card);
  1919. if (rc) {
  1920. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1921. goto out_qdio;
  1922. }
  1923. rc = qeth_ulp_setup(card);
  1924. if (rc) {
  1925. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1926. goto out_qdio;
  1927. }
  1928. rc = qeth_alloc_qdio_buffers(card);
  1929. if (rc) {
  1930. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1931. goto out_qdio;
  1932. }
  1933. rc = qeth_qdio_establish(card);
  1934. if (rc) {
  1935. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1936. qeth_free_qdio_buffers(card);
  1937. goto out_qdio;
  1938. }
  1939. rc = qeth_qdio_activate(card);
  1940. if (rc) {
  1941. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1942. goto out_qdio;
  1943. }
  1944. rc = qeth_dm_act(card);
  1945. if (rc) {
  1946. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1947. goto out_qdio;
  1948. }
  1949. return 0;
  1950. out_qdio:
  1951. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1952. return rc;
  1953. }
  1954. static void qeth_print_status_with_portname(struct qeth_card *card)
  1955. {
  1956. char dbf_text[15];
  1957. int i;
  1958. sprintf(dbf_text, "%s", card->info.portname + 1);
  1959. for (i = 0; i < 8; i++)
  1960. dbf_text[i] =
  1961. (char) _ebcasc[(__u8) dbf_text[i]];
  1962. dbf_text[8] = 0;
  1963. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1964. "with link type %s (portname: %s)\n",
  1965. qeth_get_cardname(card),
  1966. (card->info.mcl_level[0]) ? " (level: " : "",
  1967. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1968. (card->info.mcl_level[0]) ? ")" : "",
  1969. qeth_get_cardname_short(card),
  1970. dbf_text);
  1971. }
  1972. static void qeth_print_status_no_portname(struct qeth_card *card)
  1973. {
  1974. if (card->info.portname[0])
  1975. dev_info(&card->gdev->dev, "Device is a%s "
  1976. "card%s%s%s\nwith link type %s "
  1977. "(no portname needed by interface).\n",
  1978. qeth_get_cardname(card),
  1979. (card->info.mcl_level[0]) ? " (level: " : "",
  1980. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1981. (card->info.mcl_level[0]) ? ")" : "",
  1982. qeth_get_cardname_short(card));
  1983. else
  1984. dev_info(&card->gdev->dev, "Device is a%s "
  1985. "card%s%s%s\nwith link type %s.\n",
  1986. qeth_get_cardname(card),
  1987. (card->info.mcl_level[0]) ? " (level: " : "",
  1988. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1989. (card->info.mcl_level[0]) ? ")" : "",
  1990. qeth_get_cardname_short(card));
  1991. }
  1992. void qeth_print_status_message(struct qeth_card *card)
  1993. {
  1994. switch (card->info.type) {
  1995. case QETH_CARD_TYPE_OSAE:
  1996. /* VM will use a non-zero first character
  1997. * to indicate a HiperSockets like reporting
  1998. * of the level OSA sets the first character to zero
  1999. * */
  2000. if (!card->info.mcl_level[0]) {
  2001. sprintf(card->info.mcl_level, "%02x%02x",
  2002. card->info.mcl_level[2],
  2003. card->info.mcl_level[3]);
  2004. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2005. break;
  2006. }
  2007. /* fallthrough */
  2008. case QETH_CARD_TYPE_IQD:
  2009. if ((card->info.guestlan) ||
  2010. (card->info.mcl_level[0] & 0x80)) {
  2011. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2012. card->info.mcl_level[0]];
  2013. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2014. card->info.mcl_level[1]];
  2015. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2016. card->info.mcl_level[2]];
  2017. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2018. card->info.mcl_level[3]];
  2019. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2020. }
  2021. break;
  2022. default:
  2023. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2024. }
  2025. if (card->info.portname_required)
  2026. qeth_print_status_with_portname(card);
  2027. else
  2028. qeth_print_status_no_portname(card);
  2029. }
  2030. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2031. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2032. {
  2033. struct qeth_buffer_pool_entry *entry;
  2034. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2035. list_for_each_entry(entry,
  2036. &card->qdio.init_pool.entry_list, init_list) {
  2037. qeth_put_buffer_pool_entry(card, entry);
  2038. }
  2039. }
  2040. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2041. struct qeth_card *card)
  2042. {
  2043. struct list_head *plh;
  2044. struct qeth_buffer_pool_entry *entry;
  2045. int i, free;
  2046. struct page *page;
  2047. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2048. return NULL;
  2049. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2050. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2051. free = 1;
  2052. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2053. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2054. free = 0;
  2055. break;
  2056. }
  2057. }
  2058. if (free) {
  2059. list_del_init(&entry->list);
  2060. return entry;
  2061. }
  2062. }
  2063. /* no free buffer in pool so take first one and swap pages */
  2064. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2065. struct qeth_buffer_pool_entry, list);
  2066. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2067. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2068. page = alloc_page(GFP_ATOMIC);
  2069. if (!page) {
  2070. return NULL;
  2071. } else {
  2072. free_page((unsigned long)entry->elements[i]);
  2073. entry->elements[i] = page_address(page);
  2074. if (card->options.performance_stats)
  2075. card->perf_stats.sg_alloc_page_rx++;
  2076. }
  2077. }
  2078. }
  2079. list_del_init(&entry->list);
  2080. return entry;
  2081. }
  2082. static int qeth_init_input_buffer(struct qeth_card *card,
  2083. struct qeth_qdio_buffer *buf)
  2084. {
  2085. struct qeth_buffer_pool_entry *pool_entry;
  2086. int i;
  2087. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2088. if (!pool_entry)
  2089. return 1;
  2090. /*
  2091. * since the buffer is accessed only from the input_tasklet
  2092. * there shouldn't be a need to synchronize; also, since we use
  2093. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2094. * buffers
  2095. */
  2096. buf->pool_entry = pool_entry;
  2097. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2098. buf->buffer->element[i].length = PAGE_SIZE;
  2099. buf->buffer->element[i].addr = pool_entry->elements[i];
  2100. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2101. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2102. else
  2103. buf->buffer->element[i].flags = 0;
  2104. }
  2105. return 0;
  2106. }
  2107. int qeth_init_qdio_queues(struct qeth_card *card)
  2108. {
  2109. int i, j;
  2110. int rc;
  2111. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2112. /* inbound queue */
  2113. memset(card->qdio.in_q->qdio_bufs, 0,
  2114. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2115. qeth_initialize_working_pool_list(card);
  2116. /*give only as many buffers to hardware as we have buffer pool entries*/
  2117. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2118. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2119. card->qdio.in_q->next_buf_to_init =
  2120. card->qdio.in_buf_pool.buf_count - 1;
  2121. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2122. card->qdio.in_buf_pool.buf_count - 1);
  2123. if (rc) {
  2124. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2125. return rc;
  2126. }
  2127. /* outbound queue */
  2128. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2129. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2130. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2131. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2132. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2133. &card->qdio.out_qs[i]->bufs[j]);
  2134. }
  2135. card->qdio.out_qs[i]->card = card;
  2136. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2137. card->qdio.out_qs[i]->do_pack = 0;
  2138. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2139. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2140. atomic_set(&card->qdio.out_qs[i]->state,
  2141. QETH_OUT_Q_UNLOCKED);
  2142. }
  2143. return 0;
  2144. }
  2145. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2146. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2147. {
  2148. switch (link_type) {
  2149. case QETH_LINK_TYPE_HSTR:
  2150. return 2;
  2151. default:
  2152. return 1;
  2153. }
  2154. }
  2155. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2156. struct qeth_ipa_cmd *cmd, __u8 command,
  2157. enum qeth_prot_versions prot)
  2158. {
  2159. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2160. cmd->hdr.command = command;
  2161. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2162. cmd->hdr.seqno = card->seqno.ipa;
  2163. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2164. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2165. if (card->options.layer2)
  2166. cmd->hdr.prim_version_no = 2;
  2167. else
  2168. cmd->hdr.prim_version_no = 1;
  2169. cmd->hdr.param_count = 1;
  2170. cmd->hdr.prot_version = prot;
  2171. cmd->hdr.ipa_supported = 0;
  2172. cmd->hdr.ipa_enabled = 0;
  2173. }
  2174. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2175. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2176. {
  2177. struct qeth_cmd_buffer *iob;
  2178. struct qeth_ipa_cmd *cmd;
  2179. iob = qeth_wait_for_buffer(&card->write);
  2180. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2181. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2182. return iob;
  2183. }
  2184. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2185. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2186. char prot_type)
  2187. {
  2188. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2189. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2190. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2191. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2192. }
  2193. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2194. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2195. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2196. unsigned long),
  2197. void *reply_param)
  2198. {
  2199. int rc;
  2200. char prot_type;
  2201. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2202. if (card->options.layer2)
  2203. if (card->info.type == QETH_CARD_TYPE_OSN)
  2204. prot_type = QETH_PROT_OSN2;
  2205. else
  2206. prot_type = QETH_PROT_LAYER2;
  2207. else
  2208. prot_type = QETH_PROT_TCPIP;
  2209. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2210. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2211. iob, reply_cb, reply_param);
  2212. return rc;
  2213. }
  2214. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2215. static int qeth_send_startstoplan(struct qeth_card *card,
  2216. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2217. {
  2218. int rc;
  2219. struct qeth_cmd_buffer *iob;
  2220. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2221. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2222. return rc;
  2223. }
  2224. int qeth_send_startlan(struct qeth_card *card)
  2225. {
  2226. int rc;
  2227. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2228. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2229. return rc;
  2230. }
  2231. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2232. int qeth_send_stoplan(struct qeth_card *card)
  2233. {
  2234. int rc = 0;
  2235. /*
  2236. * TODO: according to the IPA format document page 14,
  2237. * TCP/IP (we!) never issue a STOPLAN
  2238. * is this right ?!?
  2239. */
  2240. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2241. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2242. return rc;
  2243. }
  2244. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2245. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2246. struct qeth_reply *reply, unsigned long data)
  2247. {
  2248. struct qeth_ipa_cmd *cmd;
  2249. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2250. cmd = (struct qeth_ipa_cmd *) data;
  2251. if (cmd->hdr.return_code == 0)
  2252. cmd->hdr.return_code =
  2253. cmd->data.setadapterparms.hdr.return_code;
  2254. return 0;
  2255. }
  2256. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2257. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2258. struct qeth_reply *reply, unsigned long data)
  2259. {
  2260. struct qeth_ipa_cmd *cmd;
  2261. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2262. cmd = (struct qeth_ipa_cmd *) data;
  2263. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2264. card->info.link_type =
  2265. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2266. card->options.adp.supported_funcs =
  2267. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2268. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2269. }
  2270. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2271. __u32 command, __u32 cmdlen)
  2272. {
  2273. struct qeth_cmd_buffer *iob;
  2274. struct qeth_ipa_cmd *cmd;
  2275. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2276. QETH_PROT_IPV4);
  2277. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2278. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2279. cmd->data.setadapterparms.hdr.command_code = command;
  2280. cmd->data.setadapterparms.hdr.used_total = 1;
  2281. cmd->data.setadapterparms.hdr.seq_no = 1;
  2282. return iob;
  2283. }
  2284. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2285. int qeth_query_setadapterparms(struct qeth_card *card)
  2286. {
  2287. int rc;
  2288. struct qeth_cmd_buffer *iob;
  2289. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2290. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2291. sizeof(struct qeth_ipacmd_setadpparms));
  2292. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2293. return rc;
  2294. }
  2295. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2296. int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
  2297. const char *dbftext)
  2298. {
  2299. if (qdio_error) {
  2300. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2301. QETH_DBF_TEXT(QERR, 2, dbftext);
  2302. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2303. buf->element[15].flags & 0xff);
  2304. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2305. buf->element[14].flags & 0xff);
  2306. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2307. return 1;
  2308. }
  2309. return 0;
  2310. }
  2311. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2312. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2313. {
  2314. struct qeth_qdio_q *queue = card->qdio.in_q;
  2315. int count;
  2316. int i;
  2317. int rc;
  2318. int newcount = 0;
  2319. count = (index < queue->next_buf_to_init)?
  2320. card->qdio.in_buf_pool.buf_count -
  2321. (queue->next_buf_to_init - index) :
  2322. card->qdio.in_buf_pool.buf_count -
  2323. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2324. /* only requeue at a certain threshold to avoid SIGAs */
  2325. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2326. for (i = queue->next_buf_to_init;
  2327. i < queue->next_buf_to_init + count; ++i) {
  2328. if (qeth_init_input_buffer(card,
  2329. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2330. break;
  2331. } else {
  2332. newcount++;
  2333. }
  2334. }
  2335. if (newcount < count) {
  2336. /* we are in memory shortage so we switch back to
  2337. traditional skb allocation and drop packages */
  2338. atomic_set(&card->force_alloc_skb, 3);
  2339. count = newcount;
  2340. } else {
  2341. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2342. }
  2343. /*
  2344. * according to old code it should be avoided to requeue all
  2345. * 128 buffers in order to benefit from PCI avoidance.
  2346. * this function keeps at least one buffer (the buffer at
  2347. * 'index') un-requeued -> this buffer is the first buffer that
  2348. * will be requeued the next time
  2349. */
  2350. if (card->options.performance_stats) {
  2351. card->perf_stats.inbound_do_qdio_cnt++;
  2352. card->perf_stats.inbound_do_qdio_start_time =
  2353. qeth_get_micros();
  2354. }
  2355. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2356. queue->next_buf_to_init, count);
  2357. if (card->options.performance_stats)
  2358. card->perf_stats.inbound_do_qdio_time +=
  2359. qeth_get_micros() -
  2360. card->perf_stats.inbound_do_qdio_start_time;
  2361. if (rc) {
  2362. dev_warn(&card->gdev->dev,
  2363. "QDIO reported an error, rc=%i\n", rc);
  2364. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2365. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2366. }
  2367. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2368. QDIO_MAX_BUFFERS_PER_Q;
  2369. }
  2370. }
  2371. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2372. static int qeth_handle_send_error(struct qeth_card *card,
  2373. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2374. {
  2375. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2376. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2377. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2378. if (sbalf15 == 0) {
  2379. qdio_err = 0;
  2380. } else {
  2381. qdio_err = 1;
  2382. }
  2383. }
  2384. qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr");
  2385. if (!qdio_err)
  2386. return QETH_SEND_ERROR_NONE;
  2387. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2388. return QETH_SEND_ERROR_RETRY;
  2389. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2390. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2391. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2392. (u16)qdio_err, (u8)sbalf15);
  2393. return QETH_SEND_ERROR_LINK_FAILURE;
  2394. }
  2395. /*
  2396. * Switched to packing state if the number of used buffers on a queue
  2397. * reaches a certain limit.
  2398. */
  2399. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2400. {
  2401. if (!queue->do_pack) {
  2402. if (atomic_read(&queue->used_buffers)
  2403. >= QETH_HIGH_WATERMARK_PACK){
  2404. /* switch non-PACKING -> PACKING */
  2405. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2406. if (queue->card->options.performance_stats)
  2407. queue->card->perf_stats.sc_dp_p++;
  2408. queue->do_pack = 1;
  2409. }
  2410. }
  2411. }
  2412. /*
  2413. * Switches from packing to non-packing mode. If there is a packing
  2414. * buffer on the queue this buffer will be prepared to be flushed.
  2415. * In that case 1 is returned to inform the caller. If no buffer
  2416. * has to be flushed, zero is returned.
  2417. */
  2418. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2419. {
  2420. struct qeth_qdio_out_buffer *buffer;
  2421. int flush_count = 0;
  2422. if (queue->do_pack) {
  2423. if (atomic_read(&queue->used_buffers)
  2424. <= QETH_LOW_WATERMARK_PACK) {
  2425. /* switch PACKING -> non-PACKING */
  2426. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2427. if (queue->card->options.performance_stats)
  2428. queue->card->perf_stats.sc_p_dp++;
  2429. queue->do_pack = 0;
  2430. /* flush packing buffers */
  2431. buffer = &queue->bufs[queue->next_buf_to_fill];
  2432. if ((atomic_read(&buffer->state) ==
  2433. QETH_QDIO_BUF_EMPTY) &&
  2434. (buffer->next_element_to_fill > 0)) {
  2435. atomic_set(&buffer->state,
  2436. QETH_QDIO_BUF_PRIMED);
  2437. flush_count++;
  2438. queue->next_buf_to_fill =
  2439. (queue->next_buf_to_fill + 1) %
  2440. QDIO_MAX_BUFFERS_PER_Q;
  2441. }
  2442. }
  2443. }
  2444. return flush_count;
  2445. }
  2446. /*
  2447. * Called to flush a packing buffer if no more pci flags are on the queue.
  2448. * Checks if there is a packing buffer and prepares it to be flushed.
  2449. * In that case returns 1, otherwise zero.
  2450. */
  2451. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2452. {
  2453. struct qeth_qdio_out_buffer *buffer;
  2454. buffer = &queue->bufs[queue->next_buf_to_fill];
  2455. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2456. (buffer->next_element_to_fill > 0)) {
  2457. /* it's a packing buffer */
  2458. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2459. queue->next_buf_to_fill =
  2460. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2461. return 1;
  2462. }
  2463. return 0;
  2464. }
  2465. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2466. int count)
  2467. {
  2468. struct qeth_qdio_out_buffer *buf;
  2469. int rc;
  2470. int i;
  2471. unsigned int qdio_flags;
  2472. for (i = index; i < index + count; ++i) {
  2473. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2474. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2475. SBAL_FLAGS_LAST_ENTRY;
  2476. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2477. continue;
  2478. if (!queue->do_pack) {
  2479. if ((atomic_read(&queue->used_buffers) >=
  2480. (QETH_HIGH_WATERMARK_PACK -
  2481. QETH_WATERMARK_PACK_FUZZ)) &&
  2482. !atomic_read(&queue->set_pci_flags_count)) {
  2483. /* it's likely that we'll go to packing
  2484. * mode soon */
  2485. atomic_inc(&queue->set_pci_flags_count);
  2486. buf->buffer->element[0].flags |= 0x40;
  2487. }
  2488. } else {
  2489. if (!atomic_read(&queue->set_pci_flags_count)) {
  2490. /*
  2491. * there's no outstanding PCI any more, so we
  2492. * have to request a PCI to be sure the the PCI
  2493. * will wake at some time in the future then we
  2494. * can flush packed buffers that might still be
  2495. * hanging around, which can happen if no
  2496. * further send was requested by the stack
  2497. */
  2498. atomic_inc(&queue->set_pci_flags_count);
  2499. buf->buffer->element[0].flags |= 0x40;
  2500. }
  2501. }
  2502. }
  2503. queue->sync_iqdio_error = 0;
  2504. queue->card->dev->trans_start = jiffies;
  2505. if (queue->card->options.performance_stats) {
  2506. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2507. queue->card->perf_stats.outbound_do_qdio_start_time =
  2508. qeth_get_micros();
  2509. }
  2510. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2511. if (atomic_read(&queue->set_pci_flags_count))
  2512. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2513. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2514. queue->queue_no, index, count);
  2515. if (queue->card->options.performance_stats)
  2516. queue->card->perf_stats.outbound_do_qdio_time +=
  2517. qeth_get_micros() -
  2518. queue->card->perf_stats.outbound_do_qdio_start_time;
  2519. if (rc > 0) {
  2520. if (!(rc & QDIO_ERROR_SIGA_BUSY))
  2521. queue->sync_iqdio_error = rc & 3;
  2522. }
  2523. if (rc) {
  2524. queue->card->stats.tx_errors += count;
  2525. /* ignore temporary SIGA errors without busy condition */
  2526. if (rc == QDIO_ERROR_SIGA_TARGET)
  2527. return;
  2528. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2529. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2530. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2531. /* this must not happen under normal circumstances. if it
  2532. * happens something is really wrong -> recover */
  2533. qeth_schedule_recovery(queue->card);
  2534. return;
  2535. }
  2536. atomic_add(count, &queue->used_buffers);
  2537. if (queue->card->options.performance_stats)
  2538. queue->card->perf_stats.bufs_sent += count;
  2539. }
  2540. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2541. {
  2542. int index;
  2543. int flush_cnt = 0;
  2544. int q_was_packing = 0;
  2545. /*
  2546. * check if weed have to switch to non-packing mode or if
  2547. * we have to get a pci flag out on the queue
  2548. */
  2549. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2550. !atomic_read(&queue->set_pci_flags_count)) {
  2551. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2552. QETH_OUT_Q_UNLOCKED) {
  2553. /*
  2554. * If we get in here, there was no action in
  2555. * do_send_packet. So, we check if there is a
  2556. * packing buffer to be flushed here.
  2557. */
  2558. netif_stop_queue(queue->card->dev);
  2559. index = queue->next_buf_to_fill;
  2560. q_was_packing = queue->do_pack;
  2561. /* queue->do_pack may change */
  2562. barrier();
  2563. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2564. if (!flush_cnt &&
  2565. !atomic_read(&queue->set_pci_flags_count))
  2566. flush_cnt +=
  2567. qeth_flush_buffers_on_no_pci(queue);
  2568. if (queue->card->options.performance_stats &&
  2569. q_was_packing)
  2570. queue->card->perf_stats.bufs_sent_pack +=
  2571. flush_cnt;
  2572. if (flush_cnt)
  2573. qeth_flush_buffers(queue, index, flush_cnt);
  2574. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2575. }
  2576. }
  2577. }
  2578. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2579. unsigned int qdio_error, int __queue, int first_element,
  2580. int count, unsigned long card_ptr)
  2581. {
  2582. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2583. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2584. struct qeth_qdio_out_buffer *buffer;
  2585. int i;
  2586. unsigned qeth_send_err;
  2587. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2588. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2589. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2590. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2591. netif_stop_queue(card->dev);
  2592. qeth_schedule_recovery(card);
  2593. return;
  2594. }
  2595. if (card->options.performance_stats) {
  2596. card->perf_stats.outbound_handler_cnt++;
  2597. card->perf_stats.outbound_handler_start_time =
  2598. qeth_get_micros();
  2599. }
  2600. for (i = first_element; i < (first_element + count); ++i) {
  2601. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2602. qeth_send_err = qeth_handle_send_error(card, buffer, qdio_error);
  2603. __qeth_clear_output_buffer(queue, buffer,
  2604. (qeth_send_err == QETH_SEND_ERROR_RETRY) ? 1 : 0);
  2605. }
  2606. atomic_sub(count, &queue->used_buffers);
  2607. /* check if we need to do something on this outbound queue */
  2608. if (card->info.type != QETH_CARD_TYPE_IQD)
  2609. qeth_check_outbound_queue(queue);
  2610. netif_wake_queue(queue->card->dev);
  2611. if (card->options.performance_stats)
  2612. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2613. card->perf_stats.outbound_handler_start_time;
  2614. }
  2615. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2616. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2617. int ipv, int cast_type)
  2618. {
  2619. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2620. return card->qdio.default_out_queue;
  2621. switch (card->qdio.no_out_queues) {
  2622. case 4:
  2623. if (cast_type && card->info.is_multicast_different)
  2624. return card->info.is_multicast_different &
  2625. (card->qdio.no_out_queues - 1);
  2626. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2627. const u8 tos = ip_hdr(skb)->tos;
  2628. if (card->qdio.do_prio_queueing ==
  2629. QETH_PRIO_Q_ING_TOS) {
  2630. if (tos & IP_TOS_NOTIMPORTANT)
  2631. return 3;
  2632. if (tos & IP_TOS_HIGHRELIABILITY)
  2633. return 2;
  2634. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2635. return 1;
  2636. if (tos & IP_TOS_LOWDELAY)
  2637. return 0;
  2638. }
  2639. if (card->qdio.do_prio_queueing ==
  2640. QETH_PRIO_Q_ING_PREC)
  2641. return 3 - (tos >> 6);
  2642. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2643. /* TODO: IPv6!!! */
  2644. }
  2645. return card->qdio.default_out_queue;
  2646. case 1: /* fallthrough for single-out-queue 1920-device */
  2647. default:
  2648. return card->qdio.default_out_queue;
  2649. }
  2650. }
  2651. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2652. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2653. struct sk_buff *skb, int elems)
  2654. {
  2655. int elements_needed = 0;
  2656. if (skb_shinfo(skb)->nr_frags > 0)
  2657. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2658. if (elements_needed == 0)
  2659. elements_needed = 1 + (((((unsigned long) skb->data) %
  2660. PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
  2661. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2662. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2663. "(Number=%d / Length=%d). Discarded.\n",
  2664. (elements_needed+elems), skb->len);
  2665. return 0;
  2666. }
  2667. return elements_needed;
  2668. }
  2669. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2670. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2671. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2672. int offset)
  2673. {
  2674. int length = skb->len;
  2675. int length_here;
  2676. int element;
  2677. char *data;
  2678. int first_lap ;
  2679. element = *next_element_to_fill;
  2680. data = skb->data;
  2681. first_lap = (is_tso == 0 ? 1 : 0);
  2682. if (offset >= 0) {
  2683. data = skb->data + offset;
  2684. length -= offset;
  2685. first_lap = 0;
  2686. }
  2687. while (length > 0) {
  2688. /* length_here is the remaining amount of data in this page */
  2689. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2690. if (length < length_here)
  2691. length_here = length;
  2692. buffer->element[element].addr = data;
  2693. buffer->element[element].length = length_here;
  2694. length -= length_here;
  2695. if (!length) {
  2696. if (first_lap)
  2697. buffer->element[element].flags = 0;
  2698. else
  2699. buffer->element[element].flags =
  2700. SBAL_FLAGS_LAST_FRAG;
  2701. } else {
  2702. if (first_lap)
  2703. buffer->element[element].flags =
  2704. SBAL_FLAGS_FIRST_FRAG;
  2705. else
  2706. buffer->element[element].flags =
  2707. SBAL_FLAGS_MIDDLE_FRAG;
  2708. }
  2709. data += length_here;
  2710. element++;
  2711. first_lap = 0;
  2712. }
  2713. *next_element_to_fill = element;
  2714. }
  2715. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2716. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2717. struct qeth_hdr *hdr, int offset, int hd_len)
  2718. {
  2719. struct qdio_buffer *buffer;
  2720. int flush_cnt = 0, hdr_len, large_send = 0;
  2721. buffer = buf->buffer;
  2722. atomic_inc(&skb->users);
  2723. skb_queue_tail(&buf->skb_list, skb);
  2724. /*check first on TSO ....*/
  2725. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2726. int element = buf->next_element_to_fill;
  2727. hdr_len = sizeof(struct qeth_hdr_tso) +
  2728. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2729. /*fill first buffer entry only with header information */
  2730. buffer->element[element].addr = skb->data;
  2731. buffer->element[element].length = hdr_len;
  2732. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2733. buf->next_element_to_fill++;
  2734. skb->data += hdr_len;
  2735. skb->len -= hdr_len;
  2736. large_send = 1;
  2737. }
  2738. if (offset >= 0) {
  2739. int element = buf->next_element_to_fill;
  2740. buffer->element[element].addr = hdr;
  2741. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2742. hd_len;
  2743. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2744. buf->is_header[element] = 1;
  2745. buf->next_element_to_fill++;
  2746. }
  2747. if (skb_shinfo(skb)->nr_frags == 0)
  2748. __qeth_fill_buffer(skb, buffer, large_send,
  2749. (int *)&buf->next_element_to_fill, offset);
  2750. else
  2751. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2752. (int *)&buf->next_element_to_fill);
  2753. if (!queue->do_pack) {
  2754. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2755. /* set state to PRIMED -> will be flushed */
  2756. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2757. flush_cnt = 1;
  2758. } else {
  2759. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2760. if (queue->card->options.performance_stats)
  2761. queue->card->perf_stats.skbs_sent_pack++;
  2762. if (buf->next_element_to_fill >=
  2763. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2764. /*
  2765. * packed buffer if full -> set state PRIMED
  2766. * -> will be flushed
  2767. */
  2768. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2769. flush_cnt = 1;
  2770. }
  2771. }
  2772. return flush_cnt;
  2773. }
  2774. int qeth_do_send_packet_fast(struct qeth_card *card,
  2775. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2776. struct qeth_hdr *hdr, int elements_needed,
  2777. int offset, int hd_len)
  2778. {
  2779. struct qeth_qdio_out_buffer *buffer;
  2780. struct sk_buff *skb1;
  2781. struct qeth_skb_data *retry_ctrl;
  2782. int index;
  2783. int rc;
  2784. /* spin until we get the queue ... */
  2785. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2786. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2787. /* ... now we've got the queue */
  2788. index = queue->next_buf_to_fill;
  2789. buffer = &queue->bufs[queue->next_buf_to_fill];
  2790. /*
  2791. * check if buffer is empty to make sure that we do not 'overtake'
  2792. * ourselves and try to fill a buffer that is already primed
  2793. */
  2794. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2795. goto out;
  2796. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2797. QDIO_MAX_BUFFERS_PER_Q;
  2798. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2799. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2800. qeth_flush_buffers(queue, index, 1);
  2801. if (queue->sync_iqdio_error == 2) {
  2802. skb1 = skb_dequeue(&buffer->skb_list);
  2803. while (skb1) {
  2804. atomic_dec(&skb1->users);
  2805. skb1 = skb_dequeue(&buffer->skb_list);
  2806. }
  2807. retry_ctrl = (struct qeth_skb_data *) &skb->cb[16];
  2808. if (retry_ctrl->magic != QETH_SKB_MAGIC) {
  2809. retry_ctrl->magic = QETH_SKB_MAGIC;
  2810. retry_ctrl->count = 0;
  2811. }
  2812. if (retry_ctrl->count < QETH_SIGA_CC2_RETRIES) {
  2813. retry_ctrl->count++;
  2814. rc = dev_queue_xmit(skb);
  2815. } else {
  2816. dev_kfree_skb_any(skb);
  2817. QETH_DBF_TEXT(QERR, 2, "qrdrop");
  2818. }
  2819. }
  2820. return 0;
  2821. out:
  2822. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2823. return -EBUSY;
  2824. }
  2825. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2826. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2827. struct sk_buff *skb, struct qeth_hdr *hdr,
  2828. int elements_needed)
  2829. {
  2830. struct qeth_qdio_out_buffer *buffer;
  2831. int start_index;
  2832. int flush_count = 0;
  2833. int do_pack = 0;
  2834. int tmp;
  2835. int rc = 0;
  2836. /* spin until we get the queue ... */
  2837. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2838. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2839. start_index = queue->next_buf_to_fill;
  2840. buffer = &queue->bufs[queue->next_buf_to_fill];
  2841. /*
  2842. * check if buffer is empty to make sure that we do not 'overtake'
  2843. * ourselves and try to fill a buffer that is already primed
  2844. */
  2845. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2846. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2847. return -EBUSY;
  2848. }
  2849. /* check if we need to switch packing state of this queue */
  2850. qeth_switch_to_packing_if_needed(queue);
  2851. if (queue->do_pack) {
  2852. do_pack = 1;
  2853. /* does packet fit in current buffer? */
  2854. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2855. buffer->next_element_to_fill) < elements_needed) {
  2856. /* ... no -> set state PRIMED */
  2857. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2858. flush_count++;
  2859. queue->next_buf_to_fill =
  2860. (queue->next_buf_to_fill + 1) %
  2861. QDIO_MAX_BUFFERS_PER_Q;
  2862. buffer = &queue->bufs[queue->next_buf_to_fill];
  2863. /* we did a step forward, so check buffer state
  2864. * again */
  2865. if (atomic_read(&buffer->state) !=
  2866. QETH_QDIO_BUF_EMPTY) {
  2867. qeth_flush_buffers(queue, start_index,
  2868. flush_count);
  2869. atomic_set(&queue->state,
  2870. QETH_OUT_Q_UNLOCKED);
  2871. return -EBUSY;
  2872. }
  2873. }
  2874. }
  2875. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2876. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2877. QDIO_MAX_BUFFERS_PER_Q;
  2878. flush_count += tmp;
  2879. if (flush_count)
  2880. qeth_flush_buffers(queue, start_index, flush_count);
  2881. else if (!atomic_read(&queue->set_pci_flags_count))
  2882. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2883. /*
  2884. * queue->state will go from LOCKED -> UNLOCKED or from
  2885. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2886. * (switch packing state or flush buffer to get another pci flag out).
  2887. * In that case we will enter this loop
  2888. */
  2889. while (atomic_dec_return(&queue->state)) {
  2890. flush_count = 0;
  2891. start_index = queue->next_buf_to_fill;
  2892. /* check if we can go back to non-packing state */
  2893. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2894. /*
  2895. * check if we need to flush a packing buffer to get a pci
  2896. * flag out on the queue
  2897. */
  2898. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2899. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2900. if (flush_count)
  2901. qeth_flush_buffers(queue, start_index, flush_count);
  2902. }
  2903. /* at this point the queue is UNLOCKED again */
  2904. if (queue->card->options.performance_stats && do_pack)
  2905. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2906. return rc;
  2907. }
  2908. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2909. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2910. struct qeth_reply *reply, unsigned long data)
  2911. {
  2912. struct qeth_ipa_cmd *cmd;
  2913. struct qeth_ipacmd_setadpparms *setparms;
  2914. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  2915. cmd = (struct qeth_ipa_cmd *) data;
  2916. setparms = &(cmd->data.setadapterparms);
  2917. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2918. if (cmd->hdr.return_code) {
  2919. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2920. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2921. }
  2922. card->info.promisc_mode = setparms->data.mode;
  2923. return 0;
  2924. }
  2925. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2926. {
  2927. enum qeth_ipa_promisc_modes mode;
  2928. struct net_device *dev = card->dev;
  2929. struct qeth_cmd_buffer *iob;
  2930. struct qeth_ipa_cmd *cmd;
  2931. QETH_DBF_TEXT(TRACE, 4, "setprom");
  2932. if (((dev->flags & IFF_PROMISC) &&
  2933. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2934. (!(dev->flags & IFF_PROMISC) &&
  2935. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2936. return;
  2937. mode = SET_PROMISC_MODE_OFF;
  2938. if (dev->flags & IFF_PROMISC)
  2939. mode = SET_PROMISC_MODE_ON;
  2940. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  2941. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  2942. sizeof(struct qeth_ipacmd_setadpparms));
  2943. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  2944. cmd->data.setadapterparms.data.mode = mode;
  2945. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  2946. }
  2947. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  2948. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  2949. {
  2950. struct qeth_card *card;
  2951. char dbf_text[15];
  2952. card = dev->ml_priv;
  2953. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  2954. sprintf(dbf_text, "%8x", new_mtu);
  2955. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  2956. if (new_mtu < 64)
  2957. return -EINVAL;
  2958. if (new_mtu > 65535)
  2959. return -EINVAL;
  2960. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  2961. (!qeth_mtu_is_valid(card, new_mtu)))
  2962. return -EINVAL;
  2963. dev->mtu = new_mtu;
  2964. return 0;
  2965. }
  2966. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  2967. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  2968. {
  2969. struct qeth_card *card;
  2970. card = dev->ml_priv;
  2971. QETH_DBF_TEXT(TRACE, 5, "getstat");
  2972. return &card->stats;
  2973. }
  2974. EXPORT_SYMBOL_GPL(qeth_get_stats);
  2975. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  2976. struct qeth_reply *reply, unsigned long data)
  2977. {
  2978. struct qeth_ipa_cmd *cmd;
  2979. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  2980. cmd = (struct qeth_ipa_cmd *) data;
  2981. if (!card->options.layer2 ||
  2982. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  2983. memcpy(card->dev->dev_addr,
  2984. &cmd->data.setadapterparms.data.change_addr.addr,
  2985. OSA_ADDR_LEN);
  2986. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  2987. }
  2988. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  2989. return 0;
  2990. }
  2991. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  2992. {
  2993. int rc;
  2994. struct qeth_cmd_buffer *iob;
  2995. struct qeth_ipa_cmd *cmd;
  2996. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  2997. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  2998. sizeof(struct qeth_ipacmd_setadpparms));
  2999. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3000. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3001. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3002. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3003. card->dev->dev_addr, OSA_ADDR_LEN);
  3004. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3005. NULL);
  3006. return rc;
  3007. }
  3008. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3009. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3010. struct qeth_reply *reply, unsigned long data)
  3011. {
  3012. struct qeth_ipa_cmd *cmd;
  3013. struct qeth_set_access_ctrl *access_ctrl_req;
  3014. int rc;
  3015. QETH_DBF_TEXT(TRACE, 4, "setaccb");
  3016. cmd = (struct qeth_ipa_cmd *) data;
  3017. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3018. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3019. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3020. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3021. cmd->data.setadapterparms.hdr.return_code);
  3022. switch (cmd->data.setadapterparms.hdr.return_code) {
  3023. case SET_ACCESS_CTRL_RC_SUCCESS:
  3024. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3025. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3026. {
  3027. card->options.isolation = access_ctrl_req->subcmd_code;
  3028. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3029. dev_info(&card->gdev->dev,
  3030. "QDIO data connection isolation is deactivated\n");
  3031. } else {
  3032. dev_info(&card->gdev->dev,
  3033. "QDIO data connection isolation is activated\n");
  3034. }
  3035. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3036. card->gdev->dev.kobj.name,
  3037. access_ctrl_req->subcmd_code,
  3038. cmd->data.setadapterparms.hdr.return_code);
  3039. rc = 0;
  3040. break;
  3041. }
  3042. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3043. {
  3044. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3045. card->gdev->dev.kobj.name,
  3046. access_ctrl_req->subcmd_code,
  3047. cmd->data.setadapterparms.hdr.return_code);
  3048. dev_err(&card->gdev->dev, "Adapter does not "
  3049. "support QDIO data connection isolation\n");
  3050. /* ensure isolation mode is "none" */
  3051. card->options.isolation = ISOLATION_MODE_NONE;
  3052. rc = -EOPNOTSUPP;
  3053. break;
  3054. }
  3055. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3056. {
  3057. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3058. card->gdev->dev.kobj.name,
  3059. access_ctrl_req->subcmd_code,
  3060. cmd->data.setadapterparms.hdr.return_code);
  3061. dev_err(&card->gdev->dev,
  3062. "Adapter is dedicated. "
  3063. "QDIO data connection isolation not supported\n");
  3064. /* ensure isolation mode is "none" */
  3065. card->options.isolation = ISOLATION_MODE_NONE;
  3066. rc = -EOPNOTSUPP;
  3067. break;
  3068. }
  3069. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3070. {
  3071. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3072. card->gdev->dev.kobj.name,
  3073. access_ctrl_req->subcmd_code,
  3074. cmd->data.setadapterparms.hdr.return_code);
  3075. dev_err(&card->gdev->dev,
  3076. "TSO does not permit QDIO data connection isolation\n");
  3077. /* ensure isolation mode is "none" */
  3078. card->options.isolation = ISOLATION_MODE_NONE;
  3079. rc = -EPERM;
  3080. break;
  3081. }
  3082. default:
  3083. {
  3084. /* this should never happen */
  3085. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3086. "==UNKNOWN\n",
  3087. card->gdev->dev.kobj.name,
  3088. access_ctrl_req->subcmd_code,
  3089. cmd->data.setadapterparms.hdr.return_code);
  3090. /* ensure isolation mode is "none" */
  3091. card->options.isolation = ISOLATION_MODE_NONE;
  3092. rc = 0;
  3093. break;
  3094. }
  3095. }
  3096. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3097. return rc;
  3098. }
  3099. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3100. enum qeth_ipa_isolation_modes isolation)
  3101. {
  3102. int rc;
  3103. struct qeth_cmd_buffer *iob;
  3104. struct qeth_ipa_cmd *cmd;
  3105. struct qeth_set_access_ctrl *access_ctrl_req;
  3106. QETH_DBF_TEXT(TRACE, 4, "setacctl");
  3107. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3108. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3109. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3110. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3111. sizeof(struct qeth_set_access_ctrl));
  3112. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3113. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3114. access_ctrl_req->subcmd_code = isolation;
  3115. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3116. NULL);
  3117. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3118. return rc;
  3119. }
  3120. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3121. {
  3122. int rc = 0;
  3123. QETH_DBF_TEXT(TRACE, 4, "setactlo");
  3124. if (card->info.type == QETH_CARD_TYPE_OSAE &&
  3125. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3126. rc = qeth_setadpparms_set_access_ctrl(card,
  3127. card->options.isolation);
  3128. if (rc) {
  3129. QETH_DBF_MESSAGE(3,
  3130. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed",
  3131. card->gdev->dev.kobj.name,
  3132. rc);
  3133. }
  3134. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3135. card->options.isolation = ISOLATION_MODE_NONE;
  3136. dev_err(&card->gdev->dev, "Adapter does not "
  3137. "support QDIO data connection isolation\n");
  3138. rc = -EOPNOTSUPP;
  3139. }
  3140. return rc;
  3141. }
  3142. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3143. void qeth_tx_timeout(struct net_device *dev)
  3144. {
  3145. struct qeth_card *card;
  3146. card = dev->ml_priv;
  3147. card->stats.tx_errors++;
  3148. qeth_schedule_recovery(card);
  3149. }
  3150. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3151. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3152. {
  3153. struct qeth_card *card = dev->ml_priv;
  3154. int rc = 0;
  3155. switch (regnum) {
  3156. case MII_BMCR: /* Basic mode control register */
  3157. rc = BMCR_FULLDPLX;
  3158. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3159. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3160. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3161. rc |= BMCR_SPEED100;
  3162. break;
  3163. case MII_BMSR: /* Basic mode status register */
  3164. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3165. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3166. BMSR_100BASE4;
  3167. break;
  3168. case MII_PHYSID1: /* PHYS ID 1 */
  3169. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3170. dev->dev_addr[2];
  3171. rc = (rc >> 5) & 0xFFFF;
  3172. break;
  3173. case MII_PHYSID2: /* PHYS ID 2 */
  3174. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3175. break;
  3176. case MII_ADVERTISE: /* Advertisement control reg */
  3177. rc = ADVERTISE_ALL;
  3178. break;
  3179. case MII_LPA: /* Link partner ability reg */
  3180. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3181. LPA_100BASE4 | LPA_LPACK;
  3182. break;
  3183. case MII_EXPANSION: /* Expansion register */
  3184. break;
  3185. case MII_DCOUNTER: /* disconnect counter */
  3186. break;
  3187. case MII_FCSCOUNTER: /* false carrier counter */
  3188. break;
  3189. case MII_NWAYTEST: /* N-way auto-neg test register */
  3190. break;
  3191. case MII_RERRCOUNTER: /* rx error counter */
  3192. rc = card->stats.rx_errors;
  3193. break;
  3194. case MII_SREVISION: /* silicon revision */
  3195. break;
  3196. case MII_RESV1: /* reserved 1 */
  3197. break;
  3198. case MII_LBRERROR: /* loopback, rx, bypass error */
  3199. break;
  3200. case MII_PHYADDR: /* physical address */
  3201. break;
  3202. case MII_RESV2: /* reserved 2 */
  3203. break;
  3204. case MII_TPISTATUS: /* TPI status for 10mbps */
  3205. break;
  3206. case MII_NCONFIG: /* network interface config */
  3207. break;
  3208. default:
  3209. break;
  3210. }
  3211. return rc;
  3212. }
  3213. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3214. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3215. struct qeth_cmd_buffer *iob, int len,
  3216. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3217. unsigned long),
  3218. void *reply_param)
  3219. {
  3220. u16 s1, s2;
  3221. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3222. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3223. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3224. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3225. /* adjust PDU length fields in IPA_PDU_HEADER */
  3226. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3227. s2 = (u32) len;
  3228. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3229. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3230. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3231. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3232. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3233. reply_cb, reply_param);
  3234. }
  3235. static int qeth_snmp_command_cb(struct qeth_card *card,
  3236. struct qeth_reply *reply, unsigned long sdata)
  3237. {
  3238. struct qeth_ipa_cmd *cmd;
  3239. struct qeth_arp_query_info *qinfo;
  3240. struct qeth_snmp_cmd *snmp;
  3241. unsigned char *data;
  3242. __u16 data_len;
  3243. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3244. cmd = (struct qeth_ipa_cmd *) sdata;
  3245. data = (unsigned char *)((char *)cmd - reply->offset);
  3246. qinfo = (struct qeth_arp_query_info *) reply->param;
  3247. snmp = &cmd->data.setadapterparms.data.snmp;
  3248. if (cmd->hdr.return_code) {
  3249. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3250. return 0;
  3251. }
  3252. if (cmd->data.setadapterparms.hdr.return_code) {
  3253. cmd->hdr.return_code =
  3254. cmd->data.setadapterparms.hdr.return_code;
  3255. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3256. return 0;
  3257. }
  3258. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3259. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3260. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3261. else
  3262. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3263. /* check if there is enough room in userspace */
  3264. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3265. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3266. cmd->hdr.return_code = -ENOMEM;
  3267. return 0;
  3268. }
  3269. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3270. cmd->data.setadapterparms.hdr.used_total);
  3271. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3272. cmd->data.setadapterparms.hdr.seq_no);
  3273. /*copy entries to user buffer*/
  3274. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3275. memcpy(qinfo->udata + qinfo->udata_offset,
  3276. (char *)snmp,
  3277. data_len + offsetof(struct qeth_snmp_cmd, data));
  3278. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3279. } else {
  3280. memcpy(qinfo->udata + qinfo->udata_offset,
  3281. (char *)&snmp->request, data_len);
  3282. }
  3283. qinfo->udata_offset += data_len;
  3284. /* check if all replies received ... */
  3285. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3286. cmd->data.setadapterparms.hdr.used_total);
  3287. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3288. cmd->data.setadapterparms.hdr.seq_no);
  3289. if (cmd->data.setadapterparms.hdr.seq_no <
  3290. cmd->data.setadapterparms.hdr.used_total)
  3291. return 1;
  3292. return 0;
  3293. }
  3294. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3295. {
  3296. struct qeth_cmd_buffer *iob;
  3297. struct qeth_ipa_cmd *cmd;
  3298. struct qeth_snmp_ureq *ureq;
  3299. int req_len;
  3300. struct qeth_arp_query_info qinfo = {0, };
  3301. int rc = 0;
  3302. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3303. if (card->info.guestlan)
  3304. return -EOPNOTSUPP;
  3305. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3306. (!card->options.layer2)) {
  3307. return -EOPNOTSUPP;
  3308. }
  3309. /* skip 4 bytes (data_len struct member) to get req_len */
  3310. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3311. return -EFAULT;
  3312. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3313. if (!ureq) {
  3314. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3315. return -ENOMEM;
  3316. }
  3317. if (copy_from_user(ureq, udata,
  3318. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3319. kfree(ureq);
  3320. return -EFAULT;
  3321. }
  3322. qinfo.udata_len = ureq->hdr.data_len;
  3323. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3324. if (!qinfo.udata) {
  3325. kfree(ureq);
  3326. return -ENOMEM;
  3327. }
  3328. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3329. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3330. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3331. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3332. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3333. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3334. qeth_snmp_command_cb, (void *)&qinfo);
  3335. if (rc)
  3336. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3337. QETH_CARD_IFNAME(card), rc);
  3338. else {
  3339. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3340. rc = -EFAULT;
  3341. }
  3342. kfree(ureq);
  3343. kfree(qinfo.udata);
  3344. return rc;
  3345. }
  3346. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3347. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3348. {
  3349. switch (card->info.type) {
  3350. case QETH_CARD_TYPE_IQD:
  3351. return 2;
  3352. default:
  3353. return 0;
  3354. }
  3355. }
  3356. static int qeth_qdio_establish(struct qeth_card *card)
  3357. {
  3358. struct qdio_initialize init_data;
  3359. char *qib_param_field;
  3360. struct qdio_buffer **in_sbal_ptrs;
  3361. struct qdio_buffer **out_sbal_ptrs;
  3362. int i, j, k;
  3363. int rc = 0;
  3364. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3365. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3366. GFP_KERNEL);
  3367. if (!qib_param_field)
  3368. return -ENOMEM;
  3369. qeth_create_qib_param_field(card, qib_param_field);
  3370. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3371. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3372. GFP_KERNEL);
  3373. if (!in_sbal_ptrs) {
  3374. kfree(qib_param_field);
  3375. return -ENOMEM;
  3376. }
  3377. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3378. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3379. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3380. out_sbal_ptrs =
  3381. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3382. sizeof(void *), GFP_KERNEL);
  3383. if (!out_sbal_ptrs) {
  3384. kfree(in_sbal_ptrs);
  3385. kfree(qib_param_field);
  3386. return -ENOMEM;
  3387. }
  3388. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3389. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3390. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3391. card->qdio.out_qs[i]->bufs[j].buffer);
  3392. }
  3393. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3394. init_data.cdev = CARD_DDEV(card);
  3395. init_data.q_format = qeth_get_qdio_q_format(card);
  3396. init_data.qib_param_field_format = 0;
  3397. init_data.qib_param_field = qib_param_field;
  3398. init_data.no_input_qs = 1;
  3399. init_data.no_output_qs = card->qdio.no_out_queues;
  3400. init_data.input_handler = card->discipline.input_handler;
  3401. init_data.output_handler = card->discipline.output_handler;
  3402. init_data.int_parm = (unsigned long) card;
  3403. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3404. QDIO_OUTBOUND_0COPY_SBALS |
  3405. QDIO_USE_OUTBOUND_PCIS;
  3406. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3407. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3408. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3409. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3410. rc = qdio_initialize(&init_data);
  3411. if (rc)
  3412. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3413. }
  3414. kfree(out_sbal_ptrs);
  3415. kfree(in_sbal_ptrs);
  3416. kfree(qib_param_field);
  3417. return rc;
  3418. }
  3419. static void qeth_core_free_card(struct qeth_card *card)
  3420. {
  3421. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3422. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3423. qeth_clean_channel(&card->read);
  3424. qeth_clean_channel(&card->write);
  3425. if (card->dev)
  3426. free_netdev(card->dev);
  3427. kfree(card->ip_tbd_list);
  3428. qeth_free_qdio_buffers(card);
  3429. unregister_service_level(&card->qeth_service_level);
  3430. kfree(card);
  3431. }
  3432. static struct ccw_device_id qeth_ids[] = {
  3433. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3434. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3435. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3436. {},
  3437. };
  3438. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3439. static struct ccw_driver qeth_ccw_driver = {
  3440. .name = "qeth",
  3441. .ids = qeth_ids,
  3442. .probe = ccwgroup_probe_ccwdev,
  3443. .remove = ccwgroup_remove_ccwdev,
  3444. };
  3445. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3446. unsigned long driver_id)
  3447. {
  3448. return ccwgroup_create_from_string(root_dev, driver_id,
  3449. &qeth_ccw_driver, 3, buf);
  3450. }
  3451. int qeth_core_hardsetup_card(struct qeth_card *card)
  3452. {
  3453. struct qdio_ssqd_desc *ssqd;
  3454. int retries = 0;
  3455. int mpno = 0;
  3456. int rc;
  3457. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3458. atomic_set(&card->force_alloc_skb, 0);
  3459. retry:
  3460. if (retries)
  3461. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3462. dev_name(&card->gdev->dev));
  3463. ccw_device_set_offline(CARD_DDEV(card));
  3464. ccw_device_set_offline(CARD_WDEV(card));
  3465. ccw_device_set_offline(CARD_RDEV(card));
  3466. rc = ccw_device_set_online(CARD_RDEV(card));
  3467. if (rc)
  3468. goto retriable;
  3469. rc = ccw_device_set_online(CARD_WDEV(card));
  3470. if (rc)
  3471. goto retriable;
  3472. rc = ccw_device_set_online(CARD_DDEV(card));
  3473. if (rc)
  3474. goto retriable;
  3475. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3476. retriable:
  3477. if (rc == -ERESTARTSYS) {
  3478. QETH_DBF_TEXT(SETUP, 2, "break1");
  3479. return rc;
  3480. } else if (rc) {
  3481. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3482. if (++retries > 3)
  3483. goto out;
  3484. else
  3485. goto retry;
  3486. }
  3487. rc = qeth_get_unitaddr(card);
  3488. if (rc) {
  3489. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3490. return rc;
  3491. }
  3492. ssqd = kmalloc(sizeof(struct qdio_ssqd_desc), GFP_KERNEL);
  3493. if (!ssqd) {
  3494. rc = -ENOMEM;
  3495. goto out;
  3496. }
  3497. rc = qdio_get_ssqd_desc(CARD_DDEV(card), ssqd);
  3498. if (rc == 0)
  3499. mpno = ssqd->pcnt;
  3500. kfree(ssqd);
  3501. if (mpno)
  3502. mpno = min(mpno - 1, QETH_MAX_PORTNO);
  3503. if (card->info.portno > mpno) {
  3504. QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d"
  3505. "\n.", CARD_BUS_ID(card), card->info.portno);
  3506. rc = -ENODEV;
  3507. goto out;
  3508. }
  3509. qeth_init_tokens(card);
  3510. qeth_init_func_level(card);
  3511. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3512. if (rc == -ERESTARTSYS) {
  3513. QETH_DBF_TEXT(SETUP, 2, "break2");
  3514. return rc;
  3515. } else if (rc) {
  3516. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3517. if (--retries < 0)
  3518. goto out;
  3519. else
  3520. goto retry;
  3521. }
  3522. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3523. if (rc == -ERESTARTSYS) {
  3524. QETH_DBF_TEXT(SETUP, 2, "break3");
  3525. return rc;
  3526. } else if (rc) {
  3527. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3528. if (--retries < 0)
  3529. goto out;
  3530. else
  3531. goto retry;
  3532. }
  3533. rc = qeth_mpc_initialize(card);
  3534. if (rc) {
  3535. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3536. goto out;
  3537. }
  3538. return 0;
  3539. out:
  3540. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3541. "an error on the device\n");
  3542. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3543. dev_name(&card->gdev->dev), rc);
  3544. return rc;
  3545. }
  3546. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3547. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3548. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3549. {
  3550. struct page *page = virt_to_page(element->addr);
  3551. if (*pskb == NULL) {
  3552. /* the upper protocol layers assume that there is data in the
  3553. * skb itself. Copy a small amount (64 bytes) to make them
  3554. * happy. */
  3555. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3556. if (!(*pskb))
  3557. return -ENOMEM;
  3558. skb_reserve(*pskb, ETH_HLEN);
  3559. if (data_len <= 64) {
  3560. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3561. data_len);
  3562. } else {
  3563. get_page(page);
  3564. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3565. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3566. data_len - 64);
  3567. (*pskb)->data_len += data_len - 64;
  3568. (*pskb)->len += data_len - 64;
  3569. (*pskb)->truesize += data_len - 64;
  3570. (*pfrag)++;
  3571. }
  3572. } else {
  3573. get_page(page);
  3574. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3575. (*pskb)->data_len += data_len;
  3576. (*pskb)->len += data_len;
  3577. (*pskb)->truesize += data_len;
  3578. (*pfrag)++;
  3579. }
  3580. return 0;
  3581. }
  3582. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3583. struct qdio_buffer *buffer,
  3584. struct qdio_buffer_element **__element, int *__offset,
  3585. struct qeth_hdr **hdr)
  3586. {
  3587. struct qdio_buffer_element *element = *__element;
  3588. int offset = *__offset;
  3589. struct sk_buff *skb = NULL;
  3590. int skb_len;
  3591. void *data_ptr;
  3592. int data_len;
  3593. int headroom = 0;
  3594. int use_rx_sg = 0;
  3595. int frag = 0;
  3596. /* qeth_hdr must not cross element boundaries */
  3597. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3598. if (qeth_is_last_sbale(element))
  3599. return NULL;
  3600. element++;
  3601. offset = 0;
  3602. if (element->length < sizeof(struct qeth_hdr))
  3603. return NULL;
  3604. }
  3605. *hdr = element->addr + offset;
  3606. offset += sizeof(struct qeth_hdr);
  3607. if (card->options.layer2) {
  3608. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3609. skb_len = (*hdr)->hdr.osn.pdu_length;
  3610. headroom = sizeof(struct qeth_hdr);
  3611. } else {
  3612. skb_len = (*hdr)->hdr.l2.pkt_length;
  3613. }
  3614. } else {
  3615. skb_len = (*hdr)->hdr.l3.length;
  3616. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3617. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3618. headroom = TR_HLEN;
  3619. else
  3620. headroom = ETH_HLEN;
  3621. }
  3622. if (!skb_len)
  3623. return NULL;
  3624. if ((skb_len >= card->options.rx_sg_cb) &&
  3625. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3626. (!atomic_read(&card->force_alloc_skb))) {
  3627. use_rx_sg = 1;
  3628. } else {
  3629. skb = dev_alloc_skb(skb_len + headroom);
  3630. if (!skb)
  3631. goto no_mem;
  3632. if (headroom)
  3633. skb_reserve(skb, headroom);
  3634. }
  3635. data_ptr = element->addr + offset;
  3636. while (skb_len) {
  3637. data_len = min(skb_len, (int)(element->length - offset));
  3638. if (data_len) {
  3639. if (use_rx_sg) {
  3640. if (qeth_create_skb_frag(element, &skb, offset,
  3641. &frag, data_len))
  3642. goto no_mem;
  3643. } else {
  3644. memcpy(skb_put(skb, data_len), data_ptr,
  3645. data_len);
  3646. }
  3647. }
  3648. skb_len -= data_len;
  3649. if (skb_len) {
  3650. if (qeth_is_last_sbale(element)) {
  3651. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3652. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3653. CARD_BUS_ID(card));
  3654. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3655. QETH_DBF_TEXT_(QERR, 2, "%s",
  3656. CARD_BUS_ID(card));
  3657. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3658. dev_kfree_skb_any(skb);
  3659. card->stats.rx_errors++;
  3660. return NULL;
  3661. }
  3662. element++;
  3663. offset = 0;
  3664. data_ptr = element->addr;
  3665. } else {
  3666. offset += data_len;
  3667. }
  3668. }
  3669. *__element = element;
  3670. *__offset = offset;
  3671. if (use_rx_sg && card->options.performance_stats) {
  3672. card->perf_stats.sg_skbs_rx++;
  3673. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3674. }
  3675. return skb;
  3676. no_mem:
  3677. if (net_ratelimit()) {
  3678. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3679. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3680. }
  3681. card->stats.rx_dropped++;
  3682. return NULL;
  3683. }
  3684. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3685. static void qeth_unregister_dbf_views(void)
  3686. {
  3687. int x;
  3688. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3689. debug_unregister(qeth_dbf[x].id);
  3690. qeth_dbf[x].id = NULL;
  3691. }
  3692. }
  3693. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3694. {
  3695. char dbf_txt_buf[32];
  3696. va_list args;
  3697. if (level > (qeth_dbf[dbf_nix].id)->level)
  3698. return;
  3699. va_start(args, fmt);
  3700. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3701. va_end(args);
  3702. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3703. }
  3704. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3705. static int qeth_register_dbf_views(void)
  3706. {
  3707. int ret;
  3708. int x;
  3709. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3710. /* register the areas */
  3711. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3712. qeth_dbf[x].pages,
  3713. qeth_dbf[x].areas,
  3714. qeth_dbf[x].len);
  3715. if (qeth_dbf[x].id == NULL) {
  3716. qeth_unregister_dbf_views();
  3717. return -ENOMEM;
  3718. }
  3719. /* register a view */
  3720. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3721. if (ret) {
  3722. qeth_unregister_dbf_views();
  3723. return ret;
  3724. }
  3725. /* set a passing level */
  3726. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3727. }
  3728. return 0;
  3729. }
  3730. int qeth_core_load_discipline(struct qeth_card *card,
  3731. enum qeth_discipline_id discipline)
  3732. {
  3733. int rc = 0;
  3734. switch (discipline) {
  3735. case QETH_DISCIPLINE_LAYER3:
  3736. card->discipline.ccwgdriver = try_then_request_module(
  3737. symbol_get(qeth_l3_ccwgroup_driver),
  3738. "qeth_l3");
  3739. break;
  3740. case QETH_DISCIPLINE_LAYER2:
  3741. card->discipline.ccwgdriver = try_then_request_module(
  3742. symbol_get(qeth_l2_ccwgroup_driver),
  3743. "qeth_l2");
  3744. break;
  3745. }
  3746. if (!card->discipline.ccwgdriver) {
  3747. dev_err(&card->gdev->dev, "There is no kernel module to "
  3748. "support discipline %d\n", discipline);
  3749. rc = -EINVAL;
  3750. }
  3751. return rc;
  3752. }
  3753. void qeth_core_free_discipline(struct qeth_card *card)
  3754. {
  3755. if (card->options.layer2)
  3756. symbol_put(qeth_l2_ccwgroup_driver);
  3757. else
  3758. symbol_put(qeth_l3_ccwgroup_driver);
  3759. card->discipline.ccwgdriver = NULL;
  3760. }
  3761. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3762. {
  3763. struct qeth_card *card;
  3764. struct device *dev;
  3765. int rc;
  3766. unsigned long flags;
  3767. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3768. dev = &gdev->dev;
  3769. if (!get_device(dev))
  3770. return -ENODEV;
  3771. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3772. card = qeth_alloc_card();
  3773. if (!card) {
  3774. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3775. rc = -ENOMEM;
  3776. goto err_dev;
  3777. }
  3778. card->read.ccwdev = gdev->cdev[0];
  3779. card->write.ccwdev = gdev->cdev[1];
  3780. card->data.ccwdev = gdev->cdev[2];
  3781. dev_set_drvdata(&gdev->dev, card);
  3782. card->gdev = gdev;
  3783. gdev->cdev[0]->handler = qeth_irq;
  3784. gdev->cdev[1]->handler = qeth_irq;
  3785. gdev->cdev[2]->handler = qeth_irq;
  3786. rc = qeth_determine_card_type(card);
  3787. if (rc) {
  3788. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3789. goto err_card;
  3790. }
  3791. rc = qeth_setup_card(card);
  3792. if (rc) {
  3793. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3794. goto err_card;
  3795. }
  3796. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3797. rc = qeth_core_create_osn_attributes(dev);
  3798. if (rc)
  3799. goto err_card;
  3800. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3801. if (rc) {
  3802. qeth_core_remove_osn_attributes(dev);
  3803. goto err_card;
  3804. }
  3805. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3806. if (rc) {
  3807. qeth_core_free_discipline(card);
  3808. qeth_core_remove_osn_attributes(dev);
  3809. goto err_card;
  3810. }
  3811. } else {
  3812. rc = qeth_core_create_device_attributes(dev);
  3813. if (rc)
  3814. goto err_card;
  3815. }
  3816. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3817. list_add_tail(&card->list, &qeth_core_card_list.list);
  3818. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3819. return 0;
  3820. err_card:
  3821. qeth_core_free_card(card);
  3822. err_dev:
  3823. put_device(dev);
  3824. return rc;
  3825. }
  3826. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3827. {
  3828. unsigned long flags;
  3829. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3830. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3831. if (card->discipline.ccwgdriver) {
  3832. card->discipline.ccwgdriver->remove(gdev);
  3833. qeth_core_free_discipline(card);
  3834. }
  3835. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3836. qeth_core_remove_osn_attributes(&gdev->dev);
  3837. } else {
  3838. qeth_core_remove_device_attributes(&gdev->dev);
  3839. }
  3840. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3841. list_del(&card->list);
  3842. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3843. qeth_core_free_card(card);
  3844. dev_set_drvdata(&gdev->dev, NULL);
  3845. put_device(&gdev->dev);
  3846. return;
  3847. }
  3848. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3849. {
  3850. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3851. int rc = 0;
  3852. int def_discipline;
  3853. if (!card->discipline.ccwgdriver) {
  3854. if (card->info.type == QETH_CARD_TYPE_IQD)
  3855. def_discipline = QETH_DISCIPLINE_LAYER3;
  3856. else
  3857. def_discipline = QETH_DISCIPLINE_LAYER2;
  3858. rc = qeth_core_load_discipline(card, def_discipline);
  3859. if (rc)
  3860. goto err;
  3861. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3862. if (rc)
  3863. goto err;
  3864. }
  3865. rc = card->discipline.ccwgdriver->set_online(gdev);
  3866. err:
  3867. return rc;
  3868. }
  3869. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3870. {
  3871. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3872. return card->discipline.ccwgdriver->set_offline(gdev);
  3873. }
  3874. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3875. {
  3876. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3877. if (card->discipline.ccwgdriver &&
  3878. card->discipline.ccwgdriver->shutdown)
  3879. card->discipline.ccwgdriver->shutdown(gdev);
  3880. }
  3881. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  3882. {
  3883. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3884. if (card->discipline.ccwgdriver &&
  3885. card->discipline.ccwgdriver->prepare)
  3886. return card->discipline.ccwgdriver->prepare(gdev);
  3887. return 0;
  3888. }
  3889. static void qeth_core_complete(struct ccwgroup_device *gdev)
  3890. {
  3891. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3892. if (card->discipline.ccwgdriver &&
  3893. card->discipline.ccwgdriver->complete)
  3894. card->discipline.ccwgdriver->complete(gdev);
  3895. }
  3896. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  3897. {
  3898. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3899. if (card->discipline.ccwgdriver &&
  3900. card->discipline.ccwgdriver->freeze)
  3901. return card->discipline.ccwgdriver->freeze(gdev);
  3902. return 0;
  3903. }
  3904. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  3905. {
  3906. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3907. if (card->discipline.ccwgdriver &&
  3908. card->discipline.ccwgdriver->thaw)
  3909. return card->discipline.ccwgdriver->thaw(gdev);
  3910. return 0;
  3911. }
  3912. static int qeth_core_restore(struct ccwgroup_device *gdev)
  3913. {
  3914. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3915. if (card->discipline.ccwgdriver &&
  3916. card->discipline.ccwgdriver->restore)
  3917. return card->discipline.ccwgdriver->restore(gdev);
  3918. return 0;
  3919. }
  3920. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3921. .owner = THIS_MODULE,
  3922. .name = "qeth",
  3923. .driver_id = 0xD8C5E3C8,
  3924. .probe = qeth_core_probe_device,
  3925. .remove = qeth_core_remove_device,
  3926. .set_online = qeth_core_set_online,
  3927. .set_offline = qeth_core_set_offline,
  3928. .shutdown = qeth_core_shutdown,
  3929. .prepare = qeth_core_prepare,
  3930. .complete = qeth_core_complete,
  3931. .freeze = qeth_core_freeze,
  3932. .thaw = qeth_core_thaw,
  3933. .restore = qeth_core_restore,
  3934. };
  3935. static ssize_t
  3936. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3937. size_t count)
  3938. {
  3939. int err;
  3940. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3941. qeth_core_ccwgroup_driver.driver_id);
  3942. if (err)
  3943. return err;
  3944. else
  3945. return count;
  3946. }
  3947. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3948. static struct {
  3949. const char str[ETH_GSTRING_LEN];
  3950. } qeth_ethtool_stats_keys[] = {
  3951. /* 0 */{"rx skbs"},
  3952. {"rx buffers"},
  3953. {"tx skbs"},
  3954. {"tx buffers"},
  3955. {"tx skbs no packing"},
  3956. {"tx buffers no packing"},
  3957. {"tx skbs packing"},
  3958. {"tx buffers packing"},
  3959. {"tx sg skbs"},
  3960. {"tx sg frags"},
  3961. /* 10 */{"rx sg skbs"},
  3962. {"rx sg frags"},
  3963. {"rx sg page allocs"},
  3964. {"tx large kbytes"},
  3965. {"tx large count"},
  3966. {"tx pk state ch n->p"},
  3967. {"tx pk state ch p->n"},
  3968. {"tx pk watermark low"},
  3969. {"tx pk watermark high"},
  3970. {"queue 0 buffer usage"},
  3971. /* 20 */{"queue 1 buffer usage"},
  3972. {"queue 2 buffer usage"},
  3973. {"queue 3 buffer usage"},
  3974. {"rx handler time"},
  3975. {"rx handler count"},
  3976. {"rx do_QDIO time"},
  3977. {"rx do_QDIO count"},
  3978. {"tx handler time"},
  3979. {"tx handler count"},
  3980. {"tx time"},
  3981. /* 30 */{"tx count"},
  3982. {"tx do_QDIO time"},
  3983. {"tx do_QDIO count"},
  3984. {"tx csum"},
  3985. {"tx lin"},
  3986. };
  3987. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  3988. {
  3989. switch (stringset) {
  3990. case ETH_SS_STATS:
  3991. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  3992. default:
  3993. return -EINVAL;
  3994. }
  3995. }
  3996. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  3997. void qeth_core_get_ethtool_stats(struct net_device *dev,
  3998. struct ethtool_stats *stats, u64 *data)
  3999. {
  4000. struct qeth_card *card = dev->ml_priv;
  4001. data[0] = card->stats.rx_packets -
  4002. card->perf_stats.initial_rx_packets;
  4003. data[1] = card->perf_stats.bufs_rec;
  4004. data[2] = card->stats.tx_packets -
  4005. card->perf_stats.initial_tx_packets;
  4006. data[3] = card->perf_stats.bufs_sent;
  4007. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4008. - card->perf_stats.skbs_sent_pack;
  4009. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4010. data[6] = card->perf_stats.skbs_sent_pack;
  4011. data[7] = card->perf_stats.bufs_sent_pack;
  4012. data[8] = card->perf_stats.sg_skbs_sent;
  4013. data[9] = card->perf_stats.sg_frags_sent;
  4014. data[10] = card->perf_stats.sg_skbs_rx;
  4015. data[11] = card->perf_stats.sg_frags_rx;
  4016. data[12] = card->perf_stats.sg_alloc_page_rx;
  4017. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4018. data[14] = card->perf_stats.large_send_cnt;
  4019. data[15] = card->perf_stats.sc_dp_p;
  4020. data[16] = card->perf_stats.sc_p_dp;
  4021. data[17] = QETH_LOW_WATERMARK_PACK;
  4022. data[18] = QETH_HIGH_WATERMARK_PACK;
  4023. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4024. data[20] = (card->qdio.no_out_queues > 1) ?
  4025. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4026. data[21] = (card->qdio.no_out_queues > 2) ?
  4027. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4028. data[22] = (card->qdio.no_out_queues > 3) ?
  4029. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4030. data[23] = card->perf_stats.inbound_time;
  4031. data[24] = card->perf_stats.inbound_cnt;
  4032. data[25] = card->perf_stats.inbound_do_qdio_time;
  4033. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4034. data[27] = card->perf_stats.outbound_handler_time;
  4035. data[28] = card->perf_stats.outbound_handler_cnt;
  4036. data[29] = card->perf_stats.outbound_time;
  4037. data[30] = card->perf_stats.outbound_cnt;
  4038. data[31] = card->perf_stats.outbound_do_qdio_time;
  4039. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4040. data[33] = card->perf_stats.tx_csum;
  4041. data[34] = card->perf_stats.tx_lin;
  4042. }
  4043. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4044. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4045. {
  4046. switch (stringset) {
  4047. case ETH_SS_STATS:
  4048. memcpy(data, &qeth_ethtool_stats_keys,
  4049. sizeof(qeth_ethtool_stats_keys));
  4050. break;
  4051. default:
  4052. WARN_ON(1);
  4053. break;
  4054. }
  4055. }
  4056. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4057. void qeth_core_get_drvinfo(struct net_device *dev,
  4058. struct ethtool_drvinfo *info)
  4059. {
  4060. struct qeth_card *card = dev->ml_priv;
  4061. if (card->options.layer2)
  4062. strcpy(info->driver, "qeth_l2");
  4063. else
  4064. strcpy(info->driver, "qeth_l3");
  4065. strcpy(info->version, "1.0");
  4066. strcpy(info->fw_version, card->info.mcl_level);
  4067. sprintf(info->bus_info, "%s/%s/%s",
  4068. CARD_RDEV_ID(card),
  4069. CARD_WDEV_ID(card),
  4070. CARD_DDEV_ID(card));
  4071. }
  4072. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4073. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4074. struct ethtool_cmd *ecmd)
  4075. {
  4076. struct qeth_card *card = netdev->ml_priv;
  4077. enum qeth_link_types link_type;
  4078. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4079. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4080. else
  4081. link_type = card->info.link_type;
  4082. ecmd->transceiver = XCVR_INTERNAL;
  4083. ecmd->supported = SUPPORTED_Autoneg;
  4084. ecmd->advertising = ADVERTISED_Autoneg;
  4085. ecmd->duplex = DUPLEX_FULL;
  4086. ecmd->autoneg = AUTONEG_ENABLE;
  4087. switch (link_type) {
  4088. case QETH_LINK_TYPE_FAST_ETH:
  4089. case QETH_LINK_TYPE_LANE_ETH100:
  4090. ecmd->supported |= SUPPORTED_10baseT_Half |
  4091. SUPPORTED_10baseT_Full |
  4092. SUPPORTED_100baseT_Half |
  4093. SUPPORTED_100baseT_Full |
  4094. SUPPORTED_TP;
  4095. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4096. ADVERTISED_10baseT_Full |
  4097. ADVERTISED_100baseT_Half |
  4098. ADVERTISED_100baseT_Full |
  4099. ADVERTISED_TP;
  4100. ecmd->speed = SPEED_100;
  4101. ecmd->port = PORT_TP;
  4102. break;
  4103. case QETH_LINK_TYPE_GBIT_ETH:
  4104. case QETH_LINK_TYPE_LANE_ETH1000:
  4105. ecmd->supported |= SUPPORTED_10baseT_Half |
  4106. SUPPORTED_10baseT_Full |
  4107. SUPPORTED_100baseT_Half |
  4108. SUPPORTED_100baseT_Full |
  4109. SUPPORTED_1000baseT_Half |
  4110. SUPPORTED_1000baseT_Full |
  4111. SUPPORTED_FIBRE;
  4112. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4113. ADVERTISED_10baseT_Full |
  4114. ADVERTISED_100baseT_Half |
  4115. ADVERTISED_100baseT_Full |
  4116. ADVERTISED_1000baseT_Half |
  4117. ADVERTISED_1000baseT_Full |
  4118. ADVERTISED_FIBRE;
  4119. ecmd->speed = SPEED_1000;
  4120. ecmd->port = PORT_FIBRE;
  4121. break;
  4122. case QETH_LINK_TYPE_10GBIT_ETH:
  4123. ecmd->supported |= SUPPORTED_10baseT_Half |
  4124. SUPPORTED_10baseT_Full |
  4125. SUPPORTED_100baseT_Half |
  4126. SUPPORTED_100baseT_Full |
  4127. SUPPORTED_1000baseT_Half |
  4128. SUPPORTED_1000baseT_Full |
  4129. SUPPORTED_10000baseT_Full |
  4130. SUPPORTED_FIBRE;
  4131. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4132. ADVERTISED_10baseT_Full |
  4133. ADVERTISED_100baseT_Half |
  4134. ADVERTISED_100baseT_Full |
  4135. ADVERTISED_1000baseT_Half |
  4136. ADVERTISED_1000baseT_Full |
  4137. ADVERTISED_10000baseT_Full |
  4138. ADVERTISED_FIBRE;
  4139. ecmd->speed = SPEED_10000;
  4140. ecmd->port = PORT_FIBRE;
  4141. break;
  4142. default:
  4143. ecmd->supported |= SUPPORTED_10baseT_Half |
  4144. SUPPORTED_10baseT_Full |
  4145. SUPPORTED_TP;
  4146. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4147. ADVERTISED_10baseT_Full |
  4148. ADVERTISED_TP;
  4149. ecmd->speed = SPEED_10;
  4150. ecmd->port = PORT_TP;
  4151. }
  4152. return 0;
  4153. }
  4154. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4155. static int __init qeth_core_init(void)
  4156. {
  4157. int rc;
  4158. pr_info("loading core functions\n");
  4159. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4160. rwlock_init(&qeth_core_card_list.rwlock);
  4161. rc = qeth_register_dbf_views();
  4162. if (rc)
  4163. goto out_err;
  4164. rc = ccw_driver_register(&qeth_ccw_driver);
  4165. if (rc)
  4166. goto ccw_err;
  4167. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4168. if (rc)
  4169. goto ccwgroup_err;
  4170. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4171. &driver_attr_group);
  4172. if (rc)
  4173. goto driver_err;
  4174. qeth_core_root_dev = root_device_register("qeth");
  4175. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4176. if (rc)
  4177. goto register_err;
  4178. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4179. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4180. if (!qeth_core_header_cache) {
  4181. rc = -ENOMEM;
  4182. goto slab_err;
  4183. }
  4184. return 0;
  4185. slab_err:
  4186. root_device_unregister(qeth_core_root_dev);
  4187. register_err:
  4188. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4189. &driver_attr_group);
  4190. driver_err:
  4191. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4192. ccwgroup_err:
  4193. ccw_driver_unregister(&qeth_ccw_driver);
  4194. ccw_err:
  4195. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4196. qeth_unregister_dbf_views();
  4197. out_err:
  4198. pr_err("Initializing the qeth device driver failed\n");
  4199. return rc;
  4200. }
  4201. static void __exit qeth_core_exit(void)
  4202. {
  4203. root_device_unregister(qeth_core_root_dev);
  4204. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4205. &driver_attr_group);
  4206. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4207. ccw_driver_unregister(&qeth_ccw_driver);
  4208. kmem_cache_destroy(qeth_core_header_cache);
  4209. qeth_unregister_dbf_views();
  4210. pr_info("core functions removed\n");
  4211. }
  4212. module_init(qeth_core_init);
  4213. module_exit(qeth_core_exit);
  4214. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4215. MODULE_DESCRIPTION("qeth core functions");
  4216. MODULE_LICENSE("GPL");