rtc-mxc.c 13 KB

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  1. /*
  2. * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. #include <linux/io.h>
  12. #include <linux/rtc.h>
  13. #include <linux/module.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/clk.h>
  17. #include <mach/hardware.h>
  18. #define RTC_INPUT_CLK_32768HZ (0x00 << 5)
  19. #define RTC_INPUT_CLK_32000HZ (0x01 << 5)
  20. #define RTC_INPUT_CLK_38400HZ (0x02 << 5)
  21. #define RTC_SW_BIT (1 << 0)
  22. #define RTC_ALM_BIT (1 << 2)
  23. #define RTC_1HZ_BIT (1 << 4)
  24. #define RTC_2HZ_BIT (1 << 7)
  25. #define RTC_SAM0_BIT (1 << 8)
  26. #define RTC_SAM1_BIT (1 << 9)
  27. #define RTC_SAM2_BIT (1 << 10)
  28. #define RTC_SAM3_BIT (1 << 11)
  29. #define RTC_SAM4_BIT (1 << 12)
  30. #define RTC_SAM5_BIT (1 << 13)
  31. #define RTC_SAM6_BIT (1 << 14)
  32. #define RTC_SAM7_BIT (1 << 15)
  33. #define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
  34. RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
  35. RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)
  36. #define RTC_ENABLE_BIT (1 << 7)
  37. #define MAX_PIE_NUM 9
  38. #define MAX_PIE_FREQ 512
  39. static const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = {
  40. { 2, RTC_2HZ_BIT },
  41. { 4, RTC_SAM0_BIT },
  42. { 8, RTC_SAM1_BIT },
  43. { 16, RTC_SAM2_BIT },
  44. { 32, RTC_SAM3_BIT },
  45. { 64, RTC_SAM4_BIT },
  46. { 128, RTC_SAM5_BIT },
  47. { 256, RTC_SAM6_BIT },
  48. { MAX_PIE_FREQ, RTC_SAM7_BIT },
  49. };
  50. /* Those are the bits from a classic RTC we want to mimic */
  51. #define RTC_IRQF 0x80 /* any of the following 3 is active */
  52. #define RTC_PF 0x40 /* Periodic interrupt */
  53. #define RTC_AF 0x20 /* Alarm interrupt */
  54. #define RTC_UF 0x10 /* Update interrupt for 1Hz RTC */
  55. #define MXC_RTC_TIME 0
  56. #define MXC_RTC_ALARM 1
  57. #define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */
  58. #define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */
  59. #define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */
  60. #define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */
  61. #define RTC_RTCCTL 0x10 /* 32bit rtc control reg */
  62. #define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */
  63. #define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */
  64. #define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */
  65. #define RTC_DAYR 0x20 /* 32bit rtc days counter reg */
  66. #define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */
  67. #define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */
  68. #define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */
  69. #define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */
  70. struct rtc_plat_data {
  71. struct rtc_device *rtc;
  72. void __iomem *ioaddr;
  73. int irq;
  74. struct clk *clk;
  75. unsigned int irqen;
  76. int alrm_sec;
  77. int alrm_min;
  78. int alrm_hour;
  79. int alrm_mday;
  80. struct timespec mxc_rtc_delta;
  81. struct rtc_time g_rtc_alarm;
  82. };
  83. /*
  84. * This function is used to obtain the RTC time or the alarm value in
  85. * second.
  86. */
  87. static u32 get_alarm_or_time(struct device *dev, int time_alarm)
  88. {
  89. struct platform_device *pdev = to_platform_device(dev);
  90. struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
  91. void __iomem *ioaddr = pdata->ioaddr;
  92. u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
  93. switch (time_alarm) {
  94. case MXC_RTC_TIME:
  95. day = readw(ioaddr + RTC_DAYR);
  96. hr_min = readw(ioaddr + RTC_HOURMIN);
  97. sec = readw(ioaddr + RTC_SECOND);
  98. break;
  99. case MXC_RTC_ALARM:
  100. day = readw(ioaddr + RTC_DAYALARM);
  101. hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
  102. sec = readw(ioaddr + RTC_ALRM_SEC);
  103. break;
  104. }
  105. hr = hr_min >> 8;
  106. min = hr_min & 0xff;
  107. return (((day * 24 + hr) * 60) + min) * 60 + sec;
  108. }
  109. /*
  110. * This function sets the RTC alarm value or the time value.
  111. */
  112. static void set_alarm_or_time(struct device *dev, int time_alarm, u32 time)
  113. {
  114. u32 day, hr, min, sec, temp;
  115. struct platform_device *pdev = to_platform_device(dev);
  116. struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
  117. void __iomem *ioaddr = pdata->ioaddr;
  118. day = time / 86400;
  119. time -= day * 86400;
  120. /* time is within a day now */
  121. hr = time / 3600;
  122. time -= hr * 3600;
  123. /* time is within an hour now */
  124. min = time / 60;
  125. sec = time - min * 60;
  126. temp = (hr << 8) + min;
  127. switch (time_alarm) {
  128. case MXC_RTC_TIME:
  129. writew(day, ioaddr + RTC_DAYR);
  130. writew(sec, ioaddr + RTC_SECOND);
  131. writew(temp, ioaddr + RTC_HOURMIN);
  132. break;
  133. case MXC_RTC_ALARM:
  134. writew(day, ioaddr + RTC_DAYALARM);
  135. writew(sec, ioaddr + RTC_ALRM_SEC);
  136. writew(temp, ioaddr + RTC_ALRM_HM);
  137. break;
  138. }
  139. }
  140. /*
  141. * This function updates the RTC alarm registers and then clears all the
  142. * interrupt status bits.
  143. */
  144. static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
  145. {
  146. struct rtc_time alarm_tm, now_tm;
  147. unsigned long now, time;
  148. int ret;
  149. struct platform_device *pdev = to_platform_device(dev);
  150. struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
  151. void __iomem *ioaddr = pdata->ioaddr;
  152. now = get_alarm_or_time(dev, MXC_RTC_TIME);
  153. rtc_time_to_tm(now, &now_tm);
  154. alarm_tm.tm_year = now_tm.tm_year;
  155. alarm_tm.tm_mon = now_tm.tm_mon;
  156. alarm_tm.tm_mday = now_tm.tm_mday;
  157. alarm_tm.tm_hour = alrm->tm_hour;
  158. alarm_tm.tm_min = alrm->tm_min;
  159. alarm_tm.tm_sec = alrm->tm_sec;
  160. rtc_tm_to_time(&now_tm, &now);
  161. rtc_tm_to_time(&alarm_tm, &time);
  162. if (time < now) {
  163. time += 60 * 60 * 24;
  164. rtc_time_to_tm(time, &alarm_tm);
  165. }
  166. ret = rtc_tm_to_time(&alarm_tm, &time);
  167. /* clear all the interrupt status bits */
  168. writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
  169. set_alarm_or_time(dev, MXC_RTC_ALARM, time);
  170. return ret;
  171. }
  172. /* This function is the RTC interrupt service routine. */
  173. static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
  174. {
  175. struct platform_device *pdev = dev_id;
  176. struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
  177. void __iomem *ioaddr = pdata->ioaddr;
  178. u32 status;
  179. u32 events = 0;
  180. spin_lock_irq(&pdata->rtc->irq_lock);
  181. status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
  182. /* clear interrupt sources */
  183. writew(status, ioaddr + RTC_RTCISR);
  184. /* clear alarm interrupt if it has occurred */
  185. if (status & RTC_ALM_BIT)
  186. status &= ~RTC_ALM_BIT;
  187. /* update irq data & counter */
  188. if (status & RTC_ALM_BIT)
  189. events |= (RTC_AF | RTC_IRQF);
  190. if (status & RTC_1HZ_BIT)
  191. events |= (RTC_UF | RTC_IRQF);
  192. if (status & PIT_ALL_ON)
  193. events |= (RTC_PF | RTC_IRQF);
  194. if ((status & RTC_ALM_BIT) && rtc_valid_tm(&pdata->g_rtc_alarm))
  195. rtc_update_alarm(&pdev->dev, &pdata->g_rtc_alarm);
  196. rtc_update_irq(pdata->rtc, 1, events);
  197. spin_unlock_irq(&pdata->rtc->irq_lock);
  198. return IRQ_HANDLED;
  199. }
  200. /*
  201. * Clear all interrupts and release the IRQ
  202. */
  203. static void mxc_rtc_release(struct device *dev)
  204. {
  205. struct platform_device *pdev = to_platform_device(dev);
  206. struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
  207. void __iomem *ioaddr = pdata->ioaddr;
  208. spin_lock_irq(&pdata->rtc->irq_lock);
  209. /* Disable all rtc interrupts */
  210. writew(0, ioaddr + RTC_RTCIENR);
  211. /* Clear all interrupt status */
  212. writew(0xffffffff, ioaddr + RTC_RTCISR);
  213. spin_unlock_irq(&pdata->rtc->irq_lock);
  214. }
  215. static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
  216. unsigned int enabled)
  217. {
  218. struct platform_device *pdev = to_platform_device(dev);
  219. struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
  220. void __iomem *ioaddr = pdata->ioaddr;
  221. u32 reg;
  222. spin_lock_irq(&pdata->rtc->irq_lock);
  223. reg = readw(ioaddr + RTC_RTCIENR);
  224. if (enabled)
  225. reg |= bit;
  226. else
  227. reg &= ~bit;
  228. writew(reg, ioaddr + RTC_RTCIENR);
  229. spin_unlock_irq(&pdata->rtc->irq_lock);
  230. }
  231. static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  232. {
  233. mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
  234. return 0;
  235. }
  236. static int mxc_rtc_update_irq_enable(struct device *dev, unsigned int enabled)
  237. {
  238. mxc_rtc_irq_enable(dev, RTC_1HZ_BIT, enabled);
  239. return 0;
  240. }
  241. /*
  242. * This function reads the current RTC time into tm in Gregorian date.
  243. */
  244. static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
  245. {
  246. u32 val;
  247. /* Avoid roll-over from reading the different registers */
  248. do {
  249. val = get_alarm_or_time(dev, MXC_RTC_TIME);
  250. } while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
  251. rtc_time_to_tm(val, tm);
  252. return 0;
  253. }
  254. /*
  255. * This function sets the internal RTC time based on tm in Gregorian date.
  256. */
  257. static int mxc_rtc_set_mmss(struct device *dev, unsigned long time)
  258. {
  259. /* Avoid roll-over from reading the different registers */
  260. do {
  261. set_alarm_or_time(dev, MXC_RTC_TIME, time);
  262. } while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
  263. return 0;
  264. }
  265. /*
  266. * This function reads the current alarm value into the passed in 'alrm'
  267. * argument. It updates the alrm's pending field value based on the whether
  268. * an alarm interrupt occurs or not.
  269. */
  270. static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  271. {
  272. struct platform_device *pdev = to_platform_device(dev);
  273. struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
  274. void __iomem *ioaddr = pdata->ioaddr;
  275. rtc_time_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
  276. alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
  277. return 0;
  278. }
  279. /*
  280. * This function sets the RTC alarm based on passed in alrm.
  281. */
  282. static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  283. {
  284. struct platform_device *pdev = to_platform_device(dev);
  285. struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
  286. int ret;
  287. if (rtc_valid_tm(&alrm->time)) {
  288. if (alrm->time.tm_sec > 59 ||
  289. alrm->time.tm_hour > 23 ||
  290. alrm->time.tm_min > 59)
  291. return -EINVAL;
  292. ret = rtc_update_alarm(dev, &alrm->time);
  293. } else {
  294. ret = rtc_valid_tm(&alrm->time);
  295. if (ret)
  296. return ret;
  297. ret = rtc_update_alarm(dev, &alrm->time);
  298. }
  299. if (ret)
  300. return ret;
  301. memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
  302. mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
  303. return 0;
  304. }
  305. /* RTC layer */
  306. static struct rtc_class_ops mxc_rtc_ops = {
  307. .release = mxc_rtc_release,
  308. .read_time = mxc_rtc_read_time,
  309. .set_mmss = mxc_rtc_set_mmss,
  310. .read_alarm = mxc_rtc_read_alarm,
  311. .set_alarm = mxc_rtc_set_alarm,
  312. .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
  313. .update_irq_enable = mxc_rtc_update_irq_enable,
  314. };
  315. static int __init mxc_rtc_probe(struct platform_device *pdev)
  316. {
  317. struct clk *clk;
  318. struct resource *res;
  319. struct rtc_device *rtc;
  320. struct rtc_plat_data *pdata = NULL;
  321. u32 reg;
  322. int ret, rate;
  323. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  324. if (!res)
  325. return -ENODEV;
  326. pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
  327. if (!pdata)
  328. return -ENOMEM;
  329. pdata->ioaddr = ioremap(res->start, resource_size(res));
  330. clk = clk_get(&pdev->dev, "ckil");
  331. if (IS_ERR(clk))
  332. return PTR_ERR(clk);
  333. rate = clk_get_rate(clk);
  334. clk_put(clk);
  335. if (rate == 32768)
  336. reg = RTC_INPUT_CLK_32768HZ;
  337. else if (rate == 32000)
  338. reg = RTC_INPUT_CLK_32000HZ;
  339. else if (rate == 38400)
  340. reg = RTC_INPUT_CLK_38400HZ;
  341. else {
  342. dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n",
  343. clk_get_rate(clk));
  344. ret = -EINVAL;
  345. goto exit_free_pdata;
  346. }
  347. reg |= RTC_ENABLE_BIT;
  348. writew(reg, (pdata->ioaddr + RTC_RTCCTL));
  349. if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
  350. dev_err(&pdev->dev, "hardware module can't be enabled!\n");
  351. ret = -EIO;
  352. goto exit_free_pdata;
  353. }
  354. pdata->clk = clk_get(&pdev->dev, "rtc");
  355. if (IS_ERR(pdata->clk)) {
  356. dev_err(&pdev->dev, "unable to get clock!\n");
  357. ret = PTR_ERR(pdata->clk);
  358. goto exit_free_pdata;
  359. }
  360. clk_enable(pdata->clk);
  361. rtc = rtc_device_register(pdev->name, &pdev->dev, &mxc_rtc_ops,
  362. THIS_MODULE);
  363. if (IS_ERR(rtc)) {
  364. ret = PTR_ERR(rtc);
  365. goto exit_put_clk;
  366. }
  367. pdata->rtc = rtc;
  368. platform_set_drvdata(pdev, pdata);
  369. /* Configure and enable the RTC */
  370. pdata->irq = platform_get_irq(pdev, 0);
  371. if (pdata->irq >= 0 &&
  372. request_irq(pdata->irq, mxc_rtc_interrupt, IRQF_SHARED,
  373. pdev->name, pdev) < 0) {
  374. dev_warn(&pdev->dev, "interrupt not available.\n");
  375. pdata->irq = -1;
  376. }
  377. return 0;
  378. exit_put_clk:
  379. clk_put(pdata->clk);
  380. exit_free_pdata:
  381. kfree(pdata);
  382. return ret;
  383. }
  384. static int __exit mxc_rtc_remove(struct platform_device *pdev)
  385. {
  386. struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
  387. rtc_device_unregister(pdata->rtc);
  388. if (pdata->irq >= 0)
  389. free_irq(pdata->irq, pdev);
  390. clk_disable(pdata->clk);
  391. clk_put(pdata->clk);
  392. kfree(pdata);
  393. platform_set_drvdata(pdev, NULL);
  394. return 0;
  395. }
  396. static struct platform_driver mxc_rtc_driver = {
  397. .driver = {
  398. .name = "mxc_rtc",
  399. .owner = THIS_MODULE,
  400. },
  401. .remove = __exit_p(mxc_rtc_remove),
  402. };
  403. static int __init mxc_rtc_init(void)
  404. {
  405. return platform_driver_probe(&mxc_rtc_driver, mxc_rtc_probe);
  406. }
  407. static void __exit mxc_rtc_exit(void)
  408. {
  409. platform_driver_unregister(&mxc_rtc_driver);
  410. }
  411. module_init(mxc_rtc_init);
  412. module_exit(mxc_rtc_exit);
  413. MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
  414. MODULE_DESCRIPTION("RTC driver for Freescale MXC");
  415. MODULE_LICENSE("GPL");