setup-res.c 6.9 KB

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  1. /*
  2. * drivers/pci/setup-res.c
  3. *
  4. * Extruded from code written by
  5. * Dave Rusling (david.rusling@reo.mts.dec.com)
  6. * David Mosberger (davidm@cs.arizona.edu)
  7. * David Miller (davem@redhat.com)
  8. *
  9. * Support routines for initializing a PCI subsystem.
  10. */
  11. /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
  12. /*
  13. * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  14. * Resource sorting
  15. */
  16. #include <linux/init.h>
  17. #include <linux/kernel.h>
  18. #include <linux/pci.h>
  19. #include <linux/errno.h>
  20. #include <linux/ioport.h>
  21. #include <linux/cache.h>
  22. #include <linux/slab.h>
  23. #include "pci.h"
  24. void pci_update_resource(struct pci_dev *dev, int resno)
  25. {
  26. struct pci_bus_region region;
  27. u32 new, check, mask;
  28. int reg;
  29. enum pci_bar_type type;
  30. struct resource *res = dev->resource + resno;
  31. /*
  32. * Ignore resources for unimplemented BARs and unused resource slots
  33. * for 64 bit BARs.
  34. */
  35. if (!res->flags)
  36. return;
  37. /*
  38. * Ignore non-moveable resources. This might be legacy resources for
  39. * which no functional BAR register exists or another important
  40. * system resource we shouldn't move around.
  41. */
  42. if (res->flags & IORESOURCE_PCI_FIXED)
  43. return;
  44. pcibios_resource_to_bus(dev, &region, res);
  45. new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
  46. if (res->flags & IORESOURCE_IO)
  47. mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
  48. else
  49. mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
  50. reg = pci_resource_bar(dev, resno, &type);
  51. if (!reg)
  52. return;
  53. if (type != pci_bar_unknown) {
  54. if (!(res->flags & IORESOURCE_ROM_ENABLE))
  55. return;
  56. new |= PCI_ROM_ADDRESS_ENABLE;
  57. }
  58. pci_write_config_dword(dev, reg, new);
  59. pci_read_config_dword(dev, reg, &check);
  60. if ((new ^ check) & mask) {
  61. dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
  62. resno, new, check);
  63. }
  64. if ((new & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
  65. (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) {
  66. new = region.start >> 16 >> 16;
  67. pci_write_config_dword(dev, reg + 4, new);
  68. pci_read_config_dword(dev, reg + 4, &check);
  69. if (check != new) {
  70. dev_err(&dev->dev, "BAR %d: error updating "
  71. "(high %#08x != %#08x)\n", resno, new, check);
  72. }
  73. }
  74. res->flags &= ~IORESOURCE_UNSET;
  75. dev_info(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx]\n",
  76. resno, res, (unsigned long long)region.start,
  77. (unsigned long long)region.end);
  78. }
  79. int pci_claim_resource(struct pci_dev *dev, int resource)
  80. {
  81. struct resource *res = &dev->resource[resource];
  82. struct resource *root;
  83. int err;
  84. root = pci_find_parent_resource(dev, res);
  85. if (!root) {
  86. dev_err(&dev->dev, "no compatible bridge window for %pR\n",
  87. res);
  88. return -EINVAL;
  89. }
  90. err = request_resource(root, res);
  91. if (err)
  92. dev_err(&dev->dev,
  93. "address space collision: %pR already in use\n", res);
  94. return err;
  95. }
  96. EXPORT_SYMBOL(pci_claim_resource);
  97. #ifdef CONFIG_PCI_QUIRKS
  98. void pci_disable_bridge_window(struct pci_dev *dev)
  99. {
  100. dev_info(&dev->dev, "disabling bridge mem windows\n");
  101. /* MMIO Base/Limit */
  102. pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
  103. /* Prefetchable MMIO Base/Limit */
  104. pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
  105. pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
  106. pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
  107. }
  108. #endif /* CONFIG_PCI_QUIRKS */
  109. static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
  110. int resno)
  111. {
  112. struct resource *res = dev->resource + resno;
  113. resource_size_t size, min, align;
  114. int ret;
  115. size = resource_size(res);
  116. min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
  117. align = pci_resource_alignment(dev, res);
  118. /* First, try exact prefetching match.. */
  119. ret = pci_bus_alloc_resource(bus, res, size, align, min,
  120. IORESOURCE_PREFETCH,
  121. pcibios_align_resource, dev);
  122. if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
  123. /*
  124. * That failed.
  125. *
  126. * But a prefetching area can handle a non-prefetching
  127. * window (it will just not perform as well).
  128. */
  129. ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
  130. pcibios_align_resource, dev);
  131. }
  132. if (!ret) {
  133. res->flags &= ~IORESOURCE_STARTALIGN;
  134. dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
  135. if (resno < PCI_BRIDGE_RESOURCES)
  136. pci_update_resource(dev, resno);
  137. }
  138. return ret;
  139. }
  140. int pci_assign_resource(struct pci_dev *dev, int resno)
  141. {
  142. struct resource *res = dev->resource + resno;
  143. resource_size_t align;
  144. struct pci_bus *bus;
  145. int ret;
  146. char *type;
  147. align = pci_resource_alignment(dev, res);
  148. if (!align) {
  149. dev_info(&dev->dev, "BAR %d: can't assign %pR "
  150. "(bogus alignment)\n", resno, res);
  151. return -EINVAL;
  152. }
  153. bus = dev->bus;
  154. while ((ret = __pci_assign_resource(bus, dev, resno))) {
  155. if (bus->parent && bus->self->transparent)
  156. bus = bus->parent;
  157. else
  158. bus = NULL;
  159. if (bus)
  160. continue;
  161. break;
  162. }
  163. if (ret) {
  164. if (res->flags & IORESOURCE_MEM)
  165. if (res->flags & IORESOURCE_PREFETCH)
  166. type = "mem pref";
  167. else
  168. type = "mem";
  169. else if (res->flags & IORESOURCE_IO)
  170. type = "io";
  171. else
  172. type = "unknown";
  173. dev_info(&dev->dev,
  174. "BAR %d: can't assign %s (size %#llx)\n",
  175. resno, type, (unsigned long long) resource_size(res));
  176. }
  177. return ret;
  178. }
  179. /* Sort resources by alignment */
  180. void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
  181. {
  182. int i;
  183. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  184. struct resource *r;
  185. struct resource_list *list, *tmp;
  186. resource_size_t r_align;
  187. r = &dev->resource[i];
  188. if (r->flags & IORESOURCE_PCI_FIXED)
  189. continue;
  190. if (!(r->flags) || r->parent)
  191. continue;
  192. r_align = pci_resource_alignment(dev, r);
  193. if (!r_align) {
  194. dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
  195. i, r);
  196. continue;
  197. }
  198. for (list = head; ; list = list->next) {
  199. resource_size_t align = 0;
  200. struct resource_list *ln = list->next;
  201. if (ln)
  202. align = pci_resource_alignment(ln->dev, ln->res);
  203. if (r_align > align) {
  204. tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
  205. if (!tmp)
  206. panic("pdev_sort_resources(): "
  207. "kmalloc() failed!\n");
  208. tmp->next = ln;
  209. tmp->res = r;
  210. tmp->dev = dev;
  211. list->next = tmp;
  212. break;
  213. }
  214. }
  215. }
  216. }
  217. int pci_enable_resources(struct pci_dev *dev, int mask)
  218. {
  219. u16 cmd, old_cmd;
  220. int i;
  221. struct resource *r;
  222. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  223. old_cmd = cmd;
  224. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  225. if (!(mask & (1 << i)))
  226. continue;
  227. r = &dev->resource[i];
  228. if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
  229. continue;
  230. if ((i == PCI_ROM_RESOURCE) &&
  231. (!(r->flags & IORESOURCE_ROM_ENABLE)))
  232. continue;
  233. if (!r->parent) {
  234. dev_err(&dev->dev, "device not available "
  235. "(can't reserve %pR)\n", r);
  236. return -EINVAL;
  237. }
  238. if (r->flags & IORESOURCE_IO)
  239. cmd |= PCI_COMMAND_IO;
  240. if (r->flags & IORESOURCE_MEM)
  241. cmd |= PCI_COMMAND_MEMORY;
  242. }
  243. if (cmd != old_cmd) {
  244. dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
  245. old_cmd, cmd);
  246. pci_write_config_word(dev, PCI_COMMAND, cmd);
  247. }
  248. return 0;
  249. }