aerdrv.h 3.3 KB

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  1. /*
  2. * Copyright (C) 2006 Intel Corp.
  3. * Tom Long Nguyen (tom.l.nguyen@intel.com)
  4. * Zhang Yanmin (yanmin.zhang@intel.com)
  5. *
  6. */
  7. #ifndef _AERDRV_H_
  8. #define _AERDRV_H_
  9. #include <linux/workqueue.h>
  10. #include <linux/pcieport_if.h>
  11. #include <linux/aer.h>
  12. #include <linux/interrupt.h>
  13. #define AER_NONFATAL 0
  14. #define AER_FATAL 1
  15. #define AER_CORRECTABLE 2
  16. /* Root Error Status Register Bits */
  17. #define ROOT_ERR_STATUS_MASKS 0x0f
  18. #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
  19. PCI_EXP_RTCTL_SENFEE| \
  20. PCI_EXP_RTCTL_SEFEE)
  21. #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
  22. PCI_ERR_ROOT_CMD_NONFATAL_EN| \
  23. PCI_ERR_ROOT_CMD_FATAL_EN)
  24. #define ERR_COR_ID(d) (d & 0xffff)
  25. #define ERR_UNCOR_ID(d) (d >> 16)
  26. #define AER_ERROR_SOURCES_MAX 100
  27. #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
  28. PCI_ERR_UNC_ECRC| \
  29. PCI_ERR_UNC_UNSUP| \
  30. PCI_ERR_UNC_COMP_ABORT| \
  31. PCI_ERR_UNC_UNX_COMP| \
  32. PCI_ERR_UNC_MALF_TLP)
  33. struct header_log_regs {
  34. unsigned int dw0;
  35. unsigned int dw1;
  36. unsigned int dw2;
  37. unsigned int dw3;
  38. };
  39. #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
  40. struct aer_err_info {
  41. struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
  42. int error_dev_num;
  43. unsigned int id:16;
  44. unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
  45. unsigned int __pad1:5;
  46. unsigned int multi_error_valid:1;
  47. unsigned int first_error:5;
  48. unsigned int __pad2:2;
  49. unsigned int tlp_header_valid:1;
  50. unsigned int status; /* COR/UNCOR Error Status */
  51. unsigned int mask; /* COR/UNCOR Error Mask */
  52. struct header_log_regs tlp; /* TLP Header */
  53. };
  54. struct aer_err_source {
  55. unsigned int status;
  56. unsigned int id;
  57. };
  58. struct aer_rpc {
  59. struct pcie_device *rpd; /* Root Port device */
  60. struct work_struct dpc_handler;
  61. struct aer_err_source e_sources[AER_ERROR_SOURCES_MAX];
  62. unsigned short prod_idx; /* Error Producer Index */
  63. unsigned short cons_idx; /* Error Consumer Index */
  64. int isr;
  65. spinlock_t e_lock; /*
  66. * Lock access to Error Status/ID Regs
  67. * and error producer/consumer index
  68. */
  69. struct mutex rpc_mutex; /*
  70. * only one thread could do
  71. * recovery on the same
  72. * root port hierarchy
  73. */
  74. wait_queue_head_t wait_release;
  75. };
  76. struct aer_broadcast_data {
  77. enum pci_channel_state state;
  78. enum pci_ers_result result;
  79. };
  80. static inline pci_ers_result_t merge_result(enum pci_ers_result orig,
  81. enum pci_ers_result new)
  82. {
  83. if (new == PCI_ERS_RESULT_NONE)
  84. return orig;
  85. switch (orig) {
  86. case PCI_ERS_RESULT_CAN_RECOVER:
  87. case PCI_ERS_RESULT_RECOVERED:
  88. orig = new;
  89. break;
  90. case PCI_ERS_RESULT_DISCONNECT:
  91. if (new == PCI_ERS_RESULT_NEED_RESET)
  92. orig = new;
  93. break;
  94. default:
  95. break;
  96. }
  97. return orig;
  98. }
  99. extern struct bus_type pcie_port_bus_type;
  100. extern void aer_enable_rootport(struct aer_rpc *rpc);
  101. extern void aer_delete_rootport(struct aer_rpc *rpc);
  102. extern int aer_init(struct pcie_device *dev);
  103. extern void aer_isr(struct work_struct *work);
  104. extern void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
  105. extern void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info);
  106. extern irqreturn_t aer_irq(int irq, void *context);
  107. #ifdef CONFIG_ACPI
  108. extern int aer_osc_setup(struct pcie_device *pciedev);
  109. #else
  110. static inline int aer_osc_setup(struct pcie_device *pciedev)
  111. {
  112. return 0;
  113. }
  114. #endif
  115. #endif /* _AERDRV_H_ */