tx.c 17 KB

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  1. /*
  2. * Intel Wireless Multicomm 3200 WiFi driver
  3. *
  4. * Copyright (C) 2009 Intel Corporation. All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. *
  10. * * Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions and the following disclaimer.
  12. * * Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in
  14. * the documentation and/or other materials provided with the
  15. * distribution.
  16. * * Neither the name of Intel Corporation nor the names of its
  17. * contributors may be used to endorse or promote products derived
  18. * from this software without specific prior written permission.
  19. *
  20. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31. *
  32. *
  33. * Intel Corporation <ilw@linux.intel.com>
  34. * Samuel Ortiz <samuel.ortiz@intel.com>
  35. * Zhu Yi <yi.zhu@intel.com>
  36. *
  37. */
  38. /*
  39. * iwm Tx theory of operation:
  40. *
  41. * 1) We receive a 802.3 frame from the stack
  42. * 2) We convert it to a 802.11 frame [iwm_xmit_frame]
  43. * 3) We queue it to its corresponding tx queue [iwm_xmit_frame]
  44. * 4) We schedule the tx worker. There is one worker per tx
  45. * queue. [iwm_xmit_frame]
  46. * 5) The tx worker is scheduled
  47. * 6) We go through every queued skb on the tx queue, and for each
  48. * and every one of them: [iwm_tx_worker]
  49. * a) We check if we have enough Tx credits (see below for a Tx
  50. * credits description) for the frame length. [iwm_tx_worker]
  51. * b) If we do, we aggregate the Tx frame into a UDMA one, by
  52. * concatenating one REPLY_TX command per Tx frame. [iwm_tx_worker]
  53. * c) When we run out of credits, or when we reach the maximum
  54. * concatenation size, we actually send the concatenated UDMA
  55. * frame. [iwm_tx_worker]
  56. *
  57. * When we run out of Tx credits, the skbs are filling the tx queue,
  58. * and eventually we will stop the netdev queue. [iwm_tx_worker]
  59. * The tx queue is emptied as we're getting new tx credits, by
  60. * scheduling the tx_worker. [iwm_tx_credit_inc]
  61. * The netdev queue is started again when we have enough tx credits,
  62. * and when our tx queue has some reasonable amout of space available
  63. * (i.e. half of the max size). [iwm_tx_worker]
  64. */
  65. #include <linux/skbuff.h>
  66. #include <linux/netdevice.h>
  67. #include <linux/ieee80211.h>
  68. #include "iwm.h"
  69. #include "debug.h"
  70. #include "commands.h"
  71. #include "hal.h"
  72. #include "umac.h"
  73. #include "bus.h"
  74. #define IWM_UMAC_PAGE_ALLOC_WRAP 0xffff
  75. #define BYTES_TO_PAGES(n) (1 + ((n) >> ilog2(IWM_UMAC_PAGE_SIZE)) - \
  76. (((n) & (IWM_UMAC_PAGE_SIZE - 1)) == 0))
  77. #define pool_id_to_queue(id) ((id < IWM_TX_CMD_QUEUE) ? id : id - 1)
  78. #define queue_to_pool_id(q) ((q < IWM_TX_CMD_QUEUE) ? q : q + 1)
  79. /* require to hold tx_credit lock */
  80. static int iwm_tx_credit_get(struct iwm_tx_credit *tx_credit, int id)
  81. {
  82. struct pool_entry *pool = &tx_credit->pools[id];
  83. struct spool_entry *spool = &tx_credit->spools[pool->sid];
  84. int spool_pages;
  85. /* number of pages can be taken from spool by this pool */
  86. spool_pages = spool->max_pages - spool->alloc_pages +
  87. max(pool->min_pages - pool->alloc_pages, 0);
  88. return min(pool->max_pages - pool->alloc_pages, spool_pages);
  89. }
  90. static bool iwm_tx_credit_ok(struct iwm_priv *iwm, int id, int nb)
  91. {
  92. u32 npages = BYTES_TO_PAGES(nb);
  93. if (npages <= iwm_tx_credit_get(&iwm->tx_credit, id))
  94. return 1;
  95. set_bit(id, &iwm->tx_credit.full_pools_map);
  96. IWM_DBG_TX(iwm, DBG, "LINK: stop txq[%d], available credit: %d\n",
  97. pool_id_to_queue(id),
  98. iwm_tx_credit_get(&iwm->tx_credit, id));
  99. return 0;
  100. }
  101. void iwm_tx_credit_inc(struct iwm_priv *iwm, int id, int total_freed_pages)
  102. {
  103. struct pool_entry *pool;
  104. struct spool_entry *spool;
  105. int freed_pages;
  106. int queue;
  107. BUG_ON(id >= IWM_MACS_OUT_GROUPS);
  108. pool = &iwm->tx_credit.pools[id];
  109. spool = &iwm->tx_credit.spools[pool->sid];
  110. freed_pages = total_freed_pages - pool->total_freed_pages;
  111. IWM_DBG_TX(iwm, DBG, "Free %d pages for pool[%d]\n", freed_pages, id);
  112. if (!freed_pages) {
  113. IWM_DBG_TX(iwm, DBG, "No pages are freed by UMAC\n");
  114. return;
  115. } else if (freed_pages < 0)
  116. freed_pages += IWM_UMAC_PAGE_ALLOC_WRAP + 1;
  117. if (pool->alloc_pages > pool->min_pages) {
  118. int spool_pages = pool->alloc_pages - pool->min_pages;
  119. spool_pages = min(spool_pages, freed_pages);
  120. spool->alloc_pages -= spool_pages;
  121. }
  122. pool->alloc_pages -= freed_pages;
  123. pool->total_freed_pages = total_freed_pages;
  124. IWM_DBG_TX(iwm, DBG, "Pool[%d] pages alloc: %d, total_freed: %d, "
  125. "Spool[%d] pages alloc: %d\n", id, pool->alloc_pages,
  126. pool->total_freed_pages, pool->sid, spool->alloc_pages);
  127. if (test_bit(id, &iwm->tx_credit.full_pools_map) &&
  128. (pool->alloc_pages < pool->max_pages / 2)) {
  129. clear_bit(id, &iwm->tx_credit.full_pools_map);
  130. queue = pool_id_to_queue(id);
  131. IWM_DBG_TX(iwm, DBG, "LINK: start txq[%d], available "
  132. "credit: %d\n", queue,
  133. iwm_tx_credit_get(&iwm->tx_credit, id));
  134. queue_work(iwm->txq[queue].wq, &iwm->txq[queue].worker);
  135. }
  136. }
  137. static void iwm_tx_credit_dec(struct iwm_priv *iwm, int id, int alloc_pages)
  138. {
  139. struct pool_entry *pool;
  140. struct spool_entry *spool;
  141. int spool_pages;
  142. IWM_DBG_TX(iwm, DBG, "Allocate %d pages for pool[%d]\n",
  143. alloc_pages, id);
  144. BUG_ON(id >= IWM_MACS_OUT_GROUPS);
  145. pool = &iwm->tx_credit.pools[id];
  146. spool = &iwm->tx_credit.spools[pool->sid];
  147. spool_pages = pool->alloc_pages + alloc_pages - pool->min_pages;
  148. if (pool->alloc_pages >= pool->min_pages)
  149. spool->alloc_pages += alloc_pages;
  150. else if (spool_pages > 0)
  151. spool->alloc_pages += spool_pages;
  152. pool->alloc_pages += alloc_pages;
  153. IWM_DBG_TX(iwm, DBG, "Pool[%d] pages alloc: %d, total_freed: %d, "
  154. "Spool[%d] pages alloc: %d\n", id, pool->alloc_pages,
  155. pool->total_freed_pages, pool->sid, spool->alloc_pages);
  156. }
  157. int iwm_tx_credit_alloc(struct iwm_priv *iwm, int id, int nb)
  158. {
  159. u32 npages = BYTES_TO_PAGES(nb);
  160. int ret = 0;
  161. spin_lock(&iwm->tx_credit.lock);
  162. if (!iwm_tx_credit_ok(iwm, id, nb)) {
  163. IWM_DBG_TX(iwm, DBG, "No credit avaliable for pool[%d]\n", id);
  164. ret = -ENOSPC;
  165. goto out;
  166. }
  167. iwm_tx_credit_dec(iwm, id, npages);
  168. out:
  169. spin_unlock(&iwm->tx_credit.lock);
  170. return ret;
  171. }
  172. /*
  173. * Since we're on an SDIO or USB bus, we are not sharing memory
  174. * for storing to be transmitted frames. The host needs to push
  175. * them upstream. As a consequence there needs to be a way for
  176. * the target to let us know if it can actually take more TX frames
  177. * or not. This is what Tx credits are for.
  178. *
  179. * For each Tx HW queue, we have a Tx pool, and then we have one
  180. * unique super pool (spool), which is actually a global pool of
  181. * all the UMAC pages.
  182. * For each Tx pool we have a min_pages, a max_pages fields, and a
  183. * alloc_pages fields. The alloc_pages tracks the number of pages
  184. * currently allocated from the tx pool.
  185. * Here are the rules to check if given a tx frame we have enough
  186. * tx credits for it:
  187. * 1) We translate the frame length into a number of UMAC pages.
  188. * Let's call them n_pages.
  189. * 2) For the corresponding tx pool, we check if n_pages +
  190. * pool->alloc_pages is higher than pool->min_pages. min_pages
  191. * represent a set of pre-allocated pages on the tx pool. If
  192. * that's the case, then we need to allocate those pages from
  193. * the spool. We can do so until we reach spool->max_pages.
  194. * 3) Each tx pool is not allowed to allocate more than pool->max_pages
  195. * from the spool, so once we're over min_pages, we can allocate
  196. * pages from the spool, but not more than max_pages.
  197. *
  198. * When the tx code path needs to send a tx frame, it checks first
  199. * if it has enough tx credits, following those rules. [iwm_tx_credit_get]
  200. * If it does, it then updates the pool and spool counters and
  201. * then send the frame. [iwm_tx_credit_alloc and iwm_tx_credit_dec]
  202. * On the other side, when the UMAC is done transmitting frames, it
  203. * will send a credit update notification to the host. This is when
  204. * the pool and spool counters gets to be decreased. [iwm_tx_credit_inc,
  205. * called from rx.c:iwm_ntf_tx_credit_update]
  206. *
  207. */
  208. void iwm_tx_credit_init_pools(struct iwm_priv *iwm,
  209. struct iwm_umac_notif_alive *alive)
  210. {
  211. int i, sid, pool_pages;
  212. spin_lock(&iwm->tx_credit.lock);
  213. iwm->tx_credit.pool_nr = le16_to_cpu(alive->page_grp_count);
  214. iwm->tx_credit.full_pools_map = 0;
  215. memset(&iwm->tx_credit.spools[0], 0, sizeof(struct spool_entry));
  216. IWM_DBG_TX(iwm, DBG, "Pools number is %d\n", iwm->tx_credit.pool_nr);
  217. for (i = 0; i < iwm->tx_credit.pool_nr; i++) {
  218. __le32 page_grp_state = alive->page_grp_state[i];
  219. iwm->tx_credit.pools[i].id = GET_VAL32(page_grp_state,
  220. UMAC_ALIVE_PAGE_STS_GRP_NUM);
  221. iwm->tx_credit.pools[i].sid = GET_VAL32(page_grp_state,
  222. UMAC_ALIVE_PAGE_STS_SGRP_NUM);
  223. iwm->tx_credit.pools[i].min_pages = GET_VAL32(page_grp_state,
  224. UMAC_ALIVE_PAGE_STS_GRP_MIN_SIZE);
  225. iwm->tx_credit.pools[i].max_pages = GET_VAL32(page_grp_state,
  226. UMAC_ALIVE_PAGE_STS_GRP_MAX_SIZE);
  227. iwm->tx_credit.pools[i].alloc_pages = 0;
  228. iwm->tx_credit.pools[i].total_freed_pages = 0;
  229. sid = iwm->tx_credit.pools[i].sid;
  230. pool_pages = iwm->tx_credit.pools[i].min_pages;
  231. if (iwm->tx_credit.spools[sid].max_pages == 0) {
  232. iwm->tx_credit.spools[sid].id = sid;
  233. iwm->tx_credit.spools[sid].max_pages =
  234. GET_VAL32(page_grp_state,
  235. UMAC_ALIVE_PAGE_STS_SGRP_MAX_SIZE);
  236. iwm->tx_credit.spools[sid].alloc_pages = 0;
  237. }
  238. iwm->tx_credit.spools[sid].alloc_pages += pool_pages;
  239. IWM_DBG_TX(iwm, DBG, "Pool idx: %d, id: %d, sid: %d, capacity "
  240. "min: %d, max: %d, pool alloc: %d, total_free: %d, "
  241. "super poll alloc: %d\n",
  242. i, iwm->tx_credit.pools[i].id,
  243. iwm->tx_credit.pools[i].sid,
  244. iwm->tx_credit.pools[i].min_pages,
  245. iwm->tx_credit.pools[i].max_pages,
  246. iwm->tx_credit.pools[i].alloc_pages,
  247. iwm->tx_credit.pools[i].total_freed_pages,
  248. iwm->tx_credit.spools[sid].alloc_pages);
  249. }
  250. spin_unlock(&iwm->tx_credit.lock);
  251. }
  252. #define IWM_UDMA_HDR_LEN sizeof(struct iwm_umac_wifi_out_hdr)
  253. static int iwm_tx_build_packet(struct iwm_priv *iwm, struct sk_buff *skb,
  254. int pool_id, u8 *buf)
  255. {
  256. struct iwm_umac_wifi_out_hdr *hdr = (struct iwm_umac_wifi_out_hdr *)buf;
  257. struct iwm_udma_wifi_cmd udma_cmd;
  258. struct iwm_umac_cmd umac_cmd;
  259. struct iwm_tx_info *tx_info = skb_to_tx_info(skb);
  260. udma_cmd.count = cpu_to_le16(skb->len +
  261. sizeof(struct iwm_umac_fw_cmd_hdr));
  262. /* set EOP to 0 here. iwm_udma_wifi_hdr_set_eop() will be
  263. * called later to set EOP for the last packet. */
  264. udma_cmd.eop = 0;
  265. udma_cmd.credit_group = pool_id;
  266. udma_cmd.ra_tid = tx_info->sta << 4 | tx_info->tid;
  267. udma_cmd.lmac_offset = 0;
  268. umac_cmd.id = REPLY_TX;
  269. umac_cmd.count = cpu_to_le16(skb->len);
  270. umac_cmd.color = tx_info->color;
  271. umac_cmd.resp = 0;
  272. umac_cmd.seq_num = cpu_to_le16(iwm_alloc_wifi_cmd_seq(iwm));
  273. iwm_build_udma_wifi_hdr(iwm, &hdr->hw_hdr, &udma_cmd);
  274. iwm_build_umac_hdr(iwm, &hdr->sw_hdr, &umac_cmd);
  275. memcpy(buf + sizeof(*hdr), skb->data, skb->len);
  276. return umac_cmd.seq_num;
  277. }
  278. static int iwm_tx_send_concat_packets(struct iwm_priv *iwm,
  279. struct iwm_tx_queue *txq)
  280. {
  281. int ret;
  282. if (!txq->concat_count)
  283. return 0;
  284. IWM_DBG_TX(iwm, DBG, "Send concatenated Tx: queue %d, %d bytes\n",
  285. txq->id, txq->concat_count);
  286. /* mark EOP for the last packet */
  287. iwm_udma_wifi_hdr_set_eop(iwm, txq->concat_ptr, 1);
  288. ret = iwm_bus_send_chunk(iwm, txq->concat_buf, txq->concat_count);
  289. txq->concat_count = 0;
  290. txq->concat_ptr = txq->concat_buf;
  291. return ret;
  292. }
  293. void iwm_tx_worker(struct work_struct *work)
  294. {
  295. struct iwm_priv *iwm;
  296. struct iwm_tx_info *tx_info = NULL;
  297. struct sk_buff *skb;
  298. struct iwm_tx_queue *txq;
  299. struct iwm_sta_info *sta_info;
  300. struct iwm_tid_info *tid_info;
  301. int cmdlen, ret, pool_id;
  302. txq = container_of(work, struct iwm_tx_queue, worker);
  303. iwm = container_of(txq, struct iwm_priv, txq[txq->id]);
  304. pool_id = queue_to_pool_id(txq->id);
  305. while (!test_bit(pool_id, &iwm->tx_credit.full_pools_map) &&
  306. !skb_queue_empty(&txq->queue)) {
  307. spin_lock_bh(&txq->lock);
  308. skb = skb_dequeue(&txq->queue);
  309. spin_unlock_bh(&txq->lock);
  310. tx_info = skb_to_tx_info(skb);
  311. sta_info = &iwm->sta_table[tx_info->sta];
  312. if (!sta_info->valid) {
  313. IWM_ERR(iwm, "Trying to send a frame to unknown STA\n");
  314. kfree_skb(skb);
  315. continue;
  316. }
  317. tid_info = &sta_info->tid_info[tx_info->tid];
  318. mutex_lock(&tid_info->mutex);
  319. /*
  320. * If the RAxTID is stopped, we queue the skb to the stopped
  321. * queue.
  322. * Whenever we'll get a UMAC notification to resume the tx flow
  323. * for this RAxTID, we'll merge back the stopped queue into the
  324. * regular queue. See iwm_ntf_stop_resume_tx() from rx.c.
  325. */
  326. if (tid_info->stopped) {
  327. IWM_DBG_TX(iwm, DBG, "%dx%d stopped\n",
  328. tx_info->sta, tx_info->tid);
  329. spin_lock_bh(&txq->lock);
  330. skb_queue_tail(&txq->stopped_queue, skb);
  331. spin_unlock_bh(&txq->lock);
  332. mutex_unlock(&tid_info->mutex);
  333. continue;
  334. }
  335. cmdlen = IWM_UDMA_HDR_LEN + skb->len;
  336. IWM_DBG_TX(iwm, DBG, "Tx frame on queue %d: skb: 0x%p, sta: "
  337. "%d, color: %d\n", txq->id, skb, tx_info->sta,
  338. tx_info->color);
  339. if (txq->concat_count + cmdlen > IWM_HAL_CONCATENATE_BUF_SIZE)
  340. iwm_tx_send_concat_packets(iwm, txq);
  341. ret = iwm_tx_credit_alloc(iwm, pool_id, cmdlen);
  342. if (ret) {
  343. IWM_DBG_TX(iwm, DBG, "not enough tx_credit for queue "
  344. "%d, Tx worker stopped\n", txq->id);
  345. spin_lock_bh(&txq->lock);
  346. skb_queue_head(&txq->queue, skb);
  347. spin_unlock_bh(&txq->lock);
  348. mutex_unlock(&tid_info->mutex);
  349. break;
  350. }
  351. txq->concat_ptr = txq->concat_buf + txq->concat_count;
  352. tid_info->last_seq_num =
  353. iwm_tx_build_packet(iwm, skb, pool_id, txq->concat_ptr);
  354. txq->concat_count += ALIGN(cmdlen, 16);
  355. mutex_unlock(&tid_info->mutex);
  356. kfree_skb(skb);
  357. }
  358. iwm_tx_send_concat_packets(iwm, txq);
  359. if (__netif_subqueue_stopped(iwm_to_ndev(iwm), txq->id) &&
  360. !test_bit(pool_id, &iwm->tx_credit.full_pools_map) &&
  361. (skb_queue_len(&txq->queue) < IWM_TX_LIST_SIZE / 2)) {
  362. IWM_DBG_TX(iwm, DBG, "LINK: start netif_subqueue[%d]", txq->id);
  363. netif_wake_subqueue(iwm_to_ndev(iwm), txq->id);
  364. }
  365. }
  366. int iwm_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
  367. {
  368. struct iwm_priv *iwm = ndev_to_iwm(netdev);
  369. struct net_device *ndev = iwm_to_ndev(iwm);
  370. struct wireless_dev *wdev = iwm_to_wdev(iwm);
  371. struct iwm_tx_info *tx_info;
  372. struct iwm_tx_queue *txq;
  373. struct iwm_sta_info *sta_info;
  374. u8 *dst_addr, sta_id;
  375. u16 queue;
  376. int ret;
  377. if (!test_bit(IWM_STATUS_ASSOCIATED, &iwm->status)) {
  378. IWM_DBG_TX(iwm, DBG, "LINK: stop netif_all_queues: "
  379. "not associated\n");
  380. netif_tx_stop_all_queues(netdev);
  381. goto drop;
  382. }
  383. queue = skb_get_queue_mapping(skb);
  384. BUG_ON(queue >= IWM_TX_DATA_QUEUES); /* no iPAN yet */
  385. txq = &iwm->txq[queue];
  386. /* No free space for Tx, tx_worker is too slow */
  387. if ((skb_queue_len(&txq->queue) > IWM_TX_LIST_SIZE) ||
  388. (skb_queue_len(&txq->stopped_queue) > IWM_TX_LIST_SIZE)) {
  389. IWM_DBG_TX(iwm, DBG, "LINK: stop netif_subqueue[%d]\n", queue);
  390. netif_stop_subqueue(netdev, queue);
  391. return NETDEV_TX_BUSY;
  392. }
  393. ret = ieee80211_data_from_8023(skb, netdev->dev_addr, wdev->iftype,
  394. iwm->bssid, 0);
  395. if (ret) {
  396. IWM_ERR(iwm, "build wifi header failed\n");
  397. goto drop;
  398. }
  399. dst_addr = ((struct ieee80211_hdr *)(skb->data))->addr1;
  400. for (sta_id = 0; sta_id < IWM_STA_TABLE_NUM; sta_id++) {
  401. sta_info = &iwm->sta_table[sta_id];
  402. if (sta_info->valid &&
  403. !memcmp(dst_addr, sta_info->addr, ETH_ALEN))
  404. break;
  405. }
  406. if (sta_id == IWM_STA_TABLE_NUM) {
  407. IWM_ERR(iwm, "STA %pM not found in sta_table, Tx ignored\n",
  408. dst_addr);
  409. goto drop;
  410. }
  411. tx_info = skb_to_tx_info(skb);
  412. tx_info->sta = sta_id;
  413. tx_info->color = sta_info->color;
  414. /* UMAC uses TID 8 (vs. 0) for non QoS packets */
  415. if (sta_info->qos)
  416. tx_info->tid = skb->priority;
  417. else
  418. tx_info->tid = IWM_UMAC_MGMT_TID;
  419. spin_lock_bh(&iwm->txq[queue].lock);
  420. skb_queue_tail(&iwm->txq[queue].queue, skb);
  421. spin_unlock_bh(&iwm->txq[queue].lock);
  422. queue_work(iwm->txq[queue].wq, &iwm->txq[queue].worker);
  423. ndev->stats.tx_packets++;
  424. ndev->stats.tx_bytes += skb->len;
  425. return NETDEV_TX_OK;
  426. drop:
  427. ndev->stats.tx_dropped++;
  428. dev_kfree_skb_any(skb);
  429. return NETDEV_TX_OK;
  430. }