sh_eth.c 39 KB

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  1. /*
  2. * SuperH Ethernet device driver
  3. *
  4. * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
  5. * Copyright (C) 2008-2009 Renesas Solutions Corp.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program; if not, write to the Free Software Foundation, Inc.,
  17. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18. *
  19. * The full GNU General Public License is included in this distribution in
  20. * the file called "COPYING".
  21. */
  22. #include <linux/init.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/delay.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/mdio-bitbang.h>
  28. #include <linux/netdevice.h>
  29. #include <linux/phy.h>
  30. #include <linux/cache.h>
  31. #include <linux/io.h>
  32. #include <linux/pm_runtime.h>
  33. #include <asm/cacheflush.h>
  34. #include "sh_eth.h"
  35. /* There is CPU dependent code */
  36. #if defined(CONFIG_CPU_SUBTYPE_SH7724)
  37. #define SH_ETH_RESET_DEFAULT 1
  38. static void sh_eth_set_duplex(struct net_device *ndev)
  39. {
  40. struct sh_eth_private *mdp = netdev_priv(ndev);
  41. u32 ioaddr = ndev->base_addr;
  42. if (mdp->duplex) /* Full */
  43. ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
  44. else /* Half */
  45. ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
  46. }
  47. static void sh_eth_set_rate(struct net_device *ndev)
  48. {
  49. struct sh_eth_private *mdp = netdev_priv(ndev);
  50. u32 ioaddr = ndev->base_addr;
  51. switch (mdp->speed) {
  52. case 10: /* 10BASE */
  53. ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_RTM, ioaddr + ECMR);
  54. break;
  55. case 100:/* 100BASE */
  56. ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_RTM, ioaddr + ECMR);
  57. break;
  58. default:
  59. break;
  60. }
  61. }
  62. /* SH7724 */
  63. static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
  64. .set_duplex = sh_eth_set_duplex,
  65. .set_rate = sh_eth_set_rate,
  66. .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
  67. .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
  68. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
  69. .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
  70. .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
  71. EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
  72. .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
  73. .apr = 1,
  74. .mpr = 1,
  75. .tpauser = 1,
  76. .hw_swap = 1,
  77. .rpadir = 1,
  78. .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
  79. };
  80. #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
  81. #define SH_ETH_HAS_TSU 1
  82. static void sh_eth_chip_reset(struct net_device *ndev)
  83. {
  84. /* reset device */
  85. ctrl_outl(ARSTR_ARSTR, ARSTR);
  86. mdelay(1);
  87. }
  88. static void sh_eth_reset(struct net_device *ndev)
  89. {
  90. u32 ioaddr = ndev->base_addr;
  91. int cnt = 100;
  92. ctrl_outl(EDSR_ENALL, ioaddr + EDSR);
  93. ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
  94. while (cnt > 0) {
  95. if (!(ctrl_inl(ioaddr + EDMR) & 0x3))
  96. break;
  97. mdelay(1);
  98. cnt--;
  99. }
  100. if (cnt == 0)
  101. printk(KERN_ERR "Device reset fail\n");
  102. /* Table Init */
  103. ctrl_outl(0x0, ioaddr + TDLAR);
  104. ctrl_outl(0x0, ioaddr + TDFAR);
  105. ctrl_outl(0x0, ioaddr + TDFXR);
  106. ctrl_outl(0x0, ioaddr + TDFFR);
  107. ctrl_outl(0x0, ioaddr + RDLAR);
  108. ctrl_outl(0x0, ioaddr + RDFAR);
  109. ctrl_outl(0x0, ioaddr + RDFXR);
  110. ctrl_outl(0x0, ioaddr + RDFFR);
  111. }
  112. static void sh_eth_set_duplex(struct net_device *ndev)
  113. {
  114. struct sh_eth_private *mdp = netdev_priv(ndev);
  115. u32 ioaddr = ndev->base_addr;
  116. if (mdp->duplex) /* Full */
  117. ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
  118. else /* Half */
  119. ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
  120. }
  121. static void sh_eth_set_rate(struct net_device *ndev)
  122. {
  123. struct sh_eth_private *mdp = netdev_priv(ndev);
  124. u32 ioaddr = ndev->base_addr;
  125. switch (mdp->speed) {
  126. case 10: /* 10BASE */
  127. ctrl_outl(GECMR_10, ioaddr + GECMR);
  128. break;
  129. case 100:/* 100BASE */
  130. ctrl_outl(GECMR_100, ioaddr + GECMR);
  131. break;
  132. case 1000: /* 1000BASE */
  133. ctrl_outl(GECMR_1000, ioaddr + GECMR);
  134. break;
  135. default:
  136. break;
  137. }
  138. }
  139. /* sh7763 */
  140. static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
  141. .chip_reset = sh_eth_chip_reset,
  142. .set_duplex = sh_eth_set_duplex,
  143. .set_rate = sh_eth_set_rate,
  144. .ecsr_value = ECSR_ICD | ECSR_MPD,
  145. .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
  146. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  147. .tx_check = EESR_TC1 | EESR_FTC,
  148. .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
  149. EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
  150. EESR_ECI,
  151. .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
  152. EESR_TFE,
  153. .apr = 1,
  154. .mpr = 1,
  155. .tpauser = 1,
  156. .bculr = 1,
  157. .hw_swap = 1,
  158. .no_trimd = 1,
  159. .no_ade = 1,
  160. };
  161. #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
  162. #define SH_ETH_RESET_DEFAULT 1
  163. static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
  164. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  165. .apr = 1,
  166. .mpr = 1,
  167. .tpauser = 1,
  168. .hw_swap = 1,
  169. };
  170. #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
  171. #define SH_ETH_RESET_DEFAULT 1
  172. #define SH_ETH_HAS_TSU 1
  173. static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
  174. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  175. };
  176. #endif
  177. static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
  178. {
  179. if (!cd->ecsr_value)
  180. cd->ecsr_value = DEFAULT_ECSR_INIT;
  181. if (!cd->ecsipr_value)
  182. cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
  183. if (!cd->fcftr_value)
  184. cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
  185. DEFAULT_FIFO_F_D_RFD;
  186. if (!cd->fdr_value)
  187. cd->fdr_value = DEFAULT_FDR_INIT;
  188. if (!cd->rmcr_value)
  189. cd->rmcr_value = DEFAULT_RMCR_VALUE;
  190. if (!cd->tx_check)
  191. cd->tx_check = DEFAULT_TX_CHECK;
  192. if (!cd->eesr_err_check)
  193. cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
  194. if (!cd->tx_error_check)
  195. cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
  196. }
  197. #if defined(SH_ETH_RESET_DEFAULT)
  198. /* Chip Reset */
  199. static void sh_eth_reset(struct net_device *ndev)
  200. {
  201. u32 ioaddr = ndev->base_addr;
  202. ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
  203. mdelay(3);
  204. ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
  205. }
  206. #endif
  207. #if defined(CONFIG_CPU_SH4)
  208. static void sh_eth_set_receive_align(struct sk_buff *skb)
  209. {
  210. int reserve;
  211. reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
  212. if (reserve)
  213. skb_reserve(skb, reserve);
  214. }
  215. #else
  216. static void sh_eth_set_receive_align(struct sk_buff *skb)
  217. {
  218. skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
  219. }
  220. #endif
  221. /* CPU <-> EDMAC endian convert */
  222. static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
  223. {
  224. switch (mdp->edmac_endian) {
  225. case EDMAC_LITTLE_ENDIAN:
  226. return cpu_to_le32(x);
  227. case EDMAC_BIG_ENDIAN:
  228. return cpu_to_be32(x);
  229. }
  230. return x;
  231. }
  232. static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
  233. {
  234. switch (mdp->edmac_endian) {
  235. case EDMAC_LITTLE_ENDIAN:
  236. return le32_to_cpu(x);
  237. case EDMAC_BIG_ENDIAN:
  238. return be32_to_cpu(x);
  239. }
  240. return x;
  241. }
  242. /*
  243. * Program the hardware MAC address from dev->dev_addr.
  244. */
  245. static void update_mac_address(struct net_device *ndev)
  246. {
  247. u32 ioaddr = ndev->base_addr;
  248. ctrl_outl((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
  249. (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]),
  250. ioaddr + MAHR);
  251. ctrl_outl((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]),
  252. ioaddr + MALR);
  253. }
  254. /*
  255. * Get MAC address from SuperH MAC address register
  256. *
  257. * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
  258. * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
  259. * When you want use this device, you must set MAC address in bootloader.
  260. *
  261. */
  262. static void read_mac_address(struct net_device *ndev, unsigned char *mac)
  263. {
  264. u32 ioaddr = ndev->base_addr;
  265. if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
  266. memcpy(ndev->dev_addr, mac, 6);
  267. } else {
  268. ndev->dev_addr[0] = (ctrl_inl(ioaddr + MAHR) >> 24);
  269. ndev->dev_addr[1] = (ctrl_inl(ioaddr + MAHR) >> 16) & 0xFF;
  270. ndev->dev_addr[2] = (ctrl_inl(ioaddr + MAHR) >> 8) & 0xFF;
  271. ndev->dev_addr[3] = (ctrl_inl(ioaddr + MAHR) & 0xFF);
  272. ndev->dev_addr[4] = (ctrl_inl(ioaddr + MALR) >> 8) & 0xFF;
  273. ndev->dev_addr[5] = (ctrl_inl(ioaddr + MALR) & 0xFF);
  274. }
  275. }
  276. struct bb_info {
  277. struct mdiobb_ctrl ctrl;
  278. u32 addr;
  279. u32 mmd_msk;/* MMD */
  280. u32 mdo_msk;
  281. u32 mdi_msk;
  282. u32 mdc_msk;
  283. };
  284. /* PHY bit set */
  285. static void bb_set(u32 addr, u32 msk)
  286. {
  287. ctrl_outl(ctrl_inl(addr) | msk, addr);
  288. }
  289. /* PHY bit clear */
  290. static void bb_clr(u32 addr, u32 msk)
  291. {
  292. ctrl_outl((ctrl_inl(addr) & ~msk), addr);
  293. }
  294. /* PHY bit read */
  295. static int bb_read(u32 addr, u32 msk)
  296. {
  297. return (ctrl_inl(addr) & msk) != 0;
  298. }
  299. /* Data I/O pin control */
  300. static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
  301. {
  302. struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
  303. if (bit)
  304. bb_set(bitbang->addr, bitbang->mmd_msk);
  305. else
  306. bb_clr(bitbang->addr, bitbang->mmd_msk);
  307. }
  308. /* Set bit data*/
  309. static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
  310. {
  311. struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
  312. if (bit)
  313. bb_set(bitbang->addr, bitbang->mdo_msk);
  314. else
  315. bb_clr(bitbang->addr, bitbang->mdo_msk);
  316. }
  317. /* Get bit data*/
  318. static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
  319. {
  320. struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
  321. return bb_read(bitbang->addr, bitbang->mdi_msk);
  322. }
  323. /* MDC pin control */
  324. static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
  325. {
  326. struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
  327. if (bit)
  328. bb_set(bitbang->addr, bitbang->mdc_msk);
  329. else
  330. bb_clr(bitbang->addr, bitbang->mdc_msk);
  331. }
  332. /* mdio bus control struct */
  333. static struct mdiobb_ops bb_ops = {
  334. .owner = THIS_MODULE,
  335. .set_mdc = sh_mdc_ctrl,
  336. .set_mdio_dir = sh_mmd_ctrl,
  337. .set_mdio_data = sh_set_mdio,
  338. .get_mdio_data = sh_get_mdio,
  339. };
  340. /* free skb and descriptor buffer */
  341. static void sh_eth_ring_free(struct net_device *ndev)
  342. {
  343. struct sh_eth_private *mdp = netdev_priv(ndev);
  344. int i;
  345. /* Free Rx skb ringbuffer */
  346. if (mdp->rx_skbuff) {
  347. for (i = 0; i < RX_RING_SIZE; i++) {
  348. if (mdp->rx_skbuff[i])
  349. dev_kfree_skb(mdp->rx_skbuff[i]);
  350. }
  351. }
  352. kfree(mdp->rx_skbuff);
  353. /* Free Tx skb ringbuffer */
  354. if (mdp->tx_skbuff) {
  355. for (i = 0; i < TX_RING_SIZE; i++) {
  356. if (mdp->tx_skbuff[i])
  357. dev_kfree_skb(mdp->tx_skbuff[i]);
  358. }
  359. }
  360. kfree(mdp->tx_skbuff);
  361. }
  362. /* format skb and descriptor buffer */
  363. static void sh_eth_ring_format(struct net_device *ndev)
  364. {
  365. u32 ioaddr = ndev->base_addr;
  366. struct sh_eth_private *mdp = netdev_priv(ndev);
  367. int i;
  368. struct sk_buff *skb;
  369. struct sh_eth_rxdesc *rxdesc = NULL;
  370. struct sh_eth_txdesc *txdesc = NULL;
  371. int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
  372. int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
  373. mdp->cur_rx = mdp->cur_tx = 0;
  374. mdp->dirty_rx = mdp->dirty_tx = 0;
  375. memset(mdp->rx_ring, 0, rx_ringsize);
  376. /* build Rx ring buffer */
  377. for (i = 0; i < RX_RING_SIZE; i++) {
  378. /* skb */
  379. mdp->rx_skbuff[i] = NULL;
  380. skb = dev_alloc_skb(mdp->rx_buf_sz);
  381. mdp->rx_skbuff[i] = skb;
  382. if (skb == NULL)
  383. break;
  384. dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
  385. DMA_FROM_DEVICE);
  386. skb->dev = ndev; /* Mark as being used by this device. */
  387. sh_eth_set_receive_align(skb);
  388. /* RX descriptor */
  389. rxdesc = &mdp->rx_ring[i];
  390. rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
  391. rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
  392. /* The size of the buffer is 16 byte boundary. */
  393. rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
  394. /* Rx descriptor address set */
  395. if (i == 0) {
  396. ctrl_outl(mdp->rx_desc_dma, ioaddr + RDLAR);
  397. #if defined(CONFIG_CPU_SUBTYPE_SH7763)
  398. ctrl_outl(mdp->rx_desc_dma, ioaddr + RDFAR);
  399. #endif
  400. }
  401. }
  402. mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
  403. /* Mark the last entry as wrapping the ring. */
  404. rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
  405. memset(mdp->tx_ring, 0, tx_ringsize);
  406. /* build Tx ring buffer */
  407. for (i = 0; i < TX_RING_SIZE; i++) {
  408. mdp->tx_skbuff[i] = NULL;
  409. txdesc = &mdp->tx_ring[i];
  410. txdesc->status = cpu_to_edmac(mdp, TD_TFP);
  411. txdesc->buffer_length = 0;
  412. if (i == 0) {
  413. /* Tx descriptor address set */
  414. ctrl_outl(mdp->tx_desc_dma, ioaddr + TDLAR);
  415. #if defined(CONFIG_CPU_SUBTYPE_SH7763)
  416. ctrl_outl(mdp->tx_desc_dma, ioaddr + TDFAR);
  417. #endif
  418. }
  419. }
  420. txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
  421. }
  422. /* Get skb and descriptor buffer */
  423. static int sh_eth_ring_init(struct net_device *ndev)
  424. {
  425. struct sh_eth_private *mdp = netdev_priv(ndev);
  426. int rx_ringsize, tx_ringsize, ret = 0;
  427. /*
  428. * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
  429. * card needs room to do 8 byte alignment, +2 so we can reserve
  430. * the first 2 bytes, and +16 gets room for the status word from the
  431. * card.
  432. */
  433. mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
  434. (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
  435. if (mdp->cd->rpadir)
  436. mdp->rx_buf_sz += NET_IP_ALIGN;
  437. /* Allocate RX and TX skb rings */
  438. mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
  439. GFP_KERNEL);
  440. if (!mdp->rx_skbuff) {
  441. dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
  442. ret = -ENOMEM;
  443. return ret;
  444. }
  445. mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
  446. GFP_KERNEL);
  447. if (!mdp->tx_skbuff) {
  448. dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
  449. ret = -ENOMEM;
  450. goto skb_ring_free;
  451. }
  452. /* Allocate all Rx descriptors. */
  453. rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
  454. mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
  455. GFP_KERNEL);
  456. if (!mdp->rx_ring) {
  457. dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
  458. rx_ringsize);
  459. ret = -ENOMEM;
  460. goto desc_ring_free;
  461. }
  462. mdp->dirty_rx = 0;
  463. /* Allocate all Tx descriptors. */
  464. tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
  465. mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
  466. GFP_KERNEL);
  467. if (!mdp->tx_ring) {
  468. dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
  469. tx_ringsize);
  470. ret = -ENOMEM;
  471. goto desc_ring_free;
  472. }
  473. return ret;
  474. desc_ring_free:
  475. /* free DMA buffer */
  476. dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
  477. skb_ring_free:
  478. /* Free Rx and Tx skb ring buffer */
  479. sh_eth_ring_free(ndev);
  480. return ret;
  481. }
  482. static int sh_eth_dev_init(struct net_device *ndev)
  483. {
  484. int ret = 0;
  485. struct sh_eth_private *mdp = netdev_priv(ndev);
  486. u32 ioaddr = ndev->base_addr;
  487. u_int32_t rx_int_var, tx_int_var;
  488. u32 val;
  489. /* Soft Reset */
  490. sh_eth_reset(ndev);
  491. /* Descriptor format */
  492. sh_eth_ring_format(ndev);
  493. if (mdp->cd->rpadir)
  494. ctrl_outl(mdp->cd->rpadir_value, ioaddr + RPADIR);
  495. /* all sh_eth int mask */
  496. ctrl_outl(0, ioaddr + EESIPR);
  497. #if defined(__LITTLE_ENDIAN__)
  498. if (mdp->cd->hw_swap)
  499. ctrl_outl(EDMR_EL, ioaddr + EDMR);
  500. else
  501. #endif
  502. ctrl_outl(0, ioaddr + EDMR);
  503. /* FIFO size set */
  504. ctrl_outl(mdp->cd->fdr_value, ioaddr + FDR);
  505. ctrl_outl(0, ioaddr + TFTR);
  506. /* Frame recv control */
  507. ctrl_outl(mdp->cd->rmcr_value, ioaddr + RMCR);
  508. rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
  509. tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
  510. ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER);
  511. if (mdp->cd->bculr)
  512. ctrl_outl(0x800, ioaddr + BCULR); /* Burst sycle set */
  513. ctrl_outl(mdp->cd->fcftr_value, ioaddr + FCFTR);
  514. if (!mdp->cd->no_trimd)
  515. ctrl_outl(0, ioaddr + TRIMD);
  516. /* Recv frame limit set register */
  517. ctrl_outl(RFLR_VALUE, ioaddr + RFLR);
  518. ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR);
  519. ctrl_outl(mdp->cd->eesipr_value, ioaddr + EESIPR);
  520. /* PAUSE Prohibition */
  521. val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) |
  522. ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
  523. ctrl_outl(val, ioaddr + ECMR);
  524. if (mdp->cd->set_rate)
  525. mdp->cd->set_rate(ndev);
  526. /* E-MAC Status Register clear */
  527. ctrl_outl(mdp->cd->ecsr_value, ioaddr + ECSR);
  528. /* E-MAC Interrupt Enable register */
  529. ctrl_outl(mdp->cd->ecsipr_value, ioaddr + ECSIPR);
  530. /* Set MAC address */
  531. update_mac_address(ndev);
  532. /* mask reset */
  533. if (mdp->cd->apr)
  534. ctrl_outl(APR_AP, ioaddr + APR);
  535. if (mdp->cd->mpr)
  536. ctrl_outl(MPR_MP, ioaddr + MPR);
  537. if (mdp->cd->tpauser)
  538. ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
  539. /* Setting the Rx mode will start the Rx process. */
  540. ctrl_outl(EDRRR_R, ioaddr + EDRRR);
  541. netif_start_queue(ndev);
  542. return ret;
  543. }
  544. /* free Tx skb function */
  545. static int sh_eth_txfree(struct net_device *ndev)
  546. {
  547. struct sh_eth_private *mdp = netdev_priv(ndev);
  548. struct sh_eth_txdesc *txdesc;
  549. int freeNum = 0;
  550. int entry = 0;
  551. for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
  552. entry = mdp->dirty_tx % TX_RING_SIZE;
  553. txdesc = &mdp->tx_ring[entry];
  554. if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
  555. break;
  556. /* Free the original skb. */
  557. if (mdp->tx_skbuff[entry]) {
  558. dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
  559. mdp->tx_skbuff[entry] = NULL;
  560. freeNum++;
  561. }
  562. txdesc->status = cpu_to_edmac(mdp, TD_TFP);
  563. if (entry >= TX_RING_SIZE - 1)
  564. txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
  565. mdp->stats.tx_packets++;
  566. mdp->stats.tx_bytes += txdesc->buffer_length;
  567. }
  568. return freeNum;
  569. }
  570. /* Packet receive function */
  571. static int sh_eth_rx(struct net_device *ndev)
  572. {
  573. struct sh_eth_private *mdp = netdev_priv(ndev);
  574. struct sh_eth_rxdesc *rxdesc;
  575. int entry = mdp->cur_rx % RX_RING_SIZE;
  576. int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
  577. struct sk_buff *skb;
  578. u16 pkt_len = 0;
  579. u32 desc_status;
  580. rxdesc = &mdp->rx_ring[entry];
  581. while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
  582. desc_status = edmac_to_cpu(mdp, rxdesc->status);
  583. pkt_len = rxdesc->frame_length;
  584. if (--boguscnt < 0)
  585. break;
  586. if (!(desc_status & RDFEND))
  587. mdp->stats.rx_length_errors++;
  588. if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
  589. RD_RFS5 | RD_RFS6 | RD_RFS10)) {
  590. mdp->stats.rx_errors++;
  591. if (desc_status & RD_RFS1)
  592. mdp->stats.rx_crc_errors++;
  593. if (desc_status & RD_RFS2)
  594. mdp->stats.rx_frame_errors++;
  595. if (desc_status & RD_RFS3)
  596. mdp->stats.rx_length_errors++;
  597. if (desc_status & RD_RFS4)
  598. mdp->stats.rx_length_errors++;
  599. if (desc_status & RD_RFS6)
  600. mdp->stats.rx_missed_errors++;
  601. if (desc_status & RD_RFS10)
  602. mdp->stats.rx_over_errors++;
  603. } else {
  604. if (!mdp->cd->hw_swap)
  605. sh_eth_soft_swap(
  606. phys_to_virt(ALIGN(rxdesc->addr, 4)),
  607. pkt_len + 2);
  608. skb = mdp->rx_skbuff[entry];
  609. mdp->rx_skbuff[entry] = NULL;
  610. if (mdp->cd->rpadir)
  611. skb_reserve(skb, NET_IP_ALIGN);
  612. skb_put(skb, pkt_len);
  613. skb->protocol = eth_type_trans(skb, ndev);
  614. netif_rx(skb);
  615. mdp->stats.rx_packets++;
  616. mdp->stats.rx_bytes += pkt_len;
  617. }
  618. rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
  619. entry = (++mdp->cur_rx) % RX_RING_SIZE;
  620. rxdesc = &mdp->rx_ring[entry];
  621. }
  622. /* Refill the Rx ring buffers. */
  623. for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
  624. entry = mdp->dirty_rx % RX_RING_SIZE;
  625. rxdesc = &mdp->rx_ring[entry];
  626. /* The size of the buffer is 16 byte boundary. */
  627. rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
  628. if (mdp->rx_skbuff[entry] == NULL) {
  629. skb = dev_alloc_skb(mdp->rx_buf_sz);
  630. mdp->rx_skbuff[entry] = skb;
  631. if (skb == NULL)
  632. break; /* Better luck next round. */
  633. dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
  634. DMA_FROM_DEVICE);
  635. skb->dev = ndev;
  636. sh_eth_set_receive_align(skb);
  637. skb->ip_summed = CHECKSUM_NONE;
  638. rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
  639. }
  640. if (entry >= RX_RING_SIZE - 1)
  641. rxdesc->status |=
  642. cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
  643. else
  644. rxdesc->status |=
  645. cpu_to_edmac(mdp, RD_RACT | RD_RFP);
  646. }
  647. /* Restart Rx engine if stopped. */
  648. /* If we don't need to check status, don't. -KDU */
  649. if (!(ctrl_inl(ndev->base_addr + EDRRR) & EDRRR_R))
  650. ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR);
  651. return 0;
  652. }
  653. /* error control function */
  654. static void sh_eth_error(struct net_device *ndev, int intr_status)
  655. {
  656. struct sh_eth_private *mdp = netdev_priv(ndev);
  657. u32 ioaddr = ndev->base_addr;
  658. u32 felic_stat;
  659. u32 link_stat;
  660. u32 mask;
  661. if (intr_status & EESR_ECI) {
  662. felic_stat = ctrl_inl(ioaddr + ECSR);
  663. ctrl_outl(felic_stat, ioaddr + ECSR); /* clear int */
  664. if (felic_stat & ECSR_ICD)
  665. mdp->stats.tx_carrier_errors++;
  666. if (felic_stat & ECSR_LCHNG) {
  667. /* Link Changed */
  668. if (mdp->cd->no_psr || mdp->no_ether_link) {
  669. if (mdp->link == PHY_DOWN)
  670. link_stat = 0;
  671. else
  672. link_stat = PHY_ST_LINK;
  673. } else {
  674. link_stat = (ctrl_inl(ioaddr + PSR));
  675. if (mdp->ether_link_active_low)
  676. link_stat = ~link_stat;
  677. }
  678. if (!(link_stat & PHY_ST_LINK)) {
  679. /* Link Down : disable tx and rx */
  680. ctrl_outl(ctrl_inl(ioaddr + ECMR) &
  681. ~(ECMR_RE | ECMR_TE), ioaddr + ECMR);
  682. } else {
  683. /* Link Up */
  684. ctrl_outl(ctrl_inl(ioaddr + EESIPR) &
  685. ~DMAC_M_ECI, ioaddr + EESIPR);
  686. /*clear int */
  687. ctrl_outl(ctrl_inl(ioaddr + ECSR),
  688. ioaddr + ECSR);
  689. ctrl_outl(ctrl_inl(ioaddr + EESIPR) |
  690. DMAC_M_ECI, ioaddr + EESIPR);
  691. /* enable tx and rx */
  692. ctrl_outl(ctrl_inl(ioaddr + ECMR) |
  693. (ECMR_RE | ECMR_TE), ioaddr + ECMR);
  694. }
  695. }
  696. }
  697. if (intr_status & EESR_TWB) {
  698. /* Write buck end. unused write back interrupt */
  699. if (intr_status & EESR_TABT) /* Transmit Abort int */
  700. mdp->stats.tx_aborted_errors++;
  701. }
  702. if (intr_status & EESR_RABT) {
  703. /* Receive Abort int */
  704. if (intr_status & EESR_RFRMER) {
  705. /* Receive Frame Overflow int */
  706. mdp->stats.rx_frame_errors++;
  707. dev_err(&ndev->dev, "Receive Frame Overflow\n");
  708. }
  709. }
  710. if (!mdp->cd->no_ade) {
  711. if (intr_status & EESR_ADE && intr_status & EESR_TDE &&
  712. intr_status & EESR_TFE)
  713. mdp->stats.tx_fifo_errors++;
  714. }
  715. if (intr_status & EESR_RDE) {
  716. /* Receive Descriptor Empty int */
  717. mdp->stats.rx_over_errors++;
  718. if (ctrl_inl(ioaddr + EDRRR) ^ EDRRR_R)
  719. ctrl_outl(EDRRR_R, ioaddr + EDRRR);
  720. dev_err(&ndev->dev, "Receive Descriptor Empty\n");
  721. }
  722. if (intr_status & EESR_RFE) {
  723. /* Receive FIFO Overflow int */
  724. mdp->stats.rx_fifo_errors++;
  725. dev_err(&ndev->dev, "Receive FIFO Overflow\n");
  726. }
  727. mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
  728. if (mdp->cd->no_ade)
  729. mask &= ~EESR_ADE;
  730. if (intr_status & mask) {
  731. /* Tx error */
  732. u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR);
  733. /* dmesg */
  734. dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
  735. intr_status, mdp->cur_tx);
  736. dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
  737. mdp->dirty_tx, (u32) ndev->state, edtrr);
  738. /* dirty buffer free */
  739. sh_eth_txfree(ndev);
  740. /* SH7712 BUG */
  741. if (edtrr ^ EDTRR_TRNS) {
  742. /* tx dma start */
  743. ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
  744. }
  745. /* wakeup */
  746. netif_wake_queue(ndev);
  747. }
  748. }
  749. static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
  750. {
  751. struct net_device *ndev = netdev;
  752. struct sh_eth_private *mdp = netdev_priv(ndev);
  753. struct sh_eth_cpu_data *cd = mdp->cd;
  754. irqreturn_t ret = IRQ_NONE;
  755. u32 ioaddr, intr_status = 0;
  756. ioaddr = ndev->base_addr;
  757. spin_lock(&mdp->lock);
  758. /* Get interrpt stat */
  759. intr_status = ctrl_inl(ioaddr + EESR);
  760. /* Clear interrupt */
  761. if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
  762. EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
  763. cd->tx_check | cd->eesr_err_check)) {
  764. ctrl_outl(intr_status, ioaddr + EESR);
  765. ret = IRQ_HANDLED;
  766. } else
  767. goto other_irq;
  768. if (intr_status & (EESR_FRC | /* Frame recv*/
  769. EESR_RMAF | /* Multi cast address recv*/
  770. EESR_RRF | /* Bit frame recv */
  771. EESR_RTLF | /* Long frame recv*/
  772. EESR_RTSF | /* short frame recv */
  773. EESR_PRE | /* PHY-LSI recv error */
  774. EESR_CERF)){ /* recv frame CRC error */
  775. sh_eth_rx(ndev);
  776. }
  777. /* Tx Check */
  778. if (intr_status & cd->tx_check) {
  779. sh_eth_txfree(ndev);
  780. netif_wake_queue(ndev);
  781. }
  782. if (intr_status & cd->eesr_err_check)
  783. sh_eth_error(ndev, intr_status);
  784. other_irq:
  785. spin_unlock(&mdp->lock);
  786. return ret;
  787. }
  788. static void sh_eth_timer(unsigned long data)
  789. {
  790. struct net_device *ndev = (struct net_device *)data;
  791. struct sh_eth_private *mdp = netdev_priv(ndev);
  792. mod_timer(&mdp->timer, jiffies + (10 * HZ));
  793. }
  794. /* PHY state control function */
  795. static void sh_eth_adjust_link(struct net_device *ndev)
  796. {
  797. struct sh_eth_private *mdp = netdev_priv(ndev);
  798. struct phy_device *phydev = mdp->phydev;
  799. u32 ioaddr = ndev->base_addr;
  800. int new_state = 0;
  801. if (phydev->link != PHY_DOWN) {
  802. if (phydev->duplex != mdp->duplex) {
  803. new_state = 1;
  804. mdp->duplex = phydev->duplex;
  805. if (mdp->cd->set_duplex)
  806. mdp->cd->set_duplex(ndev);
  807. }
  808. if (phydev->speed != mdp->speed) {
  809. new_state = 1;
  810. mdp->speed = phydev->speed;
  811. if (mdp->cd->set_rate)
  812. mdp->cd->set_rate(ndev);
  813. }
  814. if (mdp->link == PHY_DOWN) {
  815. ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF)
  816. | ECMR_DM, ioaddr + ECMR);
  817. new_state = 1;
  818. mdp->link = phydev->link;
  819. }
  820. } else if (mdp->link) {
  821. new_state = 1;
  822. mdp->link = PHY_DOWN;
  823. mdp->speed = 0;
  824. mdp->duplex = -1;
  825. }
  826. if (new_state)
  827. phy_print_status(phydev);
  828. }
  829. /* PHY init function */
  830. static int sh_eth_phy_init(struct net_device *ndev)
  831. {
  832. struct sh_eth_private *mdp = netdev_priv(ndev);
  833. char phy_id[MII_BUS_ID_SIZE + 3];
  834. struct phy_device *phydev = NULL;
  835. snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
  836. mdp->mii_bus->id , mdp->phy_id);
  837. mdp->link = PHY_DOWN;
  838. mdp->speed = 0;
  839. mdp->duplex = -1;
  840. /* Try connect to PHY */
  841. phydev = phy_connect(ndev, phy_id, &sh_eth_adjust_link,
  842. 0, PHY_INTERFACE_MODE_MII);
  843. if (IS_ERR(phydev)) {
  844. dev_err(&ndev->dev, "phy_connect failed\n");
  845. return PTR_ERR(phydev);
  846. }
  847. dev_info(&ndev->dev, "attached phy %i to driver %s\n",
  848. phydev->addr, phydev->drv->name);
  849. mdp->phydev = phydev;
  850. return 0;
  851. }
  852. /* PHY control start function */
  853. static int sh_eth_phy_start(struct net_device *ndev)
  854. {
  855. struct sh_eth_private *mdp = netdev_priv(ndev);
  856. int ret;
  857. ret = sh_eth_phy_init(ndev);
  858. if (ret)
  859. return ret;
  860. /* reset phy - this also wakes it from PDOWN */
  861. phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
  862. phy_start(mdp->phydev);
  863. return 0;
  864. }
  865. /* network device open function */
  866. static int sh_eth_open(struct net_device *ndev)
  867. {
  868. int ret = 0;
  869. struct sh_eth_private *mdp = netdev_priv(ndev);
  870. pm_runtime_get_sync(&mdp->pdev->dev);
  871. ret = request_irq(ndev->irq, sh_eth_interrupt,
  872. #if defined(CONFIG_CPU_SUBTYPE_SH7763) || defined(CONFIG_CPU_SUBTYPE_SH7764)
  873. IRQF_SHARED,
  874. #else
  875. 0,
  876. #endif
  877. ndev->name, ndev);
  878. if (ret) {
  879. dev_err(&ndev->dev, "Can not assign IRQ number\n");
  880. return ret;
  881. }
  882. /* Descriptor set */
  883. ret = sh_eth_ring_init(ndev);
  884. if (ret)
  885. goto out_free_irq;
  886. /* device init */
  887. ret = sh_eth_dev_init(ndev);
  888. if (ret)
  889. goto out_free_irq;
  890. /* PHY control start*/
  891. ret = sh_eth_phy_start(ndev);
  892. if (ret)
  893. goto out_free_irq;
  894. /* Set the timer to check for link beat. */
  895. init_timer(&mdp->timer);
  896. mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
  897. setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
  898. return ret;
  899. out_free_irq:
  900. free_irq(ndev->irq, ndev);
  901. pm_runtime_put_sync(&mdp->pdev->dev);
  902. return ret;
  903. }
  904. /* Timeout function */
  905. static void sh_eth_tx_timeout(struct net_device *ndev)
  906. {
  907. struct sh_eth_private *mdp = netdev_priv(ndev);
  908. u32 ioaddr = ndev->base_addr;
  909. struct sh_eth_rxdesc *rxdesc;
  910. int i;
  911. netif_stop_queue(ndev);
  912. /* worning message out. */
  913. printk(KERN_WARNING "%s: transmit timed out, status %8.8x,"
  914. " resetting...\n", ndev->name, (int)ctrl_inl(ioaddr + EESR));
  915. /* tx_errors count up */
  916. mdp->stats.tx_errors++;
  917. /* timer off */
  918. del_timer_sync(&mdp->timer);
  919. /* Free all the skbuffs in the Rx queue. */
  920. for (i = 0; i < RX_RING_SIZE; i++) {
  921. rxdesc = &mdp->rx_ring[i];
  922. rxdesc->status = 0;
  923. rxdesc->addr = 0xBADF00D0;
  924. if (mdp->rx_skbuff[i])
  925. dev_kfree_skb(mdp->rx_skbuff[i]);
  926. mdp->rx_skbuff[i] = NULL;
  927. }
  928. for (i = 0; i < TX_RING_SIZE; i++) {
  929. if (mdp->tx_skbuff[i])
  930. dev_kfree_skb(mdp->tx_skbuff[i]);
  931. mdp->tx_skbuff[i] = NULL;
  932. }
  933. /* device init */
  934. sh_eth_dev_init(ndev);
  935. /* timer on */
  936. mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
  937. add_timer(&mdp->timer);
  938. }
  939. /* Packet transmit function */
  940. static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
  941. {
  942. struct sh_eth_private *mdp = netdev_priv(ndev);
  943. struct sh_eth_txdesc *txdesc;
  944. u32 entry;
  945. unsigned long flags;
  946. spin_lock_irqsave(&mdp->lock, flags);
  947. if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
  948. if (!sh_eth_txfree(ndev)) {
  949. netif_stop_queue(ndev);
  950. spin_unlock_irqrestore(&mdp->lock, flags);
  951. return NETDEV_TX_BUSY;
  952. }
  953. }
  954. spin_unlock_irqrestore(&mdp->lock, flags);
  955. entry = mdp->cur_tx % TX_RING_SIZE;
  956. mdp->tx_skbuff[entry] = skb;
  957. txdesc = &mdp->tx_ring[entry];
  958. txdesc->addr = virt_to_phys(skb->data);
  959. /* soft swap. */
  960. if (!mdp->cd->hw_swap)
  961. sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
  962. skb->len + 2);
  963. /* write back */
  964. __flush_purge_region(skb->data, skb->len);
  965. if (skb->len < ETHERSMALL)
  966. txdesc->buffer_length = ETHERSMALL;
  967. else
  968. txdesc->buffer_length = skb->len;
  969. if (entry >= TX_RING_SIZE - 1)
  970. txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
  971. else
  972. txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
  973. mdp->cur_tx++;
  974. if (!(ctrl_inl(ndev->base_addr + EDTRR) & EDTRR_TRNS))
  975. ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
  976. ndev->trans_start = jiffies;
  977. return NETDEV_TX_OK;
  978. }
  979. /* device close function */
  980. static int sh_eth_close(struct net_device *ndev)
  981. {
  982. struct sh_eth_private *mdp = netdev_priv(ndev);
  983. u32 ioaddr = ndev->base_addr;
  984. int ringsize;
  985. netif_stop_queue(ndev);
  986. /* Disable interrupts by clearing the interrupt mask. */
  987. ctrl_outl(0x0000, ioaddr + EESIPR);
  988. /* Stop the chip's Tx and Rx processes. */
  989. ctrl_outl(0, ioaddr + EDTRR);
  990. ctrl_outl(0, ioaddr + EDRRR);
  991. /* PHY Disconnect */
  992. if (mdp->phydev) {
  993. phy_stop(mdp->phydev);
  994. phy_disconnect(mdp->phydev);
  995. }
  996. free_irq(ndev->irq, ndev);
  997. del_timer_sync(&mdp->timer);
  998. /* Free all the skbuffs in the Rx queue. */
  999. sh_eth_ring_free(ndev);
  1000. /* free DMA buffer */
  1001. ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
  1002. dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
  1003. /* free DMA buffer */
  1004. ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
  1005. dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
  1006. pm_runtime_put_sync(&mdp->pdev->dev);
  1007. return 0;
  1008. }
  1009. static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
  1010. {
  1011. struct sh_eth_private *mdp = netdev_priv(ndev);
  1012. u32 ioaddr = ndev->base_addr;
  1013. pm_runtime_get_sync(&mdp->pdev->dev);
  1014. mdp->stats.tx_dropped += ctrl_inl(ioaddr + TROCR);
  1015. ctrl_outl(0, ioaddr + TROCR); /* (write clear) */
  1016. mdp->stats.collisions += ctrl_inl(ioaddr + CDCR);
  1017. ctrl_outl(0, ioaddr + CDCR); /* (write clear) */
  1018. mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + LCCR);
  1019. ctrl_outl(0, ioaddr + LCCR); /* (write clear) */
  1020. #if defined(CONFIG_CPU_SUBTYPE_SH7763)
  1021. mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CERCR);/* CERCR */
  1022. ctrl_outl(0, ioaddr + CERCR); /* (write clear) */
  1023. mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CEECR);/* CEECR */
  1024. ctrl_outl(0, ioaddr + CEECR); /* (write clear) */
  1025. #else
  1026. mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CNDCR);
  1027. ctrl_outl(0, ioaddr + CNDCR); /* (write clear) */
  1028. #endif
  1029. pm_runtime_put_sync(&mdp->pdev->dev);
  1030. return &mdp->stats;
  1031. }
  1032. /* ioctl to device funciotn*/
  1033. static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
  1034. int cmd)
  1035. {
  1036. struct sh_eth_private *mdp = netdev_priv(ndev);
  1037. struct phy_device *phydev = mdp->phydev;
  1038. if (!netif_running(ndev))
  1039. return -EINVAL;
  1040. if (!phydev)
  1041. return -ENODEV;
  1042. return phy_mii_ioctl(phydev, if_mii(rq), cmd);
  1043. }
  1044. #if defined(SH_ETH_HAS_TSU)
  1045. /* Multicast reception directions set */
  1046. static void sh_eth_set_multicast_list(struct net_device *ndev)
  1047. {
  1048. u32 ioaddr = ndev->base_addr;
  1049. if (ndev->flags & IFF_PROMISC) {
  1050. /* Set promiscuous. */
  1051. ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM,
  1052. ioaddr + ECMR);
  1053. } else {
  1054. /* Normal, unicast/broadcast-only mode. */
  1055. ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT,
  1056. ioaddr + ECMR);
  1057. }
  1058. }
  1059. /* SuperH's TSU register init function */
  1060. static void sh_eth_tsu_init(u32 ioaddr)
  1061. {
  1062. ctrl_outl(0, ioaddr + TSU_FWEN0); /* Disable forward(0->1) */
  1063. ctrl_outl(0, ioaddr + TSU_FWEN1); /* Disable forward(1->0) */
  1064. ctrl_outl(0, ioaddr + TSU_FCM); /* forward fifo 3k-3k */
  1065. ctrl_outl(0xc, ioaddr + TSU_BSYSL0);
  1066. ctrl_outl(0xc, ioaddr + TSU_BSYSL1);
  1067. ctrl_outl(0, ioaddr + TSU_PRISL0);
  1068. ctrl_outl(0, ioaddr + TSU_PRISL1);
  1069. ctrl_outl(0, ioaddr + TSU_FWSL0);
  1070. ctrl_outl(0, ioaddr + TSU_FWSL1);
  1071. ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC);
  1072. #if defined(CONFIG_CPU_SUBTYPE_SH7763)
  1073. ctrl_outl(0, ioaddr + TSU_QTAG0); /* Disable QTAG(0->1) */
  1074. ctrl_outl(0, ioaddr + TSU_QTAG1); /* Disable QTAG(1->0) */
  1075. #else
  1076. ctrl_outl(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */
  1077. ctrl_outl(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */
  1078. #endif
  1079. ctrl_outl(0, ioaddr + TSU_FWSR); /* all interrupt status clear */
  1080. ctrl_outl(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */
  1081. ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */
  1082. ctrl_outl(0, ioaddr + TSU_POST1); /* Disable CAM entry [ 0- 7] */
  1083. ctrl_outl(0, ioaddr + TSU_POST2); /* Disable CAM entry [ 8-15] */
  1084. ctrl_outl(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */
  1085. ctrl_outl(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */
  1086. }
  1087. #endif /* SH_ETH_HAS_TSU */
  1088. /* MDIO bus release function */
  1089. static int sh_mdio_release(struct net_device *ndev)
  1090. {
  1091. struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
  1092. /* unregister mdio bus */
  1093. mdiobus_unregister(bus);
  1094. /* remove mdio bus info from net_device */
  1095. dev_set_drvdata(&ndev->dev, NULL);
  1096. /* free bitbang info */
  1097. free_mdio_bitbang(bus);
  1098. return 0;
  1099. }
  1100. /* MDIO bus init function */
  1101. static int sh_mdio_init(struct net_device *ndev, int id)
  1102. {
  1103. int ret, i;
  1104. struct bb_info *bitbang;
  1105. struct sh_eth_private *mdp = netdev_priv(ndev);
  1106. /* create bit control struct for PHY */
  1107. bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
  1108. if (!bitbang) {
  1109. ret = -ENOMEM;
  1110. goto out;
  1111. }
  1112. /* bitbang init */
  1113. bitbang->addr = ndev->base_addr + PIR;
  1114. bitbang->mdi_msk = 0x08;
  1115. bitbang->mdo_msk = 0x04;
  1116. bitbang->mmd_msk = 0x02;/* MMD */
  1117. bitbang->mdc_msk = 0x01;
  1118. bitbang->ctrl.ops = &bb_ops;
  1119. /* MII contorller setting */
  1120. mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
  1121. if (!mdp->mii_bus) {
  1122. ret = -ENOMEM;
  1123. goto out_free_bitbang;
  1124. }
  1125. /* Hook up MII support for ethtool */
  1126. mdp->mii_bus->name = "sh_mii";
  1127. mdp->mii_bus->parent = &ndev->dev;
  1128. snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
  1129. /* PHY IRQ */
  1130. mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
  1131. if (!mdp->mii_bus->irq) {
  1132. ret = -ENOMEM;
  1133. goto out_free_bus;
  1134. }
  1135. for (i = 0; i < PHY_MAX_ADDR; i++)
  1136. mdp->mii_bus->irq[i] = PHY_POLL;
  1137. /* regist mdio bus */
  1138. ret = mdiobus_register(mdp->mii_bus);
  1139. if (ret)
  1140. goto out_free_irq;
  1141. dev_set_drvdata(&ndev->dev, mdp->mii_bus);
  1142. return 0;
  1143. out_free_irq:
  1144. kfree(mdp->mii_bus->irq);
  1145. out_free_bus:
  1146. free_mdio_bitbang(mdp->mii_bus);
  1147. out_free_bitbang:
  1148. kfree(bitbang);
  1149. out:
  1150. return ret;
  1151. }
  1152. static const struct net_device_ops sh_eth_netdev_ops = {
  1153. .ndo_open = sh_eth_open,
  1154. .ndo_stop = sh_eth_close,
  1155. .ndo_start_xmit = sh_eth_start_xmit,
  1156. .ndo_get_stats = sh_eth_get_stats,
  1157. #if defined(SH_ETH_HAS_TSU)
  1158. .ndo_set_multicast_list = sh_eth_set_multicast_list,
  1159. #endif
  1160. .ndo_tx_timeout = sh_eth_tx_timeout,
  1161. .ndo_do_ioctl = sh_eth_do_ioctl,
  1162. .ndo_validate_addr = eth_validate_addr,
  1163. .ndo_set_mac_address = eth_mac_addr,
  1164. .ndo_change_mtu = eth_change_mtu,
  1165. };
  1166. static int sh_eth_drv_probe(struct platform_device *pdev)
  1167. {
  1168. int ret, i, devno = 0;
  1169. struct resource *res;
  1170. struct net_device *ndev = NULL;
  1171. struct sh_eth_private *mdp;
  1172. struct sh_eth_plat_data *pd;
  1173. /* get base addr */
  1174. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1175. if (unlikely(res == NULL)) {
  1176. dev_err(&pdev->dev, "invalid resource\n");
  1177. ret = -EINVAL;
  1178. goto out;
  1179. }
  1180. ndev = alloc_etherdev(sizeof(struct sh_eth_private));
  1181. if (!ndev) {
  1182. dev_err(&pdev->dev, "Could not allocate device.\n");
  1183. ret = -ENOMEM;
  1184. goto out;
  1185. }
  1186. /* The sh Ether-specific entries in the device structure. */
  1187. ndev->base_addr = res->start;
  1188. devno = pdev->id;
  1189. if (devno < 0)
  1190. devno = 0;
  1191. ndev->dma = -1;
  1192. ret = platform_get_irq(pdev, 0);
  1193. if (ret < 0) {
  1194. ret = -ENODEV;
  1195. goto out_release;
  1196. }
  1197. ndev->irq = ret;
  1198. SET_NETDEV_DEV(ndev, &pdev->dev);
  1199. /* Fill in the fields of the device structure with ethernet values. */
  1200. ether_setup(ndev);
  1201. mdp = netdev_priv(ndev);
  1202. spin_lock_init(&mdp->lock);
  1203. mdp->pdev = pdev;
  1204. pm_runtime_enable(&pdev->dev);
  1205. pm_runtime_resume(&pdev->dev);
  1206. pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
  1207. /* get PHY ID */
  1208. mdp->phy_id = pd->phy;
  1209. /* EDMAC endian */
  1210. mdp->edmac_endian = pd->edmac_endian;
  1211. mdp->no_ether_link = pd->no_ether_link;
  1212. mdp->ether_link_active_low = pd->ether_link_active_low;
  1213. /* set cpu data */
  1214. mdp->cd = &sh_eth_my_cpu_data;
  1215. sh_eth_set_default_cpu_data(mdp->cd);
  1216. /* set function */
  1217. ndev->netdev_ops = &sh_eth_netdev_ops;
  1218. ndev->watchdog_timeo = TX_TIMEOUT;
  1219. mdp->post_rx = POST_RX >> (devno << 1);
  1220. mdp->post_fw = POST_FW >> (devno << 1);
  1221. /* read and set MAC address */
  1222. read_mac_address(ndev, pd->mac_addr);
  1223. /* First device only init */
  1224. if (!devno) {
  1225. if (mdp->cd->chip_reset)
  1226. mdp->cd->chip_reset(ndev);
  1227. #if defined(SH_ETH_HAS_TSU)
  1228. /* TSU init (Init only)*/
  1229. sh_eth_tsu_init(SH_TSU_ADDR);
  1230. #endif
  1231. }
  1232. /* network device register */
  1233. ret = register_netdev(ndev);
  1234. if (ret)
  1235. goto out_release;
  1236. /* mdio bus init */
  1237. ret = sh_mdio_init(ndev, pdev->id);
  1238. if (ret)
  1239. goto out_unregister;
  1240. /* pritnt device infomation */
  1241. pr_info("Base address at 0x%x, ",
  1242. (u32)ndev->base_addr);
  1243. for (i = 0; i < 5; i++)
  1244. printk("%02X:", ndev->dev_addr[i]);
  1245. printk("%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq);
  1246. platform_set_drvdata(pdev, ndev);
  1247. return ret;
  1248. out_unregister:
  1249. unregister_netdev(ndev);
  1250. out_release:
  1251. /* net_dev free */
  1252. if (ndev)
  1253. free_netdev(ndev);
  1254. out:
  1255. return ret;
  1256. }
  1257. static int sh_eth_drv_remove(struct platform_device *pdev)
  1258. {
  1259. struct net_device *ndev = platform_get_drvdata(pdev);
  1260. sh_mdio_release(ndev);
  1261. unregister_netdev(ndev);
  1262. flush_scheduled_work();
  1263. pm_runtime_disable(&pdev->dev);
  1264. free_netdev(ndev);
  1265. platform_set_drvdata(pdev, NULL);
  1266. return 0;
  1267. }
  1268. static int sh_eth_runtime_nop(struct device *dev)
  1269. {
  1270. /*
  1271. * Runtime PM callback shared between ->runtime_suspend()
  1272. * and ->runtime_resume(). Simply returns success.
  1273. *
  1274. * This driver re-initializes all registers after
  1275. * pm_runtime_get_sync() anyway so there is no need
  1276. * to save and restore registers here.
  1277. */
  1278. return 0;
  1279. }
  1280. static struct dev_pm_ops sh_eth_dev_pm_ops = {
  1281. .runtime_suspend = sh_eth_runtime_nop,
  1282. .runtime_resume = sh_eth_runtime_nop,
  1283. };
  1284. static struct platform_driver sh_eth_driver = {
  1285. .probe = sh_eth_drv_probe,
  1286. .remove = sh_eth_drv_remove,
  1287. .driver = {
  1288. .name = CARDNAME,
  1289. .pm = &sh_eth_dev_pm_ops,
  1290. },
  1291. };
  1292. static int __init sh_eth_init(void)
  1293. {
  1294. return platform_driver_register(&sh_eth_driver);
  1295. }
  1296. static void __exit sh_eth_cleanup(void)
  1297. {
  1298. platform_driver_unregister(&sh_eth_driver);
  1299. }
  1300. module_init(sh_eth_init);
  1301. module_exit(sh_eth_cleanup);
  1302. MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
  1303. MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
  1304. MODULE_LICENSE("GPL v2");