falcon_xmac.c 12 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2006-2009 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/delay.h>
  11. #include "net_driver.h"
  12. #include "efx.h"
  13. #include "nic.h"
  14. #include "regs.h"
  15. #include "io.h"
  16. #include "mac.h"
  17. #include "mdio_10g.h"
  18. #include "phy.h"
  19. #include "workarounds.h"
  20. /**************************************************************************
  21. *
  22. * MAC operations
  23. *
  24. *************************************************************************/
  25. /* Configure the XAUI driver that is an output from Falcon */
  26. static void falcon_setup_xaui(struct efx_nic *efx)
  27. {
  28. efx_oword_t sdctl, txdrv;
  29. /* Move the XAUI into low power, unless there is no PHY, in
  30. * which case the XAUI will have to drive a cable. */
  31. if (efx->phy_type == PHY_TYPE_NONE)
  32. return;
  33. efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
  34. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
  35. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
  36. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
  37. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
  38. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
  39. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
  40. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
  41. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
  42. efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
  43. EFX_POPULATE_OWORD_8(txdrv,
  44. FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
  45. FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
  46. FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
  47. FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
  48. FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
  49. FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
  50. FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
  51. FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
  52. efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
  53. }
  54. int falcon_reset_xaui(struct efx_nic *efx)
  55. {
  56. struct falcon_nic_data *nic_data = efx->nic_data;
  57. efx_oword_t reg;
  58. int count;
  59. /* Don't fetch MAC statistics over an XMAC reset */
  60. WARN_ON(nic_data->stats_disable_count == 0);
  61. /* Start reset sequence */
  62. EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
  63. efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);
  64. /* Wait up to 10 ms for completion, then reinitialise */
  65. for (count = 0; count < 1000; count++) {
  66. efx_reado(efx, &reg, FR_AB_XX_PWR_RST);
  67. if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
  68. EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
  69. falcon_setup_xaui(efx);
  70. return 0;
  71. }
  72. udelay(10);
  73. }
  74. EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
  75. return -ETIMEDOUT;
  76. }
  77. static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
  78. {
  79. efx_oword_t reg;
  80. if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
  81. return;
  82. /* We expect xgmii faults if the wireside link is up */
  83. if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up)
  84. return;
  85. /* We can only use this interrupt to signal the negative edge of
  86. * xaui_align [we have to poll the positive edge]. */
  87. if (efx->xmac_poll_required)
  88. return;
  89. /* Flush the ISR */
  90. if (enable)
  91. efx_reado(efx, &reg, FR_AB_XM_MGT_INT_MSK);
  92. EFX_POPULATE_OWORD_2(reg,
  93. FRF_AB_XM_MSK_RMTFLT, !enable,
  94. FRF_AB_XM_MSK_LCLFLT, !enable);
  95. efx_writeo(efx, &reg, FR_AB_XM_MGT_INT_MASK);
  96. }
  97. static bool falcon_xgxs_link_ok(struct efx_nic *efx)
  98. {
  99. efx_oword_t reg;
  100. bool align_done, link_ok = false;
  101. int sync_status;
  102. /* Read link status */
  103. efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
  104. align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
  105. sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
  106. if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
  107. link_ok = true;
  108. /* Clear link status ready for next read */
  109. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
  110. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
  111. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
  112. efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
  113. return link_ok;
  114. }
  115. static bool falcon_xmac_link_ok(struct efx_nic *efx)
  116. {
  117. /*
  118. * Check MAC's XGXS link status except when using XGMII loopback
  119. * which bypasses the XGXS block.
  120. * If possible, check PHY's XGXS link status except when using
  121. * MAC loopback.
  122. */
  123. return (efx->loopback_mode == LOOPBACK_XGMII ||
  124. falcon_xgxs_link_ok(efx)) &&
  125. (!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) ||
  126. LOOPBACK_INTERNAL(efx) ||
  127. efx_mdio_phyxgxs_lane_sync(efx));
  128. }
  129. void falcon_reconfigure_xmac_core(struct efx_nic *efx)
  130. {
  131. unsigned int max_frame_len;
  132. efx_oword_t reg;
  133. bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
  134. bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
  135. /* Configure MAC - cut-thru mode is hard wired on */
  136. EFX_POPULATE_OWORD_3(reg,
  137. FRF_AB_XM_RX_JUMBO_MODE, 1,
  138. FRF_AB_XM_TX_STAT_EN, 1,
  139. FRF_AB_XM_RX_STAT_EN, 1);
  140. efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
  141. /* Configure TX */
  142. EFX_POPULATE_OWORD_6(reg,
  143. FRF_AB_XM_TXEN, 1,
  144. FRF_AB_XM_TX_PRMBL, 1,
  145. FRF_AB_XM_AUTO_PAD, 1,
  146. FRF_AB_XM_TXCRC, 1,
  147. FRF_AB_XM_FCNTL, tx_fc,
  148. FRF_AB_XM_IPG, 0x3);
  149. efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);
  150. /* Configure RX */
  151. EFX_POPULATE_OWORD_5(reg,
  152. FRF_AB_XM_RXEN, 1,
  153. FRF_AB_XM_AUTO_DEPAD, 0,
  154. FRF_AB_XM_ACPT_ALL_MCAST, 1,
  155. FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous,
  156. FRF_AB_XM_PASS_CRC_ERR, 1);
  157. efx_writeo(efx, &reg, FR_AB_XM_RX_CFG);
  158. /* Set frame length */
  159. max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
  160. EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
  161. efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);
  162. EFX_POPULATE_OWORD_2(reg,
  163. FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
  164. FRF_AB_XM_TX_JUMBO_MODE, 1);
  165. efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);
  166. EFX_POPULATE_OWORD_2(reg,
  167. FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
  168. FRF_AB_XM_DIS_FCNTL, !rx_fc);
  169. efx_writeo(efx, &reg, FR_AB_XM_FC);
  170. /* Set MAC address */
  171. memcpy(&reg, &efx->net_dev->dev_addr[0], 4);
  172. efx_writeo(efx, &reg, FR_AB_XM_ADR_LO);
  173. memcpy(&reg, &efx->net_dev->dev_addr[4], 2);
  174. efx_writeo(efx, &reg, FR_AB_XM_ADR_HI);
  175. }
  176. static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
  177. {
  178. efx_oword_t reg;
  179. bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
  180. bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
  181. bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
  182. /* XGXS block is flaky and will need to be reset if moving
  183. * into our out of XGMII, XGXS or XAUI loopbacks. */
  184. if (EFX_WORKAROUND_5147(efx)) {
  185. bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
  186. bool reset_xgxs;
  187. efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
  188. old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
  189. old_xgmii_loopback =
  190. EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
  191. efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
  192. old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
  193. /* The PHY driver may have turned XAUI off */
  194. reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
  195. (xaui_loopback != old_xaui_loopback) ||
  196. (xgmii_loopback != old_xgmii_loopback));
  197. if (reset_xgxs)
  198. falcon_reset_xaui(efx);
  199. }
  200. efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
  201. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
  202. (xgxs_loopback || xaui_loopback) ?
  203. FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
  204. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
  205. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
  206. efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
  207. efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
  208. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
  209. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
  210. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
  211. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
  212. efx_writeo(efx, &reg, FR_AB_XX_SD_CTL);
  213. }
  214. /* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
  215. static bool falcon_xmac_link_ok_retry(struct efx_nic *efx, int tries)
  216. {
  217. bool mac_up = falcon_xmac_link_ok(efx);
  218. if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
  219. efx_phy_mode_disabled(efx->phy_mode))
  220. /* XAUI link is expected to be down */
  221. return mac_up;
  222. falcon_stop_nic_stats(efx);
  223. while (!mac_up && tries) {
  224. EFX_LOG(efx, "bashing xaui\n");
  225. falcon_reset_xaui(efx);
  226. udelay(200);
  227. mac_up = falcon_xmac_link_ok(efx);
  228. --tries;
  229. }
  230. falcon_start_nic_stats(efx);
  231. return mac_up;
  232. }
  233. static bool falcon_xmac_check_fault(struct efx_nic *efx)
  234. {
  235. return !falcon_xmac_link_ok_retry(efx, 5);
  236. }
  237. static int falcon_reconfigure_xmac(struct efx_nic *efx)
  238. {
  239. falcon_mask_status_intr(efx, false);
  240. falcon_reconfigure_xgxs_core(efx);
  241. falcon_reconfigure_xmac_core(efx);
  242. falcon_reconfigure_mac_wrapper(efx);
  243. efx->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
  244. falcon_mask_status_intr(efx, true);
  245. return 0;
  246. }
  247. static void falcon_update_stats_xmac(struct efx_nic *efx)
  248. {
  249. struct efx_mac_stats *mac_stats = &efx->mac_stats;
  250. /* Update MAC stats from DMAed values */
  251. FALCON_STAT(efx, XgRxOctets, rx_bytes);
  252. FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
  253. FALCON_STAT(efx, XgRxPkts, rx_packets);
  254. FALCON_STAT(efx, XgRxPktsOK, rx_good);
  255. FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
  256. FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
  257. FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
  258. FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
  259. FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
  260. FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
  261. FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
  262. FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
  263. FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
  264. FALCON_STAT(efx, XgRxAlignError, rx_align_error);
  265. FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
  266. FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
  267. FALCON_STAT(efx, XgRxControlPkts, rx_control);
  268. FALCON_STAT(efx, XgRxPausePkts, rx_pause);
  269. FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
  270. FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
  271. FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
  272. FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
  273. FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
  274. FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
  275. FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
  276. FALCON_STAT(efx, XgRxLengthError, rx_length_error);
  277. FALCON_STAT(efx, XgTxPkts, tx_packets);
  278. FALCON_STAT(efx, XgTxOctets, tx_bytes);
  279. FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
  280. FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
  281. FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
  282. FALCON_STAT(efx, XgTxControlPkts, tx_control);
  283. FALCON_STAT(efx, XgTxPausePkts, tx_pause);
  284. FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
  285. FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
  286. FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
  287. FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
  288. FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
  289. FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
  290. FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
  291. FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
  292. FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
  293. FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
  294. FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
  295. FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
  296. /* Update derived statistics */
  297. mac_stats->tx_good_bytes =
  298. (mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
  299. mac_stats->tx_control * 64);
  300. mac_stats->rx_bad_bytes =
  301. (mac_stats->rx_bytes - mac_stats->rx_good_bytes -
  302. mac_stats->rx_control * 64);
  303. }
  304. void falcon_poll_xmac(struct efx_nic *efx)
  305. {
  306. if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up ||
  307. !efx->xmac_poll_required)
  308. return;
  309. falcon_mask_status_intr(efx, false);
  310. efx->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
  311. falcon_mask_status_intr(efx, true);
  312. }
  313. struct efx_mac_operations falcon_xmac_operations = {
  314. .reconfigure = falcon_reconfigure_xmac,
  315. .update_stats = falcon_update_stats_xmac,
  316. .check_fault = falcon_xmac_check_fault,
  317. };