e1000_82575.c 44 KB

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  1. /*******************************************************************************
  2. Intel(R) Gigabit Ethernet Linux driver
  3. Copyright(c) 2007-2009 Intel Corporation.
  4. This program is free software; you can redistribute it and/or modify it
  5. under the terms and conditions of the GNU General Public License,
  6. version 2, as published by the Free Software Foundation.
  7. This program is distributed in the hope it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc.,
  13. 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  14. The full GNU General Public License is included in this distribution in
  15. the file called "COPYING".
  16. Contact Information:
  17. e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  18. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  19. *******************************************************************************/
  20. /* e1000_82575
  21. * e1000_82576
  22. */
  23. #include <linux/types.h>
  24. #include <linux/slab.h>
  25. #include <linux/if_ether.h>
  26. #include "e1000_mac.h"
  27. #include "e1000_82575.h"
  28. static s32 igb_get_invariants_82575(struct e1000_hw *);
  29. static s32 igb_acquire_phy_82575(struct e1000_hw *);
  30. static void igb_release_phy_82575(struct e1000_hw *);
  31. static s32 igb_acquire_nvm_82575(struct e1000_hw *);
  32. static void igb_release_nvm_82575(struct e1000_hw *);
  33. static s32 igb_check_for_link_82575(struct e1000_hw *);
  34. static s32 igb_get_cfg_done_82575(struct e1000_hw *);
  35. static s32 igb_init_hw_82575(struct e1000_hw *);
  36. static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
  37. static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
  38. static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
  39. static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
  40. static s32 igb_reset_hw_82575(struct e1000_hw *);
  41. static s32 igb_reset_hw_82580(struct e1000_hw *);
  42. static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
  43. static s32 igb_setup_copper_link_82575(struct e1000_hw *);
  44. static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
  45. static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
  46. static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
  47. static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
  48. static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
  49. u16 *);
  50. static s32 igb_get_phy_id_82575(struct e1000_hw *);
  51. static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
  52. static bool igb_sgmii_active_82575(struct e1000_hw *);
  53. static s32 igb_reset_init_script_82575(struct e1000_hw *);
  54. static s32 igb_read_mac_addr_82575(struct e1000_hw *);
  55. static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
  56. static const u16 e1000_82580_rxpbs_table[] =
  57. { 36, 72, 144, 1, 2, 4, 8, 16,
  58. 35, 70, 140 };
  59. #define E1000_82580_RXPBS_TABLE_SIZE \
  60. (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
  61. static s32 igb_get_invariants_82575(struct e1000_hw *hw)
  62. {
  63. struct e1000_phy_info *phy = &hw->phy;
  64. struct e1000_nvm_info *nvm = &hw->nvm;
  65. struct e1000_mac_info *mac = &hw->mac;
  66. struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
  67. u32 eecd;
  68. s32 ret_val;
  69. u16 size;
  70. u32 ctrl_ext = 0;
  71. switch (hw->device_id) {
  72. case E1000_DEV_ID_82575EB_COPPER:
  73. case E1000_DEV_ID_82575EB_FIBER_SERDES:
  74. case E1000_DEV_ID_82575GB_QUAD_COPPER:
  75. mac->type = e1000_82575;
  76. break;
  77. case E1000_DEV_ID_82576:
  78. case E1000_DEV_ID_82576_NS:
  79. case E1000_DEV_ID_82576_NS_SERDES:
  80. case E1000_DEV_ID_82576_FIBER:
  81. case E1000_DEV_ID_82576_SERDES:
  82. case E1000_DEV_ID_82576_QUAD_COPPER:
  83. case E1000_DEV_ID_82576_SERDES_QUAD:
  84. mac->type = e1000_82576;
  85. break;
  86. case E1000_DEV_ID_82580_COPPER:
  87. case E1000_DEV_ID_82580_FIBER:
  88. case E1000_DEV_ID_82580_SERDES:
  89. case E1000_DEV_ID_82580_SGMII:
  90. case E1000_DEV_ID_82580_COPPER_DUAL:
  91. mac->type = e1000_82580;
  92. break;
  93. default:
  94. return -E1000_ERR_MAC_INIT;
  95. break;
  96. }
  97. /* Set media type */
  98. /*
  99. * The 82575 uses bits 22:23 for link mode. The mode can be changed
  100. * based on the EEPROM. We cannot rely upon device ID. There
  101. * is no distinguishable difference between fiber and internal
  102. * SerDes mode on the 82575. There can be an external PHY attached
  103. * on the SGMII interface. For this, we'll set sgmii_active to true.
  104. */
  105. phy->media_type = e1000_media_type_copper;
  106. dev_spec->sgmii_active = false;
  107. ctrl_ext = rd32(E1000_CTRL_EXT);
  108. switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
  109. case E1000_CTRL_EXT_LINK_MODE_SGMII:
  110. dev_spec->sgmii_active = true;
  111. ctrl_ext |= E1000_CTRL_I2C_ENA;
  112. break;
  113. case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
  114. case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
  115. hw->phy.media_type = e1000_media_type_internal_serdes;
  116. ctrl_ext |= E1000_CTRL_I2C_ENA;
  117. break;
  118. default:
  119. ctrl_ext &= ~E1000_CTRL_I2C_ENA;
  120. break;
  121. }
  122. wr32(E1000_CTRL_EXT, ctrl_ext);
  123. /*
  124. * if using i2c make certain the MDICNFG register is cleared to prevent
  125. * communications from being misrouted to the mdic registers
  126. */
  127. if ((ctrl_ext & E1000_CTRL_I2C_ENA) && (hw->mac.type == e1000_82580))
  128. wr32(E1000_MDICNFG, 0);
  129. /* Set mta register count */
  130. mac->mta_reg_count = 128;
  131. /* Set rar entry count */
  132. mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
  133. if (mac->type == e1000_82576)
  134. mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
  135. if (mac->type == e1000_82580)
  136. mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
  137. /* reset */
  138. if (mac->type == e1000_82580)
  139. mac->ops.reset_hw = igb_reset_hw_82580;
  140. else
  141. mac->ops.reset_hw = igb_reset_hw_82575;
  142. /* Set if part includes ASF firmware */
  143. mac->asf_firmware_present = true;
  144. /* Set if manageability features are enabled. */
  145. mac->arc_subsystem_valid =
  146. (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
  147. ? true : false;
  148. /* physical interface link setup */
  149. mac->ops.setup_physical_interface =
  150. (hw->phy.media_type == e1000_media_type_copper)
  151. ? igb_setup_copper_link_82575
  152. : igb_setup_serdes_link_82575;
  153. /* NVM initialization */
  154. eecd = rd32(E1000_EECD);
  155. nvm->opcode_bits = 8;
  156. nvm->delay_usec = 1;
  157. switch (nvm->override) {
  158. case e1000_nvm_override_spi_large:
  159. nvm->page_size = 32;
  160. nvm->address_bits = 16;
  161. break;
  162. case e1000_nvm_override_spi_small:
  163. nvm->page_size = 8;
  164. nvm->address_bits = 8;
  165. break;
  166. default:
  167. nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
  168. nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
  169. break;
  170. }
  171. nvm->type = e1000_nvm_eeprom_spi;
  172. size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
  173. E1000_EECD_SIZE_EX_SHIFT);
  174. /*
  175. * Added to a constant, "size" becomes the left-shift value
  176. * for setting word_size.
  177. */
  178. size += NVM_WORD_SIZE_BASE_SHIFT;
  179. /* EEPROM access above 16k is unsupported */
  180. if (size > 14)
  181. size = 14;
  182. nvm->word_size = 1 << size;
  183. /* if 82576 then initialize mailbox parameters */
  184. if (mac->type == e1000_82576)
  185. igb_init_mbx_params_pf(hw);
  186. /* setup PHY parameters */
  187. if (phy->media_type != e1000_media_type_copper) {
  188. phy->type = e1000_phy_none;
  189. return 0;
  190. }
  191. phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  192. phy->reset_delay_us = 100;
  193. /* PHY function pointers */
  194. if (igb_sgmii_active_82575(hw)) {
  195. phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
  196. phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
  197. phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
  198. } else if (hw->mac.type == e1000_82580) {
  199. phy->ops.reset = igb_phy_hw_reset;
  200. phy->ops.read_reg = igb_read_phy_reg_82580;
  201. phy->ops.write_reg = igb_write_phy_reg_82580;
  202. } else {
  203. phy->ops.reset = igb_phy_hw_reset;
  204. phy->ops.read_reg = igb_read_phy_reg_igp;
  205. phy->ops.write_reg = igb_write_phy_reg_igp;
  206. }
  207. /* set lan id */
  208. hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
  209. E1000_STATUS_FUNC_SHIFT;
  210. /* Set phy->phy_addr and phy->id. */
  211. ret_val = igb_get_phy_id_82575(hw);
  212. if (ret_val)
  213. return ret_val;
  214. /* Verify phy id and set remaining function pointers */
  215. switch (phy->id) {
  216. case M88E1111_I_PHY_ID:
  217. phy->type = e1000_phy_m88;
  218. phy->ops.get_phy_info = igb_get_phy_info_m88;
  219. phy->ops.get_cable_length = igb_get_cable_length_m88;
  220. phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
  221. break;
  222. case IGP03E1000_E_PHY_ID:
  223. phy->type = e1000_phy_igp_3;
  224. phy->ops.get_phy_info = igb_get_phy_info_igp;
  225. phy->ops.get_cable_length = igb_get_cable_length_igp_2;
  226. phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
  227. phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
  228. phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
  229. break;
  230. case I82580_I_PHY_ID:
  231. phy->type = e1000_phy_82580;
  232. phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
  233. phy->ops.get_cable_length = igb_get_cable_length_82580;
  234. phy->ops.get_phy_info = igb_get_phy_info_82580;
  235. break;
  236. default:
  237. return -E1000_ERR_PHY;
  238. }
  239. return 0;
  240. }
  241. /**
  242. * igb_acquire_phy_82575 - Acquire rights to access PHY
  243. * @hw: pointer to the HW structure
  244. *
  245. * Acquire access rights to the correct PHY. This is a
  246. * function pointer entry point called by the api module.
  247. **/
  248. static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
  249. {
  250. u16 mask = E1000_SWFW_PHY0_SM;
  251. if (hw->bus.func == E1000_FUNC_1)
  252. mask = E1000_SWFW_PHY1_SM;
  253. return igb_acquire_swfw_sync_82575(hw, mask);
  254. }
  255. /**
  256. * igb_release_phy_82575 - Release rights to access PHY
  257. * @hw: pointer to the HW structure
  258. *
  259. * A wrapper to release access rights to the correct PHY. This is a
  260. * function pointer entry point called by the api module.
  261. **/
  262. static void igb_release_phy_82575(struct e1000_hw *hw)
  263. {
  264. u16 mask = E1000_SWFW_PHY0_SM;
  265. if (hw->bus.func == E1000_FUNC_1)
  266. mask = E1000_SWFW_PHY1_SM;
  267. igb_release_swfw_sync_82575(hw, mask);
  268. }
  269. /**
  270. * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
  271. * @hw: pointer to the HW structure
  272. * @offset: register offset to be read
  273. * @data: pointer to the read data
  274. *
  275. * Reads the PHY register at offset using the serial gigabit media independent
  276. * interface and stores the retrieved information in data.
  277. **/
  278. static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  279. u16 *data)
  280. {
  281. s32 ret_val = -E1000_ERR_PARAM;
  282. if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
  283. hw_dbg("PHY Address %u is out of range\n", offset);
  284. goto out;
  285. }
  286. ret_val = hw->phy.ops.acquire(hw);
  287. if (ret_val)
  288. goto out;
  289. ret_val = igb_read_phy_reg_i2c(hw, offset, data);
  290. hw->phy.ops.release(hw);
  291. out:
  292. return ret_val;
  293. }
  294. /**
  295. * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
  296. * @hw: pointer to the HW structure
  297. * @offset: register offset to write to
  298. * @data: data to write at register offset
  299. *
  300. * Writes the data to PHY register at the offset using the serial gigabit
  301. * media independent interface.
  302. **/
  303. static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  304. u16 data)
  305. {
  306. s32 ret_val = -E1000_ERR_PARAM;
  307. if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
  308. hw_dbg("PHY Address %d is out of range\n", offset);
  309. goto out;
  310. }
  311. ret_val = hw->phy.ops.acquire(hw);
  312. if (ret_val)
  313. goto out;
  314. ret_val = igb_write_phy_reg_i2c(hw, offset, data);
  315. hw->phy.ops.release(hw);
  316. out:
  317. return ret_val;
  318. }
  319. /**
  320. * igb_get_phy_id_82575 - Retrieve PHY addr and id
  321. * @hw: pointer to the HW structure
  322. *
  323. * Retrieves the PHY address and ID for both PHY's which do and do not use
  324. * sgmi interface.
  325. **/
  326. static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
  327. {
  328. struct e1000_phy_info *phy = &hw->phy;
  329. s32 ret_val = 0;
  330. u16 phy_id;
  331. u32 ctrl_ext;
  332. /*
  333. * For SGMII PHYs, we try the list of possible addresses until
  334. * we find one that works. For non-SGMII PHYs
  335. * (e.g. integrated copper PHYs), an address of 1 should
  336. * work. The result of this function should mean phy->phy_addr
  337. * and phy->id are set correctly.
  338. */
  339. if (!(igb_sgmii_active_82575(hw))) {
  340. phy->addr = 1;
  341. ret_val = igb_get_phy_id(hw);
  342. goto out;
  343. }
  344. /* Power on sgmii phy if it is disabled */
  345. ctrl_ext = rd32(E1000_CTRL_EXT);
  346. wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
  347. wrfl();
  348. msleep(300);
  349. /*
  350. * The address field in the I2CCMD register is 3 bits and 0 is invalid.
  351. * Therefore, we need to test 1-7
  352. */
  353. for (phy->addr = 1; phy->addr < 8; phy->addr++) {
  354. ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
  355. if (ret_val == 0) {
  356. hw_dbg("Vendor ID 0x%08X read at address %u\n",
  357. phy_id, phy->addr);
  358. /*
  359. * At the time of this writing, The M88 part is
  360. * the only supported SGMII PHY product.
  361. */
  362. if (phy_id == M88_VENDOR)
  363. break;
  364. } else {
  365. hw_dbg("PHY address %u was unreadable\n", phy->addr);
  366. }
  367. }
  368. /* A valid PHY type couldn't be found. */
  369. if (phy->addr == 8) {
  370. phy->addr = 0;
  371. ret_val = -E1000_ERR_PHY;
  372. goto out;
  373. } else {
  374. ret_val = igb_get_phy_id(hw);
  375. }
  376. /* restore previous sfp cage power state */
  377. wr32(E1000_CTRL_EXT, ctrl_ext);
  378. out:
  379. return ret_val;
  380. }
  381. /**
  382. * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
  383. * @hw: pointer to the HW structure
  384. *
  385. * Resets the PHY using the serial gigabit media independent interface.
  386. **/
  387. static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
  388. {
  389. s32 ret_val;
  390. /*
  391. * This isn't a true "hard" reset, but is the only reset
  392. * available to us at this time.
  393. */
  394. hw_dbg("Soft resetting SGMII attached PHY...\n");
  395. /*
  396. * SFP documentation requires the following to configure the SPF module
  397. * to work on SGMII. No further documentation is given.
  398. */
  399. ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
  400. if (ret_val)
  401. goto out;
  402. ret_val = igb_phy_sw_reset(hw);
  403. out:
  404. return ret_val;
  405. }
  406. /**
  407. * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
  408. * @hw: pointer to the HW structure
  409. * @active: true to enable LPLU, false to disable
  410. *
  411. * Sets the LPLU D0 state according to the active flag. When
  412. * activating LPLU this function also disables smart speed
  413. * and vice versa. LPLU will not be activated unless the
  414. * device autonegotiation advertisement meets standards of
  415. * either 10 or 10/100 or 10/100/1000 at all duplexes.
  416. * This is a function pointer entry point only called by
  417. * PHY setup routines.
  418. **/
  419. static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
  420. {
  421. struct e1000_phy_info *phy = &hw->phy;
  422. s32 ret_val;
  423. u16 data;
  424. ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
  425. if (ret_val)
  426. goto out;
  427. if (active) {
  428. data |= IGP02E1000_PM_D0_LPLU;
  429. ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  430. data);
  431. if (ret_val)
  432. goto out;
  433. /* When LPLU is enabled, we should disable SmartSpeed */
  434. ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  435. &data);
  436. data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  437. ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  438. data);
  439. if (ret_val)
  440. goto out;
  441. } else {
  442. data &= ~IGP02E1000_PM_D0_LPLU;
  443. ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  444. data);
  445. /*
  446. * LPLU and SmartSpeed are mutually exclusive. LPLU is used
  447. * during Dx states where the power conservation is most
  448. * important. During driver activity we should enable
  449. * SmartSpeed, so performance is maintained.
  450. */
  451. if (phy->smart_speed == e1000_smart_speed_on) {
  452. ret_val = phy->ops.read_reg(hw,
  453. IGP01E1000_PHY_PORT_CONFIG, &data);
  454. if (ret_val)
  455. goto out;
  456. data |= IGP01E1000_PSCFR_SMART_SPEED;
  457. ret_val = phy->ops.write_reg(hw,
  458. IGP01E1000_PHY_PORT_CONFIG, data);
  459. if (ret_val)
  460. goto out;
  461. } else if (phy->smart_speed == e1000_smart_speed_off) {
  462. ret_val = phy->ops.read_reg(hw,
  463. IGP01E1000_PHY_PORT_CONFIG, &data);
  464. if (ret_val)
  465. goto out;
  466. data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  467. ret_val = phy->ops.write_reg(hw,
  468. IGP01E1000_PHY_PORT_CONFIG, data);
  469. if (ret_val)
  470. goto out;
  471. }
  472. }
  473. out:
  474. return ret_val;
  475. }
  476. /**
  477. * igb_acquire_nvm_82575 - Request for access to EEPROM
  478. * @hw: pointer to the HW structure
  479. *
  480. * Acquire the necessary semaphores for exclusive access to the EEPROM.
  481. * Set the EEPROM access request bit and wait for EEPROM access grant bit.
  482. * Return successful if access grant bit set, else clear the request for
  483. * EEPROM access and return -E1000_ERR_NVM (-1).
  484. **/
  485. static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
  486. {
  487. s32 ret_val;
  488. ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
  489. if (ret_val)
  490. goto out;
  491. ret_val = igb_acquire_nvm(hw);
  492. if (ret_val)
  493. igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
  494. out:
  495. return ret_val;
  496. }
  497. /**
  498. * igb_release_nvm_82575 - Release exclusive access to EEPROM
  499. * @hw: pointer to the HW structure
  500. *
  501. * Stop any current commands to the EEPROM and clear the EEPROM request bit,
  502. * then release the semaphores acquired.
  503. **/
  504. static void igb_release_nvm_82575(struct e1000_hw *hw)
  505. {
  506. igb_release_nvm(hw);
  507. igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
  508. }
  509. /**
  510. * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
  511. * @hw: pointer to the HW structure
  512. * @mask: specifies which semaphore to acquire
  513. *
  514. * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
  515. * will also specify which port we're acquiring the lock for.
  516. **/
  517. static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
  518. {
  519. u32 swfw_sync;
  520. u32 swmask = mask;
  521. u32 fwmask = mask << 16;
  522. s32 ret_val = 0;
  523. s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
  524. while (i < timeout) {
  525. if (igb_get_hw_semaphore(hw)) {
  526. ret_val = -E1000_ERR_SWFW_SYNC;
  527. goto out;
  528. }
  529. swfw_sync = rd32(E1000_SW_FW_SYNC);
  530. if (!(swfw_sync & (fwmask | swmask)))
  531. break;
  532. /*
  533. * Firmware currently using resource (fwmask)
  534. * or other software thread using resource (swmask)
  535. */
  536. igb_put_hw_semaphore(hw);
  537. mdelay(5);
  538. i++;
  539. }
  540. if (i == timeout) {
  541. hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
  542. ret_val = -E1000_ERR_SWFW_SYNC;
  543. goto out;
  544. }
  545. swfw_sync |= swmask;
  546. wr32(E1000_SW_FW_SYNC, swfw_sync);
  547. igb_put_hw_semaphore(hw);
  548. out:
  549. return ret_val;
  550. }
  551. /**
  552. * igb_release_swfw_sync_82575 - Release SW/FW semaphore
  553. * @hw: pointer to the HW structure
  554. * @mask: specifies which semaphore to acquire
  555. *
  556. * Release the SW/FW semaphore used to access the PHY or NVM. The mask
  557. * will also specify which port we're releasing the lock for.
  558. **/
  559. static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
  560. {
  561. u32 swfw_sync;
  562. while (igb_get_hw_semaphore(hw) != 0);
  563. /* Empty */
  564. swfw_sync = rd32(E1000_SW_FW_SYNC);
  565. swfw_sync &= ~mask;
  566. wr32(E1000_SW_FW_SYNC, swfw_sync);
  567. igb_put_hw_semaphore(hw);
  568. }
  569. /**
  570. * igb_get_cfg_done_82575 - Read config done bit
  571. * @hw: pointer to the HW structure
  572. *
  573. * Read the management control register for the config done bit for
  574. * completion status. NOTE: silicon which is EEPROM-less will fail trying
  575. * to read the config done bit, so an error is *ONLY* logged and returns
  576. * 0. If we were to return with error, EEPROM-less silicon
  577. * would not be able to be reset or change link.
  578. **/
  579. static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
  580. {
  581. s32 timeout = PHY_CFG_TIMEOUT;
  582. s32 ret_val = 0;
  583. u32 mask = E1000_NVM_CFG_DONE_PORT_0;
  584. if (hw->bus.func == 1)
  585. mask = E1000_NVM_CFG_DONE_PORT_1;
  586. else if (hw->bus.func == E1000_FUNC_2)
  587. mask = E1000_NVM_CFG_DONE_PORT_2;
  588. else if (hw->bus.func == E1000_FUNC_3)
  589. mask = E1000_NVM_CFG_DONE_PORT_3;
  590. while (timeout) {
  591. if (rd32(E1000_EEMNGCTL) & mask)
  592. break;
  593. msleep(1);
  594. timeout--;
  595. }
  596. if (!timeout)
  597. hw_dbg("MNG configuration cycle has not completed.\n");
  598. /* If EEPROM is not marked present, init the PHY manually */
  599. if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
  600. (hw->phy.type == e1000_phy_igp_3))
  601. igb_phy_init_script_igp3(hw);
  602. return ret_val;
  603. }
  604. /**
  605. * igb_check_for_link_82575 - Check for link
  606. * @hw: pointer to the HW structure
  607. *
  608. * If sgmii is enabled, then use the pcs register to determine link, otherwise
  609. * use the generic interface for determining link.
  610. **/
  611. static s32 igb_check_for_link_82575(struct e1000_hw *hw)
  612. {
  613. s32 ret_val;
  614. u16 speed, duplex;
  615. if (hw->phy.media_type != e1000_media_type_copper) {
  616. ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
  617. &duplex);
  618. /*
  619. * Use this flag to determine if link needs to be checked or
  620. * not. If we have link clear the flag so that we do not
  621. * continue to check for link.
  622. */
  623. hw->mac.get_link_status = !hw->mac.serdes_has_link;
  624. } else {
  625. ret_val = igb_check_for_copper_link(hw);
  626. }
  627. return ret_val;
  628. }
  629. /**
  630. * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
  631. * @hw: pointer to the HW structure
  632. * @speed: stores the current speed
  633. * @duplex: stores the current duplex
  634. *
  635. * Using the physical coding sub-layer (PCS), retrieve the current speed and
  636. * duplex, then store the values in the pointers provided.
  637. **/
  638. static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
  639. u16 *duplex)
  640. {
  641. struct e1000_mac_info *mac = &hw->mac;
  642. u32 pcs;
  643. /* Set up defaults for the return values of this function */
  644. mac->serdes_has_link = false;
  645. *speed = 0;
  646. *duplex = 0;
  647. /*
  648. * Read the PCS Status register for link state. For non-copper mode,
  649. * the status register is not accurate. The PCS status register is
  650. * used instead.
  651. */
  652. pcs = rd32(E1000_PCS_LSTAT);
  653. /*
  654. * The link up bit determines when link is up on autoneg. The sync ok
  655. * gets set once both sides sync up and agree upon link. Stable link
  656. * can be determined by checking for both link up and link sync ok
  657. */
  658. if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
  659. mac->serdes_has_link = true;
  660. /* Detect and store PCS speed */
  661. if (pcs & E1000_PCS_LSTS_SPEED_1000) {
  662. *speed = SPEED_1000;
  663. } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
  664. *speed = SPEED_100;
  665. } else {
  666. *speed = SPEED_10;
  667. }
  668. /* Detect and store PCS duplex */
  669. if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
  670. *duplex = FULL_DUPLEX;
  671. } else {
  672. *duplex = HALF_DUPLEX;
  673. }
  674. }
  675. return 0;
  676. }
  677. /**
  678. * igb_shutdown_serdes_link_82575 - Remove link during power down
  679. * @hw: pointer to the HW structure
  680. *
  681. * In the case of fiber serdes, shut down optics and PCS on driver unload
  682. * when management pass thru is not enabled.
  683. **/
  684. void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
  685. {
  686. u32 reg;
  687. u16 eeprom_data = 0;
  688. if (hw->phy.media_type != e1000_media_type_internal_serdes ||
  689. igb_sgmii_active_82575(hw))
  690. return;
  691. if (hw->bus.func == E1000_FUNC_0)
  692. hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
  693. else if (hw->mac.type == e1000_82580)
  694. hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
  695. NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
  696. &eeprom_data);
  697. else if (hw->bus.func == E1000_FUNC_1)
  698. hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
  699. /*
  700. * If APM is not enabled in the EEPROM and management interface is
  701. * not enabled, then power down.
  702. */
  703. if (!(eeprom_data & E1000_NVM_APME_82575) &&
  704. !igb_enable_mng_pass_thru(hw)) {
  705. /* Disable PCS to turn off link */
  706. reg = rd32(E1000_PCS_CFG0);
  707. reg &= ~E1000_PCS_CFG_PCS_EN;
  708. wr32(E1000_PCS_CFG0, reg);
  709. /* shutdown the laser */
  710. reg = rd32(E1000_CTRL_EXT);
  711. reg |= E1000_CTRL_EXT_SDP3_DATA;
  712. wr32(E1000_CTRL_EXT, reg);
  713. /* flush the write to verify completion */
  714. wrfl();
  715. msleep(1);
  716. }
  717. return;
  718. }
  719. /**
  720. * igb_reset_hw_82575 - Reset hardware
  721. * @hw: pointer to the HW structure
  722. *
  723. * This resets the hardware into a known state. This is a
  724. * function pointer entry point called by the api module.
  725. **/
  726. static s32 igb_reset_hw_82575(struct e1000_hw *hw)
  727. {
  728. u32 ctrl, icr;
  729. s32 ret_val;
  730. /*
  731. * Prevent the PCI-E bus from sticking if there is no TLP connection
  732. * on the last TLP read/write transaction when MAC is reset.
  733. */
  734. ret_val = igb_disable_pcie_master(hw);
  735. if (ret_val)
  736. hw_dbg("PCI-E Master disable polling has failed.\n");
  737. /* set the completion timeout for interface */
  738. ret_val = igb_set_pcie_completion_timeout(hw);
  739. if (ret_val) {
  740. hw_dbg("PCI-E Set completion timeout has failed.\n");
  741. }
  742. hw_dbg("Masking off all interrupts\n");
  743. wr32(E1000_IMC, 0xffffffff);
  744. wr32(E1000_RCTL, 0);
  745. wr32(E1000_TCTL, E1000_TCTL_PSP);
  746. wrfl();
  747. msleep(10);
  748. ctrl = rd32(E1000_CTRL);
  749. hw_dbg("Issuing a global reset to MAC\n");
  750. wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
  751. ret_val = igb_get_auto_rd_done(hw);
  752. if (ret_val) {
  753. /*
  754. * When auto config read does not complete, do not
  755. * return with an error. This can happen in situations
  756. * where there is no eeprom and prevents getting link.
  757. */
  758. hw_dbg("Auto Read Done did not complete\n");
  759. }
  760. /* If EEPROM is not present, run manual init scripts */
  761. if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
  762. igb_reset_init_script_82575(hw);
  763. /* Clear any pending interrupt events. */
  764. wr32(E1000_IMC, 0xffffffff);
  765. icr = rd32(E1000_ICR);
  766. /* Install any alternate MAC address into RAR0 */
  767. ret_val = igb_check_alt_mac_addr(hw);
  768. return ret_val;
  769. }
  770. /**
  771. * igb_init_hw_82575 - Initialize hardware
  772. * @hw: pointer to the HW structure
  773. *
  774. * This inits the hardware readying it for operation.
  775. **/
  776. static s32 igb_init_hw_82575(struct e1000_hw *hw)
  777. {
  778. struct e1000_mac_info *mac = &hw->mac;
  779. s32 ret_val;
  780. u16 i, rar_count = mac->rar_entry_count;
  781. /* Initialize identification LED */
  782. ret_val = igb_id_led_init(hw);
  783. if (ret_val) {
  784. hw_dbg("Error initializing identification LED\n");
  785. /* This is not fatal and we should not stop init due to this */
  786. }
  787. /* Disabling VLAN filtering */
  788. hw_dbg("Initializing the IEEE VLAN\n");
  789. igb_clear_vfta(hw);
  790. /* Setup the receive address */
  791. igb_init_rx_addrs(hw, rar_count);
  792. /* Zero out the Multicast HASH table */
  793. hw_dbg("Zeroing the MTA\n");
  794. for (i = 0; i < mac->mta_reg_count; i++)
  795. array_wr32(E1000_MTA, i, 0);
  796. /* Zero out the Unicast HASH table */
  797. hw_dbg("Zeroing the UTA\n");
  798. for (i = 0; i < mac->uta_reg_count; i++)
  799. array_wr32(E1000_UTA, i, 0);
  800. /* Setup link and flow control */
  801. ret_val = igb_setup_link(hw);
  802. /*
  803. * Clear all of the statistics registers (clear on read). It is
  804. * important that we do this after we have tried to establish link
  805. * because the symbol error count will increment wildly if there
  806. * is no link.
  807. */
  808. igb_clear_hw_cntrs_82575(hw);
  809. return ret_val;
  810. }
  811. /**
  812. * igb_setup_copper_link_82575 - Configure copper link settings
  813. * @hw: pointer to the HW structure
  814. *
  815. * Configures the link for auto-neg or forced speed and duplex. Then we check
  816. * for link, once link is established calls to configure collision distance
  817. * and flow control are called.
  818. **/
  819. static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
  820. {
  821. u32 ctrl;
  822. s32 ret_val;
  823. ctrl = rd32(E1000_CTRL);
  824. ctrl |= E1000_CTRL_SLU;
  825. ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  826. wr32(E1000_CTRL, ctrl);
  827. ret_val = igb_setup_serdes_link_82575(hw);
  828. if (ret_val)
  829. goto out;
  830. if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
  831. /* allow time for SFP cage time to power up phy */
  832. msleep(300);
  833. ret_val = hw->phy.ops.reset(hw);
  834. if (ret_val) {
  835. hw_dbg("Error resetting the PHY.\n");
  836. goto out;
  837. }
  838. }
  839. switch (hw->phy.type) {
  840. case e1000_phy_m88:
  841. ret_val = igb_copper_link_setup_m88(hw);
  842. break;
  843. case e1000_phy_igp_3:
  844. ret_val = igb_copper_link_setup_igp(hw);
  845. break;
  846. case e1000_phy_82580:
  847. ret_val = igb_copper_link_setup_82580(hw);
  848. break;
  849. default:
  850. ret_val = -E1000_ERR_PHY;
  851. break;
  852. }
  853. if (ret_val)
  854. goto out;
  855. ret_val = igb_setup_copper_link(hw);
  856. out:
  857. return ret_val;
  858. }
  859. /**
  860. * igb_setup_serdes_link_82575 - Setup link for serdes
  861. * @hw: pointer to the HW structure
  862. *
  863. * Configure the physical coding sub-layer (PCS) link. The PCS link is
  864. * used on copper connections where the serialized gigabit media independent
  865. * interface (sgmii), or serdes fiber is being used. Configures the link
  866. * for auto-negotiation or forces speed/duplex.
  867. **/
  868. static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
  869. {
  870. u32 ctrl_ext, ctrl_reg, reg;
  871. bool pcs_autoneg;
  872. if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
  873. !igb_sgmii_active_82575(hw))
  874. return 0;
  875. /*
  876. * On the 82575, SerDes loopback mode persists until it is
  877. * explicitly turned off or a power cycle is performed. A read to
  878. * the register does not indicate its status. Therefore, we ensure
  879. * loopback mode is disabled during initialization.
  880. */
  881. wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
  882. /* power on the sfp cage if present */
  883. ctrl_ext = rd32(E1000_CTRL_EXT);
  884. ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
  885. wr32(E1000_CTRL_EXT, ctrl_ext);
  886. ctrl_reg = rd32(E1000_CTRL);
  887. ctrl_reg |= E1000_CTRL_SLU;
  888. if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
  889. /* set both sw defined pins */
  890. ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
  891. /* Set switch control to serdes energy detect */
  892. reg = rd32(E1000_CONNSW);
  893. reg |= E1000_CONNSW_ENRGSRC;
  894. wr32(E1000_CONNSW, reg);
  895. }
  896. reg = rd32(E1000_PCS_LCTL);
  897. /* default pcs_autoneg to the same setting as mac autoneg */
  898. pcs_autoneg = hw->mac.autoneg;
  899. switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
  900. case E1000_CTRL_EXT_LINK_MODE_SGMII:
  901. /* sgmii mode lets the phy handle forcing speed/duplex */
  902. pcs_autoneg = true;
  903. /* autoneg time out should be disabled for SGMII mode */
  904. reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
  905. break;
  906. case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
  907. /* disable PCS autoneg and support parallel detect only */
  908. pcs_autoneg = false;
  909. default:
  910. /*
  911. * non-SGMII modes only supports a speed of 1000/Full for the
  912. * link so it is best to just force the MAC and let the pcs
  913. * link either autoneg or be forced to 1000/Full
  914. */
  915. ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
  916. E1000_CTRL_FD | E1000_CTRL_FRCDPX;
  917. /* set speed of 1000/Full if speed/duplex is forced */
  918. reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
  919. break;
  920. }
  921. wr32(E1000_CTRL, ctrl_reg);
  922. /*
  923. * New SerDes mode allows for forcing speed or autonegotiating speed
  924. * at 1gb. Autoneg should be default set by most drivers. This is the
  925. * mode that will be compatible with older link partners and switches.
  926. * However, both are supported by the hardware and some drivers/tools.
  927. */
  928. reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
  929. E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
  930. /*
  931. * We force flow control to prevent the CTRL register values from being
  932. * overwritten by the autonegotiated flow control values
  933. */
  934. reg |= E1000_PCS_LCTL_FORCE_FCTRL;
  935. if (pcs_autoneg) {
  936. /* Set PCS register for autoneg */
  937. reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
  938. E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
  939. hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
  940. } else {
  941. /* Set PCS register for forced link */
  942. reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
  943. hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
  944. }
  945. wr32(E1000_PCS_LCTL, reg);
  946. if (!igb_sgmii_active_82575(hw))
  947. igb_force_mac_fc(hw);
  948. return 0;
  949. }
  950. /**
  951. * igb_sgmii_active_82575 - Return sgmii state
  952. * @hw: pointer to the HW structure
  953. *
  954. * 82575 silicon has a serialized gigabit media independent interface (sgmii)
  955. * which can be enabled for use in the embedded applications. Simply
  956. * return the current state of the sgmii interface.
  957. **/
  958. static bool igb_sgmii_active_82575(struct e1000_hw *hw)
  959. {
  960. struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
  961. return dev_spec->sgmii_active;
  962. }
  963. /**
  964. * igb_reset_init_script_82575 - Inits HW defaults after reset
  965. * @hw: pointer to the HW structure
  966. *
  967. * Inits recommended HW defaults after a reset when there is no EEPROM
  968. * detected. This is only for the 82575.
  969. **/
  970. static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
  971. {
  972. if (hw->mac.type == e1000_82575) {
  973. hw_dbg("Running reset init script for 82575\n");
  974. /* SerDes configuration via SERDESCTRL */
  975. igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
  976. igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
  977. igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
  978. igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
  979. /* CCM configuration via CCMCTL register */
  980. igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
  981. igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
  982. /* PCIe lanes configuration */
  983. igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
  984. igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
  985. igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
  986. igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
  987. /* PCIe PLL Configuration */
  988. igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
  989. igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
  990. igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
  991. }
  992. return 0;
  993. }
  994. /**
  995. * igb_read_mac_addr_82575 - Read device MAC address
  996. * @hw: pointer to the HW structure
  997. **/
  998. static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
  999. {
  1000. s32 ret_val = 0;
  1001. /*
  1002. * If there's an alternate MAC address place it in RAR0
  1003. * so that it will override the Si installed default perm
  1004. * address.
  1005. */
  1006. ret_val = igb_check_alt_mac_addr(hw);
  1007. if (ret_val)
  1008. goto out;
  1009. ret_val = igb_read_mac_addr(hw);
  1010. out:
  1011. return ret_val;
  1012. }
  1013. /**
  1014. * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
  1015. * @hw: pointer to the HW structure
  1016. *
  1017. * Clears the hardware counters by reading the counter registers.
  1018. **/
  1019. static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
  1020. {
  1021. igb_clear_hw_cntrs_base(hw);
  1022. rd32(E1000_PRC64);
  1023. rd32(E1000_PRC127);
  1024. rd32(E1000_PRC255);
  1025. rd32(E1000_PRC511);
  1026. rd32(E1000_PRC1023);
  1027. rd32(E1000_PRC1522);
  1028. rd32(E1000_PTC64);
  1029. rd32(E1000_PTC127);
  1030. rd32(E1000_PTC255);
  1031. rd32(E1000_PTC511);
  1032. rd32(E1000_PTC1023);
  1033. rd32(E1000_PTC1522);
  1034. rd32(E1000_ALGNERRC);
  1035. rd32(E1000_RXERRC);
  1036. rd32(E1000_TNCRS);
  1037. rd32(E1000_CEXTERR);
  1038. rd32(E1000_TSCTC);
  1039. rd32(E1000_TSCTFC);
  1040. rd32(E1000_MGTPRC);
  1041. rd32(E1000_MGTPDC);
  1042. rd32(E1000_MGTPTC);
  1043. rd32(E1000_IAC);
  1044. rd32(E1000_ICRXOC);
  1045. rd32(E1000_ICRXPTC);
  1046. rd32(E1000_ICRXATC);
  1047. rd32(E1000_ICTXPTC);
  1048. rd32(E1000_ICTXATC);
  1049. rd32(E1000_ICTXQEC);
  1050. rd32(E1000_ICTXQMTC);
  1051. rd32(E1000_ICRXDMTC);
  1052. rd32(E1000_CBTMPC);
  1053. rd32(E1000_HTDPMC);
  1054. rd32(E1000_CBRMPC);
  1055. rd32(E1000_RPTHC);
  1056. rd32(E1000_HGPTC);
  1057. rd32(E1000_HTCBDPC);
  1058. rd32(E1000_HGORCL);
  1059. rd32(E1000_HGORCH);
  1060. rd32(E1000_HGOTCL);
  1061. rd32(E1000_HGOTCH);
  1062. rd32(E1000_LENERRS);
  1063. /* This register should not be read in copper configurations */
  1064. if (hw->phy.media_type == e1000_media_type_internal_serdes ||
  1065. igb_sgmii_active_82575(hw))
  1066. rd32(E1000_SCVPC);
  1067. }
  1068. /**
  1069. * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
  1070. * @hw: pointer to the HW structure
  1071. *
  1072. * After rx enable if managability is enabled then there is likely some
  1073. * bad data at the start of the fifo and possibly in the DMA fifo. This
  1074. * function clears the fifos and flushes any packets that came in as rx was
  1075. * being enabled.
  1076. **/
  1077. void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
  1078. {
  1079. u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
  1080. int i, ms_wait;
  1081. if (hw->mac.type != e1000_82575 ||
  1082. !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
  1083. return;
  1084. /* Disable all RX queues */
  1085. for (i = 0; i < 4; i++) {
  1086. rxdctl[i] = rd32(E1000_RXDCTL(i));
  1087. wr32(E1000_RXDCTL(i),
  1088. rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
  1089. }
  1090. /* Poll all queues to verify they have shut down */
  1091. for (ms_wait = 0; ms_wait < 10; ms_wait++) {
  1092. msleep(1);
  1093. rx_enabled = 0;
  1094. for (i = 0; i < 4; i++)
  1095. rx_enabled |= rd32(E1000_RXDCTL(i));
  1096. if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
  1097. break;
  1098. }
  1099. if (ms_wait == 10)
  1100. hw_dbg("Queue disable timed out after 10ms\n");
  1101. /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
  1102. * incoming packets are rejected. Set enable and wait 2ms so that
  1103. * any packet that was coming in as RCTL.EN was set is flushed
  1104. */
  1105. rfctl = rd32(E1000_RFCTL);
  1106. wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
  1107. rlpml = rd32(E1000_RLPML);
  1108. wr32(E1000_RLPML, 0);
  1109. rctl = rd32(E1000_RCTL);
  1110. temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
  1111. temp_rctl |= E1000_RCTL_LPE;
  1112. wr32(E1000_RCTL, temp_rctl);
  1113. wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
  1114. wrfl();
  1115. msleep(2);
  1116. /* Enable RX queues that were previously enabled and restore our
  1117. * previous state
  1118. */
  1119. for (i = 0; i < 4; i++)
  1120. wr32(E1000_RXDCTL(i), rxdctl[i]);
  1121. wr32(E1000_RCTL, rctl);
  1122. wrfl();
  1123. wr32(E1000_RLPML, rlpml);
  1124. wr32(E1000_RFCTL, rfctl);
  1125. /* Flush receive errors generated by workaround */
  1126. rd32(E1000_ROC);
  1127. rd32(E1000_RNBC);
  1128. rd32(E1000_MPC);
  1129. }
  1130. /**
  1131. * igb_set_pcie_completion_timeout - set pci-e completion timeout
  1132. * @hw: pointer to the HW structure
  1133. *
  1134. * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
  1135. * however the hardware default for these parts is 500us to 1ms which is less
  1136. * than the 10ms recommended by the pci-e spec. To address this we need to
  1137. * increase the value to either 10ms to 200ms for capability version 1 config,
  1138. * or 16ms to 55ms for version 2.
  1139. **/
  1140. static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
  1141. {
  1142. u32 gcr = rd32(E1000_GCR);
  1143. s32 ret_val = 0;
  1144. u16 pcie_devctl2;
  1145. /* only take action if timeout value is defaulted to 0 */
  1146. if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
  1147. goto out;
  1148. /*
  1149. * if capababilities version is type 1 we can write the
  1150. * timeout of 10ms to 200ms through the GCR register
  1151. */
  1152. if (!(gcr & E1000_GCR_CAP_VER2)) {
  1153. gcr |= E1000_GCR_CMPL_TMOUT_10ms;
  1154. goto out;
  1155. }
  1156. /*
  1157. * for version 2 capabilities we need to write the config space
  1158. * directly in order to set the completion timeout value for
  1159. * 16ms to 55ms
  1160. */
  1161. ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
  1162. &pcie_devctl2);
  1163. if (ret_val)
  1164. goto out;
  1165. pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
  1166. ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
  1167. &pcie_devctl2);
  1168. out:
  1169. /* disable completion timeout resend */
  1170. gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
  1171. wr32(E1000_GCR, gcr);
  1172. return ret_val;
  1173. }
  1174. /**
  1175. * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
  1176. * @hw: pointer to the hardware struct
  1177. * @enable: state to enter, either enabled or disabled
  1178. *
  1179. * enables/disables L2 switch loopback functionality.
  1180. **/
  1181. void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
  1182. {
  1183. u32 dtxswc = rd32(E1000_DTXSWC);
  1184. if (enable)
  1185. dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
  1186. else
  1187. dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
  1188. wr32(E1000_DTXSWC, dtxswc);
  1189. }
  1190. /**
  1191. * igb_vmdq_set_replication_pf - enable or disable vmdq replication
  1192. * @hw: pointer to the hardware struct
  1193. * @enable: state to enter, either enabled or disabled
  1194. *
  1195. * enables/disables replication of packets across multiple pools.
  1196. **/
  1197. void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
  1198. {
  1199. u32 vt_ctl = rd32(E1000_VT_CTL);
  1200. if (enable)
  1201. vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
  1202. else
  1203. vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
  1204. wr32(E1000_VT_CTL, vt_ctl);
  1205. }
  1206. /**
  1207. * igb_read_phy_reg_82580 - Read 82580 MDI control register
  1208. * @hw: pointer to the HW structure
  1209. * @offset: register offset to be read
  1210. * @data: pointer to the read data
  1211. *
  1212. * Reads the MDI control register in the PHY at offset and stores the
  1213. * information read to data.
  1214. **/
  1215. static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
  1216. {
  1217. u32 mdicnfg = 0;
  1218. s32 ret_val;
  1219. ret_val = hw->phy.ops.acquire(hw);
  1220. if (ret_val)
  1221. goto out;
  1222. /*
  1223. * We config the phy address in MDICNFG register now. Same bits
  1224. * as before. The values in MDIC can be written but will be
  1225. * ignored. This allows us to call the old function after
  1226. * configuring the PHY address in the new register
  1227. */
  1228. mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
  1229. wr32(E1000_MDICNFG, mdicnfg);
  1230. ret_val = igb_read_phy_reg_mdic(hw, offset, data);
  1231. hw->phy.ops.release(hw);
  1232. out:
  1233. return ret_val;
  1234. }
  1235. /**
  1236. * igb_write_phy_reg_82580 - Write 82580 MDI control register
  1237. * @hw: pointer to the HW structure
  1238. * @offset: register offset to write to
  1239. * @data: data to write to register at offset
  1240. *
  1241. * Writes data to MDI control register in the PHY at offset.
  1242. **/
  1243. static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
  1244. {
  1245. u32 mdicnfg = 0;
  1246. s32 ret_val;
  1247. ret_val = hw->phy.ops.acquire(hw);
  1248. if (ret_val)
  1249. goto out;
  1250. /*
  1251. * We config the phy address in MDICNFG register now. Same bits
  1252. * as before. The values in MDIC can be written but will be
  1253. * ignored. This allows us to call the old function after
  1254. * configuring the PHY address in the new register
  1255. */
  1256. mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
  1257. wr32(E1000_MDICNFG, mdicnfg);
  1258. ret_val = igb_write_phy_reg_mdic(hw, offset, data);
  1259. hw->phy.ops.release(hw);
  1260. out:
  1261. return ret_val;
  1262. }
  1263. /**
  1264. * igb_reset_hw_82580 - Reset hardware
  1265. * @hw: pointer to the HW structure
  1266. *
  1267. * This resets function or entire device (all ports, etc.)
  1268. * to a known state.
  1269. **/
  1270. static s32 igb_reset_hw_82580(struct e1000_hw *hw)
  1271. {
  1272. s32 ret_val = 0;
  1273. /* BH SW mailbox bit in SW_FW_SYNC */
  1274. u16 swmbsw_mask = E1000_SW_SYNCH_MB;
  1275. u32 ctrl, icr;
  1276. bool global_device_reset = hw->dev_spec._82575.global_device_reset;
  1277. hw->dev_spec._82575.global_device_reset = false;
  1278. /* Get current control state. */
  1279. ctrl = rd32(E1000_CTRL);
  1280. /*
  1281. * Prevent the PCI-E bus from sticking if there is no TLP connection
  1282. * on the last TLP read/write transaction when MAC is reset.
  1283. */
  1284. ret_val = igb_disable_pcie_master(hw);
  1285. if (ret_val)
  1286. hw_dbg("PCI-E Master disable polling has failed.\n");
  1287. hw_dbg("Masking off all interrupts\n");
  1288. wr32(E1000_IMC, 0xffffffff);
  1289. wr32(E1000_RCTL, 0);
  1290. wr32(E1000_TCTL, E1000_TCTL_PSP);
  1291. wrfl();
  1292. msleep(10);
  1293. /* Determine whether or not a global dev reset is requested */
  1294. if (global_device_reset &&
  1295. igb_acquire_swfw_sync_82575(hw, swmbsw_mask))
  1296. global_device_reset = false;
  1297. if (global_device_reset &&
  1298. !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
  1299. ctrl |= E1000_CTRL_DEV_RST;
  1300. else
  1301. ctrl |= E1000_CTRL_RST;
  1302. wr32(E1000_CTRL, ctrl);
  1303. /* Add delay to insure DEV_RST has time to complete */
  1304. if (global_device_reset)
  1305. msleep(5);
  1306. ret_val = igb_get_auto_rd_done(hw);
  1307. if (ret_val) {
  1308. /*
  1309. * When auto config read does not complete, do not
  1310. * return with an error. This can happen in situations
  1311. * where there is no eeprom and prevents getting link.
  1312. */
  1313. hw_dbg("Auto Read Done did not complete\n");
  1314. }
  1315. /* If EEPROM is not present, run manual init scripts */
  1316. if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
  1317. igb_reset_init_script_82575(hw);
  1318. /* clear global device reset status bit */
  1319. wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
  1320. /* Clear any pending interrupt events. */
  1321. wr32(E1000_IMC, 0xffffffff);
  1322. icr = rd32(E1000_ICR);
  1323. /* Install any alternate MAC address into RAR0 */
  1324. ret_val = igb_check_alt_mac_addr(hw);
  1325. /* Release semaphore */
  1326. if (global_device_reset)
  1327. igb_release_swfw_sync_82575(hw, swmbsw_mask);
  1328. return ret_val;
  1329. }
  1330. /**
  1331. * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
  1332. * @data: data received by reading RXPBS register
  1333. *
  1334. * The 82580 uses a table based approach for packet buffer allocation sizes.
  1335. * This function converts the retrieved value into the correct table value
  1336. * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
  1337. * 0x0 36 72 144 1 2 4 8 16
  1338. * 0x8 35 70 140 rsv rsv rsv rsv rsv
  1339. */
  1340. u16 igb_rxpbs_adjust_82580(u32 data)
  1341. {
  1342. u16 ret_val = 0;
  1343. if (data < E1000_82580_RXPBS_TABLE_SIZE)
  1344. ret_val = e1000_82580_rxpbs_table[data];
  1345. return ret_val;
  1346. }
  1347. static struct e1000_mac_operations e1000_mac_ops_82575 = {
  1348. .init_hw = igb_init_hw_82575,
  1349. .check_for_link = igb_check_for_link_82575,
  1350. .rar_set = igb_rar_set,
  1351. .read_mac_addr = igb_read_mac_addr_82575,
  1352. .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
  1353. };
  1354. static struct e1000_phy_operations e1000_phy_ops_82575 = {
  1355. .acquire = igb_acquire_phy_82575,
  1356. .get_cfg_done = igb_get_cfg_done_82575,
  1357. .release = igb_release_phy_82575,
  1358. };
  1359. static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
  1360. .acquire = igb_acquire_nvm_82575,
  1361. .read = igb_read_nvm_eerd,
  1362. .release = igb_release_nvm_82575,
  1363. .write = igb_write_nvm_spi,
  1364. };
  1365. const struct e1000_info e1000_82575_info = {
  1366. .get_invariants = igb_get_invariants_82575,
  1367. .mac_ops = &e1000_mac_ops_82575,
  1368. .phy_ops = &e1000_phy_ops_82575,
  1369. .nvm_ops = &e1000_nvm_ops_82575,
  1370. };