enic_main.c 50 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084
  1. /*
  2. * Copyright 2008 Cisco Systems, Inc. All rights reserved.
  3. * Copyright 2007 Nuova Systems, Inc. All rights reserved.
  4. *
  5. * This program is free software; you may redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; version 2 of the License.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  10. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  11. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  12. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  13. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  14. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  15. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  16. * SOFTWARE.
  17. *
  18. */
  19. #include <linux/module.h>
  20. #include <linux/kernel.h>
  21. #include <linux/string.h>
  22. #include <linux/errno.h>
  23. #include <linux/types.h>
  24. #include <linux/init.h>
  25. #include <linux/workqueue.h>
  26. #include <linux/pci.h>
  27. #include <linux/netdevice.h>
  28. #include <linux/etherdevice.h>
  29. #include <linux/if_ether.h>
  30. #include <linux/if_vlan.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/in.h>
  33. #include <linux/ip.h>
  34. #include <linux/ipv6.h>
  35. #include <linux/tcp.h>
  36. #include <net/ip6_checksum.h>
  37. #include "cq_enet_desc.h"
  38. #include "vnic_dev.h"
  39. #include "vnic_intr.h"
  40. #include "vnic_stats.h"
  41. #include "enic_res.h"
  42. #include "enic.h"
  43. #define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ)
  44. #define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS)
  45. #define MAX_TSO (1 << 16)
  46. #define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1)
  47. #define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
  48. /* Supported devices */
  49. static struct pci_device_id enic_id_table[] = {
  50. { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) },
  51. { 0, } /* end of table */
  52. };
  53. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  54. MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>");
  55. MODULE_LICENSE("GPL");
  56. MODULE_VERSION(DRV_VERSION);
  57. MODULE_DEVICE_TABLE(pci, enic_id_table);
  58. struct enic_stat {
  59. char name[ETH_GSTRING_LEN];
  60. unsigned int offset;
  61. };
  62. #define ENIC_TX_STAT(stat) \
  63. { .name = #stat, .offset = offsetof(struct vnic_tx_stats, stat) / 8 }
  64. #define ENIC_RX_STAT(stat) \
  65. { .name = #stat, .offset = offsetof(struct vnic_rx_stats, stat) / 8 }
  66. static const struct enic_stat enic_tx_stats[] = {
  67. ENIC_TX_STAT(tx_frames_ok),
  68. ENIC_TX_STAT(tx_unicast_frames_ok),
  69. ENIC_TX_STAT(tx_multicast_frames_ok),
  70. ENIC_TX_STAT(tx_broadcast_frames_ok),
  71. ENIC_TX_STAT(tx_bytes_ok),
  72. ENIC_TX_STAT(tx_unicast_bytes_ok),
  73. ENIC_TX_STAT(tx_multicast_bytes_ok),
  74. ENIC_TX_STAT(tx_broadcast_bytes_ok),
  75. ENIC_TX_STAT(tx_drops),
  76. ENIC_TX_STAT(tx_errors),
  77. ENIC_TX_STAT(tx_tso),
  78. };
  79. static const struct enic_stat enic_rx_stats[] = {
  80. ENIC_RX_STAT(rx_frames_ok),
  81. ENIC_RX_STAT(rx_frames_total),
  82. ENIC_RX_STAT(rx_unicast_frames_ok),
  83. ENIC_RX_STAT(rx_multicast_frames_ok),
  84. ENIC_RX_STAT(rx_broadcast_frames_ok),
  85. ENIC_RX_STAT(rx_bytes_ok),
  86. ENIC_RX_STAT(rx_unicast_bytes_ok),
  87. ENIC_RX_STAT(rx_multicast_bytes_ok),
  88. ENIC_RX_STAT(rx_broadcast_bytes_ok),
  89. ENIC_RX_STAT(rx_drop),
  90. ENIC_RX_STAT(rx_no_bufs),
  91. ENIC_RX_STAT(rx_errors),
  92. ENIC_RX_STAT(rx_rss),
  93. ENIC_RX_STAT(rx_crc_errors),
  94. ENIC_RX_STAT(rx_frames_64),
  95. ENIC_RX_STAT(rx_frames_127),
  96. ENIC_RX_STAT(rx_frames_255),
  97. ENIC_RX_STAT(rx_frames_511),
  98. ENIC_RX_STAT(rx_frames_1023),
  99. ENIC_RX_STAT(rx_frames_1518),
  100. ENIC_RX_STAT(rx_frames_to_max),
  101. };
  102. static const unsigned int enic_n_tx_stats = ARRAY_SIZE(enic_tx_stats);
  103. static const unsigned int enic_n_rx_stats = ARRAY_SIZE(enic_rx_stats);
  104. static int enic_get_settings(struct net_device *netdev,
  105. struct ethtool_cmd *ecmd)
  106. {
  107. struct enic *enic = netdev_priv(netdev);
  108. ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
  109. ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
  110. ecmd->port = PORT_FIBRE;
  111. ecmd->transceiver = XCVR_EXTERNAL;
  112. if (netif_carrier_ok(netdev)) {
  113. ecmd->speed = vnic_dev_port_speed(enic->vdev);
  114. ecmd->duplex = DUPLEX_FULL;
  115. } else {
  116. ecmd->speed = -1;
  117. ecmd->duplex = -1;
  118. }
  119. ecmd->autoneg = AUTONEG_DISABLE;
  120. return 0;
  121. }
  122. static void enic_get_drvinfo(struct net_device *netdev,
  123. struct ethtool_drvinfo *drvinfo)
  124. {
  125. struct enic *enic = netdev_priv(netdev);
  126. struct vnic_devcmd_fw_info *fw_info;
  127. spin_lock(&enic->devcmd_lock);
  128. vnic_dev_fw_info(enic->vdev, &fw_info);
  129. spin_unlock(&enic->devcmd_lock);
  130. strncpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
  131. strncpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
  132. strncpy(drvinfo->fw_version, fw_info->fw_version,
  133. sizeof(drvinfo->fw_version));
  134. strncpy(drvinfo->bus_info, pci_name(enic->pdev),
  135. sizeof(drvinfo->bus_info));
  136. }
  137. static void enic_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
  138. {
  139. unsigned int i;
  140. switch (stringset) {
  141. case ETH_SS_STATS:
  142. for (i = 0; i < enic_n_tx_stats; i++) {
  143. memcpy(data, enic_tx_stats[i].name, ETH_GSTRING_LEN);
  144. data += ETH_GSTRING_LEN;
  145. }
  146. for (i = 0; i < enic_n_rx_stats; i++) {
  147. memcpy(data, enic_rx_stats[i].name, ETH_GSTRING_LEN);
  148. data += ETH_GSTRING_LEN;
  149. }
  150. break;
  151. }
  152. }
  153. static int enic_get_sset_count(struct net_device *netdev, int sset)
  154. {
  155. switch (sset) {
  156. case ETH_SS_STATS:
  157. return enic_n_tx_stats + enic_n_rx_stats;
  158. default:
  159. return -EOPNOTSUPP;
  160. }
  161. }
  162. static void enic_get_ethtool_stats(struct net_device *netdev,
  163. struct ethtool_stats *stats, u64 *data)
  164. {
  165. struct enic *enic = netdev_priv(netdev);
  166. struct vnic_stats *vstats;
  167. unsigned int i;
  168. spin_lock(&enic->devcmd_lock);
  169. vnic_dev_stats_dump(enic->vdev, &vstats);
  170. spin_unlock(&enic->devcmd_lock);
  171. for (i = 0; i < enic_n_tx_stats; i++)
  172. *(data++) = ((u64 *)&vstats->tx)[enic_tx_stats[i].offset];
  173. for (i = 0; i < enic_n_rx_stats; i++)
  174. *(data++) = ((u64 *)&vstats->rx)[enic_rx_stats[i].offset];
  175. }
  176. static u32 enic_get_rx_csum(struct net_device *netdev)
  177. {
  178. struct enic *enic = netdev_priv(netdev);
  179. return enic->csum_rx_enabled;
  180. }
  181. static int enic_set_rx_csum(struct net_device *netdev, u32 data)
  182. {
  183. struct enic *enic = netdev_priv(netdev);
  184. if (data && !ENIC_SETTING(enic, RXCSUM))
  185. return -EINVAL;
  186. enic->csum_rx_enabled = !!data;
  187. return 0;
  188. }
  189. static int enic_set_tx_csum(struct net_device *netdev, u32 data)
  190. {
  191. struct enic *enic = netdev_priv(netdev);
  192. if (data && !ENIC_SETTING(enic, TXCSUM))
  193. return -EINVAL;
  194. if (data)
  195. netdev->features |= NETIF_F_HW_CSUM;
  196. else
  197. netdev->features &= ~NETIF_F_HW_CSUM;
  198. return 0;
  199. }
  200. static int enic_set_tso(struct net_device *netdev, u32 data)
  201. {
  202. struct enic *enic = netdev_priv(netdev);
  203. if (data && !ENIC_SETTING(enic, TSO))
  204. return -EINVAL;
  205. if (data)
  206. netdev->features |=
  207. NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN;
  208. else
  209. netdev->features &=
  210. ~(NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN);
  211. return 0;
  212. }
  213. static u32 enic_get_msglevel(struct net_device *netdev)
  214. {
  215. struct enic *enic = netdev_priv(netdev);
  216. return enic->msg_enable;
  217. }
  218. static void enic_set_msglevel(struct net_device *netdev, u32 value)
  219. {
  220. struct enic *enic = netdev_priv(netdev);
  221. enic->msg_enable = value;
  222. }
  223. static const struct ethtool_ops enic_ethtool_ops = {
  224. .get_settings = enic_get_settings,
  225. .get_drvinfo = enic_get_drvinfo,
  226. .get_msglevel = enic_get_msglevel,
  227. .set_msglevel = enic_set_msglevel,
  228. .get_link = ethtool_op_get_link,
  229. .get_strings = enic_get_strings,
  230. .get_sset_count = enic_get_sset_count,
  231. .get_ethtool_stats = enic_get_ethtool_stats,
  232. .get_rx_csum = enic_get_rx_csum,
  233. .set_rx_csum = enic_set_rx_csum,
  234. .get_tx_csum = ethtool_op_get_tx_csum,
  235. .set_tx_csum = enic_set_tx_csum,
  236. .get_sg = ethtool_op_get_sg,
  237. .set_sg = ethtool_op_set_sg,
  238. .get_tso = ethtool_op_get_tso,
  239. .set_tso = enic_set_tso,
  240. .get_flags = ethtool_op_get_flags,
  241. .set_flags = ethtool_op_set_flags,
  242. };
  243. static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf)
  244. {
  245. struct enic *enic = vnic_dev_priv(wq->vdev);
  246. if (buf->sop)
  247. pci_unmap_single(enic->pdev, buf->dma_addr,
  248. buf->len, PCI_DMA_TODEVICE);
  249. else
  250. pci_unmap_page(enic->pdev, buf->dma_addr,
  251. buf->len, PCI_DMA_TODEVICE);
  252. if (buf->os_buf)
  253. dev_kfree_skb_any(buf->os_buf);
  254. }
  255. static void enic_wq_free_buf(struct vnic_wq *wq,
  256. struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque)
  257. {
  258. enic_free_wq_buf(wq, buf);
  259. }
  260. static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
  261. u8 type, u16 q_number, u16 completed_index, void *opaque)
  262. {
  263. struct enic *enic = vnic_dev_priv(vdev);
  264. spin_lock(&enic->wq_lock[q_number]);
  265. vnic_wq_service(&enic->wq[q_number], cq_desc,
  266. completed_index, enic_wq_free_buf,
  267. opaque);
  268. if (netif_queue_stopped(enic->netdev) &&
  269. vnic_wq_desc_avail(&enic->wq[q_number]) >=
  270. (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS))
  271. netif_wake_queue(enic->netdev);
  272. spin_unlock(&enic->wq_lock[q_number]);
  273. return 0;
  274. }
  275. static void enic_log_q_error(struct enic *enic)
  276. {
  277. unsigned int i;
  278. u32 error_status;
  279. for (i = 0; i < enic->wq_count; i++) {
  280. error_status = vnic_wq_error_status(&enic->wq[i]);
  281. if (error_status)
  282. printk(KERN_ERR PFX "%s: WQ[%d] error_status %d\n",
  283. enic->netdev->name, i, error_status);
  284. }
  285. for (i = 0; i < enic->rq_count; i++) {
  286. error_status = vnic_rq_error_status(&enic->rq[i]);
  287. if (error_status)
  288. printk(KERN_ERR PFX "%s: RQ[%d] error_status %d\n",
  289. enic->netdev->name, i, error_status);
  290. }
  291. }
  292. static void enic_link_check(struct enic *enic)
  293. {
  294. int link_status = vnic_dev_link_status(enic->vdev);
  295. int carrier_ok = netif_carrier_ok(enic->netdev);
  296. if (link_status && !carrier_ok) {
  297. printk(KERN_INFO PFX "%s: Link UP\n", enic->netdev->name);
  298. netif_carrier_on(enic->netdev);
  299. } else if (!link_status && carrier_ok) {
  300. printk(KERN_INFO PFX "%s: Link DOWN\n", enic->netdev->name);
  301. netif_carrier_off(enic->netdev);
  302. }
  303. }
  304. static void enic_mtu_check(struct enic *enic)
  305. {
  306. u32 mtu = vnic_dev_mtu(enic->vdev);
  307. if (mtu && mtu != enic->port_mtu) {
  308. if (mtu < enic->netdev->mtu)
  309. printk(KERN_WARNING PFX
  310. "%s: interface MTU (%d) set higher "
  311. "than switch port MTU (%d)\n",
  312. enic->netdev->name, enic->netdev->mtu, mtu);
  313. enic->port_mtu = mtu;
  314. }
  315. }
  316. static void enic_msglvl_check(struct enic *enic)
  317. {
  318. u32 msg_enable = vnic_dev_msg_lvl(enic->vdev);
  319. if (msg_enable != enic->msg_enable) {
  320. printk(KERN_INFO PFX "%s: msg lvl changed from 0x%x to 0x%x\n",
  321. enic->netdev->name, enic->msg_enable, msg_enable);
  322. enic->msg_enable = msg_enable;
  323. }
  324. }
  325. static void enic_notify_check(struct enic *enic)
  326. {
  327. enic_msglvl_check(enic);
  328. enic_mtu_check(enic);
  329. enic_link_check(enic);
  330. }
  331. #define ENIC_TEST_INTR(pba, i) (pba & (1 << i))
  332. static irqreturn_t enic_isr_legacy(int irq, void *data)
  333. {
  334. struct net_device *netdev = data;
  335. struct enic *enic = netdev_priv(netdev);
  336. u32 pba;
  337. vnic_intr_mask(&enic->intr[ENIC_INTX_WQ_RQ]);
  338. pba = vnic_intr_legacy_pba(enic->legacy_pba);
  339. if (!pba) {
  340. vnic_intr_unmask(&enic->intr[ENIC_INTX_WQ_RQ]);
  341. return IRQ_NONE; /* not our interrupt */
  342. }
  343. if (ENIC_TEST_INTR(pba, ENIC_INTX_NOTIFY)) {
  344. vnic_intr_return_all_credits(&enic->intr[ENIC_INTX_NOTIFY]);
  345. enic_notify_check(enic);
  346. }
  347. if (ENIC_TEST_INTR(pba, ENIC_INTX_ERR)) {
  348. vnic_intr_return_all_credits(&enic->intr[ENIC_INTX_ERR]);
  349. enic_log_q_error(enic);
  350. /* schedule recovery from WQ/RQ error */
  351. schedule_work(&enic->reset);
  352. return IRQ_HANDLED;
  353. }
  354. if (ENIC_TEST_INTR(pba, ENIC_INTX_WQ_RQ)) {
  355. if (napi_schedule_prep(&enic->napi))
  356. __napi_schedule(&enic->napi);
  357. } else {
  358. vnic_intr_unmask(&enic->intr[ENIC_INTX_WQ_RQ]);
  359. }
  360. return IRQ_HANDLED;
  361. }
  362. static irqreturn_t enic_isr_msi(int irq, void *data)
  363. {
  364. struct enic *enic = data;
  365. /* With MSI, there is no sharing of interrupts, so this is
  366. * our interrupt and there is no need to ack it. The device
  367. * is not providing per-vector masking, so the OS will not
  368. * write to PCI config space to mask/unmask the interrupt.
  369. * We're using mask_on_assertion for MSI, so the device
  370. * automatically masks the interrupt when the interrupt is
  371. * generated. Later, when exiting polling, the interrupt
  372. * will be unmasked (see enic_poll).
  373. *
  374. * Also, the device uses the same PCIe Traffic Class (TC)
  375. * for Memory Write data and MSI, so there are no ordering
  376. * issues; the MSI will always arrive at the Root Complex
  377. * _after_ corresponding Memory Writes (i.e. descriptor
  378. * writes).
  379. */
  380. napi_schedule(&enic->napi);
  381. return IRQ_HANDLED;
  382. }
  383. static irqreturn_t enic_isr_msix_rq(int irq, void *data)
  384. {
  385. struct enic *enic = data;
  386. /* schedule NAPI polling for RQ cleanup */
  387. napi_schedule(&enic->napi);
  388. return IRQ_HANDLED;
  389. }
  390. static irqreturn_t enic_isr_msix_wq(int irq, void *data)
  391. {
  392. struct enic *enic = data;
  393. unsigned int wq_work_to_do = -1; /* no limit */
  394. unsigned int wq_work_done;
  395. wq_work_done = vnic_cq_service(&enic->cq[ENIC_CQ_WQ],
  396. wq_work_to_do, enic_wq_service, NULL);
  397. vnic_intr_return_credits(&enic->intr[ENIC_MSIX_WQ],
  398. wq_work_done,
  399. 1 /* unmask intr */,
  400. 1 /* reset intr timer */);
  401. return IRQ_HANDLED;
  402. }
  403. static irqreturn_t enic_isr_msix_err(int irq, void *data)
  404. {
  405. struct enic *enic = data;
  406. vnic_intr_return_all_credits(&enic->intr[ENIC_MSIX_ERR]);
  407. enic_log_q_error(enic);
  408. /* schedule recovery from WQ/RQ error */
  409. schedule_work(&enic->reset);
  410. return IRQ_HANDLED;
  411. }
  412. static irqreturn_t enic_isr_msix_notify(int irq, void *data)
  413. {
  414. struct enic *enic = data;
  415. vnic_intr_return_all_credits(&enic->intr[ENIC_MSIX_NOTIFY]);
  416. enic_notify_check(enic);
  417. return IRQ_HANDLED;
  418. }
  419. static inline void enic_queue_wq_skb_cont(struct enic *enic,
  420. struct vnic_wq *wq, struct sk_buff *skb,
  421. unsigned int len_left)
  422. {
  423. skb_frag_t *frag;
  424. /* Queue additional data fragments */
  425. for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
  426. len_left -= frag->size;
  427. enic_queue_wq_desc_cont(wq, skb,
  428. pci_map_page(enic->pdev, frag->page,
  429. frag->page_offset, frag->size,
  430. PCI_DMA_TODEVICE),
  431. frag->size,
  432. (len_left == 0)); /* EOP? */
  433. }
  434. }
  435. static inline void enic_queue_wq_skb_vlan(struct enic *enic,
  436. struct vnic_wq *wq, struct sk_buff *skb,
  437. int vlan_tag_insert, unsigned int vlan_tag)
  438. {
  439. unsigned int head_len = skb_headlen(skb);
  440. unsigned int len_left = skb->len - head_len;
  441. int eop = (len_left == 0);
  442. /* Queue the main skb fragment. The fragments are no larger
  443. * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
  444. * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
  445. * per fragment is queued.
  446. */
  447. enic_queue_wq_desc(wq, skb,
  448. pci_map_single(enic->pdev, skb->data,
  449. head_len, PCI_DMA_TODEVICE),
  450. head_len,
  451. vlan_tag_insert, vlan_tag,
  452. eop);
  453. if (!eop)
  454. enic_queue_wq_skb_cont(enic, wq, skb, len_left);
  455. }
  456. static inline void enic_queue_wq_skb_csum_l4(struct enic *enic,
  457. struct vnic_wq *wq, struct sk_buff *skb,
  458. int vlan_tag_insert, unsigned int vlan_tag)
  459. {
  460. unsigned int head_len = skb_headlen(skb);
  461. unsigned int len_left = skb->len - head_len;
  462. unsigned int hdr_len = skb_transport_offset(skb);
  463. unsigned int csum_offset = hdr_len + skb->csum_offset;
  464. int eop = (len_left == 0);
  465. /* Queue the main skb fragment. The fragments are no larger
  466. * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
  467. * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
  468. * per fragment is queued.
  469. */
  470. enic_queue_wq_desc_csum_l4(wq, skb,
  471. pci_map_single(enic->pdev, skb->data,
  472. head_len, PCI_DMA_TODEVICE),
  473. head_len,
  474. csum_offset,
  475. hdr_len,
  476. vlan_tag_insert, vlan_tag,
  477. eop);
  478. if (!eop)
  479. enic_queue_wq_skb_cont(enic, wq, skb, len_left);
  480. }
  481. static inline void enic_queue_wq_skb_tso(struct enic *enic,
  482. struct vnic_wq *wq, struct sk_buff *skb, unsigned int mss,
  483. int vlan_tag_insert, unsigned int vlan_tag)
  484. {
  485. unsigned int frag_len_left = skb_headlen(skb);
  486. unsigned int len_left = skb->len - frag_len_left;
  487. unsigned int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  488. int eop = (len_left == 0);
  489. unsigned int len;
  490. dma_addr_t dma_addr;
  491. unsigned int offset = 0;
  492. skb_frag_t *frag;
  493. /* Preload TCP csum field with IP pseudo hdr calculated
  494. * with IP length set to zero. HW will later add in length
  495. * to each TCP segment resulting from the TSO.
  496. */
  497. if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
  498. ip_hdr(skb)->check = 0;
  499. tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
  500. ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
  501. } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
  502. tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
  503. &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
  504. }
  505. /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
  506. * for the main skb fragment
  507. */
  508. while (frag_len_left) {
  509. len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN);
  510. dma_addr = pci_map_single(enic->pdev, skb->data + offset,
  511. len, PCI_DMA_TODEVICE);
  512. enic_queue_wq_desc_tso(wq, skb,
  513. dma_addr,
  514. len,
  515. mss, hdr_len,
  516. vlan_tag_insert, vlan_tag,
  517. eop && (len == frag_len_left));
  518. frag_len_left -= len;
  519. offset += len;
  520. }
  521. if (eop)
  522. return;
  523. /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
  524. * for additional data fragments
  525. */
  526. for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
  527. len_left -= frag->size;
  528. frag_len_left = frag->size;
  529. offset = frag->page_offset;
  530. while (frag_len_left) {
  531. len = min(frag_len_left,
  532. (unsigned int)WQ_ENET_MAX_DESC_LEN);
  533. dma_addr = pci_map_page(enic->pdev, frag->page,
  534. offset, len,
  535. PCI_DMA_TODEVICE);
  536. enic_queue_wq_desc_cont(wq, skb,
  537. dma_addr,
  538. len,
  539. (len_left == 0) &&
  540. (len == frag_len_left)); /* EOP? */
  541. frag_len_left -= len;
  542. offset += len;
  543. }
  544. }
  545. }
  546. static inline void enic_queue_wq_skb(struct enic *enic,
  547. struct vnic_wq *wq, struct sk_buff *skb)
  548. {
  549. unsigned int mss = skb_shinfo(skb)->gso_size;
  550. unsigned int vlan_tag = 0;
  551. int vlan_tag_insert = 0;
  552. if (enic->vlan_group && vlan_tx_tag_present(skb)) {
  553. /* VLAN tag from trunking driver */
  554. vlan_tag_insert = 1;
  555. vlan_tag = vlan_tx_tag_get(skb);
  556. }
  557. if (mss)
  558. enic_queue_wq_skb_tso(enic, wq, skb, mss,
  559. vlan_tag_insert, vlan_tag);
  560. else if (skb->ip_summed == CHECKSUM_PARTIAL)
  561. enic_queue_wq_skb_csum_l4(enic, wq, skb,
  562. vlan_tag_insert, vlan_tag);
  563. else
  564. enic_queue_wq_skb_vlan(enic, wq, skb,
  565. vlan_tag_insert, vlan_tag);
  566. }
  567. /* netif_tx_lock held, process context with BHs disabled, or BH */
  568. static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb,
  569. struct net_device *netdev)
  570. {
  571. struct enic *enic = netdev_priv(netdev);
  572. struct vnic_wq *wq = &enic->wq[0];
  573. unsigned long flags;
  574. if (skb->len <= 0) {
  575. dev_kfree_skb(skb);
  576. return NETDEV_TX_OK;
  577. }
  578. /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs,
  579. * which is very likely. In the off chance it's going to take
  580. * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb.
  581. */
  582. if (skb_shinfo(skb)->gso_size == 0 &&
  583. skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC &&
  584. skb_linearize(skb)) {
  585. dev_kfree_skb(skb);
  586. return NETDEV_TX_OK;
  587. }
  588. spin_lock_irqsave(&enic->wq_lock[0], flags);
  589. if (vnic_wq_desc_avail(wq) <
  590. skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) {
  591. netif_stop_queue(netdev);
  592. /* This is a hard error, log it */
  593. printk(KERN_ERR PFX "%s: BUG! Tx ring full when "
  594. "queue awake!\n", netdev->name);
  595. spin_unlock_irqrestore(&enic->wq_lock[0], flags);
  596. return NETDEV_TX_BUSY;
  597. }
  598. enic_queue_wq_skb(enic, wq, skb);
  599. if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)
  600. netif_stop_queue(netdev);
  601. spin_unlock_irqrestore(&enic->wq_lock[0], flags);
  602. return NETDEV_TX_OK;
  603. }
  604. /* dev_base_lock rwlock held, nominally process context */
  605. static struct net_device_stats *enic_get_stats(struct net_device *netdev)
  606. {
  607. struct enic *enic = netdev_priv(netdev);
  608. struct net_device_stats *net_stats = &netdev->stats;
  609. struct vnic_stats *stats;
  610. spin_lock(&enic->devcmd_lock);
  611. vnic_dev_stats_dump(enic->vdev, &stats);
  612. spin_unlock(&enic->devcmd_lock);
  613. net_stats->tx_packets = stats->tx.tx_frames_ok;
  614. net_stats->tx_bytes = stats->tx.tx_bytes_ok;
  615. net_stats->tx_errors = stats->tx.tx_errors;
  616. net_stats->tx_dropped = stats->tx.tx_drops;
  617. net_stats->rx_packets = stats->rx.rx_frames_ok;
  618. net_stats->rx_bytes = stats->rx.rx_bytes_ok;
  619. net_stats->rx_errors = stats->rx.rx_errors;
  620. net_stats->multicast = stats->rx.rx_multicast_frames_ok;
  621. net_stats->rx_over_errors = enic->rq_truncated_pkts;
  622. net_stats->rx_crc_errors = enic->rq_bad_fcs;
  623. net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop;
  624. return net_stats;
  625. }
  626. static void enic_reset_mcaddrs(struct enic *enic)
  627. {
  628. enic->mc_count = 0;
  629. }
  630. static int enic_set_mac_addr(struct net_device *netdev, char *addr)
  631. {
  632. if (!is_valid_ether_addr(addr))
  633. return -EADDRNOTAVAIL;
  634. memcpy(netdev->dev_addr, addr, netdev->addr_len);
  635. return 0;
  636. }
  637. /* netif_tx_lock held, BHs disabled */
  638. static void enic_set_multicast_list(struct net_device *netdev)
  639. {
  640. struct enic *enic = netdev_priv(netdev);
  641. struct dev_mc_list *list = netdev->mc_list;
  642. int directed = 1;
  643. int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0;
  644. int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0;
  645. int promisc = (netdev->flags & IFF_PROMISC) ? 1 : 0;
  646. int allmulti = (netdev->flags & IFF_ALLMULTI) ||
  647. (netdev->mc_count > ENIC_MULTICAST_PERFECT_FILTERS);
  648. u8 mc_addr[ENIC_MULTICAST_PERFECT_FILTERS][ETH_ALEN];
  649. unsigned int mc_count = netdev->mc_count;
  650. unsigned int i, j;
  651. if (mc_count > ENIC_MULTICAST_PERFECT_FILTERS)
  652. mc_count = ENIC_MULTICAST_PERFECT_FILTERS;
  653. spin_lock(&enic->devcmd_lock);
  654. vnic_dev_packet_filter(enic->vdev, directed,
  655. multicast, broadcast, promisc, allmulti);
  656. /* Is there an easier way? Trying to minimize to
  657. * calls to add/del multicast addrs. We keep the
  658. * addrs from the last call in enic->mc_addr and
  659. * look for changes to add/del.
  660. */
  661. for (i = 0; list && i < mc_count; i++) {
  662. memcpy(mc_addr[i], list->dmi_addr, ETH_ALEN);
  663. list = list->next;
  664. }
  665. for (i = 0; i < enic->mc_count; i++) {
  666. for (j = 0; j < mc_count; j++)
  667. if (compare_ether_addr(enic->mc_addr[i],
  668. mc_addr[j]) == 0)
  669. break;
  670. if (j == mc_count)
  671. enic_del_multicast_addr(enic, enic->mc_addr[i]);
  672. }
  673. for (i = 0; i < mc_count; i++) {
  674. for (j = 0; j < enic->mc_count; j++)
  675. if (compare_ether_addr(mc_addr[i],
  676. enic->mc_addr[j]) == 0)
  677. break;
  678. if (j == enic->mc_count)
  679. enic_add_multicast_addr(enic, mc_addr[i]);
  680. }
  681. /* Save the list to compare against next time
  682. */
  683. for (i = 0; i < mc_count; i++)
  684. memcpy(enic->mc_addr[i], mc_addr[i], ETH_ALEN);
  685. enic->mc_count = mc_count;
  686. spin_unlock(&enic->devcmd_lock);
  687. }
  688. /* rtnl lock is held */
  689. static void enic_vlan_rx_register(struct net_device *netdev,
  690. struct vlan_group *vlan_group)
  691. {
  692. struct enic *enic = netdev_priv(netdev);
  693. enic->vlan_group = vlan_group;
  694. }
  695. /* rtnl lock is held */
  696. static void enic_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
  697. {
  698. struct enic *enic = netdev_priv(netdev);
  699. spin_lock(&enic->devcmd_lock);
  700. enic_add_vlan(enic, vid);
  701. spin_unlock(&enic->devcmd_lock);
  702. }
  703. /* rtnl lock is held */
  704. static void enic_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
  705. {
  706. struct enic *enic = netdev_priv(netdev);
  707. spin_lock(&enic->devcmd_lock);
  708. enic_del_vlan(enic, vid);
  709. spin_unlock(&enic->devcmd_lock);
  710. }
  711. /* netif_tx_lock held, BHs disabled */
  712. static void enic_tx_timeout(struct net_device *netdev)
  713. {
  714. struct enic *enic = netdev_priv(netdev);
  715. schedule_work(&enic->reset);
  716. }
  717. static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf)
  718. {
  719. struct enic *enic = vnic_dev_priv(rq->vdev);
  720. if (!buf->os_buf)
  721. return;
  722. pci_unmap_single(enic->pdev, buf->dma_addr,
  723. buf->len, PCI_DMA_FROMDEVICE);
  724. dev_kfree_skb_any(buf->os_buf);
  725. }
  726. static int enic_rq_alloc_buf(struct vnic_rq *rq)
  727. {
  728. struct enic *enic = vnic_dev_priv(rq->vdev);
  729. struct net_device *netdev = enic->netdev;
  730. struct sk_buff *skb;
  731. unsigned int len = netdev->mtu + ETH_HLEN;
  732. unsigned int os_buf_index = 0;
  733. dma_addr_t dma_addr;
  734. skb = netdev_alloc_skb_ip_align(netdev, len);
  735. if (!skb)
  736. return -ENOMEM;
  737. dma_addr = pci_map_single(enic->pdev, skb->data,
  738. len, PCI_DMA_FROMDEVICE);
  739. enic_queue_rq_desc(rq, skb, os_buf_index,
  740. dma_addr, len);
  741. return 0;
  742. }
  743. static int enic_rq_alloc_buf_a1(struct vnic_rq *rq)
  744. {
  745. struct rq_enet_desc *desc = vnic_rq_next_desc(rq);
  746. if (vnic_rq_posting_soon(rq)) {
  747. /* SW workaround for A0 HW erratum: if we're just about
  748. * to write posted_index, insert a dummy desc
  749. * of type resvd
  750. */
  751. rq_enet_desc_enc(desc, 0, RQ_ENET_TYPE_RESV2, 0);
  752. vnic_rq_post(rq, 0, 0, 0, 0);
  753. } else {
  754. return enic_rq_alloc_buf(rq);
  755. }
  756. return 0;
  757. }
  758. static int enic_set_rq_alloc_buf(struct enic *enic)
  759. {
  760. enum vnic_dev_hw_version hw_ver;
  761. int err;
  762. err = vnic_dev_hw_version(enic->vdev, &hw_ver);
  763. if (err)
  764. return err;
  765. switch (hw_ver) {
  766. case VNIC_DEV_HW_VER_A1:
  767. enic->rq_alloc_buf = enic_rq_alloc_buf_a1;
  768. break;
  769. case VNIC_DEV_HW_VER_A2:
  770. case VNIC_DEV_HW_VER_UNKNOWN:
  771. enic->rq_alloc_buf = enic_rq_alloc_buf;
  772. break;
  773. default:
  774. return -ENODEV;
  775. }
  776. return 0;
  777. }
  778. static int enic_get_skb_header(struct sk_buff *skb, void **iphdr,
  779. void **tcph, u64 *hdr_flags, void *priv)
  780. {
  781. struct cq_enet_rq_desc *cq_desc = priv;
  782. unsigned int ip_len;
  783. struct iphdr *iph;
  784. u8 type, color, eop, sop, ingress_port, vlan_stripped;
  785. u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof;
  786. u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok;
  787. u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc;
  788. u8 packet_error;
  789. u16 q_number, completed_index, bytes_written, vlan, checksum;
  790. u32 rss_hash;
  791. cq_enet_rq_desc_dec(cq_desc,
  792. &type, &color, &q_number, &completed_index,
  793. &ingress_port, &fcoe, &eop, &sop, &rss_type,
  794. &csum_not_calc, &rss_hash, &bytes_written,
  795. &packet_error, &vlan_stripped, &vlan, &checksum,
  796. &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error,
  797. &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp,
  798. &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment,
  799. &fcs_ok);
  800. if (!(ipv4 && tcp && !ipv4_fragment))
  801. return -1;
  802. skb_reset_network_header(skb);
  803. iph = ip_hdr(skb);
  804. ip_len = ip_hdrlen(skb);
  805. skb_set_transport_header(skb, ip_len);
  806. /* check if ip header and tcp header are complete */
  807. if (ntohs(iph->tot_len) < ip_len + tcp_hdrlen(skb))
  808. return -1;
  809. *hdr_flags = LRO_IPV4 | LRO_TCP;
  810. *tcph = tcp_hdr(skb);
  811. *iphdr = iph;
  812. return 0;
  813. }
  814. static void enic_rq_indicate_buf(struct vnic_rq *rq,
  815. struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
  816. int skipped, void *opaque)
  817. {
  818. struct enic *enic = vnic_dev_priv(rq->vdev);
  819. struct net_device *netdev = enic->netdev;
  820. struct sk_buff *skb;
  821. u8 type, color, eop, sop, ingress_port, vlan_stripped;
  822. u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof;
  823. u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok;
  824. u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc;
  825. u8 packet_error;
  826. u16 q_number, completed_index, bytes_written, vlan, checksum;
  827. u32 rss_hash;
  828. if (skipped)
  829. return;
  830. skb = buf->os_buf;
  831. prefetch(skb->data - NET_IP_ALIGN);
  832. pci_unmap_single(enic->pdev, buf->dma_addr,
  833. buf->len, PCI_DMA_FROMDEVICE);
  834. cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc,
  835. &type, &color, &q_number, &completed_index,
  836. &ingress_port, &fcoe, &eop, &sop, &rss_type,
  837. &csum_not_calc, &rss_hash, &bytes_written,
  838. &packet_error, &vlan_stripped, &vlan, &checksum,
  839. &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error,
  840. &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp,
  841. &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment,
  842. &fcs_ok);
  843. if (packet_error) {
  844. if (!fcs_ok) {
  845. if (bytes_written > 0)
  846. enic->rq_bad_fcs++;
  847. else if (bytes_written == 0)
  848. enic->rq_truncated_pkts++;
  849. }
  850. dev_kfree_skb_any(skb);
  851. return;
  852. }
  853. if (eop && bytes_written > 0) {
  854. /* Good receive
  855. */
  856. skb_put(skb, bytes_written);
  857. skb->protocol = eth_type_trans(skb, netdev);
  858. if (enic->csum_rx_enabled && !csum_not_calc) {
  859. skb->csum = htons(checksum);
  860. skb->ip_summed = CHECKSUM_COMPLETE;
  861. }
  862. skb->dev = netdev;
  863. if (enic->vlan_group && vlan_stripped) {
  864. if ((netdev->features & NETIF_F_LRO) && ipv4)
  865. lro_vlan_hwaccel_receive_skb(&enic->lro_mgr,
  866. skb, enic->vlan_group,
  867. vlan, cq_desc);
  868. else
  869. vlan_hwaccel_receive_skb(skb,
  870. enic->vlan_group, vlan);
  871. } else {
  872. if ((netdev->features & NETIF_F_LRO) && ipv4)
  873. lro_receive_skb(&enic->lro_mgr, skb, cq_desc);
  874. else
  875. netif_receive_skb(skb);
  876. }
  877. } else {
  878. /* Buffer overflow
  879. */
  880. dev_kfree_skb_any(skb);
  881. }
  882. }
  883. static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
  884. u8 type, u16 q_number, u16 completed_index, void *opaque)
  885. {
  886. struct enic *enic = vnic_dev_priv(vdev);
  887. vnic_rq_service(&enic->rq[q_number], cq_desc,
  888. completed_index, VNIC_RQ_RETURN_DESC,
  889. enic_rq_indicate_buf, opaque);
  890. return 0;
  891. }
  892. static void enic_rq_drop_buf(struct vnic_rq *rq,
  893. struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
  894. int skipped, void *opaque)
  895. {
  896. struct enic *enic = vnic_dev_priv(rq->vdev);
  897. struct sk_buff *skb = buf->os_buf;
  898. if (skipped)
  899. return;
  900. pci_unmap_single(enic->pdev, buf->dma_addr,
  901. buf->len, PCI_DMA_FROMDEVICE);
  902. dev_kfree_skb_any(skb);
  903. }
  904. static int enic_rq_service_drop(struct vnic_dev *vdev, struct cq_desc *cq_desc,
  905. u8 type, u16 q_number, u16 completed_index, void *opaque)
  906. {
  907. struct enic *enic = vnic_dev_priv(vdev);
  908. vnic_rq_service(&enic->rq[q_number], cq_desc,
  909. completed_index, VNIC_RQ_RETURN_DESC,
  910. enic_rq_drop_buf, opaque);
  911. return 0;
  912. }
  913. static int enic_poll(struct napi_struct *napi, int budget)
  914. {
  915. struct enic *enic = container_of(napi, struct enic, napi);
  916. struct net_device *netdev = enic->netdev;
  917. unsigned int rq_work_to_do = budget;
  918. unsigned int wq_work_to_do = -1; /* no limit */
  919. unsigned int work_done, rq_work_done, wq_work_done;
  920. /* Service RQ (first) and WQ
  921. */
  922. rq_work_done = vnic_cq_service(&enic->cq[ENIC_CQ_RQ],
  923. rq_work_to_do, enic_rq_service, NULL);
  924. wq_work_done = vnic_cq_service(&enic->cq[ENIC_CQ_WQ],
  925. wq_work_to_do, enic_wq_service, NULL);
  926. /* Accumulate intr event credits for this polling
  927. * cycle. An intr event is the completion of a
  928. * a WQ or RQ packet.
  929. */
  930. work_done = rq_work_done + wq_work_done;
  931. if (work_done > 0)
  932. vnic_intr_return_credits(&enic->intr[ENIC_INTX_WQ_RQ],
  933. work_done,
  934. 0 /* don't unmask intr */,
  935. 0 /* don't reset intr timer */);
  936. if (rq_work_done > 0) {
  937. /* Replenish RQ
  938. */
  939. vnic_rq_fill(&enic->rq[0], enic->rq_alloc_buf);
  940. } else {
  941. /* If no work done, flush all LROs and exit polling
  942. */
  943. if (netdev->features & NETIF_F_LRO)
  944. lro_flush_all(&enic->lro_mgr);
  945. napi_complete(napi);
  946. vnic_intr_unmask(&enic->intr[ENIC_INTX_WQ_RQ]);
  947. }
  948. return rq_work_done;
  949. }
  950. static int enic_poll_msix(struct napi_struct *napi, int budget)
  951. {
  952. struct enic *enic = container_of(napi, struct enic, napi);
  953. struct net_device *netdev = enic->netdev;
  954. unsigned int work_to_do = budget;
  955. unsigned int work_done;
  956. /* Service RQ
  957. */
  958. work_done = vnic_cq_service(&enic->cq[ENIC_CQ_RQ],
  959. work_to_do, enic_rq_service, NULL);
  960. if (work_done > 0) {
  961. /* Replenish RQ
  962. */
  963. vnic_rq_fill(&enic->rq[0], enic->rq_alloc_buf);
  964. /* Return intr event credits for this polling
  965. * cycle. An intr event is the completion of a
  966. * RQ packet.
  967. */
  968. vnic_intr_return_credits(&enic->intr[ENIC_MSIX_RQ],
  969. work_done,
  970. 0 /* don't unmask intr */,
  971. 0 /* don't reset intr timer */);
  972. } else {
  973. /* If no work done, flush all LROs and exit polling
  974. */
  975. if (netdev->features & NETIF_F_LRO)
  976. lro_flush_all(&enic->lro_mgr);
  977. napi_complete(napi);
  978. vnic_intr_unmask(&enic->intr[ENIC_MSIX_RQ]);
  979. }
  980. return work_done;
  981. }
  982. static void enic_notify_timer(unsigned long data)
  983. {
  984. struct enic *enic = (struct enic *)data;
  985. enic_notify_check(enic);
  986. mod_timer(&enic->notify_timer,
  987. round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD));
  988. }
  989. static void enic_free_intr(struct enic *enic)
  990. {
  991. struct net_device *netdev = enic->netdev;
  992. unsigned int i;
  993. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  994. case VNIC_DEV_INTR_MODE_INTX:
  995. free_irq(enic->pdev->irq, netdev);
  996. break;
  997. case VNIC_DEV_INTR_MODE_MSI:
  998. free_irq(enic->pdev->irq, enic);
  999. break;
  1000. case VNIC_DEV_INTR_MODE_MSIX:
  1001. for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
  1002. if (enic->msix[i].requested)
  1003. free_irq(enic->msix_entry[i].vector,
  1004. enic->msix[i].devid);
  1005. break;
  1006. default:
  1007. break;
  1008. }
  1009. }
  1010. static int enic_request_intr(struct enic *enic)
  1011. {
  1012. struct net_device *netdev = enic->netdev;
  1013. unsigned int i;
  1014. int err = 0;
  1015. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1016. case VNIC_DEV_INTR_MODE_INTX:
  1017. err = request_irq(enic->pdev->irq, enic_isr_legacy,
  1018. IRQF_SHARED, netdev->name, netdev);
  1019. break;
  1020. case VNIC_DEV_INTR_MODE_MSI:
  1021. err = request_irq(enic->pdev->irq, enic_isr_msi,
  1022. 0, netdev->name, enic);
  1023. break;
  1024. case VNIC_DEV_INTR_MODE_MSIX:
  1025. sprintf(enic->msix[ENIC_MSIX_RQ].devname,
  1026. "%.11s-rx-0", netdev->name);
  1027. enic->msix[ENIC_MSIX_RQ].isr = enic_isr_msix_rq;
  1028. enic->msix[ENIC_MSIX_RQ].devid = enic;
  1029. sprintf(enic->msix[ENIC_MSIX_WQ].devname,
  1030. "%.11s-tx-0", netdev->name);
  1031. enic->msix[ENIC_MSIX_WQ].isr = enic_isr_msix_wq;
  1032. enic->msix[ENIC_MSIX_WQ].devid = enic;
  1033. sprintf(enic->msix[ENIC_MSIX_ERR].devname,
  1034. "%.11s-err", netdev->name);
  1035. enic->msix[ENIC_MSIX_ERR].isr = enic_isr_msix_err;
  1036. enic->msix[ENIC_MSIX_ERR].devid = enic;
  1037. sprintf(enic->msix[ENIC_MSIX_NOTIFY].devname,
  1038. "%.11s-notify", netdev->name);
  1039. enic->msix[ENIC_MSIX_NOTIFY].isr = enic_isr_msix_notify;
  1040. enic->msix[ENIC_MSIX_NOTIFY].devid = enic;
  1041. for (i = 0; i < ARRAY_SIZE(enic->msix); i++) {
  1042. err = request_irq(enic->msix_entry[i].vector,
  1043. enic->msix[i].isr, 0,
  1044. enic->msix[i].devname,
  1045. enic->msix[i].devid);
  1046. if (err) {
  1047. enic_free_intr(enic);
  1048. break;
  1049. }
  1050. enic->msix[i].requested = 1;
  1051. }
  1052. break;
  1053. default:
  1054. break;
  1055. }
  1056. return err;
  1057. }
  1058. static int enic_notify_set(struct enic *enic)
  1059. {
  1060. int err;
  1061. spin_lock(&enic->devcmd_lock);
  1062. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1063. case VNIC_DEV_INTR_MODE_INTX:
  1064. err = vnic_dev_notify_set(enic->vdev, ENIC_INTX_NOTIFY);
  1065. break;
  1066. case VNIC_DEV_INTR_MODE_MSIX:
  1067. err = vnic_dev_notify_set(enic->vdev, ENIC_MSIX_NOTIFY);
  1068. break;
  1069. default:
  1070. err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */);
  1071. break;
  1072. }
  1073. spin_unlock(&enic->devcmd_lock);
  1074. return err;
  1075. }
  1076. static void enic_notify_timer_start(struct enic *enic)
  1077. {
  1078. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1079. case VNIC_DEV_INTR_MODE_MSI:
  1080. mod_timer(&enic->notify_timer, jiffies);
  1081. break;
  1082. default:
  1083. /* Using intr for notification for INTx/MSI-X */
  1084. break;
  1085. };
  1086. }
  1087. /* rtnl lock is held, process context */
  1088. static int enic_open(struct net_device *netdev)
  1089. {
  1090. struct enic *enic = netdev_priv(netdev);
  1091. unsigned int i;
  1092. int err;
  1093. err = enic_request_intr(enic);
  1094. if (err) {
  1095. printk(KERN_ERR PFX "%s: Unable to request irq.\n",
  1096. netdev->name);
  1097. return err;
  1098. }
  1099. err = enic_notify_set(enic);
  1100. if (err) {
  1101. printk(KERN_ERR PFX
  1102. "%s: Failed to alloc notify buffer, aborting.\n",
  1103. netdev->name);
  1104. goto err_out_free_intr;
  1105. }
  1106. for (i = 0; i < enic->rq_count; i++) {
  1107. err = vnic_rq_fill(&enic->rq[i], enic->rq_alloc_buf);
  1108. if (err) {
  1109. printk(KERN_ERR PFX
  1110. "%s: Unable to alloc receive buffers.\n",
  1111. netdev->name);
  1112. goto err_out_notify_unset;
  1113. }
  1114. }
  1115. for (i = 0; i < enic->wq_count; i++)
  1116. vnic_wq_enable(&enic->wq[i]);
  1117. for (i = 0; i < enic->rq_count; i++)
  1118. vnic_rq_enable(&enic->rq[i]);
  1119. spin_lock(&enic->devcmd_lock);
  1120. enic_add_station_addr(enic);
  1121. spin_unlock(&enic->devcmd_lock);
  1122. enic_set_multicast_list(netdev);
  1123. netif_wake_queue(netdev);
  1124. napi_enable(&enic->napi);
  1125. spin_lock(&enic->devcmd_lock);
  1126. vnic_dev_enable(enic->vdev);
  1127. spin_unlock(&enic->devcmd_lock);
  1128. for (i = 0; i < enic->intr_count; i++)
  1129. vnic_intr_unmask(&enic->intr[i]);
  1130. enic_notify_timer_start(enic);
  1131. return 0;
  1132. err_out_notify_unset:
  1133. spin_lock(&enic->devcmd_lock);
  1134. vnic_dev_notify_unset(enic->vdev);
  1135. spin_unlock(&enic->devcmd_lock);
  1136. err_out_free_intr:
  1137. enic_free_intr(enic);
  1138. return err;
  1139. }
  1140. /* rtnl lock is held, process context */
  1141. static int enic_stop(struct net_device *netdev)
  1142. {
  1143. struct enic *enic = netdev_priv(netdev);
  1144. unsigned int i;
  1145. int err;
  1146. del_timer_sync(&enic->notify_timer);
  1147. spin_lock(&enic->devcmd_lock);
  1148. vnic_dev_disable(enic->vdev);
  1149. spin_unlock(&enic->devcmd_lock);
  1150. napi_disable(&enic->napi);
  1151. netif_stop_queue(netdev);
  1152. for (i = 0; i < enic->intr_count; i++)
  1153. vnic_intr_mask(&enic->intr[i]);
  1154. for (i = 0; i < enic->wq_count; i++) {
  1155. err = vnic_wq_disable(&enic->wq[i]);
  1156. if (err)
  1157. return err;
  1158. }
  1159. for (i = 0; i < enic->rq_count; i++) {
  1160. err = vnic_rq_disable(&enic->rq[i]);
  1161. if (err)
  1162. return err;
  1163. }
  1164. spin_lock(&enic->devcmd_lock);
  1165. vnic_dev_notify_unset(enic->vdev);
  1166. spin_unlock(&enic->devcmd_lock);
  1167. enic_free_intr(enic);
  1168. (void)vnic_cq_service(&enic->cq[ENIC_CQ_RQ],
  1169. -1, enic_rq_service_drop, NULL);
  1170. (void)vnic_cq_service(&enic->cq[ENIC_CQ_WQ],
  1171. -1, enic_wq_service, NULL);
  1172. for (i = 0; i < enic->wq_count; i++)
  1173. vnic_wq_clean(&enic->wq[i], enic_free_wq_buf);
  1174. for (i = 0; i < enic->rq_count; i++)
  1175. vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
  1176. for (i = 0; i < enic->cq_count; i++)
  1177. vnic_cq_clean(&enic->cq[i]);
  1178. for (i = 0; i < enic->intr_count; i++)
  1179. vnic_intr_clean(&enic->intr[i]);
  1180. return 0;
  1181. }
  1182. static int enic_change_mtu(struct net_device *netdev, int new_mtu)
  1183. {
  1184. struct enic *enic = netdev_priv(netdev);
  1185. int running = netif_running(netdev);
  1186. if (new_mtu < ENIC_MIN_MTU || new_mtu > ENIC_MAX_MTU)
  1187. return -EINVAL;
  1188. if (running)
  1189. enic_stop(netdev);
  1190. netdev->mtu = new_mtu;
  1191. if (netdev->mtu > enic->port_mtu)
  1192. printk(KERN_WARNING PFX
  1193. "%s: interface MTU (%d) set higher "
  1194. "than port MTU (%d)\n",
  1195. netdev->name, netdev->mtu, enic->port_mtu);
  1196. if (running)
  1197. enic_open(netdev);
  1198. return 0;
  1199. }
  1200. #ifdef CONFIG_NET_POLL_CONTROLLER
  1201. static void enic_poll_controller(struct net_device *netdev)
  1202. {
  1203. struct enic *enic = netdev_priv(netdev);
  1204. struct vnic_dev *vdev = enic->vdev;
  1205. switch (vnic_dev_get_intr_mode(vdev)) {
  1206. case VNIC_DEV_INTR_MODE_MSIX:
  1207. enic_isr_msix_rq(enic->pdev->irq, enic);
  1208. enic_isr_msix_wq(enic->pdev->irq, enic);
  1209. break;
  1210. case VNIC_DEV_INTR_MODE_MSI:
  1211. enic_isr_msi(enic->pdev->irq, enic);
  1212. break;
  1213. case VNIC_DEV_INTR_MODE_INTX:
  1214. enic_isr_legacy(enic->pdev->irq, netdev);
  1215. break;
  1216. default:
  1217. break;
  1218. }
  1219. }
  1220. #endif
  1221. static int enic_dev_wait(struct vnic_dev *vdev,
  1222. int (*start)(struct vnic_dev *, int),
  1223. int (*finished)(struct vnic_dev *, int *),
  1224. int arg)
  1225. {
  1226. unsigned long time;
  1227. int done;
  1228. int err;
  1229. BUG_ON(in_interrupt());
  1230. err = start(vdev, arg);
  1231. if (err)
  1232. return err;
  1233. /* Wait for func to complete...2 seconds max
  1234. */
  1235. time = jiffies + (HZ * 2);
  1236. do {
  1237. err = finished(vdev, &done);
  1238. if (err)
  1239. return err;
  1240. if (done)
  1241. return 0;
  1242. schedule_timeout_uninterruptible(HZ / 10);
  1243. } while (time_after(time, jiffies));
  1244. return -ETIMEDOUT;
  1245. }
  1246. static int enic_dev_open(struct enic *enic)
  1247. {
  1248. int err;
  1249. err = enic_dev_wait(enic->vdev, vnic_dev_open,
  1250. vnic_dev_open_done, 0);
  1251. if (err)
  1252. printk(KERN_ERR PFX
  1253. "vNIC device open failed, err %d.\n", err);
  1254. return err;
  1255. }
  1256. static int enic_dev_soft_reset(struct enic *enic)
  1257. {
  1258. int err;
  1259. err = enic_dev_wait(enic->vdev, vnic_dev_soft_reset,
  1260. vnic_dev_soft_reset_done, 0);
  1261. if (err)
  1262. printk(KERN_ERR PFX
  1263. "vNIC soft reset failed, err %d.\n", err);
  1264. return err;
  1265. }
  1266. static int enic_set_niccfg(struct enic *enic)
  1267. {
  1268. const u8 rss_default_cpu = 0;
  1269. const u8 rss_hash_type = 0;
  1270. const u8 rss_hash_bits = 0;
  1271. const u8 rss_base_cpu = 0;
  1272. const u8 rss_enable = 0;
  1273. const u8 tso_ipid_split_en = 0;
  1274. const u8 ig_vlan_strip_en = 1;
  1275. /* Enable VLAN tag stripping. RSS not enabled (yet).
  1276. */
  1277. return enic_set_nic_cfg(enic,
  1278. rss_default_cpu, rss_hash_type,
  1279. rss_hash_bits, rss_base_cpu,
  1280. rss_enable, tso_ipid_split_en,
  1281. ig_vlan_strip_en);
  1282. }
  1283. static void enic_reset(struct work_struct *work)
  1284. {
  1285. struct enic *enic = container_of(work, struct enic, reset);
  1286. if (!netif_running(enic->netdev))
  1287. return;
  1288. rtnl_lock();
  1289. spin_lock(&enic->devcmd_lock);
  1290. vnic_dev_hang_notify(enic->vdev);
  1291. spin_unlock(&enic->devcmd_lock);
  1292. enic_stop(enic->netdev);
  1293. enic_dev_soft_reset(enic);
  1294. vnic_dev_init(enic->vdev, 0);
  1295. enic_reset_mcaddrs(enic);
  1296. enic_init_vnic_resources(enic);
  1297. enic_set_niccfg(enic);
  1298. enic_open(enic->netdev);
  1299. rtnl_unlock();
  1300. }
  1301. static int enic_set_intr_mode(struct enic *enic)
  1302. {
  1303. unsigned int n = 1;
  1304. unsigned int m = 1;
  1305. unsigned int i;
  1306. /* Set interrupt mode (INTx, MSI, MSI-X) depending
  1307. * system capabilities.
  1308. *
  1309. * Try MSI-X first
  1310. *
  1311. * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs
  1312. * (the second to last INTR is used for WQ/RQ errors)
  1313. * (the last INTR is used for notifications)
  1314. */
  1315. BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2);
  1316. for (i = 0; i < n + m + 2; i++)
  1317. enic->msix_entry[i].entry = i;
  1318. if (enic->config.intr_mode < 1 &&
  1319. enic->rq_count >= n &&
  1320. enic->wq_count >= m &&
  1321. enic->cq_count >= n + m &&
  1322. enic->intr_count >= n + m + 2 &&
  1323. !pci_enable_msix(enic->pdev, enic->msix_entry, n + m + 2)) {
  1324. enic->rq_count = n;
  1325. enic->wq_count = m;
  1326. enic->cq_count = n + m;
  1327. enic->intr_count = n + m + 2;
  1328. vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSIX);
  1329. return 0;
  1330. }
  1331. /* Next try MSI
  1332. *
  1333. * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR
  1334. */
  1335. if (enic->config.intr_mode < 2 &&
  1336. enic->rq_count >= 1 &&
  1337. enic->wq_count >= 1 &&
  1338. enic->cq_count >= 2 &&
  1339. enic->intr_count >= 1 &&
  1340. !pci_enable_msi(enic->pdev)) {
  1341. enic->rq_count = 1;
  1342. enic->wq_count = 1;
  1343. enic->cq_count = 2;
  1344. enic->intr_count = 1;
  1345. vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI);
  1346. return 0;
  1347. }
  1348. /* Next try INTx
  1349. *
  1350. * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs
  1351. * (the first INTR is used for WQ/RQ)
  1352. * (the second INTR is used for WQ/RQ errors)
  1353. * (the last INTR is used for notifications)
  1354. */
  1355. if (enic->config.intr_mode < 3 &&
  1356. enic->rq_count >= 1 &&
  1357. enic->wq_count >= 1 &&
  1358. enic->cq_count >= 2 &&
  1359. enic->intr_count >= 3) {
  1360. enic->rq_count = 1;
  1361. enic->wq_count = 1;
  1362. enic->cq_count = 2;
  1363. enic->intr_count = 3;
  1364. vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX);
  1365. return 0;
  1366. }
  1367. vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
  1368. return -EINVAL;
  1369. }
  1370. static void enic_clear_intr_mode(struct enic *enic)
  1371. {
  1372. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1373. case VNIC_DEV_INTR_MODE_MSIX:
  1374. pci_disable_msix(enic->pdev);
  1375. break;
  1376. case VNIC_DEV_INTR_MODE_MSI:
  1377. pci_disable_msi(enic->pdev);
  1378. break;
  1379. default:
  1380. break;
  1381. }
  1382. vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
  1383. }
  1384. static const struct net_device_ops enic_netdev_ops = {
  1385. .ndo_open = enic_open,
  1386. .ndo_stop = enic_stop,
  1387. .ndo_start_xmit = enic_hard_start_xmit,
  1388. .ndo_get_stats = enic_get_stats,
  1389. .ndo_validate_addr = eth_validate_addr,
  1390. .ndo_set_mac_address = eth_mac_addr,
  1391. .ndo_set_multicast_list = enic_set_multicast_list,
  1392. .ndo_change_mtu = enic_change_mtu,
  1393. .ndo_vlan_rx_register = enic_vlan_rx_register,
  1394. .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
  1395. .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
  1396. .ndo_tx_timeout = enic_tx_timeout,
  1397. #ifdef CONFIG_NET_POLL_CONTROLLER
  1398. .ndo_poll_controller = enic_poll_controller,
  1399. #endif
  1400. };
  1401. void enic_dev_deinit(struct enic *enic)
  1402. {
  1403. netif_napi_del(&enic->napi);
  1404. enic_free_vnic_resources(enic);
  1405. enic_clear_intr_mode(enic);
  1406. }
  1407. int enic_dev_init(struct enic *enic)
  1408. {
  1409. struct net_device *netdev = enic->netdev;
  1410. int err;
  1411. /* Get vNIC configuration
  1412. */
  1413. err = enic_get_vnic_config(enic);
  1414. if (err) {
  1415. printk(KERN_ERR PFX
  1416. "Get vNIC configuration failed, aborting.\n");
  1417. return err;
  1418. }
  1419. /* Get available resource counts
  1420. */
  1421. enic_get_res_counts(enic);
  1422. /* Set interrupt mode based on resource counts and system
  1423. * capabilities
  1424. */
  1425. err = enic_set_intr_mode(enic);
  1426. if (err) {
  1427. printk(KERN_ERR PFX
  1428. "Failed to set intr mode, aborting.\n");
  1429. return err;
  1430. }
  1431. /* Allocate and configure vNIC resources
  1432. */
  1433. err = enic_alloc_vnic_resources(enic);
  1434. if (err) {
  1435. printk(KERN_ERR PFX
  1436. "Failed to alloc vNIC resources, aborting.\n");
  1437. goto err_out_free_vnic_resources;
  1438. }
  1439. enic_init_vnic_resources(enic);
  1440. err = enic_set_rq_alloc_buf(enic);
  1441. if (err) {
  1442. printk(KERN_ERR PFX
  1443. "Failed to set RQ buffer allocator, aborting.\n");
  1444. goto err_out_free_vnic_resources;
  1445. }
  1446. err = enic_set_niccfg(enic);
  1447. if (err) {
  1448. printk(KERN_ERR PFX
  1449. "Failed to config nic, aborting.\n");
  1450. goto err_out_free_vnic_resources;
  1451. }
  1452. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  1453. default:
  1454. netif_napi_add(netdev, &enic->napi, enic_poll, 64);
  1455. break;
  1456. case VNIC_DEV_INTR_MODE_MSIX:
  1457. netif_napi_add(netdev, &enic->napi, enic_poll_msix, 64);
  1458. break;
  1459. }
  1460. return 0;
  1461. err_out_free_vnic_resources:
  1462. enic_clear_intr_mode(enic);
  1463. enic_free_vnic_resources(enic);
  1464. return err;
  1465. }
  1466. static void enic_iounmap(struct enic *enic)
  1467. {
  1468. unsigned int i;
  1469. for (i = 0; i < ARRAY_SIZE(enic->bar); i++)
  1470. if (enic->bar[i].vaddr)
  1471. iounmap(enic->bar[i].vaddr);
  1472. }
  1473. static int __devinit enic_probe(struct pci_dev *pdev,
  1474. const struct pci_device_id *ent)
  1475. {
  1476. struct net_device *netdev;
  1477. struct enic *enic;
  1478. int using_dac = 0;
  1479. unsigned int i;
  1480. int err;
  1481. /* Allocate net device structure and initialize. Private
  1482. * instance data is initialized to zero.
  1483. */
  1484. netdev = alloc_etherdev(sizeof(struct enic));
  1485. if (!netdev) {
  1486. printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
  1487. return -ENOMEM;
  1488. }
  1489. pci_set_drvdata(pdev, netdev);
  1490. SET_NETDEV_DEV(netdev, &pdev->dev);
  1491. enic = netdev_priv(netdev);
  1492. enic->netdev = netdev;
  1493. enic->pdev = pdev;
  1494. /* Setup PCI resources
  1495. */
  1496. err = pci_enable_device(pdev);
  1497. if (err) {
  1498. printk(KERN_ERR PFX
  1499. "Cannot enable PCI device, aborting.\n");
  1500. goto err_out_free_netdev;
  1501. }
  1502. err = pci_request_regions(pdev, DRV_NAME);
  1503. if (err) {
  1504. printk(KERN_ERR PFX
  1505. "Cannot request PCI regions, aborting.\n");
  1506. goto err_out_disable_device;
  1507. }
  1508. pci_set_master(pdev);
  1509. /* Query PCI controller on system for DMA addressing
  1510. * limitation for the device. Try 40-bit first, and
  1511. * fail to 32-bit.
  1512. */
  1513. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(40));
  1514. if (err) {
  1515. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  1516. if (err) {
  1517. printk(KERN_ERR PFX
  1518. "No usable DMA configuration, aborting.\n");
  1519. goto err_out_release_regions;
  1520. }
  1521. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  1522. if (err) {
  1523. printk(KERN_ERR PFX
  1524. "Unable to obtain 32-bit DMA "
  1525. "for consistent allocations, aborting.\n");
  1526. goto err_out_release_regions;
  1527. }
  1528. } else {
  1529. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40));
  1530. if (err) {
  1531. printk(KERN_ERR PFX
  1532. "Unable to obtain 40-bit DMA "
  1533. "for consistent allocations, aborting.\n");
  1534. goto err_out_release_regions;
  1535. }
  1536. using_dac = 1;
  1537. }
  1538. /* Map vNIC resources from BAR0-5
  1539. */
  1540. for (i = 0; i < ARRAY_SIZE(enic->bar); i++) {
  1541. if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
  1542. continue;
  1543. enic->bar[i].len = pci_resource_len(pdev, i);
  1544. enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len);
  1545. if (!enic->bar[i].vaddr) {
  1546. printk(KERN_ERR PFX
  1547. "Cannot memory-map BAR %d, aborting.\n", i);
  1548. err = -ENODEV;
  1549. goto err_out_iounmap;
  1550. }
  1551. enic->bar[i].bus_addr = pci_resource_start(pdev, i);
  1552. }
  1553. /* Register vNIC device
  1554. */
  1555. enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar,
  1556. ARRAY_SIZE(enic->bar));
  1557. if (!enic->vdev) {
  1558. printk(KERN_ERR PFX
  1559. "vNIC registration failed, aborting.\n");
  1560. err = -ENODEV;
  1561. goto err_out_iounmap;
  1562. }
  1563. /* Issue device open to get device in known state
  1564. */
  1565. err = enic_dev_open(enic);
  1566. if (err) {
  1567. printk(KERN_ERR PFX
  1568. "vNIC dev open failed, aborting.\n");
  1569. goto err_out_vnic_unregister;
  1570. }
  1571. /* Issue device init to initialize the vnic-to-switch link.
  1572. * We'll start with carrier off and wait for link UP
  1573. * notification later to turn on carrier. We don't need
  1574. * to wait here for the vnic-to-switch link initialization
  1575. * to complete; link UP notification is the indication that
  1576. * the process is complete.
  1577. */
  1578. netif_carrier_off(netdev);
  1579. err = vnic_dev_init(enic->vdev, 0);
  1580. if (err) {
  1581. printk(KERN_ERR PFX
  1582. "vNIC dev init failed, aborting.\n");
  1583. goto err_out_dev_close;
  1584. }
  1585. err = enic_dev_init(enic);
  1586. if (err) {
  1587. printk(KERN_ERR PFX
  1588. "Device initialization failed, aborting.\n");
  1589. goto err_out_dev_close;
  1590. }
  1591. /* Setup notification timer, HW reset task, and locks
  1592. */
  1593. init_timer(&enic->notify_timer);
  1594. enic->notify_timer.function = enic_notify_timer;
  1595. enic->notify_timer.data = (unsigned long)enic;
  1596. INIT_WORK(&enic->reset, enic_reset);
  1597. for (i = 0; i < enic->wq_count; i++)
  1598. spin_lock_init(&enic->wq_lock[i]);
  1599. spin_lock_init(&enic->devcmd_lock);
  1600. /* Register net device
  1601. */
  1602. enic->port_mtu = enic->config.mtu;
  1603. (void)enic_change_mtu(netdev, enic->port_mtu);
  1604. err = enic_set_mac_addr(netdev, enic->mac_addr);
  1605. if (err) {
  1606. printk(KERN_ERR PFX
  1607. "Invalid MAC address, aborting.\n");
  1608. goto err_out_dev_deinit;
  1609. }
  1610. netdev->netdev_ops = &enic_netdev_ops;
  1611. netdev->watchdog_timeo = 2 * HZ;
  1612. netdev->ethtool_ops = &enic_ethtool_ops;
  1613. netdev->features |= NETIF_F_HW_VLAN_TX |
  1614. NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
  1615. if (ENIC_SETTING(enic, TXCSUM))
  1616. netdev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
  1617. if (ENIC_SETTING(enic, TSO))
  1618. netdev->features |= NETIF_F_TSO |
  1619. NETIF_F_TSO6 | NETIF_F_TSO_ECN;
  1620. if (ENIC_SETTING(enic, LRO))
  1621. netdev->features |= NETIF_F_LRO;
  1622. if (using_dac)
  1623. netdev->features |= NETIF_F_HIGHDMA;
  1624. enic->csum_rx_enabled = ENIC_SETTING(enic, RXCSUM);
  1625. enic->lro_mgr.max_aggr = ENIC_LRO_MAX_AGGR;
  1626. enic->lro_mgr.max_desc = ENIC_LRO_MAX_DESC;
  1627. enic->lro_mgr.lro_arr = enic->lro_desc;
  1628. enic->lro_mgr.get_skb_header = enic_get_skb_header;
  1629. enic->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
  1630. enic->lro_mgr.dev = netdev;
  1631. enic->lro_mgr.ip_summed = CHECKSUM_COMPLETE;
  1632. enic->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
  1633. err = register_netdev(netdev);
  1634. if (err) {
  1635. printk(KERN_ERR PFX
  1636. "Cannot register net device, aborting.\n");
  1637. goto err_out_dev_deinit;
  1638. }
  1639. return 0;
  1640. err_out_dev_deinit:
  1641. enic_dev_deinit(enic);
  1642. err_out_dev_close:
  1643. vnic_dev_close(enic->vdev);
  1644. err_out_vnic_unregister:
  1645. vnic_dev_unregister(enic->vdev);
  1646. err_out_iounmap:
  1647. enic_iounmap(enic);
  1648. err_out_release_regions:
  1649. pci_release_regions(pdev);
  1650. err_out_disable_device:
  1651. pci_disable_device(pdev);
  1652. err_out_free_netdev:
  1653. pci_set_drvdata(pdev, NULL);
  1654. free_netdev(netdev);
  1655. return err;
  1656. }
  1657. static void __devexit enic_remove(struct pci_dev *pdev)
  1658. {
  1659. struct net_device *netdev = pci_get_drvdata(pdev);
  1660. if (netdev) {
  1661. struct enic *enic = netdev_priv(netdev);
  1662. flush_scheduled_work();
  1663. unregister_netdev(netdev);
  1664. enic_dev_deinit(enic);
  1665. vnic_dev_close(enic->vdev);
  1666. vnic_dev_unregister(enic->vdev);
  1667. enic_iounmap(enic);
  1668. pci_release_regions(pdev);
  1669. pci_disable_device(pdev);
  1670. pci_set_drvdata(pdev, NULL);
  1671. free_netdev(netdev);
  1672. }
  1673. }
  1674. static struct pci_driver enic_driver = {
  1675. .name = DRV_NAME,
  1676. .id_table = enic_id_table,
  1677. .probe = enic_probe,
  1678. .remove = __devexit_p(enic_remove),
  1679. };
  1680. static int __init enic_init_module(void)
  1681. {
  1682. printk(KERN_INFO PFX "%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION);
  1683. return pci_register_driver(&enic_driver);
  1684. }
  1685. static void __exit enic_cleanup_module(void)
  1686. {
  1687. pci_unregister_driver(&enic_driver);
  1688. }
  1689. module_init(enic_init_module);
  1690. module_exit(enic_cleanup_module);