stv090x.c 118 KB

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  1. /*
  2. STV0900/0903 Multistandard Broadcast Frontend driver
  3. Copyright (C) Manu Abraham <abraham.manu@gmail.com>
  4. Copyright (C) ST Microelectronics
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. */
  17. #include <linux/init.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/string.h>
  21. #include <linux/mutex.h>
  22. #include <linux/dvb/frontend.h>
  23. #include "dvb_frontend.h"
  24. #include "stv6110x.h" /* for demodulator internal modes */
  25. #include "stv090x_reg.h"
  26. #include "stv090x.h"
  27. #include "stv090x_priv.h"
  28. static unsigned int verbose;
  29. module_param(verbose, int, 0644);
  30. struct mutex demod_lock;
  31. /* DVBS1 and DSS C/N Lookup table */
  32. static const struct stv090x_tab stv090x_s1cn_tab[] = {
  33. { 0, 8917 }, /* 0.0dB */
  34. { 5, 8801 }, /* 0.5dB */
  35. { 10, 8667 }, /* 1.0dB */
  36. { 15, 8522 }, /* 1.5dB */
  37. { 20, 8355 }, /* 2.0dB */
  38. { 25, 8175 }, /* 2.5dB */
  39. { 30, 7979 }, /* 3.0dB */
  40. { 35, 7763 }, /* 3.5dB */
  41. { 40, 7530 }, /* 4.0dB */
  42. { 45, 7282 }, /* 4.5dB */
  43. { 50, 7026 }, /* 5.0dB */
  44. { 55, 6781 }, /* 5.5dB */
  45. { 60, 6514 }, /* 6.0dB */
  46. { 65, 6241 }, /* 6.5dB */
  47. { 70, 5965 }, /* 7.0dB */
  48. { 75, 5690 }, /* 7.5dB */
  49. { 80, 5424 }, /* 8.0dB */
  50. { 85, 5161 }, /* 8.5dB */
  51. { 90, 4902 }, /* 9.0dB */
  52. { 95, 4654 }, /* 9.5dB */
  53. { 100, 4417 }, /* 10.0dB */
  54. { 105, 4186 }, /* 10.5dB */
  55. { 110, 3968 }, /* 11.0dB */
  56. { 115, 3757 }, /* 11.5dB */
  57. { 120, 3558 }, /* 12.0dB */
  58. { 125, 3366 }, /* 12.5dB */
  59. { 130, 3185 }, /* 13.0dB */
  60. { 135, 3012 }, /* 13.5dB */
  61. { 140, 2850 }, /* 14.0dB */
  62. { 145, 2698 }, /* 14.5dB */
  63. { 150, 2550 }, /* 15.0dB */
  64. { 160, 2283 }, /* 16.0dB */
  65. { 170, 2042 }, /* 17.0dB */
  66. { 180, 1827 }, /* 18.0dB */
  67. { 190, 1636 }, /* 19.0dB */
  68. { 200, 1466 }, /* 20.0dB */
  69. { 210, 1315 }, /* 21.0dB */
  70. { 220, 1181 }, /* 22.0dB */
  71. { 230, 1064 }, /* 23.0dB */
  72. { 240, 960 }, /* 24.0dB */
  73. { 250, 869 }, /* 25.0dB */
  74. { 260, 792 }, /* 26.0dB */
  75. { 270, 724 }, /* 27.0dB */
  76. { 280, 665 }, /* 28.0dB */
  77. { 290, 616 }, /* 29.0dB */
  78. { 300, 573 }, /* 30.0dB */
  79. { 310, 537 }, /* 31.0dB */
  80. { 320, 507 }, /* 32.0dB */
  81. { 330, 483 }, /* 33.0dB */
  82. { 400, 398 }, /* 40.0dB */
  83. { 450, 381 }, /* 45.0dB */
  84. { 500, 377 } /* 50.0dB */
  85. };
  86. /* DVBS2 C/N Lookup table */
  87. static const struct stv090x_tab stv090x_s2cn_tab[] = {
  88. { -30, 13348 }, /* -3.0dB */
  89. { -20, 12640 }, /* -2d.0B */
  90. { -10, 11883 }, /* -1.0dB */
  91. { 0, 11101 }, /* -0.0dB */
  92. { 5, 10718 }, /* 0.5dB */
  93. { 10, 10339 }, /* 1.0dB */
  94. { 15, 9947 }, /* 1.5dB */
  95. { 20, 9552 }, /* 2.0dB */
  96. { 25, 9183 }, /* 2.5dB */
  97. { 30, 8799 }, /* 3.0dB */
  98. { 35, 8422 }, /* 3.5dB */
  99. { 40, 8062 }, /* 4.0dB */
  100. { 45, 7707 }, /* 4.5dB */
  101. { 50, 7353 }, /* 5.0dB */
  102. { 55, 7025 }, /* 5.5dB */
  103. { 60, 6684 }, /* 6.0dB */
  104. { 65, 6331 }, /* 6.5dB */
  105. { 70, 6036 }, /* 7.0dB */
  106. { 75, 5727 }, /* 7.5dB */
  107. { 80, 5437 }, /* 8.0dB */
  108. { 85, 5164 }, /* 8.5dB */
  109. { 90, 4902 }, /* 9.0dB */
  110. { 95, 4653 }, /* 9.5dB */
  111. { 100, 4408 }, /* 10.0dB */
  112. { 105, 4187 }, /* 10.5dB */
  113. { 110, 3961 }, /* 11.0dB */
  114. { 115, 3751 }, /* 11.5dB */
  115. { 120, 3558 }, /* 12.0dB */
  116. { 125, 3368 }, /* 12.5dB */
  117. { 130, 3191 }, /* 13.0dB */
  118. { 135, 3017 }, /* 13.5dB */
  119. { 140, 2862 }, /* 14.0dB */
  120. { 145, 2710 }, /* 14.5dB */
  121. { 150, 2565 }, /* 15.0dB */
  122. { 160, 2300 }, /* 16.0dB */
  123. { 170, 2058 }, /* 17.0dB */
  124. { 180, 1849 }, /* 18.0dB */
  125. { 190, 1663 }, /* 19.0dB */
  126. { 200, 1495 }, /* 20.0dB */
  127. { 210, 1349 }, /* 21.0dB */
  128. { 220, 1222 }, /* 22.0dB */
  129. { 230, 1110 }, /* 23.0dB */
  130. { 240, 1011 }, /* 24.0dB */
  131. { 250, 925 }, /* 25.0dB */
  132. { 260, 853 }, /* 26.0dB */
  133. { 270, 789 }, /* 27.0dB */
  134. { 280, 734 }, /* 28.0dB */
  135. { 290, 690 }, /* 29.0dB */
  136. { 300, 650 }, /* 30.0dB */
  137. { 310, 619 }, /* 31.0dB */
  138. { 320, 593 }, /* 32.0dB */
  139. { 330, 571 }, /* 33.0dB */
  140. { 400, 498 }, /* 40.0dB */
  141. { 450, 484 }, /* 45.0dB */
  142. { 500, 481 } /* 50.0dB */
  143. };
  144. /* RF level C/N lookup table */
  145. static const struct stv090x_tab stv090x_rf_tab[] = {
  146. { -5, 0xcaa1 }, /* -5dBm */
  147. { -10, 0xc229 }, /* -10dBm */
  148. { -15, 0xbb08 }, /* -15dBm */
  149. { -20, 0xb4bc }, /* -20dBm */
  150. { -25, 0xad5a }, /* -25dBm */
  151. { -30, 0xa298 }, /* -30dBm */
  152. { -35, 0x98a8 }, /* -35dBm */
  153. { -40, 0x8389 }, /* -40dBm */
  154. { -45, 0x59be }, /* -45dBm */
  155. { -50, 0x3a14 }, /* -50dBm */
  156. { -55, 0x2d11 }, /* -55dBm */
  157. { -60, 0x210d }, /* -60dBm */
  158. { -65, 0xa14f }, /* -65dBm */
  159. { -70, 0x07aa } /* -70dBm */
  160. };
  161. static struct stv090x_reg stv0900_initval[] = {
  162. { STV090x_OUTCFG, 0x00 },
  163. { STV090x_MODECFG, 0xff },
  164. { STV090x_AGCRF1CFG, 0x11 },
  165. { STV090x_AGCRF2CFG, 0x13 },
  166. { STV090x_TSGENERAL1X, 0x14 },
  167. { STV090x_TSTTNR2, 0x21 },
  168. { STV090x_TSTTNR4, 0x21 },
  169. { STV090x_P2_DISTXCTL, 0x22 },
  170. { STV090x_P2_F22TX, 0xc0 },
  171. { STV090x_P2_F22RX, 0xc0 },
  172. { STV090x_P2_DISRXCTL, 0x00 },
  173. { STV090x_P2_DMDCFGMD, 0xF9 },
  174. { STV090x_P2_DEMOD, 0x08 },
  175. { STV090x_P2_DMDCFG3, 0xc4 },
  176. { STV090x_P2_CARFREQ, 0xed },
  177. { STV090x_P2_LDT, 0xd0 },
  178. { STV090x_P2_LDT2, 0xb8 },
  179. { STV090x_P2_TMGCFG, 0xd2 },
  180. { STV090x_P2_TMGTHRISE, 0x20 },
  181. { STV090x_P1_TMGCFG, 0xd2 },
  182. { STV090x_P2_TMGTHFALL, 0x00 },
  183. { STV090x_P2_FECSPY, 0x88 },
  184. { STV090x_P2_FSPYDATA, 0x3a },
  185. { STV090x_P2_FBERCPT4, 0x00 },
  186. { STV090x_P2_FSPYBER, 0x10 },
  187. { STV090x_P2_ERRCTRL1, 0x35 },
  188. { STV090x_P2_ERRCTRL2, 0xc1 },
  189. { STV090x_P2_CFRICFG, 0xf8 },
  190. { STV090x_P2_NOSCFG, 0x1c },
  191. { STV090x_P2_DMDTOM, 0x20 },
  192. { STV090x_P2_CORRELMANT, 0x70 },
  193. { STV090x_P2_CORRELABS, 0x88 },
  194. { STV090x_P2_AGC2O, 0x5b },
  195. { STV090x_P2_AGC2REF, 0x38 },
  196. { STV090x_P2_CARCFG, 0xe4 },
  197. { STV090x_P2_ACLC, 0x1A },
  198. { STV090x_P2_BCLC, 0x09 },
  199. { STV090x_P2_CARHDR, 0x08 },
  200. { STV090x_P2_KREFTMG, 0xc1 },
  201. { STV090x_P2_SFRUPRATIO, 0xf0 },
  202. { STV090x_P2_SFRLOWRATIO, 0x70 },
  203. { STV090x_P2_SFRSTEP, 0x58 },
  204. { STV090x_P2_TMGCFG2, 0x01 },
  205. { STV090x_P2_CAR2CFG, 0x26 },
  206. { STV090x_P2_BCLC2S2Q, 0x86 },
  207. { STV090x_P2_BCLC2S28, 0x86 },
  208. { STV090x_P2_SMAPCOEF7, 0x77 },
  209. { STV090x_P2_SMAPCOEF6, 0x85 },
  210. { STV090x_P2_SMAPCOEF5, 0x77 },
  211. { STV090x_P2_TSCFGL, 0x20 },
  212. { STV090x_P2_DMDCFG2, 0x3b },
  213. { STV090x_P2_MODCODLST0, 0xff },
  214. { STV090x_P2_MODCODLST1, 0xff },
  215. { STV090x_P2_MODCODLST2, 0xff },
  216. { STV090x_P2_MODCODLST3, 0xff },
  217. { STV090x_P2_MODCODLST4, 0xff },
  218. { STV090x_P2_MODCODLST5, 0xff },
  219. { STV090x_P2_MODCODLST6, 0xff },
  220. { STV090x_P2_MODCODLST7, 0xcc },
  221. { STV090x_P2_MODCODLST8, 0xcc },
  222. { STV090x_P2_MODCODLST9, 0xcc },
  223. { STV090x_P2_MODCODLSTA, 0xcc },
  224. { STV090x_P2_MODCODLSTB, 0xcc },
  225. { STV090x_P2_MODCODLSTC, 0xcc },
  226. { STV090x_P2_MODCODLSTD, 0xcc },
  227. { STV090x_P2_MODCODLSTE, 0xcc },
  228. { STV090x_P2_MODCODLSTF, 0xcf },
  229. { STV090x_P1_DISTXCTL, 0x22 },
  230. { STV090x_P1_F22TX, 0xc0 },
  231. { STV090x_P1_F22RX, 0xc0 },
  232. { STV090x_P1_DISRXCTL, 0x00 },
  233. { STV090x_P1_DMDCFGMD, 0xf9 },
  234. { STV090x_P1_DEMOD, 0x08 },
  235. { STV090x_P1_DMDCFG3, 0xc4 },
  236. { STV090x_P1_DMDTOM, 0x20 },
  237. { STV090x_P1_CARFREQ, 0xed },
  238. { STV090x_P1_LDT, 0xd0 },
  239. { STV090x_P1_LDT2, 0xb8 },
  240. { STV090x_P1_TMGCFG, 0xd2 },
  241. { STV090x_P1_TMGTHRISE, 0x20 },
  242. { STV090x_P1_TMGTHFALL, 0x00 },
  243. { STV090x_P1_SFRUPRATIO, 0xf0 },
  244. { STV090x_P1_SFRLOWRATIO, 0x70 },
  245. { STV090x_P1_TSCFGL, 0x20 },
  246. { STV090x_P1_FECSPY, 0x88 },
  247. { STV090x_P1_FSPYDATA, 0x3a },
  248. { STV090x_P1_FBERCPT4, 0x00 },
  249. { STV090x_P1_FSPYBER, 0x10 },
  250. { STV090x_P1_ERRCTRL1, 0x35 },
  251. { STV090x_P1_ERRCTRL2, 0xc1 },
  252. { STV090x_P1_CFRICFG, 0xf8 },
  253. { STV090x_P1_NOSCFG, 0x1c },
  254. { STV090x_P1_CORRELMANT, 0x70 },
  255. { STV090x_P1_CORRELABS, 0x88 },
  256. { STV090x_P1_AGC2O, 0x5b },
  257. { STV090x_P1_AGC2REF, 0x38 },
  258. { STV090x_P1_CARCFG, 0xe4 },
  259. { STV090x_P1_ACLC, 0x1A },
  260. { STV090x_P1_BCLC, 0x09 },
  261. { STV090x_P1_CARHDR, 0x08 },
  262. { STV090x_P1_KREFTMG, 0xc1 },
  263. { STV090x_P1_SFRSTEP, 0x58 },
  264. { STV090x_P1_TMGCFG2, 0x01 },
  265. { STV090x_P1_CAR2CFG, 0x26 },
  266. { STV090x_P1_BCLC2S2Q, 0x86 },
  267. { STV090x_P1_BCLC2S28, 0x86 },
  268. { STV090x_P1_SMAPCOEF7, 0x77 },
  269. { STV090x_P1_SMAPCOEF6, 0x85 },
  270. { STV090x_P1_SMAPCOEF5, 0x77 },
  271. { STV090x_P1_DMDCFG2, 0x3b },
  272. { STV090x_P1_MODCODLST0, 0xff },
  273. { STV090x_P1_MODCODLST1, 0xff },
  274. { STV090x_P1_MODCODLST2, 0xff },
  275. { STV090x_P1_MODCODLST3, 0xff },
  276. { STV090x_P1_MODCODLST4, 0xff },
  277. { STV090x_P1_MODCODLST5, 0xff },
  278. { STV090x_P1_MODCODLST6, 0xff },
  279. { STV090x_P1_MODCODLST7, 0xcc },
  280. { STV090x_P1_MODCODLST8, 0xcc },
  281. { STV090x_P1_MODCODLST9, 0xcc },
  282. { STV090x_P1_MODCODLSTA, 0xcc },
  283. { STV090x_P1_MODCODLSTB, 0xcc },
  284. { STV090x_P1_MODCODLSTC, 0xcc },
  285. { STV090x_P1_MODCODLSTD, 0xcc },
  286. { STV090x_P1_MODCODLSTE, 0xcc },
  287. { STV090x_P1_MODCODLSTF, 0xcf },
  288. { STV090x_GENCFG, 0x1d },
  289. { STV090x_NBITER_NF4, 0x37 },
  290. { STV090x_NBITER_NF5, 0x29 },
  291. { STV090x_NBITER_NF6, 0x37 },
  292. { STV090x_NBITER_NF7, 0x33 },
  293. { STV090x_NBITER_NF8, 0x31 },
  294. { STV090x_NBITER_NF9, 0x2f },
  295. { STV090x_NBITER_NF10, 0x39 },
  296. { STV090x_NBITER_NF11, 0x3a },
  297. { STV090x_NBITER_NF12, 0x29 },
  298. { STV090x_NBITER_NF13, 0x37 },
  299. { STV090x_NBITER_NF14, 0x33 },
  300. { STV090x_NBITER_NF15, 0x2f },
  301. { STV090x_NBITER_NF16, 0x39 },
  302. { STV090x_NBITER_NF17, 0x3a },
  303. { STV090x_NBITERNOERR, 0x04 },
  304. { STV090x_GAINLLR_NF4, 0x0C },
  305. { STV090x_GAINLLR_NF5, 0x0F },
  306. { STV090x_GAINLLR_NF6, 0x11 },
  307. { STV090x_GAINLLR_NF7, 0x14 },
  308. { STV090x_GAINLLR_NF8, 0x17 },
  309. { STV090x_GAINLLR_NF9, 0x19 },
  310. { STV090x_GAINLLR_NF10, 0x20 },
  311. { STV090x_GAINLLR_NF11, 0x21 },
  312. { STV090x_GAINLLR_NF12, 0x0D },
  313. { STV090x_GAINLLR_NF13, 0x0F },
  314. { STV090x_GAINLLR_NF14, 0x13 },
  315. { STV090x_GAINLLR_NF15, 0x1A },
  316. { STV090x_GAINLLR_NF16, 0x1F },
  317. { STV090x_GAINLLR_NF17, 0x21 },
  318. { STV090x_RCCFGH, 0x20 },
  319. { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
  320. { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
  321. { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
  322. { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
  323. };
  324. static struct stv090x_reg stv0903_initval[] = {
  325. { STV090x_OUTCFG, 0x00 },
  326. { STV090x_AGCRF1CFG, 0x11 },
  327. { STV090x_STOPCLK1, 0x48 },
  328. { STV090x_STOPCLK2, 0x14 },
  329. { STV090x_TSTTNR1, 0x27 },
  330. { STV090x_TSTTNR2, 0x21 },
  331. { STV090x_P1_DISTXCTL, 0x22 },
  332. { STV090x_P1_F22TX, 0xc0 },
  333. { STV090x_P1_F22RX, 0xc0 },
  334. { STV090x_P1_DISRXCTL, 0x00 },
  335. { STV090x_P1_DMDCFGMD, 0xF9 },
  336. { STV090x_P1_DEMOD, 0x08 },
  337. { STV090x_P1_DMDCFG3, 0xc4 },
  338. { STV090x_P1_CARFREQ, 0xed },
  339. { STV090x_P1_TNRCFG2, 0x82 },
  340. { STV090x_P1_LDT, 0xd0 },
  341. { STV090x_P1_LDT2, 0xb8 },
  342. { STV090x_P1_TMGCFG, 0xd2 },
  343. { STV090x_P1_TMGTHRISE, 0x20 },
  344. { STV090x_P1_TMGTHFALL, 0x00 },
  345. { STV090x_P1_SFRUPRATIO, 0xf0 },
  346. { STV090x_P1_SFRLOWRATIO, 0x70 },
  347. { STV090x_P1_TSCFGL, 0x20 },
  348. { STV090x_P1_FECSPY, 0x88 },
  349. { STV090x_P1_FSPYDATA, 0x3a },
  350. { STV090x_P1_FBERCPT4, 0x00 },
  351. { STV090x_P1_FSPYBER, 0x10 },
  352. { STV090x_P1_ERRCTRL1, 0x35 },
  353. { STV090x_P1_ERRCTRL2, 0xc1 },
  354. { STV090x_P1_CFRICFG, 0xf8 },
  355. { STV090x_P1_NOSCFG, 0x1c },
  356. { STV090x_P1_DMDTOM, 0x20 },
  357. { STV090x_P1_CORRELMANT, 0x70 },
  358. { STV090x_P1_CORRELABS, 0x88 },
  359. { STV090x_P1_AGC2O, 0x5b },
  360. { STV090x_P1_AGC2REF, 0x38 },
  361. { STV090x_P1_CARCFG, 0xe4 },
  362. { STV090x_P1_ACLC, 0x1A },
  363. { STV090x_P1_BCLC, 0x09 },
  364. { STV090x_P1_CARHDR, 0x08 },
  365. { STV090x_P1_KREFTMG, 0xc1 },
  366. { STV090x_P1_SFRSTEP, 0x58 },
  367. { STV090x_P1_TMGCFG2, 0x01 },
  368. { STV090x_P1_CAR2CFG, 0x26 },
  369. { STV090x_P1_BCLC2S2Q, 0x86 },
  370. { STV090x_P1_BCLC2S28, 0x86 },
  371. { STV090x_P1_SMAPCOEF7, 0x77 },
  372. { STV090x_P1_SMAPCOEF6, 0x85 },
  373. { STV090x_P1_SMAPCOEF5, 0x77 },
  374. { STV090x_P1_DMDCFG2, 0x3b },
  375. { STV090x_P1_MODCODLST0, 0xff },
  376. { STV090x_P1_MODCODLST1, 0xff },
  377. { STV090x_P1_MODCODLST2, 0xff },
  378. { STV090x_P1_MODCODLST3, 0xff },
  379. { STV090x_P1_MODCODLST4, 0xff },
  380. { STV090x_P1_MODCODLST5, 0xff },
  381. { STV090x_P1_MODCODLST6, 0xff },
  382. { STV090x_P1_MODCODLST7, 0xcc },
  383. { STV090x_P1_MODCODLST8, 0xcc },
  384. { STV090x_P1_MODCODLST9, 0xcc },
  385. { STV090x_P1_MODCODLSTA, 0xcc },
  386. { STV090x_P1_MODCODLSTB, 0xcc },
  387. { STV090x_P1_MODCODLSTC, 0xcc },
  388. { STV090x_P1_MODCODLSTD, 0xcc },
  389. { STV090x_P1_MODCODLSTE, 0xcc },
  390. { STV090x_P1_MODCODLSTF, 0xcf },
  391. { STV090x_GENCFG, 0x1c },
  392. { STV090x_NBITER_NF4, 0x37 },
  393. { STV090x_NBITER_NF5, 0x29 },
  394. { STV090x_NBITER_NF6, 0x37 },
  395. { STV090x_NBITER_NF7, 0x33 },
  396. { STV090x_NBITER_NF8, 0x31 },
  397. { STV090x_NBITER_NF9, 0x2f },
  398. { STV090x_NBITER_NF10, 0x39 },
  399. { STV090x_NBITER_NF11, 0x3a },
  400. { STV090x_NBITER_NF12, 0x29 },
  401. { STV090x_NBITER_NF13, 0x37 },
  402. { STV090x_NBITER_NF14, 0x33 },
  403. { STV090x_NBITER_NF15, 0x2f },
  404. { STV090x_NBITER_NF16, 0x39 },
  405. { STV090x_NBITER_NF17, 0x3a },
  406. { STV090x_NBITERNOERR, 0x04 },
  407. { STV090x_GAINLLR_NF4, 0x0C },
  408. { STV090x_GAINLLR_NF5, 0x0F },
  409. { STV090x_GAINLLR_NF6, 0x11 },
  410. { STV090x_GAINLLR_NF7, 0x14 },
  411. { STV090x_GAINLLR_NF8, 0x17 },
  412. { STV090x_GAINLLR_NF9, 0x19 },
  413. { STV090x_GAINLLR_NF10, 0x20 },
  414. { STV090x_GAINLLR_NF11, 0x21 },
  415. { STV090x_GAINLLR_NF12, 0x0D },
  416. { STV090x_GAINLLR_NF13, 0x0F },
  417. { STV090x_GAINLLR_NF14, 0x13 },
  418. { STV090x_GAINLLR_NF15, 0x1A },
  419. { STV090x_GAINLLR_NF16, 0x1F },
  420. { STV090x_GAINLLR_NF17, 0x21 },
  421. { STV090x_RCCFGH, 0x20 },
  422. { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
  423. { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
  424. };
  425. static struct stv090x_reg stv0900_cut20_val[] = {
  426. { STV090x_P2_DMDCFG3, 0xe8 },
  427. { STV090x_P2_DMDCFG4, 0x10 },
  428. { STV090x_P2_CARFREQ, 0x38 },
  429. { STV090x_P2_CARHDR, 0x20 },
  430. { STV090x_P2_KREFTMG, 0x5a },
  431. { STV090x_P2_SMAPCOEF7, 0x06 },
  432. { STV090x_P2_SMAPCOEF6, 0x00 },
  433. { STV090x_P2_SMAPCOEF5, 0x04 },
  434. { STV090x_P2_NOSCFG, 0x0c },
  435. { STV090x_P1_DMDCFG3, 0xe8 },
  436. { STV090x_P1_DMDCFG4, 0x10 },
  437. { STV090x_P1_CARFREQ, 0x38 },
  438. { STV090x_P1_CARHDR, 0x20 },
  439. { STV090x_P1_KREFTMG, 0x5a },
  440. { STV090x_P1_SMAPCOEF7, 0x06 },
  441. { STV090x_P1_SMAPCOEF6, 0x00 },
  442. { STV090x_P1_SMAPCOEF5, 0x04 },
  443. { STV090x_P1_NOSCFG, 0x0c },
  444. { STV090x_GAINLLR_NF4, 0x21 },
  445. { STV090x_GAINLLR_NF5, 0x21 },
  446. { STV090x_GAINLLR_NF6, 0x20 },
  447. { STV090x_GAINLLR_NF7, 0x1F },
  448. { STV090x_GAINLLR_NF8, 0x1E },
  449. { STV090x_GAINLLR_NF9, 0x1E },
  450. { STV090x_GAINLLR_NF10, 0x1D },
  451. { STV090x_GAINLLR_NF11, 0x1B },
  452. { STV090x_GAINLLR_NF12, 0x20 },
  453. { STV090x_GAINLLR_NF13, 0x20 },
  454. { STV090x_GAINLLR_NF14, 0x20 },
  455. { STV090x_GAINLLR_NF15, 0x20 },
  456. { STV090x_GAINLLR_NF16, 0x20 },
  457. { STV090x_GAINLLR_NF17, 0x21 },
  458. };
  459. static struct stv090x_reg stv0903_cut20_val[] = {
  460. { STV090x_P1_DMDCFG3, 0xe8 },
  461. { STV090x_P1_DMDCFG4, 0x10 },
  462. { STV090x_P1_CARFREQ, 0x38 },
  463. { STV090x_P1_CARHDR, 0x20 },
  464. { STV090x_P1_KREFTMG, 0x5a },
  465. { STV090x_P1_SMAPCOEF7, 0x06 },
  466. { STV090x_P1_SMAPCOEF6, 0x00 },
  467. { STV090x_P1_SMAPCOEF5, 0x04 },
  468. { STV090x_P1_NOSCFG, 0x0c },
  469. { STV090x_GAINLLR_NF4, 0x21 },
  470. { STV090x_GAINLLR_NF5, 0x21 },
  471. { STV090x_GAINLLR_NF6, 0x20 },
  472. { STV090x_GAINLLR_NF7, 0x1F },
  473. { STV090x_GAINLLR_NF8, 0x1E },
  474. { STV090x_GAINLLR_NF9, 0x1E },
  475. { STV090x_GAINLLR_NF10, 0x1D },
  476. { STV090x_GAINLLR_NF11, 0x1B },
  477. { STV090x_GAINLLR_NF12, 0x20 },
  478. { STV090x_GAINLLR_NF13, 0x20 },
  479. { STV090x_GAINLLR_NF14, 0x20 },
  480. { STV090x_GAINLLR_NF15, 0x20 },
  481. { STV090x_GAINLLR_NF16, 0x20 },
  482. { STV090x_GAINLLR_NF17, 0x21 }
  483. };
  484. /* Cut 2.0 Long Frame Tracking CR loop */
  485. static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
  486. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  487. { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
  488. { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
  489. { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
  490. { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  491. { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  492. { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  493. { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  494. { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  495. { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
  496. { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
  497. { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
  498. { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
  499. { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
  500. { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
  501. };
  502. /* Cut 3.0 Long Frame Tracking CR loop */
  503. static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
  504. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  505. { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
  506. { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  507. { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  508. { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  509. { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  510. { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  511. { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  512. { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  513. { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
  514. { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
  515. { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
  516. { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
  517. { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
  518. { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
  519. };
  520. /* Cut 2.0 Long Frame Tracking CR Loop */
  521. static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
  522. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  523. { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
  524. { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
  525. { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
  526. { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
  527. { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
  528. { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
  529. { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  530. { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  531. { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  532. { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  533. { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
  534. };
  535. /* Cut 3.0 Long Frame Tracking CR Loop */
  536. static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
  537. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  538. { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
  539. { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
  540. { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
  541. { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
  542. { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
  543. { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
  544. { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  545. { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  546. { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  547. { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  548. { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
  549. };
  550. static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
  551. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  552. { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
  553. { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
  554. { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
  555. };
  556. static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
  557. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  558. { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
  559. { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
  560. { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
  561. };
  562. /* Cut 2.0 Short Frame Tracking CR Loop */
  563. static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
  564. /* MODCOD 2M 5M 10M 20M 30M */
  565. { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
  566. { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
  567. { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
  568. { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
  569. };
  570. /* Cut 3.0 Short Frame Tracking CR Loop */
  571. static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
  572. /* MODCOD 2M 5M 10M 20M 30M */
  573. { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
  574. { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
  575. { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
  576. { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
  577. };
  578. static inline s32 comp2(s32 __x, s32 __width)
  579. {
  580. if (__width == 32)
  581. return __x;
  582. else
  583. return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
  584. }
  585. static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
  586. {
  587. const struct stv090x_config *config = state->config;
  588. int ret;
  589. u8 b0[] = { reg >> 8, reg & 0xff };
  590. u8 buf;
  591. struct i2c_msg msg[] = {
  592. { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
  593. { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
  594. };
  595. ret = i2c_transfer(state->i2c, msg, 2);
  596. if (ret != 2) {
  597. if (ret != -ERESTARTSYS)
  598. dprintk(FE_ERROR, 1,
  599. "Read error, Reg=[0x%02x], Status=%d",
  600. reg, ret);
  601. return ret < 0 ? ret : -EREMOTEIO;
  602. }
  603. if (unlikely(*state->verbose >= FE_DEBUGREG))
  604. dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
  605. reg, buf);
  606. return (unsigned int) buf;
  607. }
  608. static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
  609. {
  610. const struct stv090x_config *config = state->config;
  611. int ret;
  612. u8 buf[2 + count];
  613. struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
  614. buf[0] = reg >> 8;
  615. buf[1] = reg & 0xff;
  616. memcpy(&buf[2], data, count);
  617. if (unlikely(*state->verbose >= FE_DEBUGREG)) {
  618. int i;
  619. printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
  620. for (i = 0; i < count; i++)
  621. printk(" %02x", data[i]);
  622. printk("\n");
  623. }
  624. ret = i2c_transfer(state->i2c, &i2c_msg, 1);
  625. if (ret != 1) {
  626. if (ret != -ERESTARTSYS)
  627. dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
  628. reg, data[0], count, ret);
  629. return ret < 0 ? ret : -EREMOTEIO;
  630. }
  631. return 0;
  632. }
  633. static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
  634. {
  635. return stv090x_write_regs(state, reg, &data, 1);
  636. }
  637. static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  638. {
  639. struct stv090x_state *state = fe->demodulator_priv;
  640. u32 reg;
  641. reg = STV090x_READ_DEMOD(state, I2CRPT);
  642. if (enable) {
  643. dprintk(FE_DEBUG, 1, "Enable Gate");
  644. STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
  645. if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
  646. goto err;
  647. } else {
  648. dprintk(FE_DEBUG, 1, "Disable Gate");
  649. STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
  650. if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
  651. goto err;
  652. }
  653. return 0;
  654. err:
  655. dprintk(FE_ERROR, 1, "I/O error");
  656. return -1;
  657. }
  658. static void stv090x_get_lock_tmg(struct stv090x_state *state)
  659. {
  660. switch (state->algo) {
  661. case STV090x_BLIND_SEARCH:
  662. dprintk(FE_DEBUG, 1, "Blind Search");
  663. if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
  664. state->DemodTimeout = 1500;
  665. state->FecTimeout = 400;
  666. } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
  667. state->DemodTimeout = 1000;
  668. state->FecTimeout = 300;
  669. } else { /*SR >20Msps*/
  670. state->DemodTimeout = 700;
  671. state->FecTimeout = 100;
  672. }
  673. break;
  674. case STV090x_COLD_SEARCH:
  675. case STV090x_WARM_SEARCH:
  676. default:
  677. dprintk(FE_DEBUG, 1, "Normal Search");
  678. if (state->srate <= 1000000) { /*SR <=1Msps*/
  679. state->DemodTimeout = 4500;
  680. state->FecTimeout = 1700;
  681. } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
  682. state->DemodTimeout = 2500;
  683. state->FecTimeout = 1100;
  684. } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
  685. state->DemodTimeout = 1000;
  686. state->FecTimeout = 550;
  687. } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
  688. state->DemodTimeout = 700;
  689. state->FecTimeout = 250;
  690. } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
  691. state->DemodTimeout = 400;
  692. state->FecTimeout = 130;
  693. } else { /*SR >20Msps*/
  694. state->DemodTimeout = 300;
  695. state->FecTimeout = 100;
  696. }
  697. break;
  698. }
  699. if (state->algo == STV090x_WARM_SEARCH)
  700. state->DemodTimeout /= 2;
  701. }
  702. static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
  703. {
  704. u32 sym;
  705. if (srate > 60000000) {
  706. sym = (srate << 4); /* SR * 2^16 / master_clk */
  707. sym /= (state->mclk >> 12);
  708. } else if (srate > 6000000) {
  709. sym = (srate << 6);
  710. sym /= (state->mclk >> 10);
  711. } else {
  712. sym = (srate << 9);
  713. sym /= (state->mclk >> 7);
  714. }
  715. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
  716. goto err;
  717. if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
  718. goto err;
  719. return 0;
  720. err:
  721. dprintk(FE_ERROR, 1, "I/O error");
  722. return -1;
  723. }
  724. static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
  725. {
  726. u32 sym;
  727. srate = 105 * (srate / 100);
  728. if (srate > 60000000) {
  729. sym = (srate << 4); /* SR * 2^16 / master_clk */
  730. sym /= (state->mclk >> 12);
  731. } else if (srate > 6000000) {
  732. sym = (srate << 6);
  733. sym /= (state->mclk >> 10);
  734. } else {
  735. sym = (srate << 9);
  736. sym /= (state->mclk >> 7);
  737. }
  738. if (sym < 0x7fff) {
  739. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
  740. goto err;
  741. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
  742. goto err;
  743. } else {
  744. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
  745. goto err;
  746. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
  747. goto err;
  748. }
  749. return 0;
  750. err:
  751. dprintk(FE_ERROR, 1, "I/O error");
  752. return -1;
  753. }
  754. static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
  755. {
  756. u32 sym;
  757. srate = 95 * (srate / 100);
  758. if (srate > 60000000) {
  759. sym = (srate << 4); /* SR * 2^16 / master_clk */
  760. sym /= (state->mclk >> 12);
  761. } else if (srate > 6000000) {
  762. sym = (srate << 6);
  763. sym /= (state->mclk >> 10);
  764. } else {
  765. sym = (srate << 9);
  766. sym /= (state->mclk >> 7);
  767. }
  768. if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
  769. goto err;
  770. if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
  771. goto err;
  772. return 0;
  773. err:
  774. dprintk(FE_ERROR, 1, "I/O error");
  775. return -1;
  776. }
  777. static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
  778. {
  779. u32 ro;
  780. switch (rolloff) {
  781. case STV090x_RO_20:
  782. ro = 20;
  783. break;
  784. case STV090x_RO_25:
  785. ro = 25;
  786. break;
  787. case STV090x_RO_35:
  788. default:
  789. ro = 35;
  790. break;
  791. }
  792. return srate + (srate * ro) / 100;
  793. }
  794. static int stv090x_set_vit_thacq(struct stv090x_state *state)
  795. {
  796. if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
  797. goto err;
  798. if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
  799. goto err;
  800. if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
  801. goto err;
  802. if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
  803. goto err;
  804. if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
  805. goto err;
  806. if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
  807. goto err;
  808. return 0;
  809. err:
  810. dprintk(FE_ERROR, 1, "I/O error");
  811. return -1;
  812. }
  813. static int stv090x_set_vit_thtracq(struct stv090x_state *state)
  814. {
  815. if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
  816. goto err;
  817. if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
  818. goto err;
  819. if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
  820. goto err;
  821. if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
  822. goto err;
  823. if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
  824. goto err;
  825. if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
  826. goto err;
  827. return 0;
  828. err:
  829. dprintk(FE_ERROR, 1, "I/O error");
  830. return -1;
  831. }
  832. static int stv090x_set_viterbi(struct stv090x_state *state)
  833. {
  834. switch (state->search_mode) {
  835. case STV090x_SEARCH_AUTO:
  836. if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
  837. goto err;
  838. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
  839. goto err;
  840. break;
  841. case STV090x_SEARCH_DVBS1:
  842. if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
  843. goto err;
  844. switch (state->fec) {
  845. case STV090x_PR12:
  846. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
  847. goto err;
  848. break;
  849. case STV090x_PR23:
  850. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
  851. goto err;
  852. break;
  853. case STV090x_PR34:
  854. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
  855. goto err;
  856. break;
  857. case STV090x_PR56:
  858. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
  859. goto err;
  860. break;
  861. case STV090x_PR78:
  862. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
  863. goto err;
  864. break;
  865. default:
  866. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
  867. goto err;
  868. break;
  869. }
  870. break;
  871. case STV090x_SEARCH_DSS:
  872. if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
  873. goto err;
  874. switch (state->fec) {
  875. case STV090x_PR12:
  876. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
  877. goto err;
  878. break;
  879. case STV090x_PR23:
  880. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
  881. goto err;
  882. break;
  883. case STV090x_PR67:
  884. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
  885. goto err;
  886. break;
  887. default:
  888. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
  889. goto err;
  890. break;
  891. }
  892. break;
  893. default:
  894. break;
  895. }
  896. return 0;
  897. err:
  898. dprintk(FE_ERROR, 1, "I/O error");
  899. return -1;
  900. }
  901. static int stv090x_stop_modcod(struct stv090x_state *state)
  902. {
  903. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  904. goto err;
  905. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
  906. goto err;
  907. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
  908. goto err;
  909. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
  910. goto err;
  911. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
  912. goto err;
  913. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
  914. goto err;
  915. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
  916. goto err;
  917. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
  918. goto err;
  919. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
  920. goto err;
  921. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
  922. goto err;
  923. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
  924. goto err;
  925. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
  926. goto err;
  927. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
  928. goto err;
  929. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
  930. goto err;
  931. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
  932. goto err;
  933. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
  934. goto err;
  935. return 0;
  936. err:
  937. dprintk(FE_ERROR, 1, "I/O error");
  938. return -1;
  939. }
  940. static int stv090x_activate_modcod(struct stv090x_state *state)
  941. {
  942. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  943. goto err;
  944. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
  945. goto err;
  946. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
  947. goto err;
  948. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
  949. goto err;
  950. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
  951. goto err;
  952. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
  953. goto err;
  954. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
  955. goto err;
  956. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
  957. goto err;
  958. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
  959. goto err;
  960. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
  961. goto err;
  962. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
  963. goto err;
  964. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
  965. goto err;
  966. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
  967. goto err;
  968. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
  969. goto err;
  970. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
  971. goto err;
  972. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
  973. goto err;
  974. return 0;
  975. err:
  976. dprintk(FE_ERROR, 1, "I/O error");
  977. return -1;
  978. }
  979. static int stv090x_activate_modcod_single(struct stv090x_state *state)
  980. {
  981. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  982. goto err;
  983. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
  984. goto err;
  985. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
  986. goto err;
  987. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
  988. goto err;
  989. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
  990. goto err;
  991. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
  992. goto err;
  993. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
  994. goto err;
  995. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
  996. goto err;
  997. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
  998. goto err;
  999. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
  1000. goto err;
  1001. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
  1002. goto err;
  1003. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
  1004. goto err;
  1005. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
  1006. goto err;
  1007. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
  1008. goto err;
  1009. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
  1010. goto err;
  1011. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
  1012. goto err;
  1013. return 0;
  1014. err:
  1015. dprintk(FE_ERROR, 1, "I/O error");
  1016. return -1;
  1017. }
  1018. static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
  1019. {
  1020. u32 reg;
  1021. switch (state->demod) {
  1022. case STV090x_DEMODULATOR_0:
  1023. mutex_lock(&demod_lock);
  1024. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  1025. STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
  1026. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  1027. goto err;
  1028. mutex_unlock(&demod_lock);
  1029. break;
  1030. case STV090x_DEMODULATOR_1:
  1031. mutex_lock(&demod_lock);
  1032. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  1033. STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
  1034. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  1035. goto err;
  1036. mutex_unlock(&demod_lock);
  1037. break;
  1038. default:
  1039. dprintk(FE_ERROR, 1, "Wrong demodulator!");
  1040. break;
  1041. }
  1042. return 0;
  1043. err:
  1044. mutex_unlock(&demod_lock);
  1045. dprintk(FE_ERROR, 1, "I/O error");
  1046. return -1;
  1047. }
  1048. static int stv090x_dvbs_track_crl(struct stv090x_state *state)
  1049. {
  1050. if (state->dev_ver >= 0x30) {
  1051. /* Set ACLC BCLC optimised value vs SR */
  1052. if (state->srate >= 15000000) {
  1053. if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
  1054. goto err;
  1055. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
  1056. goto err;
  1057. } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
  1058. if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
  1059. goto err;
  1060. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
  1061. goto err;
  1062. } else if (state->srate < 7000000) {
  1063. if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
  1064. goto err;
  1065. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
  1066. goto err;
  1067. }
  1068. } else {
  1069. /* Cut 2.0 */
  1070. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
  1071. goto err;
  1072. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  1073. goto err;
  1074. }
  1075. return 0;
  1076. err:
  1077. dprintk(FE_ERROR, 1, "I/O error");
  1078. return -1;
  1079. }
  1080. static int stv090x_delivery_search(struct stv090x_state *state)
  1081. {
  1082. u32 reg;
  1083. switch (state->search_mode) {
  1084. case STV090x_SEARCH_DVBS1:
  1085. case STV090x_SEARCH_DSS:
  1086. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1087. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1088. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1089. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1090. goto err;
  1091. /* Activate Viterbi decoder in legacy search,
  1092. * do not use FRESVIT1, might impact VITERBI2
  1093. */
  1094. if (stv090x_vitclk_ctl(state, 0) < 0)
  1095. goto err;
  1096. if (stv090x_dvbs_track_crl(state) < 0)
  1097. goto err;
  1098. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
  1099. goto err;
  1100. if (stv090x_set_vit_thacq(state) < 0)
  1101. goto err;
  1102. if (stv090x_set_viterbi(state) < 0)
  1103. goto err;
  1104. break;
  1105. case STV090x_SEARCH_DVBS2:
  1106. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1107. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  1108. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1109. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1110. goto err;
  1111. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1112. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1113. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1114. goto err;
  1115. if (stv090x_vitclk_ctl(state, 1) < 0)
  1116. goto err;
  1117. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
  1118. goto err;
  1119. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  1120. goto err;
  1121. if (state->dev_ver <= 0x20) {
  1122. /* enable S2 carrier loop */
  1123. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
  1124. goto err;
  1125. } else {
  1126. /* > Cut 3: Stop carrier 3 */
  1127. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
  1128. goto err;
  1129. }
  1130. if (state->demod_mode != STV090x_SINGLE) {
  1131. /* Cut 2: enable link during search */
  1132. if (stv090x_activate_modcod(state) < 0)
  1133. goto err;
  1134. } else {
  1135. /* Single demodulator
  1136. * Authorize SHORT and LONG frames,
  1137. * QPSK, 8PSK, 16APSK and 32APSK
  1138. */
  1139. if (stv090x_activate_modcod_single(state) < 0)
  1140. goto err;
  1141. }
  1142. if (stv090x_set_vit_thtracq(state) < 0)
  1143. goto err;
  1144. break;
  1145. case STV090x_SEARCH_AUTO:
  1146. default:
  1147. /* enable DVB-S2 and DVB-S2 in Auto MODE */
  1148. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1149. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1150. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1151. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1152. goto err;
  1153. if (stv090x_vitclk_ctl(state, 0) < 0)
  1154. goto err;
  1155. if (stv090x_dvbs_track_crl(state) < 0)
  1156. goto err;
  1157. if (state->dev_ver <= 0x20) {
  1158. /* enable S2 carrier loop */
  1159. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
  1160. goto err;
  1161. } else {
  1162. /* > Cut 3: Stop carrier 3 */
  1163. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
  1164. goto err;
  1165. }
  1166. if (state->demod_mode != STV090x_SINGLE) {
  1167. /* Cut 2: enable link during search */
  1168. if (stv090x_activate_modcod(state) < 0)
  1169. goto err;
  1170. } else {
  1171. /* Single demodulator
  1172. * Authorize SHORT and LONG frames,
  1173. * QPSK, 8PSK, 16APSK and 32APSK
  1174. */
  1175. if (stv090x_activate_modcod_single(state) < 0)
  1176. goto err;
  1177. }
  1178. if (stv090x_set_vit_thacq(state) < 0)
  1179. goto err;
  1180. if (stv090x_set_viterbi(state) < 0)
  1181. goto err;
  1182. break;
  1183. }
  1184. return 0;
  1185. err:
  1186. dprintk(FE_ERROR, 1, "I/O error");
  1187. return -1;
  1188. }
  1189. static int stv090x_start_search(struct stv090x_state *state)
  1190. {
  1191. u32 reg, freq_abs;
  1192. s16 freq;
  1193. /* Reset demodulator */
  1194. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1195. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
  1196. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1197. goto err;
  1198. if (state->dev_ver <= 0x20) {
  1199. if (state->srate <= 5000000) {
  1200. if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
  1201. goto err;
  1202. if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
  1203. goto err;
  1204. if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
  1205. goto err;
  1206. if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
  1207. goto err;
  1208. if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
  1209. goto err;
  1210. /*enlarge the timing bandwith for Low SR*/
  1211. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
  1212. goto err;
  1213. } else {
  1214. /* If the symbol rate is >5 Msps
  1215. Set The carrier search up and low to auto mode */
  1216. if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
  1217. goto err;
  1218. /*reduce the timing bandwith for high SR*/
  1219. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
  1220. goto err;
  1221. }
  1222. } else {
  1223. /* >= Cut 3 */
  1224. if (state->srate <= 5000000) {
  1225. /* enlarge the timing bandwith for Low SR */
  1226. STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
  1227. } else {
  1228. /* reduce timing bandwith for high SR */
  1229. STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
  1230. }
  1231. /* Set CFR min and max to manual mode */
  1232. STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
  1233. if (state->algo == STV090x_WARM_SEARCH) {
  1234. /* WARM Start
  1235. * CFR min = -1MHz,
  1236. * CFR max = +1MHz
  1237. */
  1238. freq_abs = 1000 << 16;
  1239. freq_abs /= (state->mclk / 1000);
  1240. freq = (s16) freq_abs;
  1241. } else {
  1242. /* COLD Start
  1243. * CFR min =- (SearchRange / 2 + 600KHz)
  1244. * CFR max = +(SearchRange / 2 + 600KHz)
  1245. * (600KHz for the tuner step size)
  1246. */
  1247. freq_abs = (state->search_range / 2000) + 600;
  1248. freq_abs = freq_abs << 16;
  1249. freq_abs /= (state->mclk / 1000);
  1250. freq = (s16) freq_abs;
  1251. }
  1252. if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
  1253. goto err;
  1254. if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
  1255. goto err;
  1256. freq *= -1;
  1257. if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
  1258. goto err;
  1259. if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
  1260. goto err;
  1261. }
  1262. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
  1263. goto err;
  1264. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
  1265. goto err;
  1266. if (state->dev_ver >= 0x20) {
  1267. if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
  1268. goto err;
  1269. if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
  1270. goto err;
  1271. if ((state->search_mode == STV090x_DVBS1) ||
  1272. (state->search_mode == STV090x_DSS) ||
  1273. (state->search_mode == STV090x_SEARCH_AUTO)) {
  1274. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
  1275. goto err;
  1276. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
  1277. goto err;
  1278. }
  1279. }
  1280. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
  1281. goto err;
  1282. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
  1283. goto err;
  1284. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
  1285. goto err;
  1286. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1287. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
  1288. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1289. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1290. goto err;
  1291. reg = STV090x_READ_DEMOD(state, DMDCFG2);
  1292. STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
  1293. if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
  1294. goto err;
  1295. if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
  1296. goto err;
  1297. if (state->dev_ver >= 0x20) {
  1298. /*Frequency offset detector setting*/
  1299. if (state->srate < 2000000) {
  1300. if (state->dev_ver <= 0x20) {
  1301. /* Cut 2 */
  1302. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
  1303. goto err;
  1304. } else {
  1305. /* Cut 3 */
  1306. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
  1307. goto err;
  1308. }
  1309. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
  1310. goto err;
  1311. } else if (state->srate < 10000000) {
  1312. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
  1313. goto err;
  1314. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
  1315. goto err;
  1316. } else {
  1317. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
  1318. goto err;
  1319. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
  1320. goto err;
  1321. }
  1322. } else {
  1323. if (state->srate < 10000000) {
  1324. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
  1325. goto err;
  1326. } else {
  1327. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
  1328. goto err;
  1329. }
  1330. }
  1331. switch (state->algo) {
  1332. case STV090x_WARM_SEARCH:
  1333. /* The symbol rate and the exact
  1334. * carrier Frequency are known
  1335. */
  1336. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1337. goto err;
  1338. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  1339. goto err;
  1340. break;
  1341. case STV090x_COLD_SEARCH:
  1342. /* The symbol rate is known */
  1343. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1344. goto err;
  1345. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1346. goto err;
  1347. break;
  1348. default:
  1349. break;
  1350. }
  1351. return 0;
  1352. err:
  1353. dprintk(FE_ERROR, 1, "I/O error");
  1354. return -1;
  1355. }
  1356. static int stv090x_get_agc2_min_level(struct stv090x_state *state)
  1357. {
  1358. u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
  1359. s32 i, j, steps, dir;
  1360. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1361. goto err;
  1362. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1363. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
  1364. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1365. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1366. goto err;
  1367. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
  1368. goto err;
  1369. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
  1370. goto err;
  1371. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
  1372. goto err;
  1373. if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
  1374. goto err;
  1375. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
  1376. goto err;
  1377. if (stv090x_set_srate(state, 1000000) < 0)
  1378. goto err;
  1379. steps = state->search_range / 1000000;
  1380. if (steps <= 0)
  1381. steps = 1;
  1382. dir = 1;
  1383. freq_step = (1000000 * 256) / (state->mclk / 256);
  1384. freq_init = 0;
  1385. for (i = 0; i < steps; i++) {
  1386. if (dir > 0)
  1387. freq_init = freq_init + (freq_step * i);
  1388. else
  1389. freq_init = freq_init - (freq_step * i);
  1390. dir *= -1;
  1391. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
  1392. goto err;
  1393. if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
  1394. goto err;
  1395. if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
  1396. goto err;
  1397. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
  1398. goto err;
  1399. msleep(10);
  1400. agc2 = 0;
  1401. for (j = 0; j < 10; j++) {
  1402. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1403. STV090x_READ_DEMOD(state, AGC2I0);
  1404. }
  1405. agc2 /= 10;
  1406. if (agc2 < agc2_min)
  1407. agc2_min = agc2;
  1408. }
  1409. return agc2_min;
  1410. err:
  1411. dprintk(FE_ERROR, 1, "I/O error");
  1412. return -1;
  1413. }
  1414. static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
  1415. {
  1416. u8 r3, r2, r1, r0;
  1417. s32 srate, int_1, int_2, tmp_1, tmp_2;
  1418. r3 = STV090x_READ_DEMOD(state, SFR3);
  1419. r2 = STV090x_READ_DEMOD(state, SFR2);
  1420. r1 = STV090x_READ_DEMOD(state, SFR1);
  1421. r0 = STV090x_READ_DEMOD(state, SFR0);
  1422. srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
  1423. int_1 = clk >> 16;
  1424. int_2 = srate >> 16;
  1425. tmp_1 = clk % 0x10000;
  1426. tmp_2 = srate % 0x10000;
  1427. srate = (int_1 * int_2) +
  1428. ((int_1 * tmp_2) >> 16) +
  1429. ((int_2 * tmp_1) >> 16);
  1430. return srate;
  1431. }
  1432. static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
  1433. {
  1434. struct dvb_frontend *fe = &state->frontend;
  1435. int tmg_lock = 0, i;
  1436. s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
  1437. u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
  1438. u32 agc2th;
  1439. if (state->dev_ver >= 0x30)
  1440. agc2th = 0x2e00;
  1441. else
  1442. agc2th = 0x1f00;
  1443. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1444. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
  1445. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1446. goto err;
  1447. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
  1448. goto err;
  1449. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
  1450. goto err;
  1451. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
  1452. goto err;
  1453. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
  1454. goto err;
  1455. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1456. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
  1457. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1458. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1459. goto err;
  1460. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
  1461. goto err;
  1462. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
  1463. goto err;
  1464. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
  1465. goto err;
  1466. if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
  1467. goto err;
  1468. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
  1469. goto err;
  1470. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
  1471. goto err;
  1472. if (state->dev_ver >= 0x30) {
  1473. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
  1474. goto err;
  1475. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
  1476. goto err;
  1477. } else if (state->dev_ver >= 0x20) {
  1478. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
  1479. goto err;
  1480. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
  1481. goto err;
  1482. }
  1483. if (state->srate <= 2000000)
  1484. car_step = 1000;
  1485. else if (state->srate <= 5000000)
  1486. car_step = 2000;
  1487. else if (state->srate <= 12000000)
  1488. car_step = 3000;
  1489. else
  1490. car_step = 5000;
  1491. steps = -1 + ((state->search_range / 1000) / car_step);
  1492. steps /= 2;
  1493. steps = (2 * steps) + 1;
  1494. if (steps < 0)
  1495. steps = 1;
  1496. else if (steps > 10) {
  1497. steps = 11;
  1498. car_step = (state->search_range / 1000) / 10;
  1499. }
  1500. cur_step = 0;
  1501. dir = 1;
  1502. freq = state->frequency;
  1503. while ((!tmg_lock) && (cur_step < steps)) {
  1504. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
  1505. goto err;
  1506. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
  1507. goto err;
  1508. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1509. goto err;
  1510. if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
  1511. goto err;
  1512. if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
  1513. goto err;
  1514. /* trigger acquisition */
  1515. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
  1516. goto err;
  1517. msleep(50);
  1518. for (i = 0; i < 10; i++) {
  1519. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1520. if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
  1521. tmg_cpt++;
  1522. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1523. STV090x_READ_DEMOD(state, AGC2I0);
  1524. }
  1525. agc2 /= 10;
  1526. srate_coarse = stv090x_get_srate(state, state->mclk);
  1527. cur_step++;
  1528. dir *= -1;
  1529. if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
  1530. (srate_coarse < 50000000) && (srate_coarse > 850000))
  1531. tmg_lock = 1;
  1532. else if (cur_step < steps) {
  1533. if (dir > 0)
  1534. freq += cur_step * car_step;
  1535. else
  1536. freq -= cur_step * car_step;
  1537. /* Setup tuner */
  1538. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1539. goto err;
  1540. if (state->config->tuner_set_frequency) {
  1541. if (state->config->tuner_set_frequency(fe, freq) < 0)
  1542. goto err;
  1543. }
  1544. if (state->config->tuner_set_bandwidth) {
  1545. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  1546. goto err;
  1547. }
  1548. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1549. goto err;
  1550. msleep(50);
  1551. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1552. goto err;
  1553. if (state->config->tuner_get_status) {
  1554. if (state->config->tuner_get_status(fe, &reg) < 0)
  1555. goto err;
  1556. }
  1557. if (reg)
  1558. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  1559. else
  1560. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  1561. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1562. goto err;
  1563. }
  1564. }
  1565. if (!tmg_lock)
  1566. srate_coarse = 0;
  1567. else
  1568. srate_coarse = stv090x_get_srate(state, state->mclk);
  1569. return srate_coarse;
  1570. err:
  1571. dprintk(FE_ERROR, 1, "I/O error");
  1572. return -1;
  1573. }
  1574. static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
  1575. {
  1576. u32 srate_coarse, freq_coarse, sym, reg;
  1577. srate_coarse = stv090x_get_srate(state, state->mclk);
  1578. freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
  1579. freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
  1580. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1581. if (sym < state->srate)
  1582. srate_coarse = 0;
  1583. else {
  1584. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
  1585. goto err;
  1586. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
  1587. goto err;
  1588. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
  1589. goto err;
  1590. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
  1591. goto err;
  1592. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
  1593. goto err;
  1594. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1595. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
  1596. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1597. goto err;
  1598. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1599. goto err;
  1600. if (state->dev_ver >= 0x30) {
  1601. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
  1602. goto err;
  1603. } else if (state->dev_ver >= 0x20) {
  1604. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  1605. goto err;
  1606. }
  1607. if (srate_coarse > 3000000) {
  1608. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1609. sym = (sym / 1000) * 65536;
  1610. sym /= (state->mclk / 1000);
  1611. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
  1612. goto err;
  1613. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
  1614. goto err;
  1615. sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
  1616. sym = (sym / 1000) * 65536;
  1617. sym /= (state->mclk / 1000);
  1618. if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
  1619. goto err;
  1620. if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
  1621. goto err;
  1622. sym = (srate_coarse / 1000) * 65536;
  1623. sym /= (state->mclk / 1000);
  1624. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
  1625. goto err;
  1626. if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
  1627. goto err;
  1628. } else {
  1629. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1630. sym = (sym / 100) * 65536;
  1631. sym /= (state->mclk / 100);
  1632. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
  1633. goto err;
  1634. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
  1635. goto err;
  1636. sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
  1637. sym = (sym / 100) * 65536;
  1638. sym /= (state->mclk / 100);
  1639. if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
  1640. goto err;
  1641. if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
  1642. goto err;
  1643. sym = (srate_coarse / 100) * 65536;
  1644. sym /= (state->mclk / 100);
  1645. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
  1646. goto err;
  1647. if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
  1648. goto err;
  1649. }
  1650. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
  1651. goto err;
  1652. if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
  1653. goto err;
  1654. if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
  1655. goto err;
  1656. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
  1657. goto err;
  1658. }
  1659. return srate_coarse;
  1660. err:
  1661. dprintk(FE_ERROR, 1, "I/O error");
  1662. return -1;
  1663. }
  1664. static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
  1665. {
  1666. s32 timer = 0, lock = 0;
  1667. u32 reg;
  1668. u8 stat;
  1669. while ((timer < timeout) && (!lock)) {
  1670. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  1671. stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  1672. switch (stat) {
  1673. case 0: /* searching */
  1674. case 1: /* first PLH detected */
  1675. default:
  1676. dprintk(FE_DEBUG, 1, "Demodulator searching ..");
  1677. lock = 0;
  1678. break;
  1679. case 2: /* DVB-S2 mode */
  1680. case 3: /* DVB-S1/legacy mode */
  1681. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1682. lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  1683. break;
  1684. }
  1685. if (!lock)
  1686. msleep(10);
  1687. else
  1688. dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
  1689. timer += 10;
  1690. }
  1691. return lock;
  1692. }
  1693. static int stv090x_blind_search(struct stv090x_state *state)
  1694. {
  1695. u32 agc2, reg, srate_coarse;
  1696. s32 cpt_fail, agc2_ovflw, i;
  1697. u8 k_ref, k_max, k_min;
  1698. int coarse_fail, lock;
  1699. k_max = 110;
  1700. k_min = 10;
  1701. agc2 = stv090x_get_agc2_min_level(state);
  1702. if (agc2 > STV090x_SEARCH_AGC2_TH(state->dev_ver)) {
  1703. lock = 0;
  1704. } else {
  1705. if (state->dev_ver <= 0x20) {
  1706. if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
  1707. goto err;
  1708. } else {
  1709. /* > Cut 3 */
  1710. if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
  1711. goto err;
  1712. }
  1713. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
  1714. goto err;
  1715. if (state->dev_ver >= 0x20) {
  1716. if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
  1717. goto err;
  1718. if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
  1719. goto err;
  1720. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
  1721. goto err;
  1722. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
  1723. goto err;
  1724. }
  1725. k_ref = k_max;
  1726. do {
  1727. if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
  1728. goto err;
  1729. if (stv090x_srate_srch_coarse(state) != 0) {
  1730. srate_coarse = stv090x_srate_srch_fine(state);
  1731. if (srate_coarse != 0) {
  1732. stv090x_get_lock_tmg(state);
  1733. lock = stv090x_get_dmdlock(state,
  1734. state->DemodTimeout);
  1735. } else {
  1736. lock = 0;
  1737. }
  1738. } else {
  1739. cpt_fail = 0;
  1740. agc2_ovflw = 0;
  1741. for (i = 0; i < 10; i++) {
  1742. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1743. STV090x_READ_DEMOD(state, AGC2I0);
  1744. if (agc2 >= 0xff00)
  1745. agc2_ovflw++;
  1746. reg = STV090x_READ_DEMOD(state, DSTATUS2);
  1747. if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
  1748. (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
  1749. cpt_fail++;
  1750. }
  1751. if ((cpt_fail > 7) || (agc2_ovflw > 7))
  1752. coarse_fail = 1;
  1753. lock = 0;
  1754. }
  1755. k_ref -= 20;
  1756. } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
  1757. }
  1758. return lock;
  1759. err:
  1760. dprintk(FE_ERROR, 1, "I/O error");
  1761. return -1;
  1762. }
  1763. static int stv090x_chk_tmg(struct stv090x_state *state)
  1764. {
  1765. u32 reg;
  1766. s32 tmg_cpt = 0, i;
  1767. u8 freq, tmg_thh, tmg_thl;
  1768. int tmg_lock;
  1769. freq = STV090x_READ_DEMOD(state, CARFREQ);
  1770. tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
  1771. tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
  1772. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
  1773. goto err;
  1774. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
  1775. goto err;
  1776. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1777. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
  1778. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1779. goto err;
  1780. if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
  1781. goto err;
  1782. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
  1783. goto err;
  1784. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
  1785. goto err;
  1786. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
  1787. goto err;
  1788. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1789. goto err;
  1790. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
  1791. goto err;
  1792. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
  1793. goto err;
  1794. msleep(10);
  1795. for (i = 0; i < 10; i++) {
  1796. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1797. if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
  1798. tmg_cpt++;
  1799. msleep(1);
  1800. }
  1801. if (tmg_cpt >= 3)
  1802. tmg_lock = 1;
  1803. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1804. goto err;
  1805. if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
  1806. goto err;
  1807. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
  1808. goto err;
  1809. if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
  1810. goto err;
  1811. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
  1812. goto err;
  1813. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
  1814. goto err;
  1815. return tmg_lock;
  1816. err:
  1817. dprintk(FE_ERROR, 1, "I/O error");
  1818. return -1;
  1819. }
  1820. static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
  1821. {
  1822. struct dvb_frontend *fe = &state->frontend;
  1823. u32 reg;
  1824. s32 car_step, steps, cur_step, dir, freq, timeout_lock;
  1825. int lock = 0;
  1826. if (state->srate >= 10000000)
  1827. timeout_lock = timeout_dmd / 3;
  1828. else
  1829. timeout_lock = timeout_dmd / 2;
  1830. lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
  1831. if (!lock) {
  1832. if (state->srate >= 10000000) {
  1833. if (stv090x_chk_tmg(state)) {
  1834. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1835. goto err;
  1836. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1837. goto err;
  1838. lock = stv090x_get_dmdlock(state, timeout_dmd);
  1839. } else {
  1840. lock = 0;
  1841. }
  1842. } else {
  1843. if (state->srate <= 4000000)
  1844. car_step = 1000;
  1845. else if (state->srate <= 7000000)
  1846. car_step = 2000;
  1847. else if (state->srate <= 10000000)
  1848. car_step = 3000;
  1849. else
  1850. car_step = 5000;
  1851. steps = (state->search_range / 1000) / car_step;
  1852. steps /= 2;
  1853. steps = 2 * (steps + 1);
  1854. if (steps < 0)
  1855. steps = 2;
  1856. else if (steps > 12)
  1857. steps = 12;
  1858. cur_step = 1;
  1859. dir = 1;
  1860. if (!lock) {
  1861. freq = state->frequency;
  1862. state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
  1863. while ((cur_step <= steps) && (!lock)) {
  1864. if (dir > 0)
  1865. freq += cur_step * car_step;
  1866. else
  1867. freq -= cur_step * car_step;
  1868. /* Setup tuner */
  1869. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1870. goto err;
  1871. if (state->config->tuner_set_frequency) {
  1872. if (state->config->tuner_set_frequency(fe, freq) < 0)
  1873. goto err;
  1874. }
  1875. if (state->config->tuner_set_bandwidth) {
  1876. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  1877. goto err;
  1878. }
  1879. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1880. goto err;
  1881. msleep(50);
  1882. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1883. goto err;
  1884. if (state->config->tuner_get_status) {
  1885. if (state->config->tuner_get_status(fe, &reg) < 0)
  1886. goto err;
  1887. }
  1888. if (reg)
  1889. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  1890. else
  1891. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  1892. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1893. goto err;
  1894. STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
  1895. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
  1896. goto err;
  1897. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1898. goto err;
  1899. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1900. goto err;
  1901. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1902. goto err;
  1903. lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
  1904. dir *= -1;
  1905. cur_step++;
  1906. }
  1907. }
  1908. }
  1909. }
  1910. return lock;
  1911. err:
  1912. dprintk(FE_ERROR, 1, "I/O error");
  1913. return -1;
  1914. }
  1915. static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
  1916. {
  1917. s32 timeout, inc, steps_max, srate, car_max;
  1918. srate = state->srate;
  1919. car_max = state->search_range / 1000;
  1920. car_max += car_max / 10;
  1921. car_max = 65536 * (car_max / 2);
  1922. car_max /= (state->mclk / 1000);
  1923. if (car_max > 0x4000)
  1924. car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
  1925. inc = srate;
  1926. inc /= state->mclk / 1000;
  1927. inc *= 256;
  1928. inc *= 256;
  1929. inc /= 1000;
  1930. switch (state->search_mode) {
  1931. case STV090x_SEARCH_DVBS1:
  1932. case STV090x_SEARCH_DSS:
  1933. inc *= 3; /* freq step = 3% of srate */
  1934. timeout = 20;
  1935. break;
  1936. case STV090x_SEARCH_DVBS2:
  1937. inc *= 4;
  1938. timeout = 25;
  1939. break;
  1940. case STV090x_SEARCH_AUTO:
  1941. default:
  1942. inc *= 3;
  1943. timeout = 25;
  1944. break;
  1945. }
  1946. inc /= 100;
  1947. if ((inc > car_max) || (inc < 0))
  1948. inc = car_max / 2; /* increment <= 1/8 Mclk */
  1949. timeout *= 27500; /* 27.5 Msps reference */
  1950. if (srate > 0)
  1951. timeout /= (srate / 1000);
  1952. if ((timeout > 100) || (timeout < 0))
  1953. timeout = 100;
  1954. steps_max = (car_max / inc) + 1; /* min steps = 3 */
  1955. if ((steps_max > 100) || (steps_max < 0)) {
  1956. steps_max = 100; /* max steps <= 100 */
  1957. inc = car_max / steps_max;
  1958. }
  1959. *freq_inc = inc;
  1960. *timeout_sw = timeout;
  1961. *steps = steps_max;
  1962. return 0;
  1963. }
  1964. static int stv090x_chk_signal(struct stv090x_state *state)
  1965. {
  1966. s32 offst_car, agc2, car_max;
  1967. int no_signal;
  1968. offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
  1969. offst_car |= STV090x_READ_DEMOD(state, CFR1);
  1970. offst_car = comp2(offst_car, 16);
  1971. agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
  1972. agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
  1973. car_max = state->search_range / 1000;
  1974. car_max += (car_max / 10); /* 10% margin */
  1975. car_max = (65536 * car_max / 2);
  1976. car_max /= state->mclk / 1000;
  1977. if (car_max > 0x4000)
  1978. car_max = 0x4000;
  1979. if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
  1980. no_signal = 1;
  1981. dprintk(FE_DEBUG, 1, "No Signal");
  1982. } else {
  1983. no_signal = 0;
  1984. dprintk(FE_DEBUG, 1, "Found Signal");
  1985. }
  1986. return no_signal;
  1987. }
  1988. static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
  1989. {
  1990. int no_signal, lock = 0;
  1991. s32 cpt_step = 0, offst_freq, car_max;
  1992. u32 reg;
  1993. car_max = state->search_range / 1000;
  1994. car_max += (car_max / 10);
  1995. car_max = (65536 * car_max / 2);
  1996. car_max /= (state->mclk / 1000);
  1997. if (car_max > 0x4000)
  1998. car_max = 0x4000;
  1999. if (zigzag)
  2000. offst_freq = 0;
  2001. else
  2002. offst_freq = -car_max + inc;
  2003. do {
  2004. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
  2005. goto err;
  2006. if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
  2007. goto err;
  2008. if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
  2009. goto err;
  2010. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2011. goto err;
  2012. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  2013. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
  2014. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  2015. goto err;
  2016. if (zigzag) {
  2017. if (offst_freq >= 0)
  2018. offst_freq = -offst_freq - 2 * inc;
  2019. else
  2020. offst_freq = -offst_freq;
  2021. } else {
  2022. offst_freq += 2 * inc;
  2023. }
  2024. cpt_step++;
  2025. lock = stv090x_get_dmdlock(state, timeout);
  2026. no_signal = stv090x_chk_signal(state);
  2027. } while ((!lock) &&
  2028. (!no_signal) &&
  2029. ((offst_freq - inc) < car_max) &&
  2030. ((offst_freq + inc) > -car_max) &&
  2031. (cpt_step < steps_max));
  2032. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  2033. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
  2034. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  2035. goto err;
  2036. return lock;
  2037. err:
  2038. dprintk(FE_ERROR, 1, "I/O error");
  2039. return -1;
  2040. }
  2041. static int stv090x_sw_algo(struct stv090x_state *state)
  2042. {
  2043. int no_signal, zigzag, lock = 0;
  2044. u32 reg;
  2045. s32 dvbs2_fly_wheel;
  2046. s32 inc, timeout_step, trials, steps_max;
  2047. /* get params */
  2048. stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
  2049. switch (state->search_mode) {
  2050. case STV090x_SEARCH_DVBS1:
  2051. case STV090x_SEARCH_DSS:
  2052. /* accelerate the frequency detector */
  2053. if (state->dev_ver >= 0x20) {
  2054. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
  2055. goto err;
  2056. }
  2057. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
  2058. goto err;
  2059. zigzag = 0;
  2060. break;
  2061. case STV090x_SEARCH_DVBS2:
  2062. if (state->dev_ver >= 0x20) {
  2063. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2064. goto err;
  2065. }
  2066. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
  2067. goto err;
  2068. zigzag = 1;
  2069. break;
  2070. case STV090x_SEARCH_AUTO:
  2071. default:
  2072. /* accelerate the frequency detector */
  2073. if (state->dev_ver >= 0x20) {
  2074. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
  2075. goto err;
  2076. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2077. goto err;
  2078. }
  2079. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
  2080. goto err;
  2081. zigzag = 0;
  2082. break;
  2083. }
  2084. trials = 0;
  2085. do {
  2086. lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
  2087. no_signal = stv090x_chk_signal(state);
  2088. trials++;
  2089. /*run the SW search 2 times maximum*/
  2090. if (lock || no_signal || (trials == 2)) {
  2091. /*Check if the demod is not losing lock in DVBS2*/
  2092. if (state->dev_ver >= 0x20) {
  2093. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  2094. goto err;
  2095. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
  2096. goto err;
  2097. }
  2098. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2099. if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
  2100. /*Check if the demod is not losing lock in DVBS2*/
  2101. msleep(timeout_step);
  2102. reg = STV090x_READ_DEMOD(state, DMDFLYW);
  2103. dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
  2104. if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
  2105. msleep(timeout_step);
  2106. reg = STV090x_READ_DEMOD(state, DMDFLYW);
  2107. dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
  2108. }
  2109. if (dvbs2_fly_wheel < 0xd) {
  2110. /*FALSE lock, The demod is loosing lock */
  2111. lock = 0;
  2112. if (trials < 2) {
  2113. if (state->dev_ver >= 0x20) {
  2114. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2115. goto err;
  2116. }
  2117. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
  2118. goto err;
  2119. }
  2120. }
  2121. }
  2122. }
  2123. } while ((!lock) && (trials < 2) && (!no_signal));
  2124. return lock;
  2125. err:
  2126. dprintk(FE_ERROR, 1, "I/O error");
  2127. return -1;
  2128. }
  2129. static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
  2130. {
  2131. u32 reg;
  2132. enum stv090x_delsys delsys;
  2133. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2134. if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
  2135. delsys = STV090x_DVBS2;
  2136. else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
  2137. reg = STV090x_READ_DEMOD(state, FECM);
  2138. if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
  2139. delsys = STV090x_DSS;
  2140. else
  2141. delsys = STV090x_DVBS1;
  2142. } else {
  2143. delsys = STV090x_ERROR;
  2144. }
  2145. return delsys;
  2146. }
  2147. /* in Hz */
  2148. static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
  2149. {
  2150. s32 derot, int_1, int_2, tmp_1, tmp_2;
  2151. derot = STV090x_READ_DEMOD(state, CFR2) << 16;
  2152. derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
  2153. derot |= STV090x_READ_DEMOD(state, CFR0);
  2154. derot = comp2(derot, 24);
  2155. int_1 = state->mclk >> 12;
  2156. int_2 = derot >> 12;
  2157. /* carrier_frequency = MasterClock * Reg / 2^24 */
  2158. tmp_1 = state->mclk % 0x1000;
  2159. tmp_2 = derot % 0x1000;
  2160. derot = (int_1 * int_2) +
  2161. ((int_1 * tmp_2) >> 12) +
  2162. ((int_2 * tmp_1) >> 12);
  2163. return derot;
  2164. }
  2165. static int stv090x_get_viterbi(struct stv090x_state *state)
  2166. {
  2167. u32 reg, rate;
  2168. reg = STV090x_READ_DEMOD(state, VITCURPUN);
  2169. rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
  2170. switch (rate) {
  2171. case 13:
  2172. state->fec = STV090x_PR12;
  2173. break;
  2174. case 18:
  2175. state->fec = STV090x_PR23;
  2176. break;
  2177. case 21:
  2178. state->fec = STV090x_PR34;
  2179. break;
  2180. case 24:
  2181. state->fec = STV090x_PR56;
  2182. break;
  2183. case 25:
  2184. state->fec = STV090x_PR67;
  2185. break;
  2186. case 26:
  2187. state->fec = STV090x_PR78;
  2188. break;
  2189. default:
  2190. state->fec = STV090x_PRERR;
  2191. break;
  2192. }
  2193. return 0;
  2194. }
  2195. static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
  2196. {
  2197. struct dvb_frontend *fe = &state->frontend;
  2198. u8 tmg;
  2199. u32 reg;
  2200. s32 i = 0, offst_freq;
  2201. msleep(5);
  2202. if (state->algo == STV090x_BLIND_SEARCH) {
  2203. tmg = STV090x_READ_DEMOD(state, TMGREG2);
  2204. STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
  2205. while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
  2206. tmg = STV090x_READ_DEMOD(state, TMGREG2);
  2207. msleep(5);
  2208. i += 5;
  2209. }
  2210. }
  2211. state->delsys = stv090x_get_std(state);
  2212. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2213. goto err;
  2214. if (state->config->tuner_get_frequency) {
  2215. if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
  2216. goto err;
  2217. }
  2218. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2219. goto err;
  2220. offst_freq = stv090x_get_car_freq(state, state->mclk) / 1000;
  2221. state->frequency += offst_freq;
  2222. if (stv090x_get_viterbi(state) < 0)
  2223. goto err;
  2224. reg = STV090x_READ_DEMOD(state, DMDMODCOD);
  2225. state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
  2226. state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
  2227. state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
  2228. reg = STV090x_READ_DEMOD(state, TMGOBS);
  2229. state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
  2230. reg = STV090x_READ_DEMOD(state, FECM);
  2231. state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
  2232. if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
  2233. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2234. goto err;
  2235. if (state->config->tuner_get_frequency) {
  2236. if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
  2237. goto err;
  2238. }
  2239. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2240. goto err;
  2241. if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
  2242. return STV090x_RANGEOK;
  2243. else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
  2244. return STV090x_RANGEOK;
  2245. else
  2246. return STV090x_OUTOFRANGE; /* Out of Range */
  2247. } else {
  2248. if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
  2249. return STV090x_RANGEOK;
  2250. else
  2251. return STV090x_OUTOFRANGE;
  2252. }
  2253. return STV090x_OUTOFRANGE;
  2254. err:
  2255. dprintk(FE_ERROR, 1, "I/O error");
  2256. return -1;
  2257. }
  2258. static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
  2259. {
  2260. s32 offst_tmg;
  2261. offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
  2262. offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
  2263. offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
  2264. offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
  2265. if (!offst_tmg)
  2266. offst_tmg = 1;
  2267. offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
  2268. offst_tmg /= 320;
  2269. return offst_tmg;
  2270. }
  2271. static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
  2272. {
  2273. u8 aclc = 0x29;
  2274. s32 i;
  2275. struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
  2276. if (state->dev_ver == 0x20) {
  2277. car_loop = stv090x_s2_crl_cut20;
  2278. car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
  2279. car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
  2280. } else {
  2281. /* >= Cut 3 */
  2282. car_loop = stv090x_s2_crl_cut30;
  2283. car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
  2284. car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
  2285. }
  2286. if (modcod < STV090x_QPSK_12) {
  2287. i = 0;
  2288. while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
  2289. i++;
  2290. if (i >= 3)
  2291. i = 2;
  2292. } else {
  2293. i = 0;
  2294. while ((i < 14) && (modcod != car_loop[i].modcod))
  2295. i++;
  2296. if (i >= 14) {
  2297. i = 0;
  2298. while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
  2299. i++;
  2300. if (i >= 11)
  2301. i = 10;
  2302. }
  2303. }
  2304. if (modcod <= STV090x_QPSK_25) {
  2305. if (pilots) {
  2306. if (state->srate <= 3000000)
  2307. aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
  2308. else if (state->srate <= 7000000)
  2309. aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
  2310. else if (state->srate <= 15000000)
  2311. aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
  2312. else if (state->srate <= 25000000)
  2313. aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
  2314. else
  2315. aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
  2316. } else {
  2317. if (state->srate <= 3000000)
  2318. aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
  2319. else if (state->srate <= 7000000)
  2320. aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
  2321. else if (state->srate <= 15000000)
  2322. aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
  2323. else if (state->srate <= 25000000)
  2324. aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
  2325. else
  2326. aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
  2327. }
  2328. } else if (modcod <= STV090x_8PSK_910) {
  2329. if (pilots) {
  2330. if (state->srate <= 3000000)
  2331. aclc = car_loop[i].crl_pilots_on_2;
  2332. else if (state->srate <= 7000000)
  2333. aclc = car_loop[i].crl_pilots_on_5;
  2334. else if (state->srate <= 15000000)
  2335. aclc = car_loop[i].crl_pilots_on_10;
  2336. else if (state->srate <= 25000000)
  2337. aclc = car_loop[i].crl_pilots_on_20;
  2338. else
  2339. aclc = car_loop[i].crl_pilots_on_30;
  2340. } else {
  2341. if (state->srate <= 3000000)
  2342. aclc = car_loop[i].crl_pilots_off_2;
  2343. else if (state->srate <= 7000000)
  2344. aclc = car_loop[i].crl_pilots_off_5;
  2345. else if (state->srate <= 15000000)
  2346. aclc = car_loop[i].crl_pilots_off_10;
  2347. else if (state->srate <= 25000000)
  2348. aclc = car_loop[i].crl_pilots_off_20;
  2349. else
  2350. aclc = car_loop[i].crl_pilots_off_30;
  2351. }
  2352. } else { /* 16APSK and 32APSK */
  2353. if (state->srate <= 3000000)
  2354. aclc = car_loop_apsk_low[i].crl_pilots_on_2;
  2355. else if (state->srate <= 7000000)
  2356. aclc = car_loop_apsk_low[i].crl_pilots_on_5;
  2357. else if (state->srate <= 15000000)
  2358. aclc = car_loop_apsk_low[i].crl_pilots_on_10;
  2359. else if (state->srate <= 25000000)
  2360. aclc = car_loop_apsk_low[i].crl_pilots_on_20;
  2361. else
  2362. aclc = car_loop_apsk_low[i].crl_pilots_on_30;
  2363. }
  2364. return aclc;
  2365. }
  2366. static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
  2367. {
  2368. struct stv090x_short_frame_crloop *short_crl = NULL;
  2369. s32 index = 0;
  2370. u8 aclc = 0x0b;
  2371. switch (state->modulation) {
  2372. case STV090x_QPSK:
  2373. default:
  2374. index = 0;
  2375. break;
  2376. case STV090x_8PSK:
  2377. index = 1;
  2378. break;
  2379. case STV090x_16APSK:
  2380. index = 2;
  2381. break;
  2382. case STV090x_32APSK:
  2383. index = 3;
  2384. break;
  2385. }
  2386. if (state->dev_ver >= 0x30) {
  2387. /* Cut 3.0 and up */
  2388. short_crl = stv090x_s2_short_crl_cut30;
  2389. } else {
  2390. /* Cut 2.0 and up: we don't support cuts older than 2.0 */
  2391. short_crl = stv090x_s2_short_crl_cut20;
  2392. }
  2393. if (state->srate <= 3000000)
  2394. aclc = short_crl[index].crl_2;
  2395. else if (state->srate <= 7000000)
  2396. aclc = short_crl[index].crl_5;
  2397. else if (state->srate <= 15000000)
  2398. aclc = short_crl[index].crl_10;
  2399. else if (state->srate <= 25000000)
  2400. aclc = short_crl[index].crl_20;
  2401. else
  2402. aclc = short_crl[index].crl_30;
  2403. return aclc;
  2404. }
  2405. static int stv090x_optimize_track(struct stv090x_state *state)
  2406. {
  2407. struct dvb_frontend *fe = &state->frontend;
  2408. enum stv090x_rolloff rolloff;
  2409. enum stv090x_modcod modcod;
  2410. s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
  2411. u32 reg;
  2412. srate = stv090x_get_srate(state, state->mclk);
  2413. srate += stv090x_get_tmgoffst(state, srate);
  2414. switch (state->delsys) {
  2415. case STV090x_DVBS1:
  2416. case STV090x_DSS:
  2417. if (state->search_mode == STV090x_SEARCH_AUTO) {
  2418. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2419. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2420. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  2421. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2422. goto err;
  2423. }
  2424. reg = STV090x_READ_DEMOD(state, DEMOD);
  2425. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
  2426. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
  2427. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2428. goto err;
  2429. if (state->dev_ver >= 0x30) {
  2430. if (stv090x_get_viterbi(state) < 0)
  2431. goto err;
  2432. if (state->fec == STV090x_PR12) {
  2433. if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
  2434. goto err;
  2435. if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
  2436. goto err;
  2437. } else {
  2438. if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
  2439. goto err;
  2440. if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
  2441. goto err;
  2442. }
  2443. }
  2444. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
  2445. goto err;
  2446. break;
  2447. case STV090x_DVBS2:
  2448. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2449. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  2450. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  2451. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2452. goto err;
  2453. if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
  2454. goto err;
  2455. if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
  2456. goto err;
  2457. if (state->frame_len == STV090x_LONG_FRAME) {
  2458. reg = STV090x_READ_DEMOD(state, DMDMODCOD);
  2459. modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
  2460. pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
  2461. aclc = stv090x_optimize_carloop(state, modcod, pilots);
  2462. if (modcod <= STV090x_QPSK_910) {
  2463. STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
  2464. } else if (modcod <= STV090x_8PSK_910) {
  2465. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2466. goto err;
  2467. if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
  2468. goto err;
  2469. }
  2470. if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
  2471. if (modcod <= STV090x_16APSK_910) {
  2472. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2473. goto err;
  2474. if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
  2475. goto err;
  2476. } else {
  2477. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2478. goto err;
  2479. if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
  2480. goto err;
  2481. }
  2482. }
  2483. } else {
  2484. /*Carrier loop setting for short frame*/
  2485. aclc = stv090x_optimize_carloop_short(state);
  2486. if (state->modulation == STV090x_QPSK) {
  2487. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
  2488. goto err;
  2489. } else if (state->modulation == STV090x_8PSK) {
  2490. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2491. goto err;
  2492. if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
  2493. goto err;
  2494. } else if (state->modulation == STV090x_16APSK) {
  2495. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2496. goto err;
  2497. if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
  2498. goto err;
  2499. } else if (state->modulation == STV090x_32APSK) {
  2500. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2501. goto err;
  2502. if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
  2503. goto err;
  2504. }
  2505. }
  2506. STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
  2507. break;
  2508. case STV090x_UNKNOWN:
  2509. default:
  2510. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2511. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2512. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  2513. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2514. goto err;
  2515. break;
  2516. }
  2517. f_1 = STV090x_READ_DEMOD(state, CFR2);
  2518. f_0 = STV090x_READ_DEMOD(state, CFR1);
  2519. reg = STV090x_READ_DEMOD(state, TMGOBS);
  2520. rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
  2521. if (state->algo == STV090x_BLIND_SEARCH) {
  2522. STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
  2523. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2524. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
  2525. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
  2526. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2527. goto err;
  2528. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
  2529. goto err;
  2530. if (stv090x_set_srate(state, srate) < 0)
  2531. goto err;
  2532. blind_tune = 1;
  2533. if (stv090x_dvbs_track_crl(state) < 0)
  2534. goto err;
  2535. }
  2536. if (state->dev_ver >= 0x20) {
  2537. if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
  2538. (state->search_mode == STV090x_SEARCH_DSS) ||
  2539. (state->search_mode == STV090x_SEARCH_AUTO)) {
  2540. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
  2541. goto err;
  2542. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
  2543. goto err;
  2544. }
  2545. }
  2546. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  2547. goto err;
  2548. /* AUTO tracking MODE */
  2549. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
  2550. goto err;
  2551. /* AUTO tracking MODE */
  2552. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
  2553. goto err;
  2554. if ((state->dev_ver >= 0x20) || (blind_tune == 1) || (state->srate < 10000000)) {
  2555. /* update initial carrier freq with the found freq offset */
  2556. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2557. goto err;
  2558. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2559. goto err;
  2560. state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
  2561. if ((state->dev_ver >= 0x20) || (blind_tune == 1)) {
  2562. if (state->algo != STV090x_WARM_SEARCH) {
  2563. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2564. goto err;
  2565. if (state->config->tuner_set_bandwidth) {
  2566. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  2567. goto err;
  2568. }
  2569. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2570. goto err;
  2571. }
  2572. }
  2573. if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
  2574. msleep(50); /* blind search: wait 50ms for SR stabilization */
  2575. else
  2576. msleep(5);
  2577. stv090x_get_lock_tmg(state);
  2578. if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
  2579. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  2580. goto err;
  2581. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2582. goto err;
  2583. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2584. goto err;
  2585. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2586. goto err;
  2587. i = 0;
  2588. while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
  2589. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  2590. goto err;
  2591. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2592. goto err;
  2593. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2594. goto err;
  2595. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2596. goto err;
  2597. i++;
  2598. }
  2599. }
  2600. }
  2601. if (state->dev_ver >= 0x20) {
  2602. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  2603. goto err;
  2604. }
  2605. if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
  2606. stv090x_set_vit_thtracq(state);
  2607. return 0;
  2608. err:
  2609. dprintk(FE_ERROR, 1, "I/O error");
  2610. return -1;
  2611. }
  2612. static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
  2613. {
  2614. s32 timer = 0, lock = 0, stat;
  2615. u32 reg;
  2616. while ((timer < timeout) && (!lock)) {
  2617. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2618. stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  2619. switch (stat) {
  2620. case 0: /* searching */
  2621. case 1: /* first PLH detected */
  2622. default:
  2623. lock = 0;
  2624. break;
  2625. case 2: /* DVB-S2 mode */
  2626. reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
  2627. lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
  2628. break;
  2629. case 3: /* DVB-S1/legacy mode */
  2630. reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
  2631. lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
  2632. break;
  2633. }
  2634. if (!lock) {
  2635. msleep(10);
  2636. timer += 10;
  2637. }
  2638. }
  2639. return lock;
  2640. }
  2641. static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
  2642. {
  2643. u32 reg;
  2644. s32 timer = 0;
  2645. int lock;
  2646. lock = stv090x_get_dmdlock(state, timeout_dmd);
  2647. if (lock)
  2648. lock = stv090x_get_feclock(state, timeout_fec);
  2649. if (lock) {
  2650. lock = 0;
  2651. while ((timer < timeout_fec) && (!lock)) {
  2652. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  2653. lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
  2654. msleep(1);
  2655. timer++;
  2656. }
  2657. }
  2658. return lock;
  2659. }
  2660. static int stv090x_set_s2rolloff(struct stv090x_state *state)
  2661. {
  2662. u32 reg;
  2663. if (state->dev_ver <= 0x20) {
  2664. /* rolloff to auto mode if DVBS2 */
  2665. reg = STV090x_READ_DEMOD(state, DEMOD);
  2666. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
  2667. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2668. goto err;
  2669. } else {
  2670. /* DVB-S2 rolloff to auto mode if DVBS2 */
  2671. reg = STV090x_READ_DEMOD(state, DEMOD);
  2672. STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
  2673. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2674. goto err;
  2675. }
  2676. return 0;
  2677. err:
  2678. dprintk(FE_ERROR, 1, "I/O error");
  2679. return -1;
  2680. }
  2681. static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
  2682. {
  2683. struct dvb_frontend *fe = &state->frontend;
  2684. enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
  2685. u32 reg;
  2686. s32 agc1_power, power_iq = 0, i;
  2687. int lock = 0, low_sr = 0, no_signal = 0;
  2688. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2689. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
  2690. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2691. goto err;
  2692. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
  2693. goto err;
  2694. if (state->dev_ver >= 0x20) {
  2695. if (state->srate > 5000000) {
  2696. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
  2697. goto err;
  2698. } else {
  2699. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
  2700. goto err;
  2701. }
  2702. }
  2703. stv090x_get_lock_tmg(state);
  2704. if (state->algo == STV090x_BLIND_SEARCH) {
  2705. state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
  2706. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
  2707. goto err;
  2708. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
  2709. goto err;
  2710. if (stv090x_set_srate(state, 1000000) < 0) /* inital srate = 1Msps */
  2711. goto err;
  2712. } else {
  2713. /* known srate */
  2714. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
  2715. goto err;
  2716. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
  2717. goto err;
  2718. if (state->srate < 2000000) {
  2719. /* SR < 2MSPS */
  2720. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
  2721. goto err;
  2722. } else {
  2723. /* SR >= 2Msps */
  2724. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
  2725. goto err;
  2726. }
  2727. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  2728. goto err;
  2729. if (state->dev_ver >= 0x20) {
  2730. if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
  2731. goto err;
  2732. if (state->algo == STV090x_COLD_SEARCH)
  2733. state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
  2734. else if (state->algo == STV090x_WARM_SEARCH)
  2735. state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
  2736. }
  2737. /* if cold start or warm (Symbolrate is known)
  2738. * use a Narrow symbol rate scan range
  2739. */
  2740. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
  2741. goto err;
  2742. if (stv090x_set_srate(state, state->srate) < 0)
  2743. goto err;
  2744. if (stv090x_set_max_srate(state, state->mclk, state->srate) < 0)
  2745. goto err;
  2746. if (stv090x_set_min_srate(state, state->mclk, state->srate) < 0)
  2747. goto err;
  2748. if (state->srate >= 10000000)
  2749. low_sr = 0;
  2750. else
  2751. low_sr = 1;
  2752. }
  2753. /* Setup tuner */
  2754. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2755. goto err;
  2756. if (state->config->tuner_set_bbgain) {
  2757. if (state->config->tuner_set_bbgain(fe, 10) < 0) /* 10dB */
  2758. goto err;
  2759. }
  2760. if (state->config->tuner_set_frequency) {
  2761. if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
  2762. goto err;
  2763. }
  2764. if (state->config->tuner_set_bandwidth) {
  2765. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  2766. goto err;
  2767. }
  2768. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2769. goto err;
  2770. msleep(50);
  2771. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2772. goto err;
  2773. if (state->config->tuner_get_status) {
  2774. if (state->config->tuner_get_status(fe, &reg) < 0)
  2775. goto err;
  2776. }
  2777. if (reg)
  2778. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  2779. else
  2780. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  2781. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2782. goto err;
  2783. msleep(10);
  2784. agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
  2785. STV090x_READ_DEMOD(state, AGCIQIN0));
  2786. if (agc1_power == 0) {
  2787. /* If AGC1 integrator value is 0
  2788. * then read POWERI, POWERQ
  2789. */
  2790. for (i = 0; i < 5; i++) {
  2791. power_iq += (STV090x_READ_DEMOD(state, POWERI) +
  2792. STV090x_READ_DEMOD(state, POWERQ)) >> 1;
  2793. }
  2794. power_iq /= 5;
  2795. }
  2796. if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
  2797. dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
  2798. lock = 0;
  2799. signal_state = STV090x_NOAGC1;
  2800. } else {
  2801. reg = STV090x_READ_DEMOD(state, DEMOD);
  2802. STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
  2803. if (state->dev_ver <= 0x20) {
  2804. /* rolloff to auto mode if DVBS2 */
  2805. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
  2806. } else {
  2807. /* DVB-S2 rolloff to auto mode if DVBS2 */
  2808. STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
  2809. }
  2810. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2811. goto err;
  2812. if (stv090x_delivery_search(state) < 0)
  2813. goto err;
  2814. if (state->algo != STV090x_BLIND_SEARCH) {
  2815. if (stv090x_start_search(state) < 0)
  2816. goto err;
  2817. }
  2818. }
  2819. if (signal_state == STV090x_NOAGC1)
  2820. return signal_state;
  2821. if (state->algo == STV090x_BLIND_SEARCH)
  2822. lock = stv090x_blind_search(state);
  2823. else if (state->algo == STV090x_COLD_SEARCH)
  2824. lock = stv090x_get_coldlock(state, state->DemodTimeout);
  2825. else if (state->algo == STV090x_WARM_SEARCH)
  2826. lock = stv090x_get_dmdlock(state, state->DemodTimeout);
  2827. if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
  2828. if (!low_sr) {
  2829. if (stv090x_chk_tmg(state))
  2830. lock = stv090x_sw_algo(state);
  2831. }
  2832. }
  2833. if (lock)
  2834. signal_state = stv090x_get_sig_params(state);
  2835. if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
  2836. stv090x_optimize_track(state);
  2837. if (state->dev_ver >= 0x20) {
  2838. /* >= Cut 2.0 :release TS reset after
  2839. * demod lock and optimized Tracking
  2840. */
  2841. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2842. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2843. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2844. goto err;
  2845. msleep(3);
  2846. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
  2847. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2848. goto err;
  2849. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2850. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2851. goto err;
  2852. }
  2853. lock = stv090x_get_lock(state, state->FecTimeout,
  2854. state->FecTimeout);
  2855. if (lock) {
  2856. if (state->delsys == STV090x_DVBS2) {
  2857. stv090x_set_s2rolloff(state);
  2858. reg = STV090x_READ_DEMOD(state, PDELCTRL2);
  2859. STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
  2860. if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
  2861. goto err;
  2862. /* Reset DVBS2 packet delinator error counter */
  2863. reg = STV090x_READ_DEMOD(state, PDELCTRL2);
  2864. STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
  2865. if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
  2866. goto err;
  2867. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
  2868. goto err;
  2869. } else {
  2870. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
  2871. goto err;
  2872. }
  2873. /* Reset the Total packet counter */
  2874. if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
  2875. goto err;
  2876. /* Reset the packet Error counter2 */
  2877. if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
  2878. goto err;
  2879. } else {
  2880. signal_state = STV090x_NODATA;
  2881. no_signal = stv090x_chk_signal(state);
  2882. }
  2883. }
  2884. return signal_state;
  2885. err:
  2886. dprintk(FE_ERROR, 1, "I/O error");
  2887. return -1;
  2888. }
  2889. static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
  2890. {
  2891. struct stv090x_state *state = fe->demodulator_priv;
  2892. struct dtv_frontend_properties *props = &fe->dtv_property_cache;
  2893. state->delsys = props->delivery_system;
  2894. state->frequency = p->frequency;
  2895. state->srate = p->u.qpsk.symbol_rate;
  2896. state->search_mode = STV090x_SEARCH_AUTO;
  2897. state->algo = STV090x_COLD_SEARCH;
  2898. state->fec = STV090x_PRERR;
  2899. if (state->srate > 10000000) {
  2900. dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
  2901. state->search_range = 10000000;
  2902. } else {
  2903. dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
  2904. state->search_range = 5000000;
  2905. }
  2906. if (stv090x_algo(state) == STV090x_RANGEOK) {
  2907. dprintk(FE_DEBUG, 1, "Search success!");
  2908. return DVBFE_ALGO_SEARCH_SUCCESS;
  2909. } else {
  2910. dprintk(FE_DEBUG, 1, "Search failed!");
  2911. return DVBFE_ALGO_SEARCH_FAILED;
  2912. }
  2913. return DVBFE_ALGO_SEARCH_ERROR;
  2914. }
  2915. static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
  2916. {
  2917. struct stv090x_state *state = fe->demodulator_priv;
  2918. u32 reg;
  2919. u8 search_state;
  2920. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2921. search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  2922. switch (search_state) {
  2923. case 0: /* searching */
  2924. case 1: /* first PLH detected */
  2925. default:
  2926. dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
  2927. *status = 0;
  2928. break;
  2929. case 2: /* DVB-S2 mode */
  2930. dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
  2931. reg = STV090x_READ_DEMOD(state, DSTATUS);
  2932. if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
  2933. reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
  2934. if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
  2935. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  2936. if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
  2937. *status = FE_HAS_CARRIER |
  2938. FE_HAS_VITERBI |
  2939. FE_HAS_SYNC |
  2940. FE_HAS_LOCK;
  2941. }
  2942. }
  2943. }
  2944. break;
  2945. case 3: /* DVB-S1/legacy mode */
  2946. dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
  2947. reg = STV090x_READ_DEMOD(state, DSTATUS);
  2948. if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
  2949. reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
  2950. if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
  2951. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  2952. if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
  2953. *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
  2954. }
  2955. }
  2956. }
  2957. break;
  2958. }
  2959. return 0;
  2960. }
  2961. static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
  2962. {
  2963. struct stv090x_state *state = fe->demodulator_priv;
  2964. s32 count_4, count_3, count_2, count_1, count_0, count;
  2965. u32 reg, h, m, l;
  2966. enum fe_status status;
  2967. stv090x_read_status(fe, &status);
  2968. if (!(status & FE_HAS_LOCK)) {
  2969. *per = 1 << 23; /* Max PER */
  2970. } else {
  2971. /* Counter 2 */
  2972. reg = STV090x_READ_DEMOD(state, ERRCNT22);
  2973. h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
  2974. reg = STV090x_READ_DEMOD(state, ERRCNT21);
  2975. m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
  2976. reg = STV090x_READ_DEMOD(state, ERRCNT20);
  2977. l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
  2978. *per = ((h << 16) | (m << 8) | l);
  2979. count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
  2980. count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
  2981. count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
  2982. count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
  2983. count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
  2984. if ((!count_4) && (!count_3)) {
  2985. count = (count_2 & 0xff) << 16;
  2986. count |= (count_1 & 0xff) << 8;
  2987. count |= count_0 & 0xff;
  2988. } else {
  2989. count = 1 << 24;
  2990. }
  2991. if (count == 0)
  2992. *per = 1;
  2993. }
  2994. if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
  2995. goto err;
  2996. if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
  2997. goto err;
  2998. return 0;
  2999. err:
  3000. dprintk(FE_ERROR, 1, "I/O error");
  3001. return -1;
  3002. }
  3003. static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
  3004. {
  3005. int res = 0;
  3006. int min = 0, med;
  3007. if ((val >= tab[min].read && val < tab[max].read) ||
  3008. (val >= tab[max].read && val < tab[min].read)) {
  3009. while ((max - min) > 1) {
  3010. med = (max + min) / 2;
  3011. if ((val >= tab[min].read && val < tab[med].read) ||
  3012. (val >= tab[med].read && val < tab[min].read))
  3013. max = med;
  3014. else
  3015. min = med;
  3016. }
  3017. res = ((val - tab[min].read) *
  3018. (tab[max].real - tab[min].real) /
  3019. (tab[max].read - tab[min].read)) +
  3020. tab[min].real;
  3021. } else {
  3022. if (tab[min].read < tab[max].read) {
  3023. if (val < tab[min].read)
  3024. res = tab[min].real;
  3025. else if (val >= tab[max].read)
  3026. res = tab[max].real;
  3027. } else {
  3028. if (val >= tab[min].read)
  3029. res = tab[min].real;
  3030. else if (val < tab[max].read)
  3031. res = tab[max].real;
  3032. }
  3033. }
  3034. return res;
  3035. }
  3036. static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
  3037. {
  3038. struct stv090x_state *state = fe->demodulator_priv;
  3039. u32 reg;
  3040. s32 agc_0, agc_1, agc;
  3041. s32 str;
  3042. reg = STV090x_READ_DEMOD(state, AGCIQIN1);
  3043. agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
  3044. reg = STV090x_READ_DEMOD(state, AGCIQIN0);
  3045. agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
  3046. agc = MAKEWORD16(agc_1, agc_0);
  3047. str = stv090x_table_lookup(stv090x_rf_tab,
  3048. ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
  3049. if (agc > stv090x_rf_tab[0].read)
  3050. str = 0;
  3051. else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
  3052. str = -100;
  3053. *strength = (str + 100) * 0xFFFF / 100;
  3054. return 0;
  3055. }
  3056. static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
  3057. {
  3058. struct stv090x_state *state = fe->demodulator_priv;
  3059. u32 reg_0, reg_1, reg, i;
  3060. s32 val_0, val_1, val = 0;
  3061. u8 lock_f;
  3062. s32 div;
  3063. u32 last;
  3064. switch (state->delsys) {
  3065. case STV090x_DVBS2:
  3066. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3067. lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  3068. if (lock_f) {
  3069. msleep(5);
  3070. for (i = 0; i < 16; i++) {
  3071. reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
  3072. val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
  3073. reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
  3074. val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
  3075. val += MAKEWORD16(val_1, val_0);
  3076. msleep(1);
  3077. }
  3078. val /= 16;
  3079. last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
  3080. div = stv090x_s2cn_tab[0].read -
  3081. stv090x_s2cn_tab[last].read;
  3082. *cnr = 0xFFFF - ((val * 0xFFFF) / div);
  3083. }
  3084. break;
  3085. case STV090x_DVBS1:
  3086. case STV090x_DSS:
  3087. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3088. lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  3089. if (lock_f) {
  3090. msleep(5);
  3091. for (i = 0; i < 16; i++) {
  3092. reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
  3093. val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
  3094. reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
  3095. val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
  3096. val += MAKEWORD16(val_1, val_0);
  3097. msleep(1);
  3098. }
  3099. val /= 16;
  3100. last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
  3101. div = stv090x_s1cn_tab[0].read -
  3102. stv090x_s1cn_tab[last].read;
  3103. *cnr = 0xFFFF - ((val * 0xFFFF) / div);
  3104. }
  3105. break;
  3106. default:
  3107. break;
  3108. }
  3109. return 0;
  3110. }
  3111. static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
  3112. {
  3113. struct stv090x_state *state = fe->demodulator_priv;
  3114. u32 reg;
  3115. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3116. switch (tone) {
  3117. case SEC_TONE_ON:
  3118. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
  3119. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3120. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3121. goto err;
  3122. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3123. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3124. goto err;
  3125. break;
  3126. case SEC_TONE_OFF:
  3127. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
  3128. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3129. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3130. goto err;
  3131. break;
  3132. default:
  3133. return -EINVAL;
  3134. }
  3135. return 0;
  3136. err:
  3137. dprintk(FE_ERROR, 1, "I/O error");
  3138. return -1;
  3139. }
  3140. static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
  3141. {
  3142. return DVBFE_ALGO_CUSTOM;
  3143. }
  3144. static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
  3145. {
  3146. struct stv090x_state *state = fe->demodulator_priv;
  3147. u32 reg, idle = 0, fifo_full = 1;
  3148. int i;
  3149. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3150. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
  3151. (state->config->diseqc_envelope_mode) ? 4 : 2);
  3152. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3153. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3154. goto err;
  3155. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3156. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3157. goto err;
  3158. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
  3159. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3160. goto err;
  3161. for (i = 0; i < cmd->msg_len; i++) {
  3162. while (fifo_full) {
  3163. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3164. fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
  3165. }
  3166. if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
  3167. goto err;
  3168. }
  3169. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3170. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
  3171. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3172. goto err;
  3173. i = 0;
  3174. while ((!idle) && (i < 10)) {
  3175. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3176. idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
  3177. msleep(10);
  3178. i++;
  3179. }
  3180. return 0;
  3181. err:
  3182. dprintk(FE_ERROR, 1, "I/O error");
  3183. return -1;
  3184. }
  3185. static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
  3186. {
  3187. struct stv090x_state *state = fe->demodulator_priv;
  3188. u32 reg, idle = 0, fifo_full = 1;
  3189. u8 mode, value;
  3190. int i;
  3191. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3192. if (burst == SEC_MINI_A) {
  3193. mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
  3194. value = 0x00;
  3195. } else {
  3196. mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
  3197. value = 0xFF;
  3198. }
  3199. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
  3200. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3201. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3202. goto err;
  3203. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3204. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3205. goto err;
  3206. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
  3207. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3208. goto err;
  3209. while (fifo_full) {
  3210. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3211. fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
  3212. }
  3213. if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
  3214. goto err;
  3215. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3216. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
  3217. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3218. goto err;
  3219. i = 0;
  3220. while ((!idle) && (i < 10)) {
  3221. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3222. idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
  3223. msleep(10);
  3224. i++;
  3225. }
  3226. return 0;
  3227. err:
  3228. dprintk(FE_ERROR, 1, "I/O error");
  3229. return -1;
  3230. }
  3231. static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
  3232. {
  3233. struct stv090x_state *state = fe->demodulator_priv;
  3234. u32 reg = 0, i = 0, rx_end = 0;
  3235. while ((rx_end != 1) && (i < 10)) {
  3236. msleep(10);
  3237. i++;
  3238. reg = STV090x_READ_DEMOD(state, DISRX_ST0);
  3239. rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
  3240. }
  3241. if (rx_end) {
  3242. reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
  3243. for (i = 0; i < reply->msg_len; i++)
  3244. reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
  3245. }
  3246. return 0;
  3247. }
  3248. static int stv090x_sleep(struct dvb_frontend *fe)
  3249. {
  3250. struct stv090x_state *state = fe->demodulator_priv;
  3251. u32 reg;
  3252. dprintk(FE_DEBUG, 1, "Set %s to sleep",
  3253. state->device == STV0900 ? "STV0900" : "STV0903");
  3254. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3255. STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
  3256. if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
  3257. goto err;
  3258. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3259. STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
  3260. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3261. goto err;
  3262. return 0;
  3263. err:
  3264. dprintk(FE_ERROR, 1, "I/O error");
  3265. return -1;
  3266. }
  3267. static int stv090x_wakeup(struct dvb_frontend *fe)
  3268. {
  3269. struct stv090x_state *state = fe->demodulator_priv;
  3270. u32 reg;
  3271. dprintk(FE_DEBUG, 1, "Wake %s from standby",
  3272. state->device == STV0900 ? "STV0900" : "STV0903");
  3273. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3274. STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
  3275. if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
  3276. goto err;
  3277. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3278. STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
  3279. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3280. goto err;
  3281. return 0;
  3282. err:
  3283. dprintk(FE_ERROR, 1, "I/O error");
  3284. return -1;
  3285. }
  3286. static void stv090x_release(struct dvb_frontend *fe)
  3287. {
  3288. struct stv090x_state *state = fe->demodulator_priv;
  3289. kfree(state);
  3290. }
  3291. static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
  3292. {
  3293. u32 reg = 0;
  3294. reg = stv090x_read_reg(state, STV090x_GENCFG);
  3295. switch (ldpc_mode) {
  3296. case STV090x_DUAL:
  3297. default:
  3298. if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
  3299. /* set LDPC to dual mode */
  3300. if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
  3301. goto err;
  3302. state->demod_mode = STV090x_DUAL;
  3303. reg = stv090x_read_reg(state, STV090x_TSTRES0);
  3304. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
  3305. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3306. goto err;
  3307. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
  3308. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3309. goto err;
  3310. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  3311. goto err;
  3312. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
  3313. goto err;
  3314. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
  3315. goto err;
  3316. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
  3317. goto err;
  3318. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
  3319. goto err;
  3320. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
  3321. goto err;
  3322. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
  3323. goto err;
  3324. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
  3325. goto err;
  3326. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
  3327. goto err;
  3328. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
  3329. goto err;
  3330. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
  3331. goto err;
  3332. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
  3333. goto err;
  3334. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
  3335. goto err;
  3336. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
  3337. goto err;
  3338. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
  3339. goto err;
  3340. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
  3341. goto err;
  3342. }
  3343. break;
  3344. case STV090x_SINGLE:
  3345. if (stv090x_stop_modcod(state) < 0)
  3346. goto err;
  3347. if (stv090x_activate_modcod_single(state) < 0)
  3348. goto err;
  3349. if (state->demod == STV090x_DEMODULATOR_1) {
  3350. if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
  3351. goto err;
  3352. } else {
  3353. if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
  3354. goto err;
  3355. }
  3356. reg = stv090x_read_reg(state, STV090x_TSTRES0);
  3357. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
  3358. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3359. goto err;
  3360. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
  3361. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3362. goto err;
  3363. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  3364. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
  3365. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3366. goto err;
  3367. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
  3368. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3369. goto err;
  3370. break;
  3371. }
  3372. return 0;
  3373. err:
  3374. dprintk(FE_ERROR, 1, "I/O error");
  3375. return -1;
  3376. }
  3377. /* return (Hz), clk in Hz*/
  3378. static u32 stv090x_get_mclk(struct stv090x_state *state)
  3379. {
  3380. const struct stv090x_config *config = state->config;
  3381. u32 div, reg;
  3382. u8 ratio;
  3383. div = stv090x_read_reg(state, STV090x_NCOARSE);
  3384. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3385. ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
  3386. return (div + 1) * config->xtal / ratio; /* kHz */
  3387. }
  3388. static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
  3389. {
  3390. const struct stv090x_config *config = state->config;
  3391. u32 reg, div, clk_sel;
  3392. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3393. clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
  3394. div = ((clk_sel * mclk) / config->xtal) - 1;
  3395. reg = stv090x_read_reg(state, STV090x_NCOARSE);
  3396. STV090x_SETFIELD(reg, M_DIV_FIELD, div);
  3397. if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
  3398. goto err;
  3399. state->mclk = stv090x_get_mclk(state);
  3400. /*Set the DiseqC frequency to 22KHz */
  3401. div = state->mclk / 704000;
  3402. if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
  3403. goto err;
  3404. if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
  3405. goto err;
  3406. return 0;
  3407. err:
  3408. dprintk(FE_ERROR, 1, "I/O error");
  3409. return -1;
  3410. }
  3411. static int stv090x_set_tspath(struct stv090x_state *state)
  3412. {
  3413. u32 reg;
  3414. if (state->dev_ver >= 0x20) {
  3415. switch (state->config->ts1_mode) {
  3416. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3417. case STV090x_TSMODE_DVBCI:
  3418. switch (state->config->ts2_mode) {
  3419. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3420. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3421. default:
  3422. stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
  3423. break;
  3424. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3425. case STV090x_TSMODE_DVBCI:
  3426. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
  3427. goto err;
  3428. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3429. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3430. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3431. goto err;
  3432. reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
  3433. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3434. if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
  3435. goto err;
  3436. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
  3437. goto err;
  3438. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
  3439. goto err;
  3440. break;
  3441. }
  3442. break;
  3443. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3444. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3445. default:
  3446. switch (state->config->ts2_mode) {
  3447. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3448. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3449. default:
  3450. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
  3451. goto err;
  3452. break;
  3453. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3454. case STV090x_TSMODE_DVBCI:
  3455. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
  3456. goto err;
  3457. break;
  3458. }
  3459. break;
  3460. }
  3461. } else {
  3462. switch (state->config->ts1_mode) {
  3463. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3464. case STV090x_TSMODE_DVBCI:
  3465. switch (state->config->ts2_mode) {
  3466. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3467. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3468. default:
  3469. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
  3470. break;
  3471. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3472. case STV090x_TSMODE_DVBCI:
  3473. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
  3474. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3475. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3476. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3477. goto err;
  3478. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3479. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
  3480. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3481. goto err;
  3482. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
  3483. goto err;
  3484. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
  3485. goto err;
  3486. break;
  3487. }
  3488. break;
  3489. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3490. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3491. default:
  3492. switch (state->config->ts2_mode) {
  3493. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3494. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3495. default:
  3496. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
  3497. break;
  3498. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3499. case STV090x_TSMODE_DVBCI:
  3500. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
  3501. break;
  3502. }
  3503. break;
  3504. }
  3505. }
  3506. switch (state->config->ts1_mode) {
  3507. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3508. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3509. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3510. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3511. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3512. goto err;
  3513. break;
  3514. case STV090x_TSMODE_DVBCI:
  3515. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3516. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3517. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3518. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3519. goto err;
  3520. break;
  3521. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3522. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3523. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3524. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3525. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3526. goto err;
  3527. break;
  3528. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3529. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3530. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3531. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3532. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3533. goto err;
  3534. break;
  3535. default:
  3536. break;
  3537. }
  3538. switch (state->config->ts2_mode) {
  3539. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3540. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3541. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3542. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3543. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3544. goto err;
  3545. break;
  3546. case STV090x_TSMODE_DVBCI:
  3547. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3548. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3549. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3550. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3551. goto err;
  3552. break;
  3553. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3554. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3555. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3556. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3557. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3558. goto err;
  3559. break;
  3560. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3561. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3562. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3563. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3564. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3565. goto err;
  3566. break;
  3567. default:
  3568. break;
  3569. }
  3570. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3571. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  3572. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3573. goto err;
  3574. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  3575. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3576. goto err;
  3577. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3578. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  3579. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3580. goto err;
  3581. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  3582. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3583. goto err;
  3584. return 0;
  3585. err:
  3586. dprintk(FE_ERROR, 1, "I/O error");
  3587. return -1;
  3588. }
  3589. static int stv090x_init(struct dvb_frontend *fe)
  3590. {
  3591. struct stv090x_state *state = fe->demodulator_priv;
  3592. const struct stv090x_config *config = state->config;
  3593. u32 reg;
  3594. if (stv090x_wakeup(fe) < 0) {
  3595. dprintk(FE_ERROR, 1, "Error waking device");
  3596. goto err;
  3597. }
  3598. if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
  3599. goto err;
  3600. reg = STV090x_READ_DEMOD(state, TNRCFG2);
  3601. STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
  3602. if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
  3603. goto err;
  3604. reg = STV090x_READ_DEMOD(state, DEMOD);
  3605. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
  3606. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  3607. goto err;
  3608. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  3609. goto err;
  3610. if (config->tuner_set_mode) {
  3611. if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
  3612. goto err;
  3613. }
  3614. if (config->tuner_init) {
  3615. if (config->tuner_init(fe) < 0)
  3616. goto err;
  3617. }
  3618. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  3619. goto err;
  3620. if (stv090x_set_tspath(state) < 0)
  3621. goto err;
  3622. return 0;
  3623. err:
  3624. dprintk(FE_ERROR, 1, "I/O error");
  3625. return -1;
  3626. }
  3627. static int stv090x_setup(struct dvb_frontend *fe)
  3628. {
  3629. struct stv090x_state *state = fe->demodulator_priv;
  3630. const struct stv090x_config *config = state->config;
  3631. const struct stv090x_reg *stv090x_initval = NULL;
  3632. const struct stv090x_reg *stv090x_cut20_val = NULL;
  3633. unsigned long t1_size = 0, t2_size = 0;
  3634. u32 reg = 0;
  3635. int i;
  3636. if (state->device == STV0900) {
  3637. dprintk(FE_DEBUG, 1, "Initializing STV0900");
  3638. stv090x_initval = stv0900_initval;
  3639. t1_size = ARRAY_SIZE(stv0900_initval);
  3640. stv090x_cut20_val = stv0900_cut20_val;
  3641. t2_size = ARRAY_SIZE(stv0900_cut20_val);
  3642. } else if (state->device == STV0903) {
  3643. dprintk(FE_DEBUG, 1, "Initializing STV0903");
  3644. stv090x_initval = stv0903_initval;
  3645. t1_size = ARRAY_SIZE(stv0903_initval);
  3646. stv090x_cut20_val = stv0903_cut20_val;
  3647. t2_size = ARRAY_SIZE(stv0903_cut20_val);
  3648. }
  3649. /* STV090x init */
  3650. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Stop Demod */
  3651. goto err;
  3652. msleep(5);
  3653. if (STV090x_WRITE_DEMOD(state, TNRCFG, 0x6c) < 0) /* check register ! (No Tuner Mode) */
  3654. goto err;
  3655. STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
  3656. if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) /* repeater OFF */
  3657. goto err;
  3658. if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
  3659. goto err;
  3660. msleep(5);
  3661. if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
  3662. goto err;
  3663. if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
  3664. goto err;
  3665. msleep(5);
  3666. /* write initval */
  3667. dprintk(FE_DEBUG, 1, "Setting up initial values");
  3668. for (i = 0; i < t1_size; i++) {
  3669. if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
  3670. goto err;
  3671. }
  3672. state->dev_ver = stv090x_read_reg(state, STV090x_MID);
  3673. if (state->dev_ver >= 0x20) {
  3674. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
  3675. goto err;
  3676. /* write cut20_val*/
  3677. dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
  3678. for (i = 0; i < t2_size; i++) {
  3679. if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
  3680. goto err;
  3681. }
  3682. } else if (state->dev_ver < 0x20) {
  3683. dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
  3684. state->dev_ver);
  3685. goto err;
  3686. } else if (state->dev_ver > 0x30) {
  3687. /* we shouldn't bail out from here */
  3688. dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
  3689. state->dev_ver);
  3690. }
  3691. if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
  3692. goto err;
  3693. if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
  3694. goto err;
  3695. stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
  3696. msleep(5);
  3697. if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0)
  3698. goto err;
  3699. stv090x_get_mclk(state);
  3700. return 0;
  3701. err:
  3702. dprintk(FE_ERROR, 1, "I/O error");
  3703. return -1;
  3704. }
  3705. static struct dvb_frontend_ops stv090x_ops = {
  3706. .info = {
  3707. .name = "STV090x Multistandard",
  3708. .type = FE_QPSK,
  3709. .frequency_min = 950000,
  3710. .frequency_max = 2150000,
  3711. .frequency_stepsize = 0,
  3712. .frequency_tolerance = 0,
  3713. .symbol_rate_min = 1000000,
  3714. .symbol_rate_max = 45000000,
  3715. .caps = FE_CAN_INVERSION_AUTO |
  3716. FE_CAN_FEC_AUTO |
  3717. FE_CAN_QPSK |
  3718. FE_CAN_2G_MODULATION
  3719. },
  3720. .release = stv090x_release,
  3721. .init = stv090x_init,
  3722. .sleep = stv090x_sleep,
  3723. .get_frontend_algo = stv090x_frontend_algo,
  3724. .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
  3725. .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
  3726. .diseqc_send_burst = stv090x_send_diseqc_burst,
  3727. .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
  3728. .set_tone = stv090x_set_tone,
  3729. .search = stv090x_search,
  3730. .read_status = stv090x_read_status,
  3731. .read_ber = stv090x_read_per,
  3732. .read_signal_strength = stv090x_read_signal_strength,
  3733. .read_snr = stv090x_read_cnr
  3734. };
  3735. struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
  3736. struct i2c_adapter *i2c,
  3737. enum stv090x_demodulator demod)
  3738. {
  3739. struct stv090x_state *state = NULL;
  3740. state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
  3741. if (state == NULL)
  3742. goto error;
  3743. state->verbose = &verbose;
  3744. state->config = config;
  3745. state->i2c = i2c;
  3746. state->frontend.ops = stv090x_ops;
  3747. state->frontend.demodulator_priv = state;
  3748. state->demod = demod;
  3749. state->demod_mode = config->demod_mode; /* Single or Dual mode */
  3750. state->device = config->device;
  3751. state->rolloff = STV090x_RO_35; /* default */
  3752. if (state->demod == STV090x_DEMODULATOR_0)
  3753. mutex_init(&demod_lock);
  3754. if (stv090x_sleep(&state->frontend) < 0) {
  3755. dprintk(FE_ERROR, 1, "Error putting device to sleep");
  3756. goto error;
  3757. }
  3758. if (stv090x_setup(&state->frontend) < 0) {
  3759. dprintk(FE_ERROR, 1, "Error setting up device");
  3760. goto error;
  3761. }
  3762. if (stv090x_wakeup(&state->frontend) < 0) {
  3763. dprintk(FE_ERROR, 1, "Error waking device");
  3764. goto error;
  3765. }
  3766. dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x\n",
  3767. state->device == STV0900 ? "STV0900" : "STV0903",
  3768. demod,
  3769. state->dev_ver);
  3770. return &state->frontend;
  3771. error:
  3772. kfree(state);
  3773. return NULL;
  3774. }
  3775. EXPORT_SYMBOL(stv090x_attach);
  3776. MODULE_PARM_DESC(verbose, "Set Verbosity level");
  3777. MODULE_AUTHOR("Manu Abraham");
  3778. MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
  3779. MODULE_LICENSE("GPL");