stv0900_core.c 46 KB

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  1. /*
  2. * stv0900_core.c
  3. *
  4. * Driver for ST STV0900 satellite demodulator IC.
  5. *
  6. * Copyright (C) ST Microelectronics.
  7. * Copyright (C) 2009 NetUP Inc.
  8. * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. *
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/slab.h>
  29. #include <linux/i2c.h>
  30. #include "stv0900.h"
  31. #include "stv0900_reg.h"
  32. #include "stv0900_priv.h"
  33. #include "stv0900_init.h"
  34. int stvdebug = 1;
  35. module_param_named(debug, stvdebug, int, 0644);
  36. /* internal params node */
  37. struct stv0900_inode {
  38. /* pointer for internal params, one for each pair of demods */
  39. struct stv0900_internal *internal;
  40. struct stv0900_inode *next_inode;
  41. };
  42. /* first internal params */
  43. static struct stv0900_inode *stv0900_first_inode;
  44. /* find chip by i2c adapter and i2c address */
  45. static struct stv0900_inode *find_inode(struct i2c_adapter *i2c_adap,
  46. u8 i2c_addr)
  47. {
  48. struct stv0900_inode *temp_chip = stv0900_first_inode;
  49. if (temp_chip != NULL) {
  50. /*
  51. Search of the last stv0900 chip or
  52. find it by i2c adapter and i2c address */
  53. while ((temp_chip != NULL) &&
  54. ((temp_chip->internal->i2c_adap != i2c_adap) ||
  55. (temp_chip->internal->i2c_addr != i2c_addr)))
  56. temp_chip = temp_chip->next_inode;
  57. }
  58. return temp_chip;
  59. }
  60. /* deallocating chip */
  61. static void remove_inode(struct stv0900_internal *internal)
  62. {
  63. struct stv0900_inode *prev_node = stv0900_first_inode;
  64. struct stv0900_inode *del_node = find_inode(internal->i2c_adap,
  65. internal->i2c_addr);
  66. if (del_node != NULL) {
  67. if (del_node == stv0900_first_inode) {
  68. stv0900_first_inode = del_node->next_inode;
  69. } else {
  70. while (prev_node->next_inode != del_node)
  71. prev_node = prev_node->next_inode;
  72. if (del_node->next_inode == NULL)
  73. prev_node->next_inode = NULL;
  74. else
  75. prev_node->next_inode =
  76. prev_node->next_inode->next_inode;
  77. }
  78. kfree(del_node);
  79. }
  80. }
  81. /* allocating new chip */
  82. static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
  83. {
  84. struct stv0900_inode *new_node = stv0900_first_inode;
  85. if (new_node == NULL) {
  86. new_node = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
  87. stv0900_first_inode = new_node;
  88. } else {
  89. while (new_node->next_inode != NULL)
  90. new_node = new_node->next_inode;
  91. new_node->next_inode = kmalloc(sizeof(struct stv0900_inode),
  92. GFP_KERNEL);
  93. if (new_node->next_inode != NULL)
  94. new_node = new_node->next_inode;
  95. else
  96. new_node = NULL;
  97. }
  98. if (new_node != NULL) {
  99. new_node->internal = internal;
  100. new_node->next_inode = NULL;
  101. }
  102. return new_node;
  103. }
  104. s32 ge2comp(s32 a, s32 width)
  105. {
  106. if (width == 32)
  107. return a;
  108. else
  109. return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
  110. }
  111. void stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr,
  112. u8 reg_data)
  113. {
  114. u8 data[3];
  115. int ret;
  116. struct i2c_msg i2cmsg = {
  117. .addr = intp->i2c_addr,
  118. .flags = 0,
  119. .len = 3,
  120. .buf = data,
  121. };
  122. data[0] = MSB(reg_addr);
  123. data[1] = LSB(reg_addr);
  124. data[2] = reg_data;
  125. ret = i2c_transfer(intp->i2c_adap, &i2cmsg, 1);
  126. if (ret != 1)
  127. dprintk("%s: i2c error %d\n", __func__, ret);
  128. }
  129. u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg)
  130. {
  131. int ret;
  132. u8 b0[] = { MSB(reg), LSB(reg) };
  133. u8 buf = 0;
  134. struct i2c_msg msg[] = {
  135. {
  136. .addr = intp->i2c_addr,
  137. .flags = 0,
  138. .buf = b0,
  139. .len = 2,
  140. }, {
  141. .addr = intp->i2c_addr,
  142. .flags = I2C_M_RD,
  143. .buf = &buf,
  144. .len = 1,
  145. },
  146. };
  147. ret = i2c_transfer(intp->i2c_adap, msg, 2);
  148. if (ret != 2)
  149. dprintk("%s: i2c error %d, reg[0x%02x]\n",
  150. __func__, ret, reg);
  151. return buf;
  152. }
  153. void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
  154. {
  155. u8 position = 0, i = 0;
  156. (*mask) = label & 0xff;
  157. while ((position == 0) && (i < 8)) {
  158. position = ((*mask) >> i) & 0x01;
  159. i++;
  160. }
  161. (*pos) = (i - 1);
  162. }
  163. void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val)
  164. {
  165. u8 reg, mask, pos;
  166. reg = stv0900_read_reg(intp, (label >> 16) & 0xffff);
  167. extract_mask_pos(label, &mask, &pos);
  168. val = mask & (val << pos);
  169. reg = (reg & (~mask)) | val;
  170. stv0900_write_reg(intp, (label >> 16) & 0xffff, reg);
  171. }
  172. u8 stv0900_get_bits(struct stv0900_internal *intp, u32 label)
  173. {
  174. u8 val = 0xff;
  175. u8 mask, pos;
  176. extract_mask_pos(label, &mask, &pos);
  177. val = stv0900_read_reg(intp, label >> 16);
  178. val = (val & mask) >> pos;
  179. return val;
  180. }
  181. enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *intp)
  182. {
  183. s32 i;
  184. if (intp == NULL)
  185. return STV0900_INVALID_HANDLE;
  186. intp->chip_id = stv0900_read_reg(intp, R0900_MID);
  187. if (intp->errs != STV0900_NO_ERROR)
  188. return intp->errs;
  189. /*Startup sequence*/
  190. stv0900_write_reg(intp, R0900_P1_DMDISTATE, 0x5c);
  191. stv0900_write_reg(intp, R0900_P2_DMDISTATE, 0x5c);
  192. msleep(3);
  193. stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x6c);
  194. stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x6f);
  195. stv0900_write_reg(intp, R0900_P1_I2CRPT, 0x20);
  196. stv0900_write_reg(intp, R0900_P2_I2CRPT, 0x20);
  197. stv0900_write_reg(intp, R0900_NCOARSE, 0x13);
  198. msleep(3);
  199. stv0900_write_reg(intp, R0900_I2CCFG, 0x08);
  200. switch (intp->clkmode) {
  201. case 0:
  202. case 2:
  203. stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20
  204. | intp->clkmode);
  205. break;
  206. default:
  207. /* preserve SELOSCI bit */
  208. i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
  209. stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | i);
  210. break;
  211. }
  212. msleep(3);
  213. for (i = 0; i < 181; i++)
  214. stv0900_write_reg(intp, STV0900_InitVal[i][0],
  215. STV0900_InitVal[i][1]);
  216. if (stv0900_read_reg(intp, R0900_MID) >= 0x20) {
  217. stv0900_write_reg(intp, R0900_TSGENERAL, 0x0c);
  218. for (i = 0; i < 32; i++)
  219. stv0900_write_reg(intp, STV0900_Cut20_AddOnVal[i][0],
  220. STV0900_Cut20_AddOnVal[i][1]);
  221. }
  222. stv0900_write_reg(intp, R0900_P1_FSPYCFG, 0x6c);
  223. stv0900_write_reg(intp, R0900_P2_FSPYCFG, 0x6c);
  224. stv0900_write_reg(intp, R0900_P1_PDELCTRL2, 0x01);
  225. stv0900_write_reg(intp, R0900_P2_PDELCTRL2, 0x21);
  226. stv0900_write_reg(intp, R0900_P1_PDELCTRL3, 0x20);
  227. stv0900_write_reg(intp, R0900_P2_PDELCTRL3, 0x20);
  228. stv0900_write_reg(intp, R0900_TSTRES0, 0x80);
  229. stv0900_write_reg(intp, R0900_TSTRES0, 0x00);
  230. return STV0900_NO_ERROR;
  231. }
  232. u32 stv0900_get_mclk_freq(struct stv0900_internal *intp, u32 ext_clk)
  233. {
  234. u32 mclk = 90000000, div = 0, ad_div = 0;
  235. div = stv0900_get_bits(intp, F0900_M_DIV);
  236. ad_div = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
  237. mclk = (div + 1) * ext_clk / ad_div;
  238. dprintk("%s: Calculated Mclk = %d\n", __func__, mclk);
  239. return mclk;
  240. }
  241. enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk)
  242. {
  243. u32 m_div, clk_sel;
  244. dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
  245. intp->quartz);
  246. if (intp == NULL)
  247. return STV0900_INVALID_HANDLE;
  248. if (intp->errs)
  249. return STV0900_I2C_ERROR;
  250. clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
  251. m_div = ((clk_sel * mclk) / intp->quartz) - 1;
  252. stv0900_write_bits(intp, F0900_M_DIV, m_div);
  253. intp->mclk = stv0900_get_mclk_freq(intp,
  254. intp->quartz);
  255. /*Set the DiseqC frequency to 22KHz */
  256. /*
  257. Formula:
  258. DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
  259. DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
  260. */
  261. m_div = intp->mclk / 704000;
  262. stv0900_write_reg(intp, R0900_P1_F22TX, m_div);
  263. stv0900_write_reg(intp, R0900_P1_F22RX, m_div);
  264. stv0900_write_reg(intp, R0900_P2_F22TX, m_div);
  265. stv0900_write_reg(intp, R0900_P2_F22RX, m_div);
  266. if ((intp->errs))
  267. return STV0900_I2C_ERROR;
  268. return STV0900_NO_ERROR;
  269. }
  270. u32 stv0900_get_err_count(struct stv0900_internal *intp, int cntr,
  271. enum fe_stv0900_demod_num demod)
  272. {
  273. u32 lsb, msb, hsb, err_val;
  274. switch (cntr) {
  275. case 0:
  276. default:
  277. hsb = stv0900_get_bits(intp, ERR_CNT12);
  278. msb = stv0900_get_bits(intp, ERR_CNT11);
  279. lsb = stv0900_get_bits(intp, ERR_CNT10);
  280. break;
  281. case 1:
  282. hsb = stv0900_get_bits(intp, ERR_CNT22);
  283. msb = stv0900_get_bits(intp, ERR_CNT21);
  284. lsb = stv0900_get_bits(intp, ERR_CNT20);
  285. break;
  286. }
  287. err_val = (hsb << 16) + (msb << 8) + (lsb);
  288. return err_val;
  289. }
  290. static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  291. {
  292. struct stv0900_state *state = fe->demodulator_priv;
  293. struct stv0900_internal *intp = state->internal;
  294. enum fe_stv0900_demod_num demod = state->demod;
  295. stv0900_write_bits(intp, I2CT_ON, enable);
  296. return 0;
  297. }
  298. static void stv0900_set_ts_parallel_serial(struct stv0900_internal *intp,
  299. enum fe_stv0900_clock_type path1_ts,
  300. enum fe_stv0900_clock_type path2_ts)
  301. {
  302. dprintk("%s\n", __func__);
  303. if (intp->chip_id >= 0x20) {
  304. switch (path1_ts) {
  305. case STV0900_PARALLEL_PUNCT_CLOCK:
  306. case STV0900_DVBCI_CLOCK:
  307. switch (path2_ts) {
  308. case STV0900_SERIAL_PUNCT_CLOCK:
  309. case STV0900_SERIAL_CONT_CLOCK:
  310. default:
  311. stv0900_write_reg(intp, R0900_TSGENERAL,
  312. 0x00);
  313. break;
  314. case STV0900_PARALLEL_PUNCT_CLOCK:
  315. case STV0900_DVBCI_CLOCK:
  316. stv0900_write_reg(intp, R0900_TSGENERAL,
  317. 0x06);
  318. stv0900_write_bits(intp,
  319. F0900_P1_TSFIFO_MANSPEED, 3);
  320. stv0900_write_bits(intp,
  321. F0900_P2_TSFIFO_MANSPEED, 0);
  322. stv0900_write_reg(intp,
  323. R0900_P1_TSSPEED, 0x14);
  324. stv0900_write_reg(intp,
  325. R0900_P2_TSSPEED, 0x28);
  326. break;
  327. }
  328. break;
  329. case STV0900_SERIAL_PUNCT_CLOCK:
  330. case STV0900_SERIAL_CONT_CLOCK:
  331. default:
  332. switch (path2_ts) {
  333. case STV0900_SERIAL_PUNCT_CLOCK:
  334. case STV0900_SERIAL_CONT_CLOCK:
  335. default:
  336. stv0900_write_reg(intp,
  337. R0900_TSGENERAL, 0x0C);
  338. break;
  339. case STV0900_PARALLEL_PUNCT_CLOCK:
  340. case STV0900_DVBCI_CLOCK:
  341. stv0900_write_reg(intp,
  342. R0900_TSGENERAL, 0x0A);
  343. dprintk("%s: 0x0a\n", __func__);
  344. break;
  345. }
  346. break;
  347. }
  348. } else {
  349. switch (path1_ts) {
  350. case STV0900_PARALLEL_PUNCT_CLOCK:
  351. case STV0900_DVBCI_CLOCK:
  352. switch (path2_ts) {
  353. case STV0900_SERIAL_PUNCT_CLOCK:
  354. case STV0900_SERIAL_CONT_CLOCK:
  355. default:
  356. stv0900_write_reg(intp, R0900_TSGENERAL1X,
  357. 0x10);
  358. break;
  359. case STV0900_PARALLEL_PUNCT_CLOCK:
  360. case STV0900_DVBCI_CLOCK:
  361. stv0900_write_reg(intp, R0900_TSGENERAL1X,
  362. 0x16);
  363. stv0900_write_bits(intp,
  364. F0900_P1_TSFIFO_MANSPEED, 3);
  365. stv0900_write_bits(intp,
  366. F0900_P2_TSFIFO_MANSPEED, 0);
  367. stv0900_write_reg(intp, R0900_P1_TSSPEED,
  368. 0x14);
  369. stv0900_write_reg(intp, R0900_P2_TSSPEED,
  370. 0x28);
  371. break;
  372. }
  373. break;
  374. case STV0900_SERIAL_PUNCT_CLOCK:
  375. case STV0900_SERIAL_CONT_CLOCK:
  376. default:
  377. switch (path2_ts) {
  378. case STV0900_SERIAL_PUNCT_CLOCK:
  379. case STV0900_SERIAL_CONT_CLOCK:
  380. default:
  381. stv0900_write_reg(intp, R0900_TSGENERAL1X,
  382. 0x14);
  383. break;
  384. case STV0900_PARALLEL_PUNCT_CLOCK:
  385. case STV0900_DVBCI_CLOCK:
  386. stv0900_write_reg(intp, R0900_TSGENERAL1X,
  387. 0x12);
  388. dprintk("%s: 0x12\n", __func__);
  389. break;
  390. }
  391. break;
  392. }
  393. }
  394. switch (path1_ts) {
  395. case STV0900_PARALLEL_PUNCT_CLOCK:
  396. stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
  397. stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
  398. break;
  399. case STV0900_DVBCI_CLOCK:
  400. stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
  401. stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
  402. break;
  403. case STV0900_SERIAL_PUNCT_CLOCK:
  404. stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
  405. stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
  406. break;
  407. case STV0900_SERIAL_CONT_CLOCK:
  408. stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
  409. stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
  410. break;
  411. default:
  412. break;
  413. }
  414. switch (path2_ts) {
  415. case STV0900_PARALLEL_PUNCT_CLOCK:
  416. stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
  417. stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
  418. break;
  419. case STV0900_DVBCI_CLOCK:
  420. stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
  421. stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
  422. break;
  423. case STV0900_SERIAL_PUNCT_CLOCK:
  424. stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
  425. stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
  426. break;
  427. case STV0900_SERIAL_CONT_CLOCK:
  428. stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
  429. stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
  430. break;
  431. default:
  432. break;
  433. }
  434. stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
  435. stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
  436. stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
  437. stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
  438. }
  439. void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
  440. u32 bandwidth)
  441. {
  442. struct dvb_frontend_ops *frontend_ops = NULL;
  443. struct dvb_tuner_ops *tuner_ops = NULL;
  444. if (&fe->ops)
  445. frontend_ops = &fe->ops;
  446. if (&frontend_ops->tuner_ops)
  447. tuner_ops = &frontend_ops->tuner_ops;
  448. if (tuner_ops->set_frequency) {
  449. if ((tuner_ops->set_frequency(fe, frequency)) < 0)
  450. dprintk("%s: Invalid parameter\n", __func__);
  451. else
  452. dprintk("%s: Frequency=%d\n", __func__, frequency);
  453. }
  454. if (tuner_ops->set_bandwidth) {
  455. if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
  456. dprintk("%s: Invalid parameter\n", __func__);
  457. else
  458. dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
  459. }
  460. }
  461. void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
  462. {
  463. struct dvb_frontend_ops *frontend_ops = NULL;
  464. struct dvb_tuner_ops *tuner_ops = NULL;
  465. if (&fe->ops)
  466. frontend_ops = &fe->ops;
  467. if (&frontend_ops->tuner_ops)
  468. tuner_ops = &frontend_ops->tuner_ops;
  469. if (tuner_ops->set_bandwidth) {
  470. if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
  471. dprintk("%s: Invalid parameter\n", __func__);
  472. else
  473. dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
  474. }
  475. }
  476. static s32 stv0900_get_rf_level(struct stv0900_internal *intp,
  477. const struct stv0900_table *lookup,
  478. enum fe_stv0900_demod_num demod)
  479. {
  480. s32 agc_gain = 0,
  481. imin,
  482. imax,
  483. i,
  484. rf_lvl = 0;
  485. dprintk("%s\n", __func__);
  486. if ((lookup == NULL) || (lookup->size <= 0))
  487. return 0;
  488. agc_gain = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
  489. stv0900_get_bits(intp, AGCIQ_VALUE0));
  490. imin = 0;
  491. imax = lookup->size - 1;
  492. if (INRANGE(lookup->table[imin].regval, agc_gain,
  493. lookup->table[imax].regval)) {
  494. while ((imax - imin) > 1) {
  495. i = (imax + imin) >> 1;
  496. if (INRANGE(lookup->table[imin].regval,
  497. agc_gain,
  498. lookup->table[i].regval))
  499. imax = i;
  500. else
  501. imin = i;
  502. }
  503. rf_lvl = (s32)agc_gain - lookup->table[imin].regval;
  504. rf_lvl *= (lookup->table[imax].realval -
  505. lookup->table[imin].realval);
  506. rf_lvl /= (lookup->table[imax].regval -
  507. lookup->table[imin].regval);
  508. rf_lvl += lookup->table[imin].realval;
  509. } else if (agc_gain > lookup->table[0].regval)
  510. rf_lvl = 5;
  511. else if (agc_gain < lookup->table[lookup->size-1].regval)
  512. rf_lvl = -100;
  513. dprintk("%s: RFLevel = %d\n", __func__, rf_lvl);
  514. return rf_lvl;
  515. }
  516. static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
  517. {
  518. struct stv0900_state *state = fe->demodulator_priv;
  519. struct stv0900_internal *internal = state->internal;
  520. s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf,
  521. state->demod);
  522. rflevel = (rflevel + 100) * (65535 / 70);
  523. if (rflevel < 0)
  524. rflevel = 0;
  525. if (rflevel > 65535)
  526. rflevel = 65535;
  527. *strength = rflevel;
  528. return 0;
  529. }
  530. static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
  531. const struct stv0900_table *lookup)
  532. {
  533. struct stv0900_state *state = fe->demodulator_priv;
  534. struct stv0900_internal *intp = state->internal;
  535. enum fe_stv0900_demod_num demod = state->demod;
  536. s32 c_n = -100,
  537. regval,
  538. imin,
  539. imax,
  540. i,
  541. noise_field1,
  542. noise_field0;
  543. dprintk("%s\n", __func__);
  544. if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
  545. noise_field1 = NOSPLHT_NORMED1;
  546. noise_field0 = NOSPLHT_NORMED0;
  547. } else {
  548. noise_field1 = NOSDATAT_NORMED1;
  549. noise_field0 = NOSDATAT_NORMED0;
  550. }
  551. if (stv0900_get_bits(intp, LOCK_DEFINITIF)) {
  552. if ((lookup != NULL) && lookup->size) {
  553. regval = 0;
  554. msleep(5);
  555. for (i = 0; i < 16; i++) {
  556. regval += MAKEWORD(stv0900_get_bits(intp,
  557. noise_field1),
  558. stv0900_get_bits(intp,
  559. noise_field0));
  560. msleep(1);
  561. }
  562. regval /= 16;
  563. imin = 0;
  564. imax = lookup->size - 1;
  565. if (INRANGE(lookup->table[imin].regval,
  566. regval,
  567. lookup->table[imax].regval)) {
  568. while ((imax - imin) > 1) {
  569. i = (imax + imin) >> 1;
  570. if (INRANGE(lookup->table[imin].regval,
  571. regval,
  572. lookup->table[i].regval))
  573. imax = i;
  574. else
  575. imin = i;
  576. }
  577. c_n = ((regval - lookup->table[imin].regval)
  578. * (lookup->table[imax].realval
  579. - lookup->table[imin].realval)
  580. / (lookup->table[imax].regval
  581. - lookup->table[imin].regval))
  582. + lookup->table[imin].realval;
  583. } else if (regval < lookup->table[imin].regval)
  584. c_n = 1000;
  585. }
  586. }
  587. return c_n;
  588. }
  589. static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
  590. {
  591. struct stv0900_state *state = fe->demodulator_priv;
  592. struct stv0900_internal *intp = state->internal;
  593. enum fe_stv0900_demod_num demod = state->demod;
  594. u8 err_val1, err_val0;
  595. u32 header_err_val = 0;
  596. *ucblocks = 0x0;
  597. if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
  598. /* DVB-S2 delineator errors count */
  599. /* retreiving number for errnous headers */
  600. err_val1 = stv0900_read_reg(intp, BBFCRCKO1);
  601. err_val0 = stv0900_read_reg(intp, BBFCRCKO0);
  602. header_err_val = (err_val1 << 8) | err_val0;
  603. /* retreiving number for errnous packets */
  604. err_val1 = stv0900_read_reg(intp, UPCRCKO1);
  605. err_val0 = stv0900_read_reg(intp, UPCRCKO0);
  606. *ucblocks = (err_val1 << 8) | err_val0;
  607. *ucblocks += header_err_val;
  608. }
  609. return 0;
  610. }
  611. static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
  612. {
  613. s32 snrlcl = stv0900_carr_get_quality(fe,
  614. (const struct stv0900_table *)&stv0900_s2_cn);
  615. snrlcl = (snrlcl + 30) * 384;
  616. if (snrlcl < 0)
  617. snrlcl = 0;
  618. if (snrlcl > 65535)
  619. snrlcl = 65535;
  620. *snr = snrlcl;
  621. return 0;
  622. }
  623. static u32 stv0900_get_ber(struct stv0900_internal *intp,
  624. enum fe_stv0900_demod_num demod)
  625. {
  626. u32 ber = 10000000, i;
  627. s32 demod_state;
  628. demod_state = stv0900_get_bits(intp, HEADER_MODE);
  629. switch (demod_state) {
  630. case STV0900_SEARCH:
  631. case STV0900_PLH_DETECTED:
  632. default:
  633. ber = 10000000;
  634. break;
  635. case STV0900_DVBS_FOUND:
  636. ber = 0;
  637. for (i = 0; i < 5; i++) {
  638. msleep(5);
  639. ber += stv0900_get_err_count(intp, 0, demod);
  640. }
  641. ber /= 5;
  642. if (stv0900_get_bits(intp, PRFVIT)) {
  643. ber *= 9766;
  644. ber = ber >> 13;
  645. }
  646. break;
  647. case STV0900_DVBS2_FOUND:
  648. ber = 0;
  649. for (i = 0; i < 5; i++) {
  650. msleep(5);
  651. ber += stv0900_get_err_count(intp, 0, demod);
  652. }
  653. ber /= 5;
  654. if (stv0900_get_bits(intp, PKTDELIN_LOCK)) {
  655. ber *= 9766;
  656. ber = ber >> 13;
  657. }
  658. break;
  659. }
  660. return ber;
  661. }
  662. static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
  663. {
  664. struct stv0900_state *state = fe->demodulator_priv;
  665. struct stv0900_internal *internal = state->internal;
  666. *ber = stv0900_get_ber(internal, state->demod);
  667. return 0;
  668. }
  669. int stv0900_get_demod_lock(struct stv0900_internal *intp,
  670. enum fe_stv0900_demod_num demod, s32 time_out)
  671. {
  672. s32 timer = 0,
  673. lock = 0;
  674. enum fe_stv0900_search_state dmd_state;
  675. while ((timer < time_out) && (lock == 0)) {
  676. dmd_state = stv0900_get_bits(intp, HEADER_MODE);
  677. dprintk("Demod State = %d\n", dmd_state);
  678. switch (dmd_state) {
  679. case STV0900_SEARCH:
  680. case STV0900_PLH_DETECTED:
  681. default:
  682. lock = 0;
  683. break;
  684. case STV0900_DVBS2_FOUND:
  685. case STV0900_DVBS_FOUND:
  686. lock = stv0900_get_bits(intp, LOCK_DEFINITIF);
  687. break;
  688. }
  689. if (lock == 0)
  690. msleep(10);
  691. timer += 10;
  692. }
  693. if (lock)
  694. dprintk("DEMOD LOCK OK\n");
  695. else
  696. dprintk("DEMOD LOCK FAIL\n");
  697. return lock;
  698. }
  699. void stv0900_stop_all_s2_modcod(struct stv0900_internal *intp,
  700. enum fe_stv0900_demod_num demod)
  701. {
  702. s32 regflist,
  703. i;
  704. dprintk("%s\n", __func__);
  705. regflist = MODCODLST0;
  706. for (i = 0; i < 16; i++)
  707. stv0900_write_reg(intp, regflist + i, 0xff);
  708. }
  709. void stv0900_activate_s2_modcod(struct stv0900_internal *intp,
  710. enum fe_stv0900_demod_num demod)
  711. {
  712. u32 matype,
  713. mod_code,
  714. fmod,
  715. reg_index,
  716. field_index;
  717. dprintk("%s\n", __func__);
  718. if (intp->chip_id <= 0x11) {
  719. msleep(5);
  720. mod_code = stv0900_read_reg(intp, PLHMODCOD);
  721. matype = mod_code & 0x3;
  722. mod_code = (mod_code & 0x7f) >> 2;
  723. reg_index = MODCODLSTF - mod_code / 2;
  724. field_index = mod_code % 2;
  725. switch (matype) {
  726. case 0:
  727. default:
  728. fmod = 14;
  729. break;
  730. case 1:
  731. fmod = 13;
  732. break;
  733. case 2:
  734. fmod = 11;
  735. break;
  736. case 3:
  737. fmod = 7;
  738. break;
  739. }
  740. if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
  741. && (matype <= 1)) {
  742. if (field_index == 0)
  743. stv0900_write_reg(intp, reg_index,
  744. 0xf0 | fmod);
  745. else
  746. stv0900_write_reg(intp, reg_index,
  747. (fmod << 4) | 0xf);
  748. }
  749. } else if (intp->chip_id >= 0x12) {
  750. for (reg_index = 0; reg_index < 7; reg_index++)
  751. stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff);
  752. stv0900_write_reg(intp, MODCODLSTE, 0xff);
  753. stv0900_write_reg(intp, MODCODLSTF, 0xcf);
  754. for (reg_index = 0; reg_index < 8; reg_index++)
  755. stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc);
  756. }
  757. }
  758. void stv0900_activate_s2_modcod_single(struct stv0900_internal *intp,
  759. enum fe_stv0900_demod_num demod)
  760. {
  761. u32 reg_index;
  762. dprintk("%s\n", __func__);
  763. stv0900_write_reg(intp, MODCODLST0, 0xff);
  764. stv0900_write_reg(intp, MODCODLST1, 0xf0);
  765. stv0900_write_reg(intp, MODCODLSTF, 0x0f);
  766. for (reg_index = 0; reg_index < 13; reg_index++)
  767. stv0900_write_reg(intp, MODCODLST2 + reg_index, 0);
  768. }
  769. static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
  770. {
  771. return DVBFE_ALGO_CUSTOM;
  772. }
  773. static int stb0900_set_property(struct dvb_frontend *fe,
  774. struct dtv_property *tvp)
  775. {
  776. dprintk("%s(..)\n", __func__);
  777. return 0;
  778. }
  779. static int stb0900_get_property(struct dvb_frontend *fe,
  780. struct dtv_property *tvp)
  781. {
  782. dprintk("%s(..)\n", __func__);
  783. return 0;
  784. }
  785. void stv0900_start_search(struct stv0900_internal *intp,
  786. enum fe_stv0900_demod_num demod)
  787. {
  788. u32 freq;
  789. s16 freq_s16 ;
  790. stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
  791. if (intp->chip_id == 0x10)
  792. stv0900_write_reg(intp, CORRELEXP, 0xaa);
  793. if (intp->chip_id < 0x20)
  794. stv0900_write_reg(intp, CARHDR, 0x55);
  795. if (intp->chip_id <= 0x20) {
  796. if (intp->symbol_rate[0] <= 5000000) {
  797. stv0900_write_reg(intp, CARCFG, 0x44);
  798. stv0900_write_reg(intp, CFRUP1, 0x0f);
  799. stv0900_write_reg(intp, CFRUP0, 0xff);
  800. stv0900_write_reg(intp, CFRLOW1, 0xf0);
  801. stv0900_write_reg(intp, CFRLOW0, 0x00);
  802. stv0900_write_reg(intp, RTCS2, 0x68);
  803. } else {
  804. stv0900_write_reg(intp, CARCFG, 0xc4);
  805. stv0900_write_reg(intp, RTCS2, 0x44);
  806. }
  807. } else { /*cut 3.0 above*/
  808. if (intp->symbol_rate[demod] <= 5000000)
  809. stv0900_write_reg(intp, RTCS2, 0x68);
  810. else
  811. stv0900_write_reg(intp, RTCS2, 0x44);
  812. stv0900_write_reg(intp, CARCFG, 0x46);
  813. if (intp->srch_algo[demod] == STV0900_WARM_START) {
  814. freq = 1000 << 16;
  815. freq /= (intp->mclk / 1000);
  816. freq_s16 = (s16)freq;
  817. } else {
  818. freq = (intp->srch_range[demod] / 2000);
  819. if (intp->symbol_rate[demod] <= 5000000)
  820. freq += 80;
  821. else
  822. freq += 600;
  823. freq = freq << 16;
  824. freq /= (intp->mclk / 1000);
  825. freq_s16 = (s16)freq;
  826. }
  827. stv0900_write_bits(intp, CFR_UP1, MSB(freq_s16));
  828. stv0900_write_bits(intp, CFR_UP0, LSB(freq_s16));
  829. freq_s16 *= (-1);
  830. stv0900_write_bits(intp, CFR_LOW1, MSB(freq_s16));
  831. stv0900_write_bits(intp, CFR_LOW0, LSB(freq_s16));
  832. }
  833. stv0900_write_reg(intp, CFRINIT1, 0);
  834. stv0900_write_reg(intp, CFRINIT0, 0);
  835. if (intp->chip_id >= 0x20) {
  836. stv0900_write_reg(intp, EQUALCFG, 0x41);
  837. stv0900_write_reg(intp, FFECFG, 0x41);
  838. if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
  839. (intp->srch_standard[demod] == STV0900_SEARCH_DSS) ||
  840. (intp->srch_standard[demod] == STV0900_AUTO_SEARCH)) {
  841. stv0900_write_reg(intp, VITSCALE,
  842. 0x82);
  843. stv0900_write_reg(intp, VAVSRVIT, 0x0);
  844. }
  845. }
  846. stv0900_write_reg(intp, SFRSTEP, 0x00);
  847. stv0900_write_reg(intp, TMGTHRISE, 0xe0);
  848. stv0900_write_reg(intp, TMGTHFALL, 0xc0);
  849. stv0900_write_bits(intp, SCAN_ENABLE, 0);
  850. stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
  851. stv0900_write_bits(intp, S1S2_SEQUENTIAL, 0);
  852. stv0900_write_reg(intp, RTC, 0x88);
  853. if (intp->chip_id >= 0x20) {
  854. if (intp->symbol_rate[demod] < 2000000) {
  855. if (intp->chip_id <= 0x20)
  856. stv0900_write_reg(intp, CARFREQ, 0x39);
  857. else /*cut 3.0*/
  858. stv0900_write_reg(intp, CARFREQ, 0x89);
  859. stv0900_write_reg(intp, CARHDR, 0x40);
  860. } else if (intp->symbol_rate[demod] < 10000000) {
  861. stv0900_write_reg(intp, CARFREQ, 0x4c);
  862. stv0900_write_reg(intp, CARHDR, 0x20);
  863. } else {
  864. stv0900_write_reg(intp, CARFREQ, 0x4b);
  865. stv0900_write_reg(intp, CARHDR, 0x20);
  866. }
  867. } else {
  868. if (intp->symbol_rate[demod] < 10000000)
  869. stv0900_write_reg(intp, CARFREQ, 0xef);
  870. else
  871. stv0900_write_reg(intp, CARFREQ, 0xed);
  872. }
  873. switch (intp->srch_algo[demod]) {
  874. case STV0900_WARM_START:
  875. stv0900_write_reg(intp, DMDISTATE, 0x1f);
  876. stv0900_write_reg(intp, DMDISTATE, 0x18);
  877. break;
  878. case STV0900_COLD_START:
  879. stv0900_write_reg(intp, DMDISTATE, 0x1f);
  880. stv0900_write_reg(intp, DMDISTATE, 0x15);
  881. break;
  882. default:
  883. break;
  884. }
  885. }
  886. u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
  887. s32 pilot, u8 chip_id)
  888. {
  889. u8 aclc_value = 0x29;
  890. s32 i;
  891. const struct stv0900_car_loop_optim *cls2, *cllqs2, *cllas2;
  892. dprintk("%s\n", __func__);
  893. if (chip_id <= 0x12) {
  894. cls2 = FE_STV0900_S2CarLoop;
  895. cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
  896. cllas2 = FE_STV0900_S2APSKCarLoopCut30;
  897. } else if (chip_id == 0x20) {
  898. cls2 = FE_STV0900_S2CarLoopCut20;
  899. cllqs2 = FE_STV0900_S2LowQPCarLoopCut20;
  900. cllas2 = FE_STV0900_S2APSKCarLoopCut20;
  901. } else {
  902. cls2 = FE_STV0900_S2CarLoopCut30;
  903. cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
  904. cllas2 = FE_STV0900_S2APSKCarLoopCut30;
  905. }
  906. if (modcode < STV0900_QPSK_12) {
  907. i = 0;
  908. while ((i < 3) && (modcode != cllqs2[i].modcode))
  909. i++;
  910. if (i >= 3)
  911. i = 2;
  912. } else {
  913. i = 0;
  914. while ((i < 14) && (modcode != cls2[i].modcode))
  915. i++;
  916. if (i >= 14) {
  917. i = 0;
  918. while ((i < 11) && (modcode != cllas2[i].modcode))
  919. i++;
  920. if (i >= 11)
  921. i = 10;
  922. }
  923. }
  924. if (modcode <= STV0900_QPSK_25) {
  925. if (pilot) {
  926. if (srate <= 3000000)
  927. aclc_value = cllqs2[i].car_loop_pilots_on_2;
  928. else if (srate <= 7000000)
  929. aclc_value = cllqs2[i].car_loop_pilots_on_5;
  930. else if (srate <= 15000000)
  931. aclc_value = cllqs2[i].car_loop_pilots_on_10;
  932. else if (srate <= 25000000)
  933. aclc_value = cllqs2[i].car_loop_pilots_on_20;
  934. else
  935. aclc_value = cllqs2[i].car_loop_pilots_on_30;
  936. } else {
  937. if (srate <= 3000000)
  938. aclc_value = cllqs2[i].car_loop_pilots_off_2;
  939. else if (srate <= 7000000)
  940. aclc_value = cllqs2[i].car_loop_pilots_off_5;
  941. else if (srate <= 15000000)
  942. aclc_value = cllqs2[i].car_loop_pilots_off_10;
  943. else if (srate <= 25000000)
  944. aclc_value = cllqs2[i].car_loop_pilots_off_20;
  945. else
  946. aclc_value = cllqs2[i].car_loop_pilots_off_30;
  947. }
  948. } else if (modcode <= STV0900_8PSK_910) {
  949. if (pilot) {
  950. if (srate <= 3000000)
  951. aclc_value = cls2[i].car_loop_pilots_on_2;
  952. else if (srate <= 7000000)
  953. aclc_value = cls2[i].car_loop_pilots_on_5;
  954. else if (srate <= 15000000)
  955. aclc_value = cls2[i].car_loop_pilots_on_10;
  956. else if (srate <= 25000000)
  957. aclc_value = cls2[i].car_loop_pilots_on_20;
  958. else
  959. aclc_value = cls2[i].car_loop_pilots_on_30;
  960. } else {
  961. if (srate <= 3000000)
  962. aclc_value = cls2[i].car_loop_pilots_off_2;
  963. else if (srate <= 7000000)
  964. aclc_value = cls2[i].car_loop_pilots_off_5;
  965. else if (srate <= 15000000)
  966. aclc_value = cls2[i].car_loop_pilots_off_10;
  967. else if (srate <= 25000000)
  968. aclc_value = cls2[i].car_loop_pilots_off_20;
  969. else
  970. aclc_value = cls2[i].car_loop_pilots_off_30;
  971. }
  972. } else {
  973. if (srate <= 3000000)
  974. aclc_value = cllas2[i].car_loop_pilots_on_2;
  975. else if (srate <= 7000000)
  976. aclc_value = cllas2[i].car_loop_pilots_on_5;
  977. else if (srate <= 15000000)
  978. aclc_value = cllas2[i].car_loop_pilots_on_10;
  979. else if (srate <= 25000000)
  980. aclc_value = cllas2[i].car_loop_pilots_on_20;
  981. else
  982. aclc_value = cllas2[i].car_loop_pilots_on_30;
  983. }
  984. return aclc_value;
  985. }
  986. u8 stv0900_get_optim_short_carr_loop(s32 srate,
  987. enum fe_stv0900_modulation modulation,
  988. u8 chip_id)
  989. {
  990. const struct stv0900_short_frames_car_loop_optim *s2scl;
  991. const struct stv0900_short_frames_car_loop_optim_vs_mod *s2sclc30;
  992. s32 mod_index = 0;
  993. u8 aclc_value = 0x0b;
  994. dprintk("%s\n", __func__);
  995. s2scl = FE_STV0900_S2ShortCarLoop;
  996. s2sclc30 = FE_STV0900_S2ShortCarLoopCut30;
  997. switch (modulation) {
  998. case STV0900_QPSK:
  999. default:
  1000. mod_index = 0;
  1001. break;
  1002. case STV0900_8PSK:
  1003. mod_index = 1;
  1004. break;
  1005. case STV0900_16APSK:
  1006. mod_index = 2;
  1007. break;
  1008. case STV0900_32APSK:
  1009. mod_index = 3;
  1010. break;
  1011. }
  1012. if (chip_id >= 0x30) {
  1013. if (srate <= 3000000)
  1014. aclc_value = s2sclc30[mod_index].car_loop_2;
  1015. else if (srate <= 7000000)
  1016. aclc_value = s2sclc30[mod_index].car_loop_5;
  1017. else if (srate <= 15000000)
  1018. aclc_value = s2sclc30[mod_index].car_loop_10;
  1019. else if (srate <= 25000000)
  1020. aclc_value = s2sclc30[mod_index].car_loop_20;
  1021. else
  1022. aclc_value = s2sclc30[mod_index].car_loop_30;
  1023. } else if (chip_id >= 0x20) {
  1024. if (srate <= 3000000)
  1025. aclc_value = s2scl[mod_index].car_loop_cut20_2;
  1026. else if (srate <= 7000000)
  1027. aclc_value = s2scl[mod_index].car_loop_cut20_5;
  1028. else if (srate <= 15000000)
  1029. aclc_value = s2scl[mod_index].car_loop_cut20_10;
  1030. else if (srate <= 25000000)
  1031. aclc_value = s2scl[mod_index].car_loop_cut20_20;
  1032. else
  1033. aclc_value = s2scl[mod_index].car_loop_cut20_30;
  1034. } else {
  1035. if (srate <= 3000000)
  1036. aclc_value = s2scl[mod_index].car_loop_cut12_2;
  1037. else if (srate <= 7000000)
  1038. aclc_value = s2scl[mod_index].car_loop_cut12_5;
  1039. else if (srate <= 15000000)
  1040. aclc_value = s2scl[mod_index].car_loop_cut12_10;
  1041. else if (srate <= 25000000)
  1042. aclc_value = s2scl[mod_index].car_loop_cut12_20;
  1043. else
  1044. aclc_value = s2scl[mod_index].car_loop_cut12_30;
  1045. }
  1046. return aclc_value;
  1047. }
  1048. static
  1049. enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *intp,
  1050. enum fe_stv0900_demod_mode LDPC_Mode,
  1051. enum fe_stv0900_demod_num demod)
  1052. {
  1053. enum fe_stv0900_error error = STV0900_NO_ERROR;
  1054. s32 reg_ind;
  1055. dprintk("%s\n", __func__);
  1056. switch (LDPC_Mode) {
  1057. case STV0900_DUAL:
  1058. default:
  1059. if ((intp->demod_mode != STV0900_DUAL)
  1060. || (stv0900_get_bits(intp, F0900_DDEMOD) != 1)) {
  1061. stv0900_write_reg(intp, R0900_GENCFG, 0x1d);
  1062. intp->demod_mode = STV0900_DUAL;
  1063. stv0900_write_bits(intp, F0900_FRESFEC, 1);
  1064. stv0900_write_bits(intp, F0900_FRESFEC, 0);
  1065. for (reg_ind = 0; reg_ind < 7; reg_ind++)
  1066. stv0900_write_reg(intp,
  1067. R0900_P1_MODCODLST0 + reg_ind,
  1068. 0xff);
  1069. for (reg_ind = 0; reg_ind < 8; reg_ind++)
  1070. stv0900_write_reg(intp,
  1071. R0900_P1_MODCODLST7 + reg_ind,
  1072. 0xcc);
  1073. stv0900_write_reg(intp, R0900_P1_MODCODLSTE, 0xff);
  1074. stv0900_write_reg(intp, R0900_P1_MODCODLSTF, 0xcf);
  1075. for (reg_ind = 0; reg_ind < 7; reg_ind++)
  1076. stv0900_write_reg(intp,
  1077. R0900_P2_MODCODLST0 + reg_ind,
  1078. 0xff);
  1079. for (reg_ind = 0; reg_ind < 8; reg_ind++)
  1080. stv0900_write_reg(intp,
  1081. R0900_P2_MODCODLST7 + reg_ind,
  1082. 0xcc);
  1083. stv0900_write_reg(intp, R0900_P2_MODCODLSTE, 0xff);
  1084. stv0900_write_reg(intp, R0900_P2_MODCODLSTF, 0xcf);
  1085. }
  1086. break;
  1087. case STV0900_SINGLE:
  1088. if (demod == STV0900_DEMOD_2) {
  1089. stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_1);
  1090. stv0900_activate_s2_modcod_single(intp,
  1091. STV0900_DEMOD_2);
  1092. stv0900_write_reg(intp, R0900_GENCFG, 0x06);
  1093. } else {
  1094. stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_2);
  1095. stv0900_activate_s2_modcod_single(intp,
  1096. STV0900_DEMOD_1);
  1097. stv0900_write_reg(intp, R0900_GENCFG, 0x04);
  1098. }
  1099. intp->demod_mode = STV0900_SINGLE;
  1100. stv0900_write_bits(intp, F0900_FRESFEC, 1);
  1101. stv0900_write_bits(intp, F0900_FRESFEC, 0);
  1102. stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 1);
  1103. stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 0);
  1104. stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 1);
  1105. stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 0);
  1106. break;
  1107. }
  1108. return error;
  1109. }
  1110. static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
  1111. struct stv0900_init_params *p_init)
  1112. {
  1113. struct stv0900_state *state = fe->demodulator_priv;
  1114. enum fe_stv0900_error error = STV0900_NO_ERROR;
  1115. enum fe_stv0900_error demodError = STV0900_NO_ERROR;
  1116. struct stv0900_internal *intp = NULL;
  1117. int selosci, i;
  1118. struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
  1119. state->config->demod_address);
  1120. dprintk("%s\n", __func__);
  1121. if ((temp_int != NULL) && (p_init->demod_mode == STV0900_DUAL)) {
  1122. state->internal = temp_int->internal;
  1123. (state->internal->dmds_used)++;
  1124. dprintk("%s: Find Internal Structure!\n", __func__);
  1125. return STV0900_NO_ERROR;
  1126. } else {
  1127. state->internal = kmalloc(sizeof(struct stv0900_internal),
  1128. GFP_KERNEL);
  1129. temp_int = append_internal(state->internal);
  1130. state->internal->dmds_used = 1;
  1131. state->internal->i2c_adap = state->i2c_adap;
  1132. state->internal->i2c_addr = state->config->demod_address;
  1133. state->internal->clkmode = state->config->clkmode;
  1134. state->internal->errs = STV0900_NO_ERROR;
  1135. dprintk("%s: Create New Internal Structure!\n", __func__);
  1136. }
  1137. if (state->internal == NULL) {
  1138. error = STV0900_INVALID_HANDLE;
  1139. return error;
  1140. }
  1141. demodError = stv0900_initialize(state->internal);
  1142. if (demodError == STV0900_NO_ERROR) {
  1143. error = STV0900_NO_ERROR;
  1144. } else {
  1145. if (demodError == STV0900_INVALID_HANDLE)
  1146. error = STV0900_INVALID_HANDLE;
  1147. else
  1148. error = STV0900_I2C_ERROR;
  1149. return error;
  1150. }
  1151. if (state->internal == NULL) {
  1152. error = STV0900_INVALID_HANDLE;
  1153. return error;
  1154. }
  1155. intp = state->internal;
  1156. intp->demod_mode = p_init->demod_mode;
  1157. stv0900_st_dvbs2_single(intp, intp->demod_mode, STV0900_DEMOD_1);
  1158. intp->chip_id = stv0900_read_reg(intp, R0900_MID);
  1159. intp->rolloff = p_init->rolloff;
  1160. intp->quartz = p_init->dmd_ref_clk;
  1161. stv0900_write_bits(intp, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
  1162. stv0900_write_bits(intp, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
  1163. intp->ts_config = p_init->ts_config;
  1164. if (intp->ts_config == NULL)
  1165. stv0900_set_ts_parallel_serial(intp,
  1166. p_init->path1_ts_clock,
  1167. p_init->path2_ts_clock);
  1168. else {
  1169. for (i = 0; intp->ts_config[i].addr != 0xffff; i++)
  1170. stv0900_write_reg(intp,
  1171. intp->ts_config[i].addr,
  1172. intp->ts_config[i].val);
  1173. stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
  1174. stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
  1175. stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
  1176. stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
  1177. }
  1178. stv0900_write_bits(intp, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
  1179. switch (p_init->tuner1_adc) {
  1180. case 1:
  1181. stv0900_write_reg(intp, R0900_TSTTNR1, 0x26);
  1182. break;
  1183. default:
  1184. break;
  1185. }
  1186. stv0900_write_bits(intp, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
  1187. switch (p_init->tuner2_adc) {
  1188. case 1:
  1189. stv0900_write_reg(intp, R0900_TSTTNR3, 0x26);
  1190. break;
  1191. default:
  1192. break;
  1193. }
  1194. stv0900_write_bits(intp, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inv);
  1195. stv0900_write_bits(intp, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inv);
  1196. stv0900_set_mclk(intp, 135000000);
  1197. msleep(3);
  1198. switch (intp->clkmode) {
  1199. case 0:
  1200. case 2:
  1201. stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | intp->clkmode);
  1202. break;
  1203. default:
  1204. selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
  1205. stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | selosci);
  1206. break;
  1207. }
  1208. msleep(3);
  1209. intp->mclk = stv0900_get_mclk_freq(intp, intp->quartz);
  1210. if (intp->errs)
  1211. error = STV0900_I2C_ERROR;
  1212. return error;
  1213. }
  1214. static int stv0900_status(struct stv0900_internal *intp,
  1215. enum fe_stv0900_demod_num demod)
  1216. {
  1217. enum fe_stv0900_search_state demod_state;
  1218. int locked = FALSE;
  1219. u8 tsbitrate0_val, tsbitrate1_val;
  1220. s32 bitrate;
  1221. demod_state = stv0900_get_bits(intp, HEADER_MODE);
  1222. switch (demod_state) {
  1223. case STV0900_SEARCH:
  1224. case STV0900_PLH_DETECTED:
  1225. default:
  1226. locked = FALSE;
  1227. break;
  1228. case STV0900_DVBS2_FOUND:
  1229. locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
  1230. stv0900_get_bits(intp, PKTDELIN_LOCK) &&
  1231. stv0900_get_bits(intp, TSFIFO_LINEOK);
  1232. break;
  1233. case STV0900_DVBS_FOUND:
  1234. locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
  1235. stv0900_get_bits(intp, LOCKEDVIT) &&
  1236. stv0900_get_bits(intp, TSFIFO_LINEOK);
  1237. break;
  1238. }
  1239. dprintk("%s: locked = %d\n", __func__, locked);
  1240. if (stvdebug) {
  1241. /* Print TS bitrate */
  1242. tsbitrate0_val = stv0900_read_reg(intp, TSBITRATE0);
  1243. tsbitrate1_val = stv0900_read_reg(intp, TSBITRATE1);
  1244. /* Formula Bit rate = Mclk * px_tsfifo_bitrate / 16384 */
  1245. bitrate = (stv0900_get_mclk_freq(intp, intp->quartz)/1000000)
  1246. * (tsbitrate1_val << 8 | tsbitrate0_val);
  1247. bitrate /= 16384;
  1248. dprintk("TS bitrate = %d Mbit/sec \n", bitrate);
  1249. };
  1250. return locked;
  1251. }
  1252. static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
  1253. struct dvb_frontend_parameters *params)
  1254. {
  1255. struct stv0900_state *state = fe->demodulator_priv;
  1256. struct stv0900_internal *intp = state->internal;
  1257. enum fe_stv0900_demod_num demod = state->demod;
  1258. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1259. struct stv0900_search_params p_search;
  1260. struct stv0900_signal_info p_result;
  1261. enum fe_stv0900_error error = STV0900_NO_ERROR;
  1262. dprintk("%s: ", __func__);
  1263. if (!(INRANGE(100000, c->symbol_rate, 70000000)))
  1264. return DVBFE_ALGO_SEARCH_FAILED;
  1265. if (state->config->set_ts_params)
  1266. state->config->set_ts_params(fe, 0);
  1267. p_result.locked = FALSE;
  1268. p_search.path = demod;
  1269. p_search.frequency = c->frequency;
  1270. p_search.symbol_rate = c->symbol_rate;
  1271. p_search.search_range = 10000000;
  1272. p_search.fec = STV0900_FEC_UNKNOWN;
  1273. p_search.standard = STV0900_AUTO_SEARCH;
  1274. p_search.iq_inversion = STV0900_IQ_AUTO;
  1275. p_search.search_algo = STV0900_BLIND_SEARCH;
  1276. intp->srch_standard[demod] = p_search.standard;
  1277. intp->symbol_rate[demod] = p_search.symbol_rate;
  1278. intp->srch_range[demod] = p_search.search_range;
  1279. intp->freq[demod] = p_search.frequency;
  1280. intp->srch_algo[demod] = p_search.search_algo;
  1281. intp->srch_iq_inv[demod] = p_search.iq_inversion;
  1282. intp->fec[demod] = p_search.fec;
  1283. if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
  1284. (intp->errs == STV0900_NO_ERROR)) {
  1285. p_result.locked = intp->result[demod].locked;
  1286. p_result.standard = intp->result[demod].standard;
  1287. p_result.frequency = intp->result[demod].frequency;
  1288. p_result.symbol_rate = intp->result[demod].symbol_rate;
  1289. p_result.fec = intp->result[demod].fec;
  1290. p_result.modcode = intp->result[demod].modcode;
  1291. p_result.pilot = intp->result[demod].pilot;
  1292. p_result.frame_len = intp->result[demod].frame_len;
  1293. p_result.spectrum = intp->result[demod].spectrum;
  1294. p_result.rolloff = intp->result[demod].rolloff;
  1295. p_result.modulation = intp->result[demod].modulation;
  1296. } else {
  1297. p_result.locked = FALSE;
  1298. switch (intp->err[demod]) {
  1299. case STV0900_I2C_ERROR:
  1300. error = STV0900_I2C_ERROR;
  1301. break;
  1302. case STV0900_NO_ERROR:
  1303. default:
  1304. error = STV0900_SEARCH_FAILED;
  1305. break;
  1306. }
  1307. }
  1308. if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
  1309. dprintk("Search Success\n");
  1310. return DVBFE_ALGO_SEARCH_SUCCESS;
  1311. } else {
  1312. dprintk("Search Fail\n");
  1313. return DVBFE_ALGO_SEARCH_FAILED;
  1314. }
  1315. }
  1316. static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
  1317. {
  1318. struct stv0900_state *state = fe->demodulator_priv;
  1319. dprintk("%s: ", __func__);
  1320. if ((stv0900_status(state->internal, state->demod)) == TRUE) {
  1321. dprintk("DEMOD LOCK OK\n");
  1322. *status = FE_HAS_CARRIER
  1323. | FE_HAS_VITERBI
  1324. | FE_HAS_SYNC
  1325. | FE_HAS_LOCK;
  1326. } else
  1327. dprintk("DEMOD LOCK FAIL\n");
  1328. return 0;
  1329. }
  1330. static int stv0900_track(struct dvb_frontend *fe,
  1331. struct dvb_frontend_parameters *p)
  1332. {
  1333. return 0;
  1334. }
  1335. static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
  1336. {
  1337. struct stv0900_state *state = fe->demodulator_priv;
  1338. struct stv0900_internal *intp = state->internal;
  1339. enum fe_stv0900_demod_num demod = state->demod;
  1340. if (stop_ts == TRUE)
  1341. stv0900_write_bits(intp, RST_HWARE, 1);
  1342. else
  1343. stv0900_write_bits(intp, RST_HWARE, 0);
  1344. return 0;
  1345. }
  1346. static int stv0900_diseqc_init(struct dvb_frontend *fe)
  1347. {
  1348. struct stv0900_state *state = fe->demodulator_priv;
  1349. struct stv0900_internal *intp = state->internal;
  1350. enum fe_stv0900_demod_num demod = state->demod;
  1351. stv0900_write_bits(intp, DISTX_MODE, state->config->diseqc_mode);
  1352. stv0900_write_bits(intp, DISEQC_RESET, 1);
  1353. stv0900_write_bits(intp, DISEQC_RESET, 0);
  1354. return 0;
  1355. }
  1356. static int stv0900_init(struct dvb_frontend *fe)
  1357. {
  1358. dprintk("%s\n", __func__);
  1359. stv0900_stop_ts(fe, 1);
  1360. stv0900_diseqc_init(fe);
  1361. return 0;
  1362. }
  1363. static int stv0900_diseqc_send(struct stv0900_internal *intp , u8 *data,
  1364. u32 NbData, enum fe_stv0900_demod_num demod)
  1365. {
  1366. s32 i = 0;
  1367. stv0900_write_bits(intp, DIS_PRECHARGE, 1);
  1368. while (i < NbData) {
  1369. while (stv0900_get_bits(intp, FIFO_FULL))
  1370. ;/* checkpatch complains */
  1371. stv0900_write_reg(intp, DISTXDATA, data[i]);
  1372. i++;
  1373. }
  1374. stv0900_write_bits(intp, DIS_PRECHARGE, 0);
  1375. i = 0;
  1376. while ((stv0900_get_bits(intp, TX_IDLE) != 1) && (i < 10)) {
  1377. msleep(10);
  1378. i++;
  1379. }
  1380. return 0;
  1381. }
  1382. static int stv0900_send_master_cmd(struct dvb_frontend *fe,
  1383. struct dvb_diseqc_master_cmd *cmd)
  1384. {
  1385. struct stv0900_state *state = fe->demodulator_priv;
  1386. return stv0900_diseqc_send(state->internal,
  1387. cmd->msg,
  1388. cmd->msg_len,
  1389. state->demod);
  1390. }
  1391. static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
  1392. {
  1393. struct stv0900_state *state = fe->demodulator_priv;
  1394. struct stv0900_internal *intp = state->internal;
  1395. enum fe_stv0900_demod_num demod = state->demod;
  1396. u8 data;
  1397. switch (burst) {
  1398. case SEC_MINI_A:
  1399. stv0900_write_bits(intp, DISTX_MODE, 3);/* Unmodulated */
  1400. data = 0x00;
  1401. stv0900_diseqc_send(intp, &data, 1, state->demod);
  1402. break;
  1403. case SEC_MINI_B:
  1404. stv0900_write_bits(intp, DISTX_MODE, 2);/* Modulated */
  1405. data = 0xff;
  1406. stv0900_diseqc_send(intp, &data, 1, state->demod);
  1407. break;
  1408. }
  1409. return 0;
  1410. }
  1411. static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
  1412. struct dvb_diseqc_slave_reply *reply)
  1413. {
  1414. struct stv0900_state *state = fe->demodulator_priv;
  1415. struct stv0900_internal *intp = state->internal;
  1416. enum fe_stv0900_demod_num demod = state->demod;
  1417. s32 i = 0;
  1418. reply->msg_len = 0;
  1419. while ((stv0900_get_bits(intp, RX_END) != 1) && (i < 10)) {
  1420. msleep(10);
  1421. i++;
  1422. }
  1423. if (stv0900_get_bits(intp, RX_END)) {
  1424. reply->msg_len = stv0900_get_bits(intp, FIFO_BYTENBR);
  1425. for (i = 0; i < reply->msg_len; i++)
  1426. reply->msg[i] = stv0900_read_reg(intp, DISRXDATA);
  1427. }
  1428. return 0;
  1429. }
  1430. static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t toneoff)
  1431. {
  1432. struct stv0900_state *state = fe->demodulator_priv;
  1433. struct stv0900_internal *intp = state->internal;
  1434. enum fe_stv0900_demod_num demod = state->demod;
  1435. dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off"));
  1436. switch (toneoff) {
  1437. case SEC_TONE_ON:
  1438. /*Set the DiseqC mode to 22Khz _continues_ tone*/
  1439. stv0900_write_bits(intp, DISTX_MODE, 0);
  1440. stv0900_write_bits(intp, DISEQC_RESET, 1);
  1441. /*release DiseqC reset to enable the 22KHz tone*/
  1442. stv0900_write_bits(intp, DISEQC_RESET, 0);
  1443. break;
  1444. case SEC_TONE_OFF:
  1445. /*return diseqc mode to config->diseqc_mode.
  1446. Usually it's without _continues_ tone */
  1447. stv0900_write_bits(intp, DISTX_MODE,
  1448. state->config->diseqc_mode);
  1449. /*maintain the DiseqC reset to disable the 22KHz tone*/
  1450. stv0900_write_bits(intp, DISEQC_RESET, 1);
  1451. stv0900_write_bits(intp, DISEQC_RESET, 0);
  1452. break;
  1453. default:
  1454. return -EINVAL;
  1455. }
  1456. return 0;
  1457. }
  1458. static void stv0900_release(struct dvb_frontend *fe)
  1459. {
  1460. struct stv0900_state *state = fe->demodulator_priv;
  1461. dprintk("%s\n", __func__);
  1462. if ((--(state->internal->dmds_used)) <= 0) {
  1463. dprintk("%s: Actually removing\n", __func__);
  1464. remove_inode(state->internal);
  1465. kfree(state->internal);
  1466. }
  1467. kfree(state);
  1468. }
  1469. static struct dvb_frontend_ops stv0900_ops = {
  1470. .info = {
  1471. .name = "STV0900 frontend",
  1472. .type = FE_QPSK,
  1473. .frequency_min = 950000,
  1474. .frequency_max = 2150000,
  1475. .frequency_stepsize = 125,
  1476. .frequency_tolerance = 0,
  1477. .symbol_rate_min = 1000000,
  1478. .symbol_rate_max = 45000000,
  1479. .symbol_rate_tolerance = 500,
  1480. .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
  1481. FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
  1482. FE_CAN_FEC_7_8 | FE_CAN_QPSK |
  1483. FE_CAN_2G_MODULATION |
  1484. FE_CAN_FEC_AUTO
  1485. },
  1486. .release = stv0900_release,
  1487. .init = stv0900_init,
  1488. .get_frontend_algo = stv0900_frontend_algo,
  1489. .i2c_gate_ctrl = stv0900_i2c_gate_ctrl,
  1490. .diseqc_send_master_cmd = stv0900_send_master_cmd,
  1491. .diseqc_send_burst = stv0900_send_burst,
  1492. .diseqc_recv_slave_reply = stv0900_recv_slave_reply,
  1493. .set_tone = stv0900_set_tone,
  1494. .set_property = stb0900_set_property,
  1495. .get_property = stb0900_get_property,
  1496. .search = stv0900_search,
  1497. .track = stv0900_track,
  1498. .read_status = stv0900_read_status,
  1499. .read_ber = stv0900_read_ber,
  1500. .read_signal_strength = stv0900_read_signal_strength,
  1501. .read_snr = stv0900_read_snr,
  1502. .read_ucblocks = stv0900_read_ucblocks,
  1503. };
  1504. struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
  1505. struct i2c_adapter *i2c,
  1506. int demod)
  1507. {
  1508. struct stv0900_state *state = NULL;
  1509. struct stv0900_init_params init_params;
  1510. enum fe_stv0900_error err_stv0900;
  1511. state = kzalloc(sizeof(struct stv0900_state), GFP_KERNEL);
  1512. if (state == NULL)
  1513. goto error;
  1514. state->demod = demod;
  1515. state->config = config;
  1516. state->i2c_adap = i2c;
  1517. memcpy(&state->frontend.ops, &stv0900_ops,
  1518. sizeof(struct dvb_frontend_ops));
  1519. state->frontend.demodulator_priv = state;
  1520. switch (demod) {
  1521. case 0:
  1522. case 1:
  1523. init_params.dmd_ref_clk = config->xtal;
  1524. init_params.demod_mode = config->demod_mode;
  1525. init_params.rolloff = STV0900_35;
  1526. init_params.path1_ts_clock = config->path1_mode;
  1527. init_params.tun1_maddress = config->tun1_maddress;
  1528. init_params.tun1_iq_inv = STV0900_IQ_NORMAL;
  1529. init_params.tuner1_adc = config->tun1_adc;
  1530. init_params.path2_ts_clock = config->path2_mode;
  1531. init_params.ts_config = config->ts_config_regs;
  1532. init_params.tun2_maddress = config->tun2_maddress;
  1533. init_params.tuner2_adc = config->tun2_adc;
  1534. init_params.tun2_iq_inv = STV0900_IQ_SWAPPED;
  1535. err_stv0900 = stv0900_init_internal(&state->frontend,
  1536. &init_params);
  1537. if (err_stv0900)
  1538. goto error;
  1539. break;
  1540. default:
  1541. goto error;
  1542. break;
  1543. }
  1544. dprintk("%s: Attaching STV0900 demodulator(%d) \n", __func__, demod);
  1545. return &state->frontend;
  1546. error:
  1547. dprintk("%s: Failed to attach STV0900 demodulator(%d) \n",
  1548. __func__, demod);
  1549. kfree(state);
  1550. return NULL;
  1551. }
  1552. EXPORT_SYMBOL(stv0900_attach);
  1553. MODULE_PARM_DESC(debug, "Set debug");
  1554. MODULE_AUTHOR("Igor M. Liplianin");
  1555. MODULE_DESCRIPTION("ST STV0900 frontend");
  1556. MODULE_LICENSE("GPL");