nes_utils.c 31 KB

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  1. /*
  2. * Copyright (c) 2006 - 2009 Intel Corporation. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. */
  33. #include <linux/module.h>
  34. #include <linux/moduleparam.h>
  35. #include <linux/netdevice.h>
  36. #include <linux/etherdevice.h>
  37. #include <linux/ethtool.h>
  38. #include <linux/mii.h>
  39. #include <linux/if_vlan.h>
  40. #include <linux/crc32.h>
  41. #include <linux/in.h>
  42. #include <linux/ip.h>
  43. #include <linux/tcp.h>
  44. #include <linux/init.h>
  45. #include <asm/io.h>
  46. #include <asm/irq.h>
  47. #include <asm/byteorder.h>
  48. #include "nes.h"
  49. static u16 nes_read16_eeprom(void __iomem *addr, u16 offset);
  50. u32 mh_detected;
  51. u32 mh_pauses_sent;
  52. /**
  53. * nes_read_eeprom_values -
  54. */
  55. int nes_read_eeprom_values(struct nes_device *nesdev, struct nes_adapter *nesadapter)
  56. {
  57. u32 mac_addr_low;
  58. u16 mac_addr_high;
  59. u16 eeprom_data;
  60. u16 eeprom_offset;
  61. u16 next_section_address;
  62. u16 sw_section_ver;
  63. u8 major_ver = 0;
  64. u8 minor_ver = 0;
  65. /* TODO: deal with EEPROM endian issues */
  66. if (nesadapter->firmware_eeprom_offset == 0) {
  67. /* Read the EEPROM Parameters */
  68. eeprom_data = nes_read16_eeprom(nesdev->regs, 0);
  69. nes_debug(NES_DBG_HW, "EEPROM Offset 0 = 0x%04X\n", eeprom_data);
  70. eeprom_offset = 2 + (((eeprom_data & 0x007f) << 3) <<
  71. ((eeprom_data & 0x0080) >> 7));
  72. nes_debug(NES_DBG_HW, "Firmware Offset = 0x%04X\n", eeprom_offset);
  73. nesadapter->firmware_eeprom_offset = eeprom_offset;
  74. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
  75. if (eeprom_data != 0x5746) {
  76. nes_debug(NES_DBG_HW, "Not a valid Firmware Image = 0x%04X\n", eeprom_data);
  77. return -1;
  78. }
  79. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  80. nes_debug(NES_DBG_HW, "EEPROM Offset %u = 0x%04X\n",
  81. eeprom_offset + 2, eeprom_data);
  82. eeprom_offset += ((eeprom_data & 0x00ff) << 3) << ((eeprom_data & 0x0100) >> 8);
  83. nes_debug(NES_DBG_HW, "Software Offset = 0x%04X\n", eeprom_offset);
  84. nesadapter->software_eeprom_offset = eeprom_offset;
  85. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
  86. if (eeprom_data != 0x5753) {
  87. printk("Not a valid Software Image = 0x%04X\n", eeprom_data);
  88. return -1;
  89. }
  90. sw_section_ver = nes_read16_eeprom(nesdev->regs, nesadapter->software_eeprom_offset + 6);
  91. nes_debug(NES_DBG_HW, "Software section version number = 0x%04X\n",
  92. sw_section_ver);
  93. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  94. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  95. eeprom_offset + 2, eeprom_data);
  96. next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
  97. ((eeprom_data & 0x0100) >> 8));
  98. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  99. if (eeprom_data != 0x414d) {
  100. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
  101. eeprom_data);
  102. goto no_fw_rev;
  103. }
  104. eeprom_offset = next_section_address;
  105. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  106. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  107. eeprom_offset + 2, eeprom_data);
  108. next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
  109. ((eeprom_data & 0x0100) >> 8));
  110. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  111. if (eeprom_data != 0x4f52) {
  112. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x4f52 but was 0x%04X\n",
  113. eeprom_data);
  114. goto no_fw_rev;
  115. }
  116. eeprom_offset = next_section_address;
  117. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  118. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  119. eeprom_offset + 2, eeprom_data);
  120. next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
  121. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  122. if (eeprom_data != 0x5746) {
  123. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5746 but was 0x%04X\n",
  124. eeprom_data);
  125. goto no_fw_rev;
  126. }
  127. eeprom_offset = next_section_address;
  128. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  129. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  130. eeprom_offset + 2, eeprom_data);
  131. next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
  132. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  133. if (eeprom_data != 0x5753) {
  134. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5753 but was 0x%04X\n",
  135. eeprom_data);
  136. goto no_fw_rev;
  137. }
  138. eeprom_offset = next_section_address;
  139. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  140. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  141. eeprom_offset + 2, eeprom_data);
  142. next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
  143. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  144. if (eeprom_data != 0x414d) {
  145. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
  146. eeprom_data);
  147. goto no_fw_rev;
  148. }
  149. eeprom_offset = next_section_address;
  150. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  151. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  152. eeprom_offset + 2, eeprom_data);
  153. next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
  154. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  155. if (eeprom_data != 0x464e) {
  156. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x464e but was 0x%04X\n",
  157. eeprom_data);
  158. goto no_fw_rev;
  159. }
  160. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 8);
  161. printk(PFX "Firmware version %u.%u\n", (u8)(eeprom_data>>8), (u8)eeprom_data);
  162. major_ver = (u8)(eeprom_data >> 8);
  163. minor_ver = (u8)(eeprom_data);
  164. if (nes_drv_opt & NES_DRV_OPT_DISABLE_VIRT_WQ) {
  165. nes_debug(NES_DBG_HW, "Virtual WQs have been disabled\n");
  166. } else if (((major_ver == 2) && (minor_ver > 21)) || ((major_ver > 2) && (major_ver != 255))) {
  167. nesadapter->virtwq = 1;
  168. }
  169. if (((major_ver == 3) && (minor_ver >= 16)) || (major_ver > 3))
  170. nesadapter->send_term_ok = 1;
  171. nesadapter->firmware_version = (((u32)(u8)(eeprom_data>>8)) << 16) +
  172. (u32)((u8)eeprom_data);
  173. no_fw_rev:
  174. /* eeprom is valid */
  175. eeprom_offset = nesadapter->software_eeprom_offset;
  176. eeprom_offset += 8;
  177. nesadapter->netdev_max = (u8)nes_read16_eeprom(nesdev->regs, eeprom_offset);
  178. eeprom_offset += 2;
  179. mac_addr_high = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  180. eeprom_offset += 2;
  181. mac_addr_low = (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
  182. eeprom_offset += 2;
  183. mac_addr_low <<= 16;
  184. mac_addr_low += (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
  185. nes_debug(NES_DBG_HW, "Base MAC Address = 0x%04X%08X\n",
  186. mac_addr_high, mac_addr_low);
  187. nes_debug(NES_DBG_HW, "MAC Address count = %u\n", nesadapter->netdev_max);
  188. nesadapter->mac_addr_low = mac_addr_low;
  189. nesadapter->mac_addr_high = mac_addr_high;
  190. /* Read the Phy Type array */
  191. eeprom_offset += 10;
  192. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  193. nesadapter->phy_type[0] = (u8)(eeprom_data >> 8);
  194. nesadapter->phy_type[1] = (u8)eeprom_data;
  195. /* Read the port array */
  196. eeprom_offset += 2;
  197. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  198. nesadapter->phy_type[2] = (u8)(eeprom_data >> 8);
  199. nesadapter->phy_type[3] = (u8)eeprom_data;
  200. /* port_count is set by soft reset reg */
  201. nes_debug(NES_DBG_HW, "port_count = %u, port 0 -> %u, port 1 -> %u,"
  202. " port 2 -> %u, port 3 -> %u\n",
  203. nesadapter->port_count,
  204. nesadapter->phy_type[0], nesadapter->phy_type[1],
  205. nesadapter->phy_type[2], nesadapter->phy_type[3]);
  206. /* Read PD config array */
  207. eeprom_offset += 10;
  208. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  209. nesadapter->pd_config_size[0] = eeprom_data;
  210. eeprom_offset += 2;
  211. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  212. nesadapter->pd_config_base[0] = eeprom_data;
  213. nes_debug(NES_DBG_HW, "PD0 config, size=0x%04x, base=0x%04x\n",
  214. nesadapter->pd_config_size[0], nesadapter->pd_config_base[0]);
  215. eeprom_offset += 2;
  216. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  217. nesadapter->pd_config_size[1] = eeprom_data;
  218. eeprom_offset += 2;
  219. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  220. nesadapter->pd_config_base[1] = eeprom_data;
  221. nes_debug(NES_DBG_HW, "PD1 config, size=0x%04x, base=0x%04x\n",
  222. nesadapter->pd_config_size[1], nesadapter->pd_config_base[1]);
  223. eeprom_offset += 2;
  224. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  225. nesadapter->pd_config_size[2] = eeprom_data;
  226. eeprom_offset += 2;
  227. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  228. nesadapter->pd_config_base[2] = eeprom_data;
  229. nes_debug(NES_DBG_HW, "PD2 config, size=0x%04x, base=0x%04x\n",
  230. nesadapter->pd_config_size[2], nesadapter->pd_config_base[2]);
  231. eeprom_offset += 2;
  232. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  233. nesadapter->pd_config_size[3] = eeprom_data;
  234. eeprom_offset += 2;
  235. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  236. nesadapter->pd_config_base[3] = eeprom_data;
  237. nes_debug(NES_DBG_HW, "PD3 config, size=0x%04x, base=0x%04x\n",
  238. nesadapter->pd_config_size[3], nesadapter->pd_config_base[3]);
  239. /* Read Rx Pool Size */
  240. eeprom_offset += 22; /* 46 */
  241. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  242. eeprom_offset += 2;
  243. nesadapter->rx_pool_size = (((u32)eeprom_data) << 16) +
  244. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  245. nes_debug(NES_DBG_HW, "rx_pool_size = 0x%08X\n", nesadapter->rx_pool_size);
  246. eeprom_offset += 2;
  247. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  248. eeprom_offset += 2;
  249. nesadapter->tx_pool_size = (((u32)eeprom_data) << 16) +
  250. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  251. nes_debug(NES_DBG_HW, "tx_pool_size = 0x%08X\n", nesadapter->tx_pool_size);
  252. eeprom_offset += 2;
  253. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  254. eeprom_offset += 2;
  255. nesadapter->rx_threshold = (((u32)eeprom_data) << 16) +
  256. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  257. nes_debug(NES_DBG_HW, "rx_threshold = 0x%08X\n", nesadapter->rx_threshold);
  258. eeprom_offset += 2;
  259. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  260. eeprom_offset += 2;
  261. nesadapter->tcp_timer_core_clk_divisor = (((u32)eeprom_data) << 16) +
  262. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  263. nes_debug(NES_DBG_HW, "tcp_timer_core_clk_divisor = 0x%08X\n",
  264. nesadapter->tcp_timer_core_clk_divisor);
  265. eeprom_offset += 2;
  266. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  267. eeprom_offset += 2;
  268. nesadapter->iwarp_config = (((u32)eeprom_data) << 16) +
  269. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  270. nes_debug(NES_DBG_HW, "iwarp_config = 0x%08X\n", nesadapter->iwarp_config);
  271. eeprom_offset += 2;
  272. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  273. eeprom_offset += 2;
  274. nesadapter->cm_config = (((u32)eeprom_data) << 16) +
  275. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  276. nes_debug(NES_DBG_HW, "cm_config = 0x%08X\n", nesadapter->cm_config);
  277. eeprom_offset += 2;
  278. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  279. eeprom_offset += 2;
  280. nesadapter->sws_timer_config = (((u32)eeprom_data) << 16) +
  281. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  282. nes_debug(NES_DBG_HW, "sws_timer_config = 0x%08X\n", nesadapter->sws_timer_config);
  283. eeprom_offset += 2;
  284. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  285. eeprom_offset += 2;
  286. nesadapter->tcp_config1 = (((u32)eeprom_data) << 16) +
  287. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  288. nes_debug(NES_DBG_HW, "tcp_config1 = 0x%08X\n", nesadapter->tcp_config1);
  289. eeprom_offset += 2;
  290. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  291. eeprom_offset += 2;
  292. nesadapter->wqm_wat = (((u32)eeprom_data) << 16) +
  293. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  294. nes_debug(NES_DBG_HW, "wqm_wat = 0x%08X\n", nesadapter->wqm_wat);
  295. eeprom_offset += 2;
  296. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  297. eeprom_offset += 2;
  298. nesadapter->core_clock = (((u32)eeprom_data) << 16) +
  299. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  300. nes_debug(NES_DBG_HW, "core_clock = 0x%08X\n", nesadapter->core_clock);
  301. if ((sw_section_ver) && (nesadapter->hw_rev != NE020_REV)) {
  302. eeprom_offset += 2;
  303. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  304. nesadapter->phy_index[0] = (eeprom_data & 0xff00)>>8;
  305. nesadapter->phy_index[1] = eeprom_data & 0x00ff;
  306. eeprom_offset += 2;
  307. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  308. nesadapter->phy_index[2] = (eeprom_data & 0xff00)>>8;
  309. nesadapter->phy_index[3] = eeprom_data & 0x00ff;
  310. } else {
  311. nesadapter->phy_index[0] = 4;
  312. nesadapter->phy_index[1] = 5;
  313. nesadapter->phy_index[2] = 6;
  314. nesadapter->phy_index[3] = 7;
  315. }
  316. nes_debug(NES_DBG_HW, "Phy address map = 0 > %u, 1 > %u, 2 > %u, 3 > %u\n",
  317. nesadapter->phy_index[0],nesadapter->phy_index[1],
  318. nesadapter->phy_index[2],nesadapter->phy_index[3]);
  319. }
  320. return 0;
  321. }
  322. /**
  323. * nes_read16_eeprom
  324. */
  325. static u16 nes_read16_eeprom(void __iomem *addr, u16 offset)
  326. {
  327. writel(NES_EEPROM_READ_REQUEST + (offset >> 1),
  328. (void __iomem *)addr + NES_EEPROM_COMMAND);
  329. do {
  330. } while (readl((void __iomem *)addr + NES_EEPROM_COMMAND) &
  331. NES_EEPROM_READ_REQUEST);
  332. return readw((void __iomem *)addr + NES_EEPROM_DATA);
  333. }
  334. /**
  335. * nes_write_1G_phy_reg
  336. */
  337. void nes_write_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 data)
  338. {
  339. struct nes_adapter *nesadapter = nesdev->nesadapter;
  340. u32 u32temp;
  341. u32 counter;
  342. unsigned long flags;
  343. spin_lock_irqsave(&nesadapter->phy_lock, flags);
  344. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  345. 0x50020000 | data | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
  346. for (counter = 0; counter < 100 ; counter++) {
  347. udelay(30);
  348. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  349. if (u32temp & 1) {
  350. /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
  351. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  352. break;
  353. }
  354. }
  355. if (!(u32temp & 1))
  356. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  357. u32temp);
  358. spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
  359. }
  360. /**
  361. * nes_read_1G_phy_reg
  362. * This routine only issues the read, the data must be read
  363. * separately.
  364. */
  365. void nes_read_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 *data)
  366. {
  367. struct nes_adapter *nesadapter = nesdev->nesadapter;
  368. u32 u32temp;
  369. u32 counter;
  370. unsigned long flags;
  371. /* nes_debug(NES_DBG_PHY, "phy addr = %d, mac_index = %d\n",
  372. phy_addr, nesdev->mac_index); */
  373. spin_lock_irqsave(&nesadapter->phy_lock, flags);
  374. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  375. 0x60020000 | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
  376. for (counter = 0; counter < 100 ; counter++) {
  377. udelay(30);
  378. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  379. if (u32temp & 1) {
  380. /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
  381. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  382. break;
  383. }
  384. }
  385. if (!(u32temp & 1)) {
  386. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  387. u32temp);
  388. *data = 0xffff;
  389. } else {
  390. *data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
  391. }
  392. spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
  393. }
  394. /**
  395. * nes_write_10G_phy_reg
  396. */
  397. void nes_write_10G_phy_reg(struct nes_device *nesdev, u16 phy_addr, u8 dev_addr, u16 phy_reg,
  398. u16 data)
  399. {
  400. u32 port_addr;
  401. u32 u32temp;
  402. u32 counter;
  403. port_addr = phy_addr;
  404. /* set address */
  405. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  406. 0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
  407. for (counter = 0; counter < 100 ; counter++) {
  408. udelay(30);
  409. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  410. if (u32temp & 1) {
  411. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  412. break;
  413. }
  414. }
  415. if (!(u32temp & 1))
  416. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  417. u32temp);
  418. /* set data */
  419. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  420. 0x10020000 | (u32)data | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
  421. for (counter = 0; counter < 100 ; counter++) {
  422. udelay(30);
  423. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  424. if (u32temp & 1) {
  425. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  426. break;
  427. }
  428. }
  429. if (!(u32temp & 1))
  430. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  431. u32temp);
  432. }
  433. /**
  434. * nes_read_10G_phy_reg
  435. * This routine only issues the read, the data must be read
  436. * separately.
  437. */
  438. void nes_read_10G_phy_reg(struct nes_device *nesdev, u8 phy_addr, u8 dev_addr, u16 phy_reg)
  439. {
  440. u32 port_addr;
  441. u32 u32temp;
  442. u32 counter;
  443. port_addr = phy_addr;
  444. /* set address */
  445. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  446. 0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
  447. for (counter = 0; counter < 100 ; counter++) {
  448. udelay(30);
  449. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  450. if (u32temp & 1) {
  451. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  452. break;
  453. }
  454. }
  455. if (!(u32temp & 1))
  456. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  457. u32temp);
  458. /* issue read */
  459. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  460. 0x30020000 | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
  461. for (counter = 0; counter < 100 ; counter++) {
  462. udelay(30);
  463. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  464. if (u32temp & 1) {
  465. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  466. break;
  467. }
  468. }
  469. if (!(u32temp & 1))
  470. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  471. u32temp);
  472. }
  473. /**
  474. * nes_get_cqp_request
  475. */
  476. struct nes_cqp_request *nes_get_cqp_request(struct nes_device *nesdev)
  477. {
  478. unsigned long flags;
  479. struct nes_cqp_request *cqp_request = NULL;
  480. if (!list_empty(&nesdev->cqp_avail_reqs)) {
  481. spin_lock_irqsave(&nesdev->cqp.lock, flags);
  482. if (!list_empty(&nesdev->cqp_avail_reqs)) {
  483. cqp_request = list_entry(nesdev->cqp_avail_reqs.next,
  484. struct nes_cqp_request, list);
  485. list_del_init(&cqp_request->list);
  486. }
  487. spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
  488. }
  489. if (cqp_request == NULL) {
  490. cqp_request = kzalloc(sizeof(struct nes_cqp_request), GFP_ATOMIC);
  491. if (cqp_request) {
  492. cqp_request->dynamic = 1;
  493. INIT_LIST_HEAD(&cqp_request->list);
  494. }
  495. }
  496. if (cqp_request) {
  497. init_waitqueue_head(&cqp_request->waitq);
  498. cqp_request->waiting = 0;
  499. cqp_request->request_done = 0;
  500. cqp_request->callback = 0;
  501. init_waitqueue_head(&cqp_request->waitq);
  502. nes_debug(NES_DBG_CQP, "Got cqp request %p from the available list \n",
  503. cqp_request);
  504. } else
  505. printk(KERN_ERR PFX "%s: Could not allocated a CQP request.\n",
  506. __func__);
  507. return cqp_request;
  508. }
  509. void nes_free_cqp_request(struct nes_device *nesdev,
  510. struct nes_cqp_request *cqp_request)
  511. {
  512. unsigned long flags;
  513. nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) freed.\n",
  514. cqp_request,
  515. le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX]) & 0x3f);
  516. if (cqp_request->dynamic) {
  517. kfree(cqp_request);
  518. } else {
  519. spin_lock_irqsave(&nesdev->cqp.lock, flags);
  520. list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
  521. spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
  522. }
  523. }
  524. void nes_put_cqp_request(struct nes_device *nesdev,
  525. struct nes_cqp_request *cqp_request)
  526. {
  527. if (atomic_dec_and_test(&cqp_request->refcount))
  528. nes_free_cqp_request(nesdev, cqp_request);
  529. }
  530. /**
  531. * nes_post_cqp_request
  532. */
  533. void nes_post_cqp_request(struct nes_device *nesdev,
  534. struct nes_cqp_request *cqp_request)
  535. {
  536. struct nes_hw_cqp_wqe *cqp_wqe;
  537. unsigned long flags;
  538. u32 cqp_head;
  539. u64 u64temp;
  540. spin_lock_irqsave(&nesdev->cqp.lock, flags);
  541. if (((((nesdev->cqp.sq_tail+(nesdev->cqp.sq_size*2))-nesdev->cqp.sq_head) &
  542. (nesdev->cqp.sq_size - 1)) != 1)
  543. && (list_empty(&nesdev->cqp_pending_reqs))) {
  544. cqp_head = nesdev->cqp.sq_head++;
  545. nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
  546. cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
  547. memcpy(cqp_wqe, &cqp_request->cqp_wqe, sizeof(*cqp_wqe));
  548. barrier();
  549. u64temp = (unsigned long)cqp_request;
  550. set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_COMP_SCRATCH_LOW_IDX,
  551. u64temp);
  552. nes_debug(NES_DBG_CQP, "CQP request (opcode 0x%02X), line 1 = 0x%08X put on CQPs SQ,"
  553. " request = %p, cqp_head = %u, cqp_tail = %u, cqp_size = %u,"
  554. " waiting = %d, refcount = %d.\n",
  555. le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f,
  556. le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX]), cqp_request,
  557. nesdev->cqp.sq_head, nesdev->cqp.sq_tail, nesdev->cqp.sq_size,
  558. cqp_request->waiting, atomic_read(&cqp_request->refcount));
  559. barrier();
  560. /* Ring doorbell (1 WQEs) */
  561. nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x01800000 | nesdev->cqp.qp_id);
  562. barrier();
  563. } else {
  564. nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X), line 1 = 0x%08X"
  565. " put on the pending queue.\n",
  566. cqp_request,
  567. le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f,
  568. le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_ID_IDX]));
  569. list_add_tail(&cqp_request->list, &nesdev->cqp_pending_reqs);
  570. }
  571. spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
  572. return;
  573. }
  574. /**
  575. * nes_arp_table
  576. */
  577. int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 action)
  578. {
  579. struct nes_adapter *nesadapter = nesdev->nesadapter;
  580. int arp_index;
  581. int err = 0;
  582. __be32 tmp_addr;
  583. for (arp_index = 0; (u32) arp_index < nesadapter->arp_table_size; arp_index++) {
  584. if (nesadapter->arp_table[arp_index].ip_addr == ip_addr)
  585. break;
  586. }
  587. if (action == NES_ARP_ADD) {
  588. if (arp_index != nesadapter->arp_table_size) {
  589. return -1;
  590. }
  591. arp_index = 0;
  592. err = nes_alloc_resource(nesadapter, nesadapter->allocated_arps,
  593. nesadapter->arp_table_size, (u32 *)&arp_index, &nesadapter->next_arp_index);
  594. if (err) {
  595. nes_debug(NES_DBG_NETDEV, "nes_alloc_resource returned error = %u\n", err);
  596. return err;
  597. }
  598. nes_debug(NES_DBG_NETDEV, "ADD, arp_index=%d\n", arp_index);
  599. nesadapter->arp_table[arp_index].ip_addr = ip_addr;
  600. memcpy(nesadapter->arp_table[arp_index].mac_addr, mac_addr, ETH_ALEN);
  601. return arp_index;
  602. }
  603. /* DELETE or RESOLVE */
  604. if (arp_index == nesadapter->arp_table_size) {
  605. tmp_addr = cpu_to_be32(ip_addr);
  606. nes_debug(NES_DBG_NETDEV, "MAC for %pI4 not in ARP table - cannot %s\n",
  607. &tmp_addr, action == NES_ARP_RESOLVE ? "resolve" : "delete");
  608. return -1;
  609. }
  610. if (action == NES_ARP_RESOLVE) {
  611. nes_debug(NES_DBG_NETDEV, "RESOLVE, arp_index=%d\n", arp_index);
  612. return arp_index;
  613. }
  614. if (action == NES_ARP_DELETE) {
  615. nes_debug(NES_DBG_NETDEV, "DELETE, arp_index=%d\n", arp_index);
  616. nesadapter->arp_table[arp_index].ip_addr = 0;
  617. memset(nesadapter->arp_table[arp_index].mac_addr, 0x00, ETH_ALEN);
  618. nes_free_resource(nesadapter, nesadapter->allocated_arps, arp_index);
  619. return arp_index;
  620. }
  621. return -1;
  622. }
  623. /**
  624. * nes_mh_fix
  625. */
  626. void nes_mh_fix(unsigned long parm)
  627. {
  628. unsigned long flags;
  629. struct nes_device *nesdev = (struct nes_device *)parm;
  630. struct nes_adapter *nesadapter = nesdev->nesadapter;
  631. struct nes_vnic *nesvnic;
  632. u32 used_chunks_tx;
  633. u32 temp_used_chunks_tx;
  634. u32 temp_last_used_chunks_tx;
  635. u32 used_chunks_mask;
  636. u32 mac_tx_frames_low;
  637. u32 mac_tx_frames_high;
  638. u32 mac_tx_pauses;
  639. u32 serdes_status;
  640. u32 reset_value;
  641. u32 tx_control;
  642. u32 tx_config;
  643. u32 tx_pause_quanta;
  644. u32 rx_control;
  645. u32 rx_config;
  646. u32 mac_exact_match;
  647. u32 mpp_debug;
  648. u32 i=0;
  649. u32 chunks_tx_progress = 0;
  650. spin_lock_irqsave(&nesadapter->phy_lock, flags);
  651. if ((nesadapter->mac_sw_state[0] != NES_MAC_SW_IDLE) || (nesadapter->mac_link_down[0])) {
  652. spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
  653. goto no_mh_work;
  654. }
  655. nesadapter->mac_sw_state[0] = NES_MAC_SW_MH;
  656. spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
  657. do {
  658. mac_tx_frames_low = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_LOW);
  659. mac_tx_frames_high = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_HIGH);
  660. mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
  661. used_chunks_tx = nes_read_indexed(nesdev, NES_IDX_USED_CHUNKS_TX);
  662. nesdev->mac_pause_frames_sent += mac_tx_pauses;
  663. used_chunks_mask = 0;
  664. temp_used_chunks_tx = used_chunks_tx;
  665. temp_last_used_chunks_tx = nesdev->last_used_chunks_tx;
  666. if (nesdev->netdev[0]) {
  667. nesvnic = netdev_priv(nesdev->netdev[0]);
  668. } else {
  669. break;
  670. }
  671. for (i=0; i<4; i++) {
  672. used_chunks_mask <<= 8;
  673. if (nesvnic->qp_nic_index[i] != 0xff) {
  674. used_chunks_mask |= 0xff;
  675. if ((temp_used_chunks_tx&0xff)<(temp_last_used_chunks_tx&0xff)) {
  676. chunks_tx_progress = 1;
  677. }
  678. }
  679. temp_used_chunks_tx >>= 8;
  680. temp_last_used_chunks_tx >>= 8;
  681. }
  682. if ((mac_tx_frames_low) || (mac_tx_frames_high) ||
  683. (!(used_chunks_tx&used_chunks_mask)) ||
  684. (!(nesdev->last_used_chunks_tx&used_chunks_mask)) ||
  685. (chunks_tx_progress) ) {
  686. nesdev->last_used_chunks_tx = used_chunks_tx;
  687. break;
  688. }
  689. nesdev->last_used_chunks_tx = used_chunks_tx;
  690. barrier();
  691. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000005);
  692. mh_pauses_sent++;
  693. mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
  694. if (mac_tx_pauses) {
  695. nesdev->mac_pause_frames_sent += mac_tx_pauses;
  696. break;
  697. }
  698. tx_control = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONTROL);
  699. tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
  700. tx_pause_quanta = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA);
  701. rx_control = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONTROL);
  702. rx_config = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONFIG);
  703. mac_exact_match = nes_read_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM);
  704. mpp_debug = nes_read_indexed(nesdev, NES_IDX_MPP_DEBUG);
  705. /* one last ditch effort to avoid a false positive */
  706. mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
  707. if (mac_tx_pauses) {
  708. nesdev->last_mac_tx_pauses = nesdev->mac_pause_frames_sent;
  709. nes_debug(NES_DBG_HW, "failsafe caught slow outbound pause\n");
  710. break;
  711. }
  712. mh_detected++;
  713. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000000);
  714. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, 0x00000000);
  715. reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
  716. nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value | 0x0000001d);
  717. while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
  718. & 0x00000040) != 0x00000040) && (i++ < 5000)) {
  719. /* mdelay(1); */
  720. }
  721. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
  722. serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0);
  723. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
  724. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
  725. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE0, 0x0ff00000);
  726. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET0, 0x00000000);
  727. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS0, 0x00000000);
  728. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0, 0x00000000);
  729. if (nesadapter->OneG_Mode) {
  730. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0182222);
  731. } else {
  732. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
  733. }
  734. serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_STATUS0);
  735. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
  736. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, tx_control);
  737. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
  738. nes_write_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA, tx_pause_quanta);
  739. nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONTROL, rx_control);
  740. nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONFIG, rx_config);
  741. nes_write_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM, mac_exact_match);
  742. nes_write_indexed(nesdev, NES_IDX_MPP_DEBUG, mpp_debug);
  743. } while (0);
  744. nesadapter->mac_sw_state[0] = NES_MAC_SW_IDLE;
  745. no_mh_work:
  746. nesdev->nesadapter->mh_timer.expires = jiffies + (HZ/5);
  747. add_timer(&nesdev->nesadapter->mh_timer);
  748. }
  749. /**
  750. * nes_clc
  751. */
  752. void nes_clc(unsigned long parm)
  753. {
  754. unsigned long flags;
  755. struct nes_device *nesdev = (struct nes_device *)parm;
  756. struct nes_adapter *nesadapter = nesdev->nesadapter;
  757. spin_lock_irqsave(&nesadapter->phy_lock, flags);
  758. nesadapter->link_interrupt_count[0] = 0;
  759. nesadapter->link_interrupt_count[1] = 0;
  760. nesadapter->link_interrupt_count[2] = 0;
  761. nesadapter->link_interrupt_count[3] = 0;
  762. spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
  763. nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
  764. add_timer(&nesadapter->lc_timer);
  765. }
  766. /**
  767. * nes_dump_mem
  768. */
  769. void nes_dump_mem(unsigned int dump_debug_level, void *addr, int length)
  770. {
  771. char xlate[] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
  772. 'a', 'b', 'c', 'd', 'e', 'f'};
  773. char *ptr;
  774. char hex_buf[80];
  775. char ascii_buf[20];
  776. int num_char;
  777. int num_ascii;
  778. int num_hex;
  779. if (!(nes_debug_level & dump_debug_level)) {
  780. return;
  781. }
  782. ptr = addr;
  783. if (length > 0x100) {
  784. nes_debug(dump_debug_level, "Length truncated from %x to %x\n", length, 0x100);
  785. length = 0x100;
  786. }
  787. nes_debug(dump_debug_level, "Address=0x%p, length=0x%x (%d)\n", ptr, length, length);
  788. memset(ascii_buf, 0, 20);
  789. memset(hex_buf, 0, 80);
  790. num_ascii = 0;
  791. num_hex = 0;
  792. for (num_char = 0; num_char < length; num_char++) {
  793. if (num_ascii == 8) {
  794. ascii_buf[num_ascii++] = ' ';
  795. hex_buf[num_hex++] = '-';
  796. hex_buf[num_hex++] = ' ';
  797. }
  798. if (*ptr < 0x20 || *ptr > 0x7e)
  799. ascii_buf[num_ascii++] = '.';
  800. else
  801. ascii_buf[num_ascii++] = *ptr;
  802. hex_buf[num_hex++] = xlate[((*ptr & 0xf0) >> 4)];
  803. hex_buf[num_hex++] = xlate[*ptr & 0x0f];
  804. hex_buf[num_hex++] = ' ';
  805. ptr++;
  806. if (num_ascii >= 17) {
  807. /* output line and reset */
  808. nes_debug(dump_debug_level, " %s | %s\n", hex_buf, ascii_buf);
  809. memset(ascii_buf, 0, 20);
  810. memset(hex_buf, 0, 80);
  811. num_ascii = 0;
  812. num_hex = 0;
  813. }
  814. }
  815. /* output the rest */
  816. if (num_ascii) {
  817. while (num_ascii < 17) {
  818. if (num_ascii == 8) {
  819. hex_buf[num_hex++] = ' ';
  820. hex_buf[num_hex++] = ' ';
  821. }
  822. hex_buf[num_hex++] = ' ';
  823. hex_buf[num_hex++] = ' ';
  824. hex_buf[num_hex++] = ' ';
  825. num_ascii++;
  826. }
  827. nes_debug(dump_debug_level, " %s | %s\n", hex_buf, ascii_buf);
  828. }
  829. }