c2.c 33 KB

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  1. /*
  2. * Copyright (c) 2005 Ammasso, Inc. All rights reserved.
  3. * Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/module.h>
  34. #include <linux/moduleparam.h>
  35. #include <linux/pci.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/etherdevice.h>
  38. #include <linux/inetdevice.h>
  39. #include <linux/delay.h>
  40. #include <linux/ethtool.h>
  41. #include <linux/mii.h>
  42. #include <linux/if_vlan.h>
  43. #include <linux/crc32.h>
  44. #include <linux/in.h>
  45. #include <linux/ip.h>
  46. #include <linux/tcp.h>
  47. #include <linux/init.h>
  48. #include <linux/dma-mapping.h>
  49. #include <asm/io.h>
  50. #include <asm/irq.h>
  51. #include <asm/byteorder.h>
  52. #include <rdma/ib_smi.h>
  53. #include "c2.h"
  54. #include "c2_provider.h"
  55. MODULE_AUTHOR("Tom Tucker <tom@opengridcomputing.com>");
  56. MODULE_DESCRIPTION("Ammasso AMSO1100 Low-level iWARP Driver");
  57. MODULE_LICENSE("Dual BSD/GPL");
  58. MODULE_VERSION(DRV_VERSION);
  59. static const u32 default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  60. | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  61. static int debug = -1; /* defaults above */
  62. module_param(debug, int, 0);
  63. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  64. static int c2_up(struct net_device *netdev);
  65. static int c2_down(struct net_device *netdev);
  66. static int c2_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
  67. static void c2_tx_interrupt(struct net_device *netdev);
  68. static void c2_rx_interrupt(struct net_device *netdev);
  69. static irqreturn_t c2_interrupt(int irq, void *dev_id);
  70. static void c2_tx_timeout(struct net_device *netdev);
  71. static int c2_change_mtu(struct net_device *netdev, int new_mtu);
  72. static void c2_reset(struct c2_port *c2_port);
  73. static struct pci_device_id c2_pci_table[] = {
  74. { PCI_DEVICE(0x18b8, 0xb001) },
  75. { 0 }
  76. };
  77. MODULE_DEVICE_TABLE(pci, c2_pci_table);
  78. static void c2_print_macaddr(struct net_device *netdev)
  79. {
  80. pr_debug("%s: MAC %pM, IRQ %u\n", netdev->name, netdev->dev_addr, netdev->irq);
  81. }
  82. static void c2_set_rxbufsize(struct c2_port *c2_port)
  83. {
  84. struct net_device *netdev = c2_port->netdev;
  85. if (netdev->mtu > RX_BUF_SIZE)
  86. c2_port->rx_buf_size =
  87. netdev->mtu + ETH_HLEN + sizeof(struct c2_rxp_hdr) +
  88. NET_IP_ALIGN;
  89. else
  90. c2_port->rx_buf_size = sizeof(struct c2_rxp_hdr) + RX_BUF_SIZE;
  91. }
  92. /*
  93. * Allocate TX ring elements and chain them together.
  94. * One-to-one association of adapter descriptors with ring elements.
  95. */
  96. static int c2_tx_ring_alloc(struct c2_ring *tx_ring, void *vaddr,
  97. dma_addr_t base, void __iomem * mmio_txp_ring)
  98. {
  99. struct c2_tx_desc *tx_desc;
  100. struct c2_txp_desc __iomem *txp_desc;
  101. struct c2_element *elem;
  102. int i;
  103. tx_ring->start = kmalloc(sizeof(*elem) * tx_ring->count, GFP_KERNEL);
  104. if (!tx_ring->start)
  105. return -ENOMEM;
  106. elem = tx_ring->start;
  107. tx_desc = vaddr;
  108. txp_desc = mmio_txp_ring;
  109. for (i = 0; i < tx_ring->count; i++, elem++, tx_desc++, txp_desc++) {
  110. tx_desc->len = 0;
  111. tx_desc->status = 0;
  112. /* Set TXP_HTXD_UNINIT */
  113. __raw_writeq((__force u64) cpu_to_be64(0x1122334455667788ULL),
  114. (void __iomem *) txp_desc + C2_TXP_ADDR);
  115. __raw_writew(0, (void __iomem *) txp_desc + C2_TXP_LEN);
  116. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_UNINIT),
  117. (void __iomem *) txp_desc + C2_TXP_FLAGS);
  118. elem->skb = NULL;
  119. elem->ht_desc = tx_desc;
  120. elem->hw_desc = txp_desc;
  121. if (i == tx_ring->count - 1) {
  122. elem->next = tx_ring->start;
  123. tx_desc->next_offset = base;
  124. } else {
  125. elem->next = elem + 1;
  126. tx_desc->next_offset =
  127. base + (i + 1) * sizeof(*tx_desc);
  128. }
  129. }
  130. tx_ring->to_use = tx_ring->to_clean = tx_ring->start;
  131. return 0;
  132. }
  133. /*
  134. * Allocate RX ring elements and chain them together.
  135. * One-to-one association of adapter descriptors with ring elements.
  136. */
  137. static int c2_rx_ring_alloc(struct c2_ring *rx_ring, void *vaddr,
  138. dma_addr_t base, void __iomem * mmio_rxp_ring)
  139. {
  140. struct c2_rx_desc *rx_desc;
  141. struct c2_rxp_desc __iomem *rxp_desc;
  142. struct c2_element *elem;
  143. int i;
  144. rx_ring->start = kmalloc(sizeof(*elem) * rx_ring->count, GFP_KERNEL);
  145. if (!rx_ring->start)
  146. return -ENOMEM;
  147. elem = rx_ring->start;
  148. rx_desc = vaddr;
  149. rxp_desc = mmio_rxp_ring;
  150. for (i = 0; i < rx_ring->count; i++, elem++, rx_desc++, rxp_desc++) {
  151. rx_desc->len = 0;
  152. rx_desc->status = 0;
  153. /* Set RXP_HRXD_UNINIT */
  154. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_OK),
  155. (void __iomem *) rxp_desc + C2_RXP_STATUS);
  156. __raw_writew(0, (void __iomem *) rxp_desc + C2_RXP_COUNT);
  157. __raw_writew(0, (void __iomem *) rxp_desc + C2_RXP_LEN);
  158. __raw_writeq((__force u64) cpu_to_be64(0x99aabbccddeeffULL),
  159. (void __iomem *) rxp_desc + C2_RXP_ADDR);
  160. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_UNINIT),
  161. (void __iomem *) rxp_desc + C2_RXP_FLAGS);
  162. elem->skb = NULL;
  163. elem->ht_desc = rx_desc;
  164. elem->hw_desc = rxp_desc;
  165. if (i == rx_ring->count - 1) {
  166. elem->next = rx_ring->start;
  167. rx_desc->next_offset = base;
  168. } else {
  169. elem->next = elem + 1;
  170. rx_desc->next_offset =
  171. base + (i + 1) * sizeof(*rx_desc);
  172. }
  173. }
  174. rx_ring->to_use = rx_ring->to_clean = rx_ring->start;
  175. return 0;
  176. }
  177. /* Setup buffer for receiving */
  178. static inline int c2_rx_alloc(struct c2_port *c2_port, struct c2_element *elem)
  179. {
  180. struct c2_dev *c2dev = c2_port->c2dev;
  181. struct c2_rx_desc *rx_desc = elem->ht_desc;
  182. struct sk_buff *skb;
  183. dma_addr_t mapaddr;
  184. u32 maplen;
  185. struct c2_rxp_hdr *rxp_hdr;
  186. skb = dev_alloc_skb(c2_port->rx_buf_size);
  187. if (unlikely(!skb)) {
  188. pr_debug("%s: out of memory for receive\n",
  189. c2_port->netdev->name);
  190. return -ENOMEM;
  191. }
  192. /* Zero out the rxp hdr in the sk_buff */
  193. memset(skb->data, 0, sizeof(*rxp_hdr));
  194. skb->dev = c2_port->netdev;
  195. maplen = c2_port->rx_buf_size;
  196. mapaddr =
  197. pci_map_single(c2dev->pcidev, skb->data, maplen,
  198. PCI_DMA_FROMDEVICE);
  199. /* Set the sk_buff RXP_header to RXP_HRXD_READY */
  200. rxp_hdr = (struct c2_rxp_hdr *) skb->data;
  201. rxp_hdr->flags = RXP_HRXD_READY;
  202. __raw_writew(0, elem->hw_desc + C2_RXP_STATUS);
  203. __raw_writew((__force u16) cpu_to_be16((u16) maplen - sizeof(*rxp_hdr)),
  204. elem->hw_desc + C2_RXP_LEN);
  205. __raw_writeq((__force u64) cpu_to_be64(mapaddr), elem->hw_desc + C2_RXP_ADDR);
  206. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_READY),
  207. elem->hw_desc + C2_RXP_FLAGS);
  208. elem->skb = skb;
  209. elem->mapaddr = mapaddr;
  210. elem->maplen = maplen;
  211. rx_desc->len = maplen;
  212. return 0;
  213. }
  214. /*
  215. * Allocate buffers for the Rx ring
  216. * For receive: rx_ring.to_clean is next received frame
  217. */
  218. static int c2_rx_fill(struct c2_port *c2_port)
  219. {
  220. struct c2_ring *rx_ring = &c2_port->rx_ring;
  221. struct c2_element *elem;
  222. int ret = 0;
  223. elem = rx_ring->start;
  224. do {
  225. if (c2_rx_alloc(c2_port, elem)) {
  226. ret = 1;
  227. break;
  228. }
  229. } while ((elem = elem->next) != rx_ring->start);
  230. rx_ring->to_clean = rx_ring->start;
  231. return ret;
  232. }
  233. /* Free all buffers in RX ring, assumes receiver stopped */
  234. static void c2_rx_clean(struct c2_port *c2_port)
  235. {
  236. struct c2_dev *c2dev = c2_port->c2dev;
  237. struct c2_ring *rx_ring = &c2_port->rx_ring;
  238. struct c2_element *elem;
  239. struct c2_rx_desc *rx_desc;
  240. elem = rx_ring->start;
  241. do {
  242. rx_desc = elem->ht_desc;
  243. rx_desc->len = 0;
  244. __raw_writew(0, elem->hw_desc + C2_RXP_STATUS);
  245. __raw_writew(0, elem->hw_desc + C2_RXP_COUNT);
  246. __raw_writew(0, elem->hw_desc + C2_RXP_LEN);
  247. __raw_writeq((__force u64) cpu_to_be64(0x99aabbccddeeffULL),
  248. elem->hw_desc + C2_RXP_ADDR);
  249. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_UNINIT),
  250. elem->hw_desc + C2_RXP_FLAGS);
  251. if (elem->skb) {
  252. pci_unmap_single(c2dev->pcidev, elem->mapaddr,
  253. elem->maplen, PCI_DMA_FROMDEVICE);
  254. dev_kfree_skb(elem->skb);
  255. elem->skb = NULL;
  256. }
  257. } while ((elem = elem->next) != rx_ring->start);
  258. }
  259. static inline int c2_tx_free(struct c2_dev *c2dev, struct c2_element *elem)
  260. {
  261. struct c2_tx_desc *tx_desc = elem->ht_desc;
  262. tx_desc->len = 0;
  263. pci_unmap_single(c2dev->pcidev, elem->mapaddr, elem->maplen,
  264. PCI_DMA_TODEVICE);
  265. if (elem->skb) {
  266. dev_kfree_skb_any(elem->skb);
  267. elem->skb = NULL;
  268. }
  269. return 0;
  270. }
  271. /* Free all buffers in TX ring, assumes transmitter stopped */
  272. static void c2_tx_clean(struct c2_port *c2_port)
  273. {
  274. struct c2_ring *tx_ring = &c2_port->tx_ring;
  275. struct c2_element *elem;
  276. struct c2_txp_desc txp_htxd;
  277. int retry;
  278. unsigned long flags;
  279. spin_lock_irqsave(&c2_port->tx_lock, flags);
  280. elem = tx_ring->start;
  281. do {
  282. retry = 0;
  283. do {
  284. txp_htxd.flags =
  285. readw(elem->hw_desc + C2_TXP_FLAGS);
  286. if (txp_htxd.flags == TXP_HTXD_READY) {
  287. retry = 1;
  288. __raw_writew(0,
  289. elem->hw_desc + C2_TXP_LEN);
  290. __raw_writeq(0,
  291. elem->hw_desc + C2_TXP_ADDR);
  292. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_DONE),
  293. elem->hw_desc + C2_TXP_FLAGS);
  294. c2_port->netdev->stats.tx_dropped++;
  295. break;
  296. } else {
  297. __raw_writew(0,
  298. elem->hw_desc + C2_TXP_LEN);
  299. __raw_writeq((__force u64) cpu_to_be64(0x1122334455667788ULL),
  300. elem->hw_desc + C2_TXP_ADDR);
  301. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_UNINIT),
  302. elem->hw_desc + C2_TXP_FLAGS);
  303. }
  304. c2_tx_free(c2_port->c2dev, elem);
  305. } while ((elem = elem->next) != tx_ring->start);
  306. } while (retry);
  307. c2_port->tx_avail = c2_port->tx_ring.count - 1;
  308. c2_port->c2dev->cur_tx = tx_ring->to_use - tx_ring->start;
  309. if (c2_port->tx_avail > MAX_SKB_FRAGS + 1)
  310. netif_wake_queue(c2_port->netdev);
  311. spin_unlock_irqrestore(&c2_port->tx_lock, flags);
  312. }
  313. /*
  314. * Process transmit descriptors marked 'DONE' by the firmware,
  315. * freeing up their unneeded sk_buffs.
  316. */
  317. static void c2_tx_interrupt(struct net_device *netdev)
  318. {
  319. struct c2_port *c2_port = netdev_priv(netdev);
  320. struct c2_dev *c2dev = c2_port->c2dev;
  321. struct c2_ring *tx_ring = &c2_port->tx_ring;
  322. struct c2_element *elem;
  323. struct c2_txp_desc txp_htxd;
  324. spin_lock(&c2_port->tx_lock);
  325. for (elem = tx_ring->to_clean; elem != tx_ring->to_use;
  326. elem = elem->next) {
  327. txp_htxd.flags =
  328. be16_to_cpu((__force __be16) readw(elem->hw_desc + C2_TXP_FLAGS));
  329. if (txp_htxd.flags != TXP_HTXD_DONE)
  330. break;
  331. if (netif_msg_tx_done(c2_port)) {
  332. /* PCI reads are expensive in fast path */
  333. txp_htxd.len =
  334. be16_to_cpu((__force __be16) readw(elem->hw_desc + C2_TXP_LEN));
  335. pr_debug("%s: tx done slot %3Zu status 0x%x len "
  336. "%5u bytes\n",
  337. netdev->name, elem - tx_ring->start,
  338. txp_htxd.flags, txp_htxd.len);
  339. }
  340. c2_tx_free(c2dev, elem);
  341. ++(c2_port->tx_avail);
  342. }
  343. tx_ring->to_clean = elem;
  344. if (netif_queue_stopped(netdev)
  345. && c2_port->tx_avail > MAX_SKB_FRAGS + 1)
  346. netif_wake_queue(netdev);
  347. spin_unlock(&c2_port->tx_lock);
  348. }
  349. static void c2_rx_error(struct c2_port *c2_port, struct c2_element *elem)
  350. {
  351. struct c2_rx_desc *rx_desc = elem->ht_desc;
  352. struct c2_rxp_hdr *rxp_hdr = (struct c2_rxp_hdr *) elem->skb->data;
  353. if (rxp_hdr->status != RXP_HRXD_OK ||
  354. rxp_hdr->len > (rx_desc->len - sizeof(*rxp_hdr))) {
  355. pr_debug("BAD RXP_HRXD\n");
  356. pr_debug(" rx_desc : %p\n", rx_desc);
  357. pr_debug(" index : %Zu\n",
  358. elem - c2_port->rx_ring.start);
  359. pr_debug(" len : %u\n", rx_desc->len);
  360. pr_debug(" rxp_hdr : %p [PA %p]\n", rxp_hdr,
  361. (void *) __pa((unsigned long) rxp_hdr));
  362. pr_debug(" flags : 0x%x\n", rxp_hdr->flags);
  363. pr_debug(" status: 0x%x\n", rxp_hdr->status);
  364. pr_debug(" len : %u\n", rxp_hdr->len);
  365. pr_debug(" rsvd : 0x%x\n", rxp_hdr->rsvd);
  366. }
  367. /* Setup the skb for reuse since we're dropping this pkt */
  368. elem->skb->data = elem->skb->head;
  369. skb_reset_tail_pointer(elem->skb);
  370. /* Zero out the rxp hdr in the sk_buff */
  371. memset(elem->skb->data, 0, sizeof(*rxp_hdr));
  372. /* Write the descriptor to the adapter's rx ring */
  373. __raw_writew(0, elem->hw_desc + C2_RXP_STATUS);
  374. __raw_writew(0, elem->hw_desc + C2_RXP_COUNT);
  375. __raw_writew((__force u16) cpu_to_be16((u16) elem->maplen - sizeof(*rxp_hdr)),
  376. elem->hw_desc + C2_RXP_LEN);
  377. __raw_writeq((__force u64) cpu_to_be64(elem->mapaddr),
  378. elem->hw_desc + C2_RXP_ADDR);
  379. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_READY),
  380. elem->hw_desc + C2_RXP_FLAGS);
  381. pr_debug("packet dropped\n");
  382. c2_port->netdev->stats.rx_dropped++;
  383. }
  384. static void c2_rx_interrupt(struct net_device *netdev)
  385. {
  386. struct c2_port *c2_port = netdev_priv(netdev);
  387. struct c2_dev *c2dev = c2_port->c2dev;
  388. struct c2_ring *rx_ring = &c2_port->rx_ring;
  389. struct c2_element *elem;
  390. struct c2_rx_desc *rx_desc;
  391. struct c2_rxp_hdr *rxp_hdr;
  392. struct sk_buff *skb;
  393. dma_addr_t mapaddr;
  394. u32 maplen, buflen;
  395. unsigned long flags;
  396. spin_lock_irqsave(&c2dev->lock, flags);
  397. /* Begin where we left off */
  398. rx_ring->to_clean = rx_ring->start + c2dev->cur_rx;
  399. for (elem = rx_ring->to_clean; elem->next != rx_ring->to_clean;
  400. elem = elem->next) {
  401. rx_desc = elem->ht_desc;
  402. mapaddr = elem->mapaddr;
  403. maplen = elem->maplen;
  404. skb = elem->skb;
  405. rxp_hdr = (struct c2_rxp_hdr *) skb->data;
  406. if (rxp_hdr->flags != RXP_HRXD_DONE)
  407. break;
  408. buflen = rxp_hdr->len;
  409. /* Sanity check the RXP header */
  410. if (rxp_hdr->status != RXP_HRXD_OK ||
  411. buflen > (rx_desc->len - sizeof(*rxp_hdr))) {
  412. c2_rx_error(c2_port, elem);
  413. continue;
  414. }
  415. /*
  416. * Allocate and map a new skb for replenishing the host
  417. * RX desc
  418. */
  419. if (c2_rx_alloc(c2_port, elem)) {
  420. c2_rx_error(c2_port, elem);
  421. continue;
  422. }
  423. /* Unmap the old skb */
  424. pci_unmap_single(c2dev->pcidev, mapaddr, maplen,
  425. PCI_DMA_FROMDEVICE);
  426. prefetch(skb->data);
  427. /*
  428. * Skip past the leading 8 bytes comprising of the
  429. * "struct c2_rxp_hdr", prepended by the adapter
  430. * to the usual Ethernet header ("struct ethhdr"),
  431. * to the start of the raw Ethernet packet.
  432. *
  433. * Fix up the various fields in the sk_buff before
  434. * passing it up to netif_rx(). The transfer size
  435. * (in bytes) specified by the adapter len field of
  436. * the "struct rxp_hdr_t" does NOT include the
  437. * "sizeof(struct c2_rxp_hdr)".
  438. */
  439. skb->data += sizeof(*rxp_hdr);
  440. skb_set_tail_pointer(skb, buflen);
  441. skb->len = buflen;
  442. skb->protocol = eth_type_trans(skb, netdev);
  443. netif_rx(skb);
  444. netdev->stats.rx_packets++;
  445. netdev->stats.rx_bytes += buflen;
  446. }
  447. /* Save where we left off */
  448. rx_ring->to_clean = elem;
  449. c2dev->cur_rx = elem - rx_ring->start;
  450. C2_SET_CUR_RX(c2dev, c2dev->cur_rx);
  451. spin_unlock_irqrestore(&c2dev->lock, flags);
  452. }
  453. /*
  454. * Handle netisr0 TX & RX interrupts.
  455. */
  456. static irqreturn_t c2_interrupt(int irq, void *dev_id)
  457. {
  458. unsigned int netisr0, dmaisr;
  459. int handled = 0;
  460. struct c2_dev *c2dev = (struct c2_dev *) dev_id;
  461. /* Process CCILNET interrupts */
  462. netisr0 = readl(c2dev->regs + C2_NISR0);
  463. if (netisr0) {
  464. /*
  465. * There is an issue with the firmware that always
  466. * provides the status of RX for both TX & RX
  467. * interrupts. So process both queues here.
  468. */
  469. c2_rx_interrupt(c2dev->netdev);
  470. c2_tx_interrupt(c2dev->netdev);
  471. /* Clear the interrupt */
  472. writel(netisr0, c2dev->regs + C2_NISR0);
  473. handled++;
  474. }
  475. /* Process RNIC interrupts */
  476. dmaisr = readl(c2dev->regs + C2_DISR);
  477. if (dmaisr) {
  478. writel(dmaisr, c2dev->regs + C2_DISR);
  479. c2_rnic_interrupt(c2dev);
  480. handled++;
  481. }
  482. if (handled) {
  483. return IRQ_HANDLED;
  484. } else {
  485. return IRQ_NONE;
  486. }
  487. }
  488. static int c2_up(struct net_device *netdev)
  489. {
  490. struct c2_port *c2_port = netdev_priv(netdev);
  491. struct c2_dev *c2dev = c2_port->c2dev;
  492. struct c2_element *elem;
  493. struct c2_rxp_hdr *rxp_hdr;
  494. struct in_device *in_dev;
  495. size_t rx_size, tx_size;
  496. int ret, i;
  497. unsigned int netimr0;
  498. if (netif_msg_ifup(c2_port))
  499. pr_debug("%s: enabling interface\n", netdev->name);
  500. /* Set the Rx buffer size based on MTU */
  501. c2_set_rxbufsize(c2_port);
  502. /* Allocate DMA'able memory for Tx/Rx host descriptor rings */
  503. rx_size = c2_port->rx_ring.count * sizeof(struct c2_rx_desc);
  504. tx_size = c2_port->tx_ring.count * sizeof(struct c2_tx_desc);
  505. c2_port->mem_size = tx_size + rx_size;
  506. c2_port->mem = pci_alloc_consistent(c2dev->pcidev, c2_port->mem_size,
  507. &c2_port->dma);
  508. if (c2_port->mem == NULL) {
  509. pr_debug("Unable to allocate memory for "
  510. "host descriptor rings\n");
  511. return -ENOMEM;
  512. }
  513. memset(c2_port->mem, 0, c2_port->mem_size);
  514. /* Create the Rx host descriptor ring */
  515. if ((ret =
  516. c2_rx_ring_alloc(&c2_port->rx_ring, c2_port->mem, c2_port->dma,
  517. c2dev->mmio_rxp_ring))) {
  518. pr_debug("Unable to create RX ring\n");
  519. goto bail0;
  520. }
  521. /* Allocate Rx buffers for the host descriptor ring */
  522. if (c2_rx_fill(c2_port)) {
  523. pr_debug("Unable to fill RX ring\n");
  524. goto bail1;
  525. }
  526. /* Create the Tx host descriptor ring */
  527. if ((ret = c2_tx_ring_alloc(&c2_port->tx_ring, c2_port->mem + rx_size,
  528. c2_port->dma + rx_size,
  529. c2dev->mmio_txp_ring))) {
  530. pr_debug("Unable to create TX ring\n");
  531. goto bail1;
  532. }
  533. /* Set the TX pointer to where we left off */
  534. c2_port->tx_avail = c2_port->tx_ring.count - 1;
  535. c2_port->tx_ring.to_use = c2_port->tx_ring.to_clean =
  536. c2_port->tx_ring.start + c2dev->cur_tx;
  537. /* missing: Initialize MAC */
  538. BUG_ON(c2_port->tx_ring.to_use != c2_port->tx_ring.to_clean);
  539. /* Reset the adapter, ensures the driver is in sync with the RXP */
  540. c2_reset(c2_port);
  541. /* Reset the READY bit in the sk_buff RXP headers & adapter HRXDQ */
  542. for (i = 0, elem = c2_port->rx_ring.start; i < c2_port->rx_ring.count;
  543. i++, elem++) {
  544. rxp_hdr = (struct c2_rxp_hdr *) elem->skb->data;
  545. rxp_hdr->flags = 0;
  546. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_READY),
  547. elem->hw_desc + C2_RXP_FLAGS);
  548. }
  549. /* Enable network packets */
  550. netif_start_queue(netdev);
  551. /* Enable IRQ */
  552. writel(0, c2dev->regs + C2_IDIS);
  553. netimr0 = readl(c2dev->regs + C2_NIMR0);
  554. netimr0 &= ~(C2_PCI_HTX_INT | C2_PCI_HRX_INT);
  555. writel(netimr0, c2dev->regs + C2_NIMR0);
  556. /* Tell the stack to ignore arp requests for ipaddrs bound to
  557. * other interfaces. This is needed to prevent the host stack
  558. * from responding to arp requests to the ipaddr bound on the
  559. * rdma interface.
  560. */
  561. in_dev = in_dev_get(netdev);
  562. IN_DEV_CONF_SET(in_dev, ARP_IGNORE, 1);
  563. in_dev_put(in_dev);
  564. return 0;
  565. bail1:
  566. c2_rx_clean(c2_port);
  567. kfree(c2_port->rx_ring.start);
  568. bail0:
  569. pci_free_consistent(c2dev->pcidev, c2_port->mem_size, c2_port->mem,
  570. c2_port->dma);
  571. return ret;
  572. }
  573. static int c2_down(struct net_device *netdev)
  574. {
  575. struct c2_port *c2_port = netdev_priv(netdev);
  576. struct c2_dev *c2dev = c2_port->c2dev;
  577. if (netif_msg_ifdown(c2_port))
  578. pr_debug("%s: disabling interface\n",
  579. netdev->name);
  580. /* Wait for all the queued packets to get sent */
  581. c2_tx_interrupt(netdev);
  582. /* Disable network packets */
  583. netif_stop_queue(netdev);
  584. /* Disable IRQs by clearing the interrupt mask */
  585. writel(1, c2dev->regs + C2_IDIS);
  586. writel(0, c2dev->regs + C2_NIMR0);
  587. /* missing: Stop transmitter */
  588. /* missing: Stop receiver */
  589. /* Reset the adapter, ensures the driver is in sync with the RXP */
  590. c2_reset(c2_port);
  591. /* missing: Turn off LEDs here */
  592. /* Free all buffers in the host descriptor rings */
  593. c2_tx_clean(c2_port);
  594. c2_rx_clean(c2_port);
  595. /* Free the host descriptor rings */
  596. kfree(c2_port->rx_ring.start);
  597. kfree(c2_port->tx_ring.start);
  598. pci_free_consistent(c2dev->pcidev, c2_port->mem_size, c2_port->mem,
  599. c2_port->dma);
  600. return 0;
  601. }
  602. static void c2_reset(struct c2_port *c2_port)
  603. {
  604. struct c2_dev *c2dev = c2_port->c2dev;
  605. unsigned int cur_rx = c2dev->cur_rx;
  606. /* Tell the hardware to quiesce */
  607. C2_SET_CUR_RX(c2dev, cur_rx | C2_PCI_HRX_QUI);
  608. /*
  609. * The hardware will reset the C2_PCI_HRX_QUI bit once
  610. * the RXP is quiesced. Wait 2 seconds for this.
  611. */
  612. ssleep(2);
  613. cur_rx = C2_GET_CUR_RX(c2dev);
  614. if (cur_rx & C2_PCI_HRX_QUI)
  615. pr_debug("c2_reset: failed to quiesce the hardware!\n");
  616. cur_rx &= ~C2_PCI_HRX_QUI;
  617. c2dev->cur_rx = cur_rx;
  618. pr_debug("Current RX: %u\n", c2dev->cur_rx);
  619. }
  620. static int c2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
  621. {
  622. struct c2_port *c2_port = netdev_priv(netdev);
  623. struct c2_dev *c2dev = c2_port->c2dev;
  624. struct c2_ring *tx_ring = &c2_port->tx_ring;
  625. struct c2_element *elem;
  626. dma_addr_t mapaddr;
  627. u32 maplen;
  628. unsigned long flags;
  629. unsigned int i;
  630. spin_lock_irqsave(&c2_port->tx_lock, flags);
  631. if (unlikely(c2_port->tx_avail < (skb_shinfo(skb)->nr_frags + 1))) {
  632. netif_stop_queue(netdev);
  633. spin_unlock_irqrestore(&c2_port->tx_lock, flags);
  634. pr_debug("%s: Tx ring full when queue awake!\n",
  635. netdev->name);
  636. return NETDEV_TX_BUSY;
  637. }
  638. maplen = skb_headlen(skb);
  639. mapaddr =
  640. pci_map_single(c2dev->pcidev, skb->data, maplen, PCI_DMA_TODEVICE);
  641. elem = tx_ring->to_use;
  642. elem->skb = skb;
  643. elem->mapaddr = mapaddr;
  644. elem->maplen = maplen;
  645. /* Tell HW to xmit */
  646. __raw_writeq((__force u64) cpu_to_be64(mapaddr),
  647. elem->hw_desc + C2_TXP_ADDR);
  648. __raw_writew((__force u16) cpu_to_be16(maplen),
  649. elem->hw_desc + C2_TXP_LEN);
  650. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_READY),
  651. elem->hw_desc + C2_TXP_FLAGS);
  652. netdev->stats.tx_packets++;
  653. netdev->stats.tx_bytes += maplen;
  654. /* Loop thru additional data fragments and queue them */
  655. if (skb_shinfo(skb)->nr_frags) {
  656. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  657. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  658. maplen = frag->size;
  659. mapaddr =
  660. pci_map_page(c2dev->pcidev, frag->page,
  661. frag->page_offset, maplen,
  662. PCI_DMA_TODEVICE);
  663. elem = elem->next;
  664. elem->skb = NULL;
  665. elem->mapaddr = mapaddr;
  666. elem->maplen = maplen;
  667. /* Tell HW to xmit */
  668. __raw_writeq((__force u64) cpu_to_be64(mapaddr),
  669. elem->hw_desc + C2_TXP_ADDR);
  670. __raw_writew((__force u16) cpu_to_be16(maplen),
  671. elem->hw_desc + C2_TXP_LEN);
  672. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_READY),
  673. elem->hw_desc + C2_TXP_FLAGS);
  674. netdev->stats.tx_packets++;
  675. netdev->stats.tx_bytes += maplen;
  676. }
  677. }
  678. tx_ring->to_use = elem->next;
  679. c2_port->tx_avail -= (skb_shinfo(skb)->nr_frags + 1);
  680. if (c2_port->tx_avail <= MAX_SKB_FRAGS + 1) {
  681. netif_stop_queue(netdev);
  682. if (netif_msg_tx_queued(c2_port))
  683. pr_debug("%s: transmit queue full\n",
  684. netdev->name);
  685. }
  686. spin_unlock_irqrestore(&c2_port->tx_lock, flags);
  687. netdev->trans_start = jiffies;
  688. return NETDEV_TX_OK;
  689. }
  690. static void c2_tx_timeout(struct net_device *netdev)
  691. {
  692. struct c2_port *c2_port = netdev_priv(netdev);
  693. if (netif_msg_timer(c2_port))
  694. pr_debug("%s: tx timeout\n", netdev->name);
  695. c2_tx_clean(c2_port);
  696. }
  697. static int c2_change_mtu(struct net_device *netdev, int new_mtu)
  698. {
  699. int ret = 0;
  700. if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
  701. return -EINVAL;
  702. netdev->mtu = new_mtu;
  703. if (netif_running(netdev)) {
  704. c2_down(netdev);
  705. c2_up(netdev);
  706. }
  707. return ret;
  708. }
  709. static const struct net_device_ops c2_netdev = {
  710. .ndo_open = c2_up,
  711. .ndo_stop = c2_down,
  712. .ndo_start_xmit = c2_xmit_frame,
  713. .ndo_tx_timeout = c2_tx_timeout,
  714. .ndo_change_mtu = c2_change_mtu,
  715. .ndo_set_mac_address = eth_mac_addr,
  716. .ndo_validate_addr = eth_validate_addr,
  717. };
  718. /* Initialize network device */
  719. static struct net_device *c2_devinit(struct c2_dev *c2dev,
  720. void __iomem * mmio_addr)
  721. {
  722. struct c2_port *c2_port = NULL;
  723. struct net_device *netdev = alloc_etherdev(sizeof(*c2_port));
  724. if (!netdev) {
  725. pr_debug("c2_port etherdev alloc failed");
  726. return NULL;
  727. }
  728. SET_NETDEV_DEV(netdev, &c2dev->pcidev->dev);
  729. netdev->netdev_ops = &c2_netdev;
  730. netdev->watchdog_timeo = C2_TX_TIMEOUT;
  731. netdev->irq = c2dev->pcidev->irq;
  732. c2_port = netdev_priv(netdev);
  733. c2_port->netdev = netdev;
  734. c2_port->c2dev = c2dev;
  735. c2_port->msg_enable = netif_msg_init(debug, default_msg);
  736. c2_port->tx_ring.count = C2_NUM_TX_DESC;
  737. c2_port->rx_ring.count = C2_NUM_RX_DESC;
  738. spin_lock_init(&c2_port->tx_lock);
  739. /* Copy our 48-bit ethernet hardware address */
  740. memcpy_fromio(netdev->dev_addr, mmio_addr + C2_REGS_ENADDR, 6);
  741. /* Validate the MAC address */
  742. if (!is_valid_ether_addr(netdev->dev_addr)) {
  743. pr_debug("Invalid MAC Address\n");
  744. c2_print_macaddr(netdev);
  745. free_netdev(netdev);
  746. return NULL;
  747. }
  748. c2dev->netdev = netdev;
  749. return netdev;
  750. }
  751. static int __devinit c2_probe(struct pci_dev *pcidev,
  752. const struct pci_device_id *ent)
  753. {
  754. int ret = 0, i;
  755. unsigned long reg0_start, reg0_flags, reg0_len;
  756. unsigned long reg2_start, reg2_flags, reg2_len;
  757. unsigned long reg4_start, reg4_flags, reg4_len;
  758. unsigned kva_map_size;
  759. struct net_device *netdev = NULL;
  760. struct c2_dev *c2dev = NULL;
  761. void __iomem *mmio_regs = NULL;
  762. printk(KERN_INFO PFX "AMSO1100 Gigabit Ethernet driver v%s loaded\n",
  763. DRV_VERSION);
  764. /* Enable PCI device */
  765. ret = pci_enable_device(pcidev);
  766. if (ret) {
  767. printk(KERN_ERR PFX "%s: Unable to enable PCI device\n",
  768. pci_name(pcidev));
  769. goto bail0;
  770. }
  771. reg0_start = pci_resource_start(pcidev, BAR_0);
  772. reg0_len = pci_resource_len(pcidev, BAR_0);
  773. reg0_flags = pci_resource_flags(pcidev, BAR_0);
  774. reg2_start = pci_resource_start(pcidev, BAR_2);
  775. reg2_len = pci_resource_len(pcidev, BAR_2);
  776. reg2_flags = pci_resource_flags(pcidev, BAR_2);
  777. reg4_start = pci_resource_start(pcidev, BAR_4);
  778. reg4_len = pci_resource_len(pcidev, BAR_4);
  779. reg4_flags = pci_resource_flags(pcidev, BAR_4);
  780. pr_debug("BAR0 size = 0x%lX bytes\n", reg0_len);
  781. pr_debug("BAR2 size = 0x%lX bytes\n", reg2_len);
  782. pr_debug("BAR4 size = 0x%lX bytes\n", reg4_len);
  783. /* Make sure PCI base addr are MMIO */
  784. if (!(reg0_flags & IORESOURCE_MEM) ||
  785. !(reg2_flags & IORESOURCE_MEM) || !(reg4_flags & IORESOURCE_MEM)) {
  786. printk(KERN_ERR PFX "PCI regions not an MMIO resource\n");
  787. ret = -ENODEV;
  788. goto bail1;
  789. }
  790. /* Check for weird/broken PCI region reporting */
  791. if ((reg0_len < C2_REG0_SIZE) ||
  792. (reg2_len < C2_REG2_SIZE) || (reg4_len < C2_REG4_SIZE)) {
  793. printk(KERN_ERR PFX "Invalid PCI region sizes\n");
  794. ret = -ENODEV;
  795. goto bail1;
  796. }
  797. /* Reserve PCI I/O and memory resources */
  798. ret = pci_request_regions(pcidev, DRV_NAME);
  799. if (ret) {
  800. printk(KERN_ERR PFX "%s: Unable to request regions\n",
  801. pci_name(pcidev));
  802. goto bail1;
  803. }
  804. if ((sizeof(dma_addr_t) > 4)) {
  805. ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(64));
  806. if (ret < 0) {
  807. printk(KERN_ERR PFX "64b DMA configuration failed\n");
  808. goto bail2;
  809. }
  810. } else {
  811. ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
  812. if (ret < 0) {
  813. printk(KERN_ERR PFX "32b DMA configuration failed\n");
  814. goto bail2;
  815. }
  816. }
  817. /* Enables bus-mastering on the device */
  818. pci_set_master(pcidev);
  819. /* Remap the adapter PCI registers in BAR4 */
  820. mmio_regs = ioremap_nocache(reg4_start + C2_PCI_REGS_OFFSET,
  821. sizeof(struct c2_adapter_pci_regs));
  822. if (!mmio_regs) {
  823. printk(KERN_ERR PFX
  824. "Unable to remap adapter PCI registers in BAR4\n");
  825. ret = -EIO;
  826. goto bail2;
  827. }
  828. /* Validate PCI regs magic */
  829. for (i = 0; i < sizeof(c2_magic); i++) {
  830. if (c2_magic[i] != readb(mmio_regs + C2_REGS_MAGIC + i)) {
  831. printk(KERN_ERR PFX "Downlevel Firmware boot loader "
  832. "[%d/%Zd: got 0x%x, exp 0x%x]. Use the cc_flash "
  833. "utility to update your boot loader\n",
  834. i + 1, sizeof(c2_magic),
  835. readb(mmio_regs + C2_REGS_MAGIC + i),
  836. c2_magic[i]);
  837. printk(KERN_ERR PFX "Adapter not claimed\n");
  838. iounmap(mmio_regs);
  839. ret = -EIO;
  840. goto bail2;
  841. }
  842. }
  843. /* Validate the adapter version */
  844. if (be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_VERS)) != C2_VERSION) {
  845. printk(KERN_ERR PFX "Version mismatch "
  846. "[fw=%u, c2=%u], Adapter not claimed\n",
  847. be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_VERS)),
  848. C2_VERSION);
  849. ret = -EINVAL;
  850. iounmap(mmio_regs);
  851. goto bail2;
  852. }
  853. /* Validate the adapter IVN */
  854. if (be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_IVN)) != C2_IVN) {
  855. printk(KERN_ERR PFX "Downlevel FIrmware level. You should be using "
  856. "the OpenIB device support kit. "
  857. "[fw=0x%x, c2=0x%x], Adapter not claimed\n",
  858. be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_IVN)),
  859. C2_IVN);
  860. ret = -EINVAL;
  861. iounmap(mmio_regs);
  862. goto bail2;
  863. }
  864. /* Allocate hardware structure */
  865. c2dev = (struct c2_dev *) ib_alloc_device(sizeof(*c2dev));
  866. if (!c2dev) {
  867. printk(KERN_ERR PFX "%s: Unable to alloc hardware struct\n",
  868. pci_name(pcidev));
  869. ret = -ENOMEM;
  870. iounmap(mmio_regs);
  871. goto bail2;
  872. }
  873. memset(c2dev, 0, sizeof(*c2dev));
  874. spin_lock_init(&c2dev->lock);
  875. c2dev->pcidev = pcidev;
  876. c2dev->cur_tx = 0;
  877. /* Get the last RX index */
  878. c2dev->cur_rx =
  879. (be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_HRX_CUR)) -
  880. 0xffffc000) / sizeof(struct c2_rxp_desc);
  881. /* Request an interrupt line for the driver */
  882. ret = request_irq(pcidev->irq, c2_interrupt, IRQF_SHARED, DRV_NAME, c2dev);
  883. if (ret) {
  884. printk(KERN_ERR PFX "%s: requested IRQ %u is busy\n",
  885. pci_name(pcidev), pcidev->irq);
  886. iounmap(mmio_regs);
  887. goto bail3;
  888. }
  889. /* Set driver specific data */
  890. pci_set_drvdata(pcidev, c2dev);
  891. /* Initialize network device */
  892. if ((netdev = c2_devinit(c2dev, mmio_regs)) == NULL) {
  893. iounmap(mmio_regs);
  894. goto bail4;
  895. }
  896. /* Save off the actual size prior to unmapping mmio_regs */
  897. kva_map_size = be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_PCI_WINSIZE));
  898. /* Unmap the adapter PCI registers in BAR4 */
  899. iounmap(mmio_regs);
  900. /* Register network device */
  901. ret = register_netdev(netdev);
  902. if (ret) {
  903. printk(KERN_ERR PFX "Unable to register netdev, ret = %d\n",
  904. ret);
  905. goto bail5;
  906. }
  907. /* Disable network packets */
  908. netif_stop_queue(netdev);
  909. /* Remap the adapter HRXDQ PA space to kernel VA space */
  910. c2dev->mmio_rxp_ring = ioremap_nocache(reg4_start + C2_RXP_HRXDQ_OFFSET,
  911. C2_RXP_HRXDQ_SIZE);
  912. if (!c2dev->mmio_rxp_ring) {
  913. printk(KERN_ERR PFX "Unable to remap MMIO HRXDQ region\n");
  914. ret = -EIO;
  915. goto bail6;
  916. }
  917. /* Remap the adapter HTXDQ PA space to kernel VA space */
  918. c2dev->mmio_txp_ring = ioremap_nocache(reg4_start + C2_TXP_HTXDQ_OFFSET,
  919. C2_TXP_HTXDQ_SIZE);
  920. if (!c2dev->mmio_txp_ring) {
  921. printk(KERN_ERR PFX "Unable to remap MMIO HTXDQ region\n");
  922. ret = -EIO;
  923. goto bail7;
  924. }
  925. /* Save off the current RX index in the last 4 bytes of the TXP Ring */
  926. C2_SET_CUR_RX(c2dev, c2dev->cur_rx);
  927. /* Remap the PCI registers in adapter BAR0 to kernel VA space */
  928. c2dev->regs = ioremap_nocache(reg0_start, reg0_len);
  929. if (!c2dev->regs) {
  930. printk(KERN_ERR PFX "Unable to remap BAR0\n");
  931. ret = -EIO;
  932. goto bail8;
  933. }
  934. /* Remap the PCI registers in adapter BAR4 to kernel VA space */
  935. c2dev->pa = reg4_start + C2_PCI_REGS_OFFSET;
  936. c2dev->kva = ioremap_nocache(reg4_start + C2_PCI_REGS_OFFSET,
  937. kva_map_size);
  938. if (!c2dev->kva) {
  939. printk(KERN_ERR PFX "Unable to remap BAR4\n");
  940. ret = -EIO;
  941. goto bail9;
  942. }
  943. /* Print out the MAC address */
  944. c2_print_macaddr(netdev);
  945. ret = c2_rnic_init(c2dev);
  946. if (ret) {
  947. printk(KERN_ERR PFX "c2_rnic_init failed: %d\n", ret);
  948. goto bail10;
  949. }
  950. if (c2_register_device(c2dev))
  951. goto bail10;
  952. return 0;
  953. bail10:
  954. iounmap(c2dev->kva);
  955. bail9:
  956. iounmap(c2dev->regs);
  957. bail8:
  958. iounmap(c2dev->mmio_txp_ring);
  959. bail7:
  960. iounmap(c2dev->mmio_rxp_ring);
  961. bail6:
  962. unregister_netdev(netdev);
  963. bail5:
  964. free_netdev(netdev);
  965. bail4:
  966. free_irq(pcidev->irq, c2dev);
  967. bail3:
  968. ib_dealloc_device(&c2dev->ibdev);
  969. bail2:
  970. pci_release_regions(pcidev);
  971. bail1:
  972. pci_disable_device(pcidev);
  973. bail0:
  974. return ret;
  975. }
  976. static void __devexit c2_remove(struct pci_dev *pcidev)
  977. {
  978. struct c2_dev *c2dev = pci_get_drvdata(pcidev);
  979. struct net_device *netdev = c2dev->netdev;
  980. /* Unregister with OpenIB */
  981. c2_unregister_device(c2dev);
  982. /* Clean up the RNIC resources */
  983. c2_rnic_term(c2dev);
  984. /* Remove network device from the kernel */
  985. unregister_netdev(netdev);
  986. /* Free network device */
  987. free_netdev(netdev);
  988. /* Free the interrupt line */
  989. free_irq(pcidev->irq, c2dev);
  990. /* missing: Turn LEDs off here */
  991. /* Unmap adapter PA space */
  992. iounmap(c2dev->kva);
  993. iounmap(c2dev->regs);
  994. iounmap(c2dev->mmio_txp_ring);
  995. iounmap(c2dev->mmio_rxp_ring);
  996. /* Free the hardware structure */
  997. ib_dealloc_device(&c2dev->ibdev);
  998. /* Release reserved PCI I/O and memory resources */
  999. pci_release_regions(pcidev);
  1000. /* Disable PCI device */
  1001. pci_disable_device(pcidev);
  1002. /* Clear driver specific data */
  1003. pci_set_drvdata(pcidev, NULL);
  1004. }
  1005. static struct pci_driver c2_pci_driver = {
  1006. .name = DRV_NAME,
  1007. .id_table = c2_pci_table,
  1008. .probe = c2_probe,
  1009. .remove = __devexit_p(c2_remove),
  1010. };
  1011. static int __init c2_init_module(void)
  1012. {
  1013. return pci_register_driver(&c2_pci_driver);
  1014. }
  1015. static void __exit c2_exit_module(void)
  1016. {
  1017. pci_unregister_driver(&c2_pci_driver);
  1018. }
  1019. module_init(c2_init_module);
  1020. module_exit(c2_exit_module);