video1394.c 42 KB

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  1. /*
  2. * video1394.c - video driver for OHCI 1394 boards
  3. * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
  4. * Peter Schlaile <udbz@rz.uni-karlsruhe.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software Foundation,
  18. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. *
  20. * NOTES:
  21. *
  22. * ioctl return codes:
  23. * EFAULT is only for invalid address for the argp
  24. * EINVAL for out of range values
  25. * EBUSY when trying to use an already used resource
  26. * ESRCH when trying to free/stop a not used resource
  27. * EAGAIN for resource allocation failure that could perhaps succeed later
  28. * ENOTTY for unsupported ioctl request
  29. *
  30. */
  31. #include <linux/kernel.h>
  32. #include <linux/list.h>
  33. #include <linux/sched.h>
  34. #include <linux/slab.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/wait.h>
  37. #include <linux/errno.h>
  38. #include <linux/module.h>
  39. #include <linux/init.h>
  40. #include <linux/pci.h>
  41. #include <linux/fs.h>
  42. #include <linux/poll.h>
  43. #include <linux/delay.h>
  44. #include <linux/bitops.h>
  45. #include <linux/types.h>
  46. #include <linux/vmalloc.h>
  47. #include <linux/timex.h>
  48. #include <linux/mm.h>
  49. #include <linux/compat.h>
  50. #include <linux/cdev.h>
  51. #include "dma.h"
  52. #include "highlevel.h"
  53. #include "hosts.h"
  54. #include "ieee1394.h"
  55. #include "ieee1394_core.h"
  56. #include "ieee1394_hotplug.h"
  57. #include "ieee1394_types.h"
  58. #include "nodemgr.h"
  59. #include "ohci1394.h"
  60. #include "video1394.h"
  61. #define ISO_CHANNELS 64
  62. struct it_dma_prg {
  63. struct dma_cmd begin;
  64. quadlet_t data[4];
  65. struct dma_cmd end;
  66. quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
  67. };
  68. struct dma_iso_ctx {
  69. struct ti_ohci *ohci;
  70. int type; /* OHCI_ISO_TRANSMIT or OHCI_ISO_RECEIVE */
  71. struct ohci1394_iso_tasklet iso_tasklet;
  72. int channel;
  73. int ctx;
  74. int last_buffer;
  75. int * next_buffer; /* For ISO Transmit of video packets
  76. to write the correct SYT field
  77. into the next block */
  78. unsigned int num_desc;
  79. unsigned int buf_size;
  80. unsigned int frame_size;
  81. unsigned int packet_size;
  82. unsigned int left_size;
  83. unsigned int nb_cmd;
  84. struct dma_region dma;
  85. struct dma_prog_region *prg_reg;
  86. struct dma_cmd **ir_prg;
  87. struct it_dma_prg **it_prg;
  88. unsigned int *buffer_status;
  89. unsigned int *buffer_prg_assignment;
  90. struct timeval *buffer_time; /* time when the buffer was received */
  91. unsigned int *last_used_cmd; /* For ISO Transmit with
  92. variable sized packets only ! */
  93. int ctrlClear;
  94. int ctrlSet;
  95. int cmdPtr;
  96. int ctxMatch;
  97. wait_queue_head_t waitq;
  98. spinlock_t lock;
  99. unsigned int syt_offset;
  100. int flags;
  101. struct list_head link;
  102. };
  103. struct file_ctx {
  104. struct ti_ohci *ohci;
  105. struct list_head context_list;
  106. struct dma_iso_ctx *current_ctx;
  107. };
  108. #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
  109. #define VIDEO1394_DEBUG
  110. #endif
  111. #ifdef DBGMSG
  112. #undef DBGMSG
  113. #endif
  114. #ifdef VIDEO1394_DEBUG
  115. #define DBGMSG(card, fmt, args...) \
  116. printk(KERN_INFO "video1394_%d: " fmt "\n" , card , ## args)
  117. #else
  118. #define DBGMSG(card, fmt, args...) do {} while (0)
  119. #endif
  120. /* print general (card independent) information */
  121. #define PRINT_G(level, fmt, args...) \
  122. printk(level "video1394: " fmt "\n" , ## args)
  123. /* print card specific information */
  124. #define PRINT(level, card, fmt, args...) \
  125. printk(level "video1394_%d: " fmt "\n" , card , ## args)
  126. static void wakeup_dma_ir_ctx(unsigned long l);
  127. static void wakeup_dma_it_ctx(unsigned long l);
  128. static struct hpsb_highlevel video1394_highlevel;
  129. static int free_dma_iso_ctx(struct dma_iso_ctx *d)
  130. {
  131. int i;
  132. DBGMSG(d->ohci->host->id, "Freeing dma_iso_ctx %d", d->ctx);
  133. ohci1394_stop_context(d->ohci, d->ctrlClear, NULL);
  134. if (d->iso_tasklet.link.next != NULL)
  135. ohci1394_unregister_iso_tasklet(d->ohci, &d->iso_tasklet);
  136. dma_region_free(&d->dma);
  137. if (d->prg_reg) {
  138. for (i = 0; i < d->num_desc; i++)
  139. dma_prog_region_free(&d->prg_reg[i]);
  140. kfree(d->prg_reg);
  141. }
  142. kfree(d->ir_prg);
  143. kfree(d->it_prg);
  144. kfree(d->buffer_status);
  145. kfree(d->buffer_prg_assignment);
  146. kfree(d->buffer_time);
  147. kfree(d->last_used_cmd);
  148. kfree(d->next_buffer);
  149. list_del(&d->link);
  150. kfree(d);
  151. return 0;
  152. }
  153. static struct dma_iso_ctx *
  154. alloc_dma_iso_ctx(struct ti_ohci *ohci, int type, int num_desc,
  155. int buf_size, int channel, unsigned int packet_size)
  156. {
  157. struct dma_iso_ctx *d;
  158. int i;
  159. d = kzalloc(sizeof(*d), GFP_KERNEL);
  160. if (!d) {
  161. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma_iso_ctx");
  162. return NULL;
  163. }
  164. d->ohci = ohci;
  165. d->type = type;
  166. d->channel = channel;
  167. d->num_desc = num_desc;
  168. d->frame_size = buf_size;
  169. d->buf_size = PAGE_ALIGN(buf_size);
  170. d->last_buffer = -1;
  171. INIT_LIST_HEAD(&d->link);
  172. init_waitqueue_head(&d->waitq);
  173. /* Init the regions for easy cleanup */
  174. dma_region_init(&d->dma);
  175. if (dma_region_alloc(&d->dma, (d->num_desc - 1) * d->buf_size, ohci->dev,
  176. PCI_DMA_BIDIRECTIONAL)) {
  177. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma buffer");
  178. free_dma_iso_ctx(d);
  179. return NULL;
  180. }
  181. if (type == OHCI_ISO_RECEIVE)
  182. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  183. wakeup_dma_ir_ctx,
  184. (unsigned long) d);
  185. else
  186. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  187. wakeup_dma_it_ctx,
  188. (unsigned long) d);
  189. if (ohci1394_register_iso_tasklet(ohci, &d->iso_tasklet) < 0) {
  190. PRINT(KERN_ERR, ohci->host->id, "no free iso %s contexts",
  191. type == OHCI_ISO_RECEIVE ? "receive" : "transmit");
  192. free_dma_iso_ctx(d);
  193. return NULL;
  194. }
  195. d->ctx = d->iso_tasklet.context;
  196. d->prg_reg = kmalloc(d->num_desc * sizeof(*d->prg_reg), GFP_KERNEL);
  197. if (!d->prg_reg) {
  198. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate ir prg regs");
  199. free_dma_iso_ctx(d);
  200. return NULL;
  201. }
  202. /* Makes for easier cleanup */
  203. for (i = 0; i < d->num_desc; i++)
  204. dma_prog_region_init(&d->prg_reg[i]);
  205. if (type == OHCI_ISO_RECEIVE) {
  206. d->ctrlSet = OHCI1394_IsoRcvContextControlSet+32*d->ctx;
  207. d->ctrlClear = OHCI1394_IsoRcvContextControlClear+32*d->ctx;
  208. d->cmdPtr = OHCI1394_IsoRcvCommandPtr+32*d->ctx;
  209. d->ctxMatch = OHCI1394_IsoRcvContextMatch+32*d->ctx;
  210. d->ir_prg = kzalloc(d->num_desc * sizeof(*d->ir_prg),
  211. GFP_KERNEL);
  212. if (!d->ir_prg) {
  213. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  214. free_dma_iso_ctx(d);
  215. return NULL;
  216. }
  217. d->nb_cmd = d->buf_size / PAGE_SIZE + 1;
  218. d->left_size = (d->frame_size % PAGE_SIZE) ?
  219. d->frame_size % PAGE_SIZE : PAGE_SIZE;
  220. for (i = 0;i < d->num_desc; i++) {
  221. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  222. sizeof(struct dma_cmd), ohci->dev)) {
  223. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  224. free_dma_iso_ctx(d);
  225. return NULL;
  226. }
  227. d->ir_prg[i] = (struct dma_cmd *)d->prg_reg[i].kvirt;
  228. }
  229. } else { /* OHCI_ISO_TRANSMIT */
  230. d->ctrlSet = OHCI1394_IsoXmitContextControlSet+16*d->ctx;
  231. d->ctrlClear = OHCI1394_IsoXmitContextControlClear+16*d->ctx;
  232. d->cmdPtr = OHCI1394_IsoXmitCommandPtr+16*d->ctx;
  233. d->it_prg = kzalloc(d->num_desc * sizeof(*d->it_prg),
  234. GFP_KERNEL);
  235. if (!d->it_prg) {
  236. PRINT(KERN_ERR, ohci->host->id,
  237. "Failed to allocate dma it prg");
  238. free_dma_iso_ctx(d);
  239. return NULL;
  240. }
  241. d->packet_size = packet_size;
  242. if (PAGE_SIZE % packet_size || packet_size>4096) {
  243. PRINT(KERN_ERR, ohci->host->id,
  244. "Packet size %d (page_size: %ld) "
  245. "not yet supported\n",
  246. packet_size, PAGE_SIZE);
  247. free_dma_iso_ctx(d);
  248. return NULL;
  249. }
  250. d->nb_cmd = d->frame_size / d->packet_size;
  251. if (d->frame_size % d->packet_size) {
  252. d->nb_cmd++;
  253. d->left_size = d->frame_size % d->packet_size;
  254. } else
  255. d->left_size = d->packet_size;
  256. for (i = 0; i < d->num_desc; i++) {
  257. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  258. sizeof(struct it_dma_prg), ohci->dev)) {
  259. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma it prg");
  260. free_dma_iso_ctx(d);
  261. return NULL;
  262. }
  263. d->it_prg[i] = (struct it_dma_prg *)d->prg_reg[i].kvirt;
  264. }
  265. }
  266. d->buffer_status =
  267. kzalloc(d->num_desc * sizeof(*d->buffer_status), GFP_KERNEL);
  268. d->buffer_prg_assignment =
  269. kzalloc(d->num_desc * sizeof(*d->buffer_prg_assignment), GFP_KERNEL);
  270. d->buffer_time =
  271. kzalloc(d->num_desc * sizeof(*d->buffer_time), GFP_KERNEL);
  272. d->last_used_cmd =
  273. kzalloc(d->num_desc * sizeof(*d->last_used_cmd), GFP_KERNEL);
  274. d->next_buffer =
  275. kzalloc(d->num_desc * sizeof(*d->next_buffer), GFP_KERNEL);
  276. if (!d->buffer_status || !d->buffer_prg_assignment || !d->buffer_time ||
  277. !d->last_used_cmd || !d->next_buffer) {
  278. PRINT(KERN_ERR, ohci->host->id,
  279. "Failed to allocate dma_iso_ctx member");
  280. free_dma_iso_ctx(d);
  281. return NULL;
  282. }
  283. spin_lock_init(&d->lock);
  284. DBGMSG(ohci->host->id, "Iso %s DMA: %d buffers "
  285. "of size %d allocated for a frame size %d, each with %d prgs",
  286. (type == OHCI_ISO_RECEIVE) ? "receive" : "transmit",
  287. d->num_desc - 1, d->buf_size, d->frame_size, d->nb_cmd);
  288. return d;
  289. }
  290. static void reset_ir_status(struct dma_iso_ctx *d, int n)
  291. {
  292. int i;
  293. d->ir_prg[n][0].status = cpu_to_le32(4);
  294. d->ir_prg[n][1].status = cpu_to_le32(PAGE_SIZE-4);
  295. for (i = 2; i < d->nb_cmd - 1; i++)
  296. d->ir_prg[n][i].status = cpu_to_le32(PAGE_SIZE);
  297. d->ir_prg[n][i].status = cpu_to_le32(d->left_size);
  298. }
  299. static void reprogram_dma_ir_prg(struct dma_iso_ctx *d, int n, int buffer, int flags)
  300. {
  301. struct dma_cmd *ir_prg = d->ir_prg[n];
  302. unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
  303. int i;
  304. d->buffer_prg_assignment[n] = buffer;
  305. ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
  306. (unsigned long)d->dma.kvirt));
  307. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  308. (buf + 4) - (unsigned long)d->dma.kvirt));
  309. for (i=2;i<d->nb_cmd-1;i++) {
  310. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  311. (buf+(i-1)*PAGE_SIZE) -
  312. (unsigned long)d->dma.kvirt));
  313. }
  314. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  315. DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
  316. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  317. (buf+(i-1)*PAGE_SIZE) - (unsigned long)d->dma.kvirt));
  318. }
  319. static void initialize_dma_ir_prg(struct dma_iso_ctx *d, int n, int flags)
  320. {
  321. struct dma_cmd *ir_prg = d->ir_prg[n];
  322. struct dma_prog_region *ir_reg = &d->prg_reg[n];
  323. unsigned long buf = (unsigned long)d->dma.kvirt;
  324. int i;
  325. /* the first descriptor will read only 4 bytes */
  326. ir_prg[0].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  327. DMA_CTL_BRANCH | 4);
  328. /* set the sync flag */
  329. if (flags & VIDEO1394_SYNC_FRAMES)
  330. ir_prg[0].control |= cpu_to_le32(DMA_CTL_WAIT);
  331. ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
  332. (unsigned long)d->dma.kvirt));
  333. ir_prg[0].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  334. 1 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  335. /* If there is *not* only one DMA page per frame (hence, d->nb_cmd==2) */
  336. if (d->nb_cmd > 2) {
  337. /* The second descriptor will read PAGE_SIZE-4 bytes */
  338. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  339. DMA_CTL_BRANCH | (PAGE_SIZE-4));
  340. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf + 4) -
  341. (unsigned long)d->dma.kvirt));
  342. ir_prg[1].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  343. 2 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  344. for (i = 2; i < d->nb_cmd - 1; i++) {
  345. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  346. DMA_CTL_BRANCH | PAGE_SIZE);
  347. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  348. (buf+(i-1)*PAGE_SIZE) -
  349. (unsigned long)d->dma.kvirt));
  350. ir_prg[i].branchAddress =
  351. cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  352. (i + 1) * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  353. }
  354. /* The last descriptor will generate an interrupt */
  355. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  356. DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
  357. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  358. (buf+(i-1)*PAGE_SIZE) -
  359. (unsigned long)d->dma.kvirt));
  360. } else {
  361. /* Only one DMA page is used. Read d->left_size immediately and */
  362. /* generate an interrupt as this is also the last page. */
  363. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  364. DMA_CTL_IRQ | DMA_CTL_BRANCH | (d->left_size-4));
  365. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  366. (buf + 4) - (unsigned long)d->dma.kvirt));
  367. }
  368. }
  369. static void initialize_dma_ir_ctx(struct dma_iso_ctx *d, int tag, int flags)
  370. {
  371. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  372. int i;
  373. d->flags = flags;
  374. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  375. for (i=0;i<d->num_desc;i++) {
  376. initialize_dma_ir_prg(d, i, flags);
  377. reset_ir_status(d, i);
  378. }
  379. /* reset the ctrl register */
  380. reg_write(ohci, d->ctrlClear, 0xf0000000);
  381. /* Set bufferFill */
  382. reg_write(ohci, d->ctrlSet, 0x80000000);
  383. /* Set isoch header */
  384. if (flags & VIDEO1394_INCLUDE_ISO_HEADERS)
  385. reg_write(ohci, d->ctrlSet, 0x40000000);
  386. /* Set the context match register to match on all tags,
  387. sync for sync tag, and listen to d->channel */
  388. reg_write(ohci, d->ctxMatch, 0xf0000000|((tag&0xf)<<8)|d->channel);
  389. /* Set up isoRecvIntMask to generate interrupts */
  390. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1<<d->ctx);
  391. }
  392. /* find which context is listening to this channel */
  393. static struct dma_iso_ctx *
  394. find_ctx(struct list_head *list, int type, int channel)
  395. {
  396. struct dma_iso_ctx *ctx;
  397. list_for_each_entry(ctx, list, link) {
  398. if (ctx->type == type && ctx->channel == channel)
  399. return ctx;
  400. }
  401. return NULL;
  402. }
  403. static void wakeup_dma_ir_ctx(unsigned long l)
  404. {
  405. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  406. int i;
  407. spin_lock(&d->lock);
  408. for (i = 0; i < d->num_desc; i++) {
  409. if (d->ir_prg[i][d->nb_cmd-1].status & cpu_to_le32(0xFFFF0000)) {
  410. reset_ir_status(d, i);
  411. d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
  412. do_gettimeofday(&d->buffer_time[d->buffer_prg_assignment[i]]);
  413. dma_region_sync_for_cpu(&d->dma,
  414. d->buffer_prg_assignment[i] * d->buf_size,
  415. d->buf_size);
  416. }
  417. }
  418. spin_unlock(&d->lock);
  419. if (waitqueue_active(&d->waitq))
  420. wake_up_interruptible(&d->waitq);
  421. }
  422. static inline void put_timestamp(struct ti_ohci *ohci, struct dma_iso_ctx * d,
  423. int n)
  424. {
  425. unsigned char* buf = d->dma.kvirt + n * d->buf_size;
  426. u32 cycleTimer;
  427. u32 timeStamp;
  428. if (n == -1) {
  429. return;
  430. }
  431. cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  432. timeStamp = ((cycleTimer & 0x0fff) + d->syt_offset); /* 11059 = 450 us */
  433. timeStamp = (timeStamp % 3072 + ((timeStamp / 3072) << 12)
  434. + (cycleTimer & 0xf000)) & 0xffff;
  435. buf[6] = timeStamp >> 8;
  436. buf[7] = timeStamp & 0xff;
  437. /* if first packet is empty packet, then put timestamp into the next full one too */
  438. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  439. buf += d->packet_size;
  440. buf[6] = timeStamp >> 8;
  441. buf[7] = timeStamp & 0xff;
  442. }
  443. /* do the next buffer frame too in case of irq latency */
  444. n = d->next_buffer[n];
  445. if (n == -1) {
  446. return;
  447. }
  448. buf = d->dma.kvirt + n * d->buf_size;
  449. timeStamp += (d->last_used_cmd[n] << 12) & 0xffff;
  450. buf[6] = timeStamp >> 8;
  451. buf[7] = timeStamp & 0xff;
  452. /* if first packet is empty packet, then put timestamp into the next full one too */
  453. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  454. buf += d->packet_size;
  455. buf[6] = timeStamp >> 8;
  456. buf[7] = timeStamp & 0xff;
  457. }
  458. #if 0
  459. printk("curr: %d, next: %d, cycleTimer: %08x timeStamp: %08x\n",
  460. curr, n, cycleTimer, timeStamp);
  461. #endif
  462. }
  463. static void wakeup_dma_it_ctx(unsigned long l)
  464. {
  465. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  466. struct ti_ohci *ohci = d->ohci;
  467. int i;
  468. spin_lock(&d->lock);
  469. for (i = 0; i < d->num_desc; i++) {
  470. if (d->it_prg[i][d->last_used_cmd[i]].end.status &
  471. cpu_to_le32(0xFFFF0000)) {
  472. int next = d->next_buffer[i];
  473. put_timestamp(ohci, d, next);
  474. d->it_prg[i][d->last_used_cmd[i]].end.status = 0;
  475. d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
  476. }
  477. }
  478. spin_unlock(&d->lock);
  479. if (waitqueue_active(&d->waitq))
  480. wake_up_interruptible(&d->waitq);
  481. }
  482. static void reprogram_dma_it_prg(struct dma_iso_ctx *d, int n, int buffer)
  483. {
  484. struct it_dma_prg *it_prg = d->it_prg[n];
  485. unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
  486. int i;
  487. d->buffer_prg_assignment[n] = buffer;
  488. for (i=0;i<d->nb_cmd;i++) {
  489. it_prg[i].end.address =
  490. cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  491. (buf+i*d->packet_size) - (unsigned long)d->dma.kvirt));
  492. }
  493. }
  494. static void initialize_dma_it_prg(struct dma_iso_ctx *d, int n, int sync_tag)
  495. {
  496. struct it_dma_prg *it_prg = d->it_prg[n];
  497. struct dma_prog_region *it_reg = &d->prg_reg[n];
  498. unsigned long buf = (unsigned long)d->dma.kvirt;
  499. int i;
  500. d->last_used_cmd[n] = d->nb_cmd - 1;
  501. for (i=0;i<d->nb_cmd;i++) {
  502. it_prg[i].begin.control = cpu_to_le32(DMA_CTL_OUTPUT_MORE |
  503. DMA_CTL_IMMEDIATE | 8) ;
  504. it_prg[i].begin.address = 0;
  505. it_prg[i].begin.status = 0;
  506. it_prg[i].data[0] = cpu_to_le32(
  507. (IEEE1394_SPEED_100 << 16)
  508. | (/* tag */ 1 << 14)
  509. | (d->channel << 8)
  510. | (TCODE_ISO_DATA << 4));
  511. if (i==0) it_prg[i].data[0] |= cpu_to_le32(sync_tag);
  512. it_prg[i].data[1] = cpu_to_le32(d->packet_size << 16);
  513. it_prg[i].data[2] = 0;
  514. it_prg[i].data[3] = 0;
  515. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST |
  516. DMA_CTL_BRANCH);
  517. it_prg[i].end.address =
  518. cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf+i*d->packet_size) -
  519. (unsigned long)d->dma.kvirt));
  520. if (i<d->nb_cmd-1) {
  521. it_prg[i].end.control |= cpu_to_le32(d->packet_size);
  522. it_prg[i].begin.branchAddress =
  523. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  524. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  525. it_prg[i].end.branchAddress =
  526. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  527. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  528. } else {
  529. /* the last prg generates an interrupt */
  530. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  531. DMA_CTL_IRQ | d->left_size);
  532. /* the last prg doesn't branch */
  533. it_prg[i].begin.branchAddress = 0;
  534. it_prg[i].end.branchAddress = 0;
  535. }
  536. it_prg[i].end.status = 0;
  537. }
  538. }
  539. static void initialize_dma_it_prg_var_packet_queue(
  540. struct dma_iso_ctx *d, int n, unsigned int * packet_sizes,
  541. struct ti_ohci *ohci)
  542. {
  543. struct it_dma_prg *it_prg = d->it_prg[n];
  544. struct dma_prog_region *it_reg = &d->prg_reg[n];
  545. int i;
  546. #if 0
  547. if (n != -1) {
  548. put_timestamp(ohci, d, n);
  549. }
  550. #endif
  551. d->last_used_cmd[n] = d->nb_cmd - 1;
  552. for (i = 0; i < d->nb_cmd; i++) {
  553. unsigned int size;
  554. if (packet_sizes[i] > d->packet_size) {
  555. size = d->packet_size;
  556. } else {
  557. size = packet_sizes[i];
  558. }
  559. it_prg[i].data[1] = cpu_to_le32(size << 16);
  560. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST | DMA_CTL_BRANCH);
  561. if (i < d->nb_cmd-1 && packet_sizes[i+1] != 0) {
  562. it_prg[i].end.control |= cpu_to_le32(size);
  563. it_prg[i].begin.branchAddress =
  564. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  565. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  566. it_prg[i].end.branchAddress =
  567. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  568. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  569. } else {
  570. /* the last prg generates an interrupt */
  571. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  572. DMA_CTL_IRQ | size);
  573. /* the last prg doesn't branch */
  574. it_prg[i].begin.branchAddress = 0;
  575. it_prg[i].end.branchAddress = 0;
  576. d->last_used_cmd[n] = i;
  577. break;
  578. }
  579. }
  580. }
  581. static void initialize_dma_it_ctx(struct dma_iso_ctx *d, int sync_tag,
  582. unsigned int syt_offset, int flags)
  583. {
  584. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  585. int i;
  586. d->flags = flags;
  587. d->syt_offset = (syt_offset == 0 ? 11000 : syt_offset);
  588. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  589. for (i=0;i<d->num_desc;i++)
  590. initialize_dma_it_prg(d, i, sync_tag);
  591. /* Set up isoRecvIntMask to generate interrupts */
  592. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1<<d->ctx);
  593. }
  594. static inline unsigned video1394_buffer_state(struct dma_iso_ctx *d,
  595. unsigned int buffer)
  596. {
  597. unsigned long flags;
  598. unsigned int ret;
  599. spin_lock_irqsave(&d->lock, flags);
  600. ret = d->buffer_status[buffer];
  601. spin_unlock_irqrestore(&d->lock, flags);
  602. return ret;
  603. }
  604. static long video1394_ioctl(struct file *file,
  605. unsigned int cmd, unsigned long arg)
  606. {
  607. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  608. struct ti_ohci *ohci = ctx->ohci;
  609. unsigned long flags;
  610. void __user *argp = (void __user *)arg;
  611. switch(cmd)
  612. {
  613. case VIDEO1394_IOC_LISTEN_CHANNEL:
  614. case VIDEO1394_IOC_TALK_CHANNEL:
  615. {
  616. struct video1394_mmap v;
  617. u64 mask;
  618. struct dma_iso_ctx *d;
  619. int i;
  620. if (copy_from_user(&v, argp, sizeof(v)))
  621. return -EFAULT;
  622. /* if channel < 0, find lowest available one */
  623. if (v.channel < 0) {
  624. mask = (u64)0x1;
  625. for (i=0; ; i++) {
  626. if (i == ISO_CHANNELS) {
  627. PRINT(KERN_ERR, ohci->host->id,
  628. "No free channel found");
  629. return -EAGAIN;
  630. }
  631. if (!(ohci->ISO_channel_usage & mask)) {
  632. v.channel = i;
  633. PRINT(KERN_INFO, ohci->host->id, "Found free channel %d", i);
  634. break;
  635. }
  636. mask = mask << 1;
  637. }
  638. } else if (v.channel >= ISO_CHANNELS) {
  639. PRINT(KERN_ERR, ohci->host->id,
  640. "Iso channel %d out of bounds", v.channel);
  641. return -EINVAL;
  642. } else {
  643. mask = (u64)0x1<<v.channel;
  644. }
  645. DBGMSG(ohci->host->id, "mask: %08X%08X usage: %08X%08X\n",
  646. (u32)(mask>>32),(u32)(mask&0xffffffff),
  647. (u32)(ohci->ISO_channel_usage>>32),
  648. (u32)(ohci->ISO_channel_usage&0xffffffff));
  649. if (ohci->ISO_channel_usage & mask) {
  650. PRINT(KERN_ERR, ohci->host->id,
  651. "Channel %d is already taken", v.channel);
  652. return -EBUSY;
  653. }
  654. if (v.buf_size == 0 || v.buf_size > VIDEO1394_MAX_SIZE) {
  655. PRINT(KERN_ERR, ohci->host->id,
  656. "Invalid %d length buffer requested",v.buf_size);
  657. return -EINVAL;
  658. }
  659. if (v.nb_buffers == 0 || v.nb_buffers > VIDEO1394_MAX_SIZE) {
  660. PRINT(KERN_ERR, ohci->host->id,
  661. "Invalid %d buffers requested",v.nb_buffers);
  662. return -EINVAL;
  663. }
  664. if (v.nb_buffers * v.buf_size > VIDEO1394_MAX_SIZE) {
  665. PRINT(KERN_ERR, ohci->host->id,
  666. "%d buffers of size %d bytes is too big",
  667. v.nb_buffers, v.buf_size);
  668. return -EINVAL;
  669. }
  670. if (cmd == VIDEO1394_IOC_LISTEN_CHANNEL) {
  671. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_RECEIVE,
  672. v.nb_buffers + 1, v.buf_size,
  673. v.channel, 0);
  674. if (d == NULL) {
  675. PRINT(KERN_ERR, ohci->host->id,
  676. "Couldn't allocate ir context");
  677. return -EAGAIN;
  678. }
  679. initialize_dma_ir_ctx(d, v.sync_tag, v.flags);
  680. ctx->current_ctx = d;
  681. v.buf_size = d->buf_size;
  682. list_add_tail(&d->link, &ctx->context_list);
  683. DBGMSG(ohci->host->id,
  684. "iso context %d listen on channel %d",
  685. d->ctx, v.channel);
  686. }
  687. else {
  688. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_TRANSMIT,
  689. v.nb_buffers + 1, v.buf_size,
  690. v.channel, v.packet_size);
  691. if (d == NULL) {
  692. PRINT(KERN_ERR, ohci->host->id,
  693. "Couldn't allocate it context");
  694. return -EAGAIN;
  695. }
  696. initialize_dma_it_ctx(d, v.sync_tag,
  697. v.syt_offset, v.flags);
  698. ctx->current_ctx = d;
  699. v.buf_size = d->buf_size;
  700. list_add_tail(&d->link, &ctx->context_list);
  701. DBGMSG(ohci->host->id,
  702. "Iso context %d talk on channel %d", d->ctx,
  703. v.channel);
  704. }
  705. if (copy_to_user(argp, &v, sizeof(v))) {
  706. /* FIXME : free allocated dma resources */
  707. return -EFAULT;
  708. }
  709. ohci->ISO_channel_usage |= mask;
  710. return 0;
  711. }
  712. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  713. case VIDEO1394_IOC_UNTALK_CHANNEL:
  714. {
  715. int channel;
  716. u64 mask;
  717. struct dma_iso_ctx *d;
  718. if (copy_from_user(&channel, argp, sizeof(int)))
  719. return -EFAULT;
  720. if (channel < 0 || channel >= ISO_CHANNELS) {
  721. PRINT(KERN_ERR, ohci->host->id,
  722. "Iso channel %d out of bound", channel);
  723. return -EINVAL;
  724. }
  725. mask = (u64)0x1<<channel;
  726. if (!(ohci->ISO_channel_usage & mask)) {
  727. PRINT(KERN_ERR, ohci->host->id,
  728. "Channel %d is not being used", channel);
  729. return -ESRCH;
  730. }
  731. /* Mark this channel as unused */
  732. ohci->ISO_channel_usage &= ~mask;
  733. if (cmd == VIDEO1394_IOC_UNLISTEN_CHANNEL)
  734. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, channel);
  735. else
  736. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, channel);
  737. if (d == NULL) return -ESRCH;
  738. DBGMSG(ohci->host->id, "Iso context %d "
  739. "stop talking on channel %d", d->ctx, channel);
  740. free_dma_iso_ctx(d);
  741. return 0;
  742. }
  743. case VIDEO1394_IOC_LISTEN_QUEUE_BUFFER:
  744. {
  745. struct video1394_wait v;
  746. struct dma_iso_ctx *d;
  747. int next_prg;
  748. if (unlikely(copy_from_user(&v, argp, sizeof(v))))
  749. return -EFAULT;
  750. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  751. if (unlikely(d == NULL))
  752. return -EFAULT;
  753. if (unlikely(v.buffer >= d->num_desc - 1)) {
  754. PRINT(KERN_ERR, ohci->host->id,
  755. "Buffer %d out of range",v.buffer);
  756. return -EINVAL;
  757. }
  758. spin_lock_irqsave(&d->lock,flags);
  759. if (unlikely(d->buffer_status[v.buffer]==VIDEO1394_BUFFER_QUEUED)) {
  760. PRINT(KERN_ERR, ohci->host->id,
  761. "Buffer %d is already used",v.buffer);
  762. spin_unlock_irqrestore(&d->lock,flags);
  763. return -EBUSY;
  764. }
  765. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  766. next_prg = (d->last_buffer + 1) % d->num_desc;
  767. if (d->last_buffer>=0)
  768. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress =
  769. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0)
  770. & 0xfffffff0) | 0x1);
  771. d->last_buffer = next_prg;
  772. reprogram_dma_ir_prg(d, d->last_buffer, v.buffer, d->flags);
  773. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress = 0;
  774. spin_unlock_irqrestore(&d->lock,flags);
  775. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  776. {
  777. DBGMSG(ohci->host->id, "Starting iso DMA ctx=%d",d->ctx);
  778. /* Tell the controller where the first program is */
  779. reg_write(ohci, d->cmdPtr,
  780. dma_prog_region_offset_to_bus(&d->prg_reg[d->last_buffer], 0) | 0x1);
  781. /* Run IR context */
  782. reg_write(ohci, d->ctrlSet, 0x8000);
  783. }
  784. else {
  785. /* Wake up dma context if necessary */
  786. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  787. DBGMSG(ohci->host->id,
  788. "Waking up iso dma ctx=%d", d->ctx);
  789. reg_write(ohci, d->ctrlSet, 0x1000);
  790. }
  791. }
  792. return 0;
  793. }
  794. case VIDEO1394_IOC_LISTEN_WAIT_BUFFER:
  795. case VIDEO1394_IOC_LISTEN_POLL_BUFFER:
  796. {
  797. struct video1394_wait v;
  798. struct dma_iso_ctx *d;
  799. int i = 0;
  800. if (unlikely(copy_from_user(&v, argp, sizeof(v))))
  801. return -EFAULT;
  802. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  803. if (unlikely(d == NULL))
  804. return -EFAULT;
  805. if (unlikely(v.buffer > d->num_desc - 1)) {
  806. PRINT(KERN_ERR, ohci->host->id,
  807. "Buffer %d out of range",v.buffer);
  808. return -EINVAL;
  809. }
  810. /*
  811. * I change the way it works so that it returns
  812. * the last received frame.
  813. */
  814. spin_lock_irqsave(&d->lock, flags);
  815. switch(d->buffer_status[v.buffer]) {
  816. case VIDEO1394_BUFFER_READY:
  817. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  818. break;
  819. case VIDEO1394_BUFFER_QUEUED:
  820. if (cmd == VIDEO1394_IOC_LISTEN_POLL_BUFFER) {
  821. /* for polling, return error code EINTR */
  822. spin_unlock_irqrestore(&d->lock, flags);
  823. return -EINTR;
  824. }
  825. spin_unlock_irqrestore(&d->lock, flags);
  826. wait_event_interruptible(d->waitq,
  827. video1394_buffer_state(d, v.buffer) ==
  828. VIDEO1394_BUFFER_READY);
  829. if (signal_pending(current))
  830. return -EINTR;
  831. spin_lock_irqsave(&d->lock, flags);
  832. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  833. break;
  834. default:
  835. PRINT(KERN_ERR, ohci->host->id,
  836. "Buffer %d is not queued",v.buffer);
  837. spin_unlock_irqrestore(&d->lock, flags);
  838. return -ESRCH;
  839. }
  840. /* set time of buffer */
  841. v.filltime = d->buffer_time[v.buffer];
  842. /*
  843. * Look ahead to see how many more buffers have been received
  844. */
  845. i=0;
  846. while (d->buffer_status[(v.buffer+1)%(d->num_desc - 1)]==
  847. VIDEO1394_BUFFER_READY) {
  848. v.buffer=(v.buffer+1)%(d->num_desc - 1);
  849. i++;
  850. }
  851. spin_unlock_irqrestore(&d->lock, flags);
  852. v.buffer=i;
  853. if (unlikely(copy_to_user(argp, &v, sizeof(v))))
  854. return -EFAULT;
  855. return 0;
  856. }
  857. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  858. {
  859. struct video1394_wait v;
  860. unsigned int *psizes = NULL;
  861. struct dma_iso_ctx *d;
  862. int next_prg;
  863. if (copy_from_user(&v, argp, sizeof(v)))
  864. return -EFAULT;
  865. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  866. if (d == NULL) return -EFAULT;
  867. if (v.buffer >= d->num_desc - 1) {
  868. PRINT(KERN_ERR, ohci->host->id,
  869. "Buffer %d out of range",v.buffer);
  870. return -EINVAL;
  871. }
  872. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  873. int buf_size = d->nb_cmd * sizeof(*psizes);
  874. struct video1394_queue_variable __user *p = argp;
  875. unsigned int __user *qv;
  876. if (get_user(qv, &p->packet_sizes))
  877. return -EFAULT;
  878. psizes = kmalloc(buf_size, GFP_KERNEL);
  879. if (!psizes)
  880. return -ENOMEM;
  881. if (copy_from_user(psizes, qv, buf_size)) {
  882. kfree(psizes);
  883. return -EFAULT;
  884. }
  885. }
  886. spin_lock_irqsave(&d->lock,flags);
  887. /* last_buffer is last_prg */
  888. next_prg = (d->last_buffer + 1) % d->num_desc;
  889. if (d->buffer_status[v.buffer]!=VIDEO1394_BUFFER_FREE) {
  890. PRINT(KERN_ERR, ohci->host->id,
  891. "Buffer %d is already used",v.buffer);
  892. spin_unlock_irqrestore(&d->lock,flags);
  893. kfree(psizes);
  894. return -EBUSY;
  895. }
  896. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  897. initialize_dma_it_prg_var_packet_queue(
  898. d, next_prg, psizes, ohci);
  899. }
  900. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  901. if (d->last_buffer >= 0) {
  902. d->it_prg[d->last_buffer]
  903. [ d->last_used_cmd[d->last_buffer] ].end.branchAddress =
  904. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg],
  905. 0) & 0xfffffff0) | 0x3);
  906. d->it_prg[d->last_buffer]
  907. [ d->last_used_cmd[d->last_buffer] ].begin.branchAddress =
  908. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg],
  909. 0) & 0xfffffff0) | 0x3);
  910. d->next_buffer[d->last_buffer] = (v.buffer + 1) % (d->num_desc - 1);
  911. }
  912. d->last_buffer = next_prg;
  913. reprogram_dma_it_prg(d, d->last_buffer, v.buffer);
  914. d->next_buffer[d->last_buffer] = -1;
  915. d->it_prg[d->last_buffer][d->last_used_cmd[d->last_buffer]].end.branchAddress = 0;
  916. spin_unlock_irqrestore(&d->lock,flags);
  917. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  918. {
  919. DBGMSG(ohci->host->id, "Starting iso transmit DMA ctx=%d",
  920. d->ctx);
  921. put_timestamp(ohci, d, d->last_buffer);
  922. dma_region_sync_for_device(&d->dma,
  923. v.buffer * d->buf_size, d->buf_size);
  924. /* Tell the controller where the first program is */
  925. reg_write(ohci, d->cmdPtr,
  926. dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0) | 0x3);
  927. /* Run IT context */
  928. reg_write(ohci, d->ctrlSet, 0x8000);
  929. }
  930. else {
  931. /* Wake up dma context if necessary */
  932. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  933. DBGMSG(ohci->host->id,
  934. "Waking up iso transmit dma ctx=%d",
  935. d->ctx);
  936. put_timestamp(ohci, d, d->last_buffer);
  937. dma_region_sync_for_device(&d->dma,
  938. v.buffer * d->buf_size, d->buf_size);
  939. reg_write(ohci, d->ctrlSet, 0x1000);
  940. }
  941. }
  942. kfree(psizes);
  943. return 0;
  944. }
  945. case VIDEO1394_IOC_TALK_WAIT_BUFFER:
  946. {
  947. struct video1394_wait v;
  948. struct dma_iso_ctx *d;
  949. if (copy_from_user(&v, argp, sizeof(v)))
  950. return -EFAULT;
  951. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  952. if (d == NULL) return -EFAULT;
  953. if (v.buffer >= d->num_desc - 1) {
  954. PRINT(KERN_ERR, ohci->host->id,
  955. "Buffer %d out of range",v.buffer);
  956. return -EINVAL;
  957. }
  958. switch(d->buffer_status[v.buffer]) {
  959. case VIDEO1394_BUFFER_READY:
  960. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  961. return 0;
  962. case VIDEO1394_BUFFER_QUEUED:
  963. wait_event_interruptible(d->waitq,
  964. (d->buffer_status[v.buffer] == VIDEO1394_BUFFER_READY));
  965. if (signal_pending(current))
  966. return -EINTR;
  967. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  968. return 0;
  969. default:
  970. PRINT(KERN_ERR, ohci->host->id,
  971. "Buffer %d is not queued",v.buffer);
  972. return -ESRCH;
  973. }
  974. }
  975. default:
  976. return -ENOTTY;
  977. }
  978. }
  979. /*
  980. * This maps the vmalloced and reserved buffer to user space.
  981. *
  982. * FIXME:
  983. * - PAGE_READONLY should suffice!?
  984. * - remap_pfn_range is kind of inefficient for page by page remapping.
  985. * But e.g. pte_alloc() does not work in modules ... :-(
  986. */
  987. static int video1394_mmap(struct file *file, struct vm_area_struct *vma)
  988. {
  989. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  990. if (ctx->current_ctx == NULL) {
  991. PRINT(KERN_ERR, ctx->ohci->host->id,
  992. "Current iso context not set");
  993. return -EINVAL;
  994. }
  995. return dma_region_mmap(&ctx->current_ctx->dma, file, vma);
  996. }
  997. static unsigned int video1394_poll(struct file *file, poll_table *pt)
  998. {
  999. struct file_ctx *ctx;
  1000. unsigned int mask = 0;
  1001. unsigned long flags;
  1002. struct dma_iso_ctx *d;
  1003. int i;
  1004. ctx = file->private_data;
  1005. d = ctx->current_ctx;
  1006. if (d == NULL) {
  1007. PRINT(KERN_ERR, ctx->ohci->host->id,
  1008. "Current iso context not set");
  1009. return POLLERR;
  1010. }
  1011. poll_wait(file, &d->waitq, pt);
  1012. spin_lock_irqsave(&d->lock, flags);
  1013. for (i = 0; i < d->num_desc; i++) {
  1014. if (d->buffer_status[i] == VIDEO1394_BUFFER_READY) {
  1015. mask |= POLLIN | POLLRDNORM;
  1016. break;
  1017. }
  1018. }
  1019. spin_unlock_irqrestore(&d->lock, flags);
  1020. return mask;
  1021. }
  1022. static int video1394_open(struct inode *inode, struct file *file)
  1023. {
  1024. int i = ieee1394_file_to_instance(file);
  1025. struct ti_ohci *ohci;
  1026. struct file_ctx *ctx;
  1027. ohci = hpsb_get_hostinfo_bykey(&video1394_highlevel, i);
  1028. if (ohci == NULL)
  1029. return -EIO;
  1030. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  1031. if (!ctx) {
  1032. PRINT(KERN_ERR, ohci->host->id, "Cannot malloc file_ctx");
  1033. return -ENOMEM;
  1034. }
  1035. ctx->ohci = ohci;
  1036. INIT_LIST_HEAD(&ctx->context_list);
  1037. ctx->current_ctx = NULL;
  1038. file->private_data = ctx;
  1039. return 0;
  1040. }
  1041. static int video1394_release(struct inode *inode, struct file *file)
  1042. {
  1043. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  1044. struct ti_ohci *ohci = ctx->ohci;
  1045. struct list_head *lh, *next;
  1046. u64 mask;
  1047. list_for_each_safe(lh, next, &ctx->context_list) {
  1048. struct dma_iso_ctx *d;
  1049. d = list_entry(lh, struct dma_iso_ctx, link);
  1050. mask = (u64) 1 << d->channel;
  1051. if (!(ohci->ISO_channel_usage & mask))
  1052. PRINT(KERN_ERR, ohci->host->id, "On release: Channel %d "
  1053. "is not being used", d->channel);
  1054. else
  1055. ohci->ISO_channel_usage &= ~mask;
  1056. DBGMSG(ohci->host->id, "On release: Iso %s context "
  1057. "%d stop listening on channel %d",
  1058. d->type == OHCI_ISO_RECEIVE ? "receive" : "transmit",
  1059. d->ctx, d->channel);
  1060. free_dma_iso_ctx(d);
  1061. }
  1062. kfree(ctx);
  1063. file->private_data = NULL;
  1064. return 0;
  1065. }
  1066. #ifdef CONFIG_COMPAT
  1067. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg);
  1068. #endif
  1069. static struct cdev video1394_cdev;
  1070. static const struct file_operations video1394_fops=
  1071. {
  1072. .owner = THIS_MODULE,
  1073. .unlocked_ioctl = video1394_ioctl,
  1074. #ifdef CONFIG_COMPAT
  1075. .compat_ioctl = video1394_compat_ioctl,
  1076. #endif
  1077. .poll = video1394_poll,
  1078. .mmap = video1394_mmap,
  1079. .open = video1394_open,
  1080. .release = video1394_release
  1081. };
  1082. /*** HOTPLUG STUFF **********************************************************/
  1083. /*
  1084. * Export information about protocols/devices supported by this driver.
  1085. */
  1086. #ifdef MODULE
  1087. static const struct ieee1394_device_id video1394_id_table[] = {
  1088. {
  1089. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1090. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1091. .version = CAMERA_SW_VERSION_ENTRY & 0xffffff
  1092. },
  1093. {
  1094. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1095. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1096. .version = (CAMERA_SW_VERSION_ENTRY + 1) & 0xffffff
  1097. },
  1098. {
  1099. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1100. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1101. .version = (CAMERA_SW_VERSION_ENTRY + 2) & 0xffffff
  1102. },
  1103. { }
  1104. };
  1105. MODULE_DEVICE_TABLE(ieee1394, video1394_id_table);
  1106. #endif /* MODULE */
  1107. static struct hpsb_protocol_driver video1394_driver = {
  1108. .name = VIDEO1394_DRIVER_NAME,
  1109. };
  1110. static void video1394_add_host (struct hpsb_host *host)
  1111. {
  1112. struct ti_ohci *ohci;
  1113. int minor;
  1114. /* We only work with the OHCI-1394 driver */
  1115. if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
  1116. return;
  1117. ohci = (struct ti_ohci *)host->hostdata;
  1118. if (!hpsb_create_hostinfo(&video1394_highlevel, host, 0)) {
  1119. PRINT(KERN_ERR, ohci->host->id, "Cannot allocate hostinfo");
  1120. return;
  1121. }
  1122. hpsb_set_hostinfo(&video1394_highlevel, host, ohci);
  1123. hpsb_set_hostinfo_key(&video1394_highlevel, host, ohci->host->id);
  1124. minor = IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id;
  1125. device_create(hpsb_protocol_class, NULL, MKDEV(IEEE1394_MAJOR, minor),
  1126. NULL, "%s-%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1127. }
  1128. static void video1394_remove_host (struct hpsb_host *host)
  1129. {
  1130. struct ti_ohci *ohci = hpsb_get_hostinfo(&video1394_highlevel, host);
  1131. if (ohci)
  1132. device_destroy(hpsb_protocol_class, MKDEV(IEEE1394_MAJOR,
  1133. IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id));
  1134. return;
  1135. }
  1136. static struct hpsb_highlevel video1394_highlevel = {
  1137. .name = VIDEO1394_DRIVER_NAME,
  1138. .add_host = video1394_add_host,
  1139. .remove_host = video1394_remove_host,
  1140. };
  1141. MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
  1142. MODULE_DESCRIPTION("driver for digital video on OHCI board");
  1143. MODULE_SUPPORTED_DEVICE(VIDEO1394_DRIVER_NAME);
  1144. MODULE_LICENSE("GPL");
  1145. #ifdef CONFIG_COMPAT
  1146. #define VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER \
  1147. _IOW ('#', 0x12, struct video1394_wait32)
  1148. #define VIDEO1394_IOC32_LISTEN_WAIT_BUFFER \
  1149. _IOWR('#', 0x13, struct video1394_wait32)
  1150. #define VIDEO1394_IOC32_TALK_WAIT_BUFFER \
  1151. _IOW ('#', 0x17, struct video1394_wait32)
  1152. #define VIDEO1394_IOC32_LISTEN_POLL_BUFFER \
  1153. _IOWR('#', 0x18, struct video1394_wait32)
  1154. struct video1394_wait32 {
  1155. u32 channel;
  1156. u32 buffer;
  1157. struct compat_timeval filltime;
  1158. };
  1159. static int video1394_wr_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1160. {
  1161. struct video1394_wait32 __user *argp = (void __user *)arg;
  1162. struct video1394_wait32 wait32;
  1163. struct video1394_wait wait;
  1164. mm_segment_t old_fs;
  1165. int ret;
  1166. if (copy_from_user(&wait32, argp, sizeof(wait32)))
  1167. return -EFAULT;
  1168. wait.channel = wait32.channel;
  1169. wait.buffer = wait32.buffer;
  1170. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1171. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1172. old_fs = get_fs();
  1173. set_fs(KERNEL_DS);
  1174. if (cmd == VIDEO1394_IOC32_LISTEN_WAIT_BUFFER)
  1175. ret = video1394_ioctl(file,
  1176. VIDEO1394_IOC_LISTEN_WAIT_BUFFER,
  1177. (unsigned long) &wait);
  1178. else
  1179. ret = video1394_ioctl(file,
  1180. VIDEO1394_IOC_LISTEN_POLL_BUFFER,
  1181. (unsigned long) &wait);
  1182. set_fs(old_fs);
  1183. if (!ret) {
  1184. wait32.channel = wait.channel;
  1185. wait32.buffer = wait.buffer;
  1186. wait32.filltime.tv_sec = (int)wait.filltime.tv_sec;
  1187. wait32.filltime.tv_usec = (int)wait.filltime.tv_usec;
  1188. if (copy_to_user(argp, &wait32, sizeof(wait32)))
  1189. ret = -EFAULT;
  1190. }
  1191. return ret;
  1192. }
  1193. static int video1394_w_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1194. {
  1195. struct video1394_wait32 wait32;
  1196. struct video1394_wait wait;
  1197. mm_segment_t old_fs;
  1198. int ret;
  1199. if (copy_from_user(&wait32, (void __user *)arg, sizeof(wait32)))
  1200. return -EFAULT;
  1201. wait.channel = wait32.channel;
  1202. wait.buffer = wait32.buffer;
  1203. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1204. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1205. old_fs = get_fs();
  1206. set_fs(KERNEL_DS);
  1207. if (cmd == VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER)
  1208. ret = video1394_ioctl(file,
  1209. VIDEO1394_IOC_LISTEN_QUEUE_BUFFER,
  1210. (unsigned long) &wait);
  1211. else
  1212. ret = video1394_ioctl(file,
  1213. VIDEO1394_IOC_TALK_WAIT_BUFFER,
  1214. (unsigned long) &wait);
  1215. set_fs(old_fs);
  1216. return ret;
  1217. }
  1218. static int video1394_queue_buf32(struct file *file, unsigned int cmd, unsigned long arg)
  1219. {
  1220. return -EFAULT; /* ??? was there before. */
  1221. return video1394_ioctl(file,
  1222. VIDEO1394_IOC_TALK_QUEUE_BUFFER, arg);
  1223. }
  1224. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg)
  1225. {
  1226. switch (cmd) {
  1227. case VIDEO1394_IOC_LISTEN_CHANNEL:
  1228. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  1229. case VIDEO1394_IOC_TALK_CHANNEL:
  1230. case VIDEO1394_IOC_UNTALK_CHANNEL:
  1231. return video1394_ioctl(f, cmd, arg);
  1232. case VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER:
  1233. return video1394_w_wait32(f, cmd, arg);
  1234. case VIDEO1394_IOC32_LISTEN_WAIT_BUFFER:
  1235. return video1394_wr_wait32(f, cmd, arg);
  1236. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  1237. return video1394_queue_buf32(f, cmd, arg);
  1238. case VIDEO1394_IOC32_TALK_WAIT_BUFFER:
  1239. return video1394_w_wait32(f, cmd, arg);
  1240. case VIDEO1394_IOC32_LISTEN_POLL_BUFFER:
  1241. return video1394_wr_wait32(f, cmd, arg);
  1242. default:
  1243. return -ENOIOCTLCMD;
  1244. }
  1245. }
  1246. #endif /* CONFIG_COMPAT */
  1247. static void __exit video1394_exit_module (void)
  1248. {
  1249. hpsb_unregister_protocol(&video1394_driver);
  1250. hpsb_unregister_highlevel(&video1394_highlevel);
  1251. cdev_del(&video1394_cdev);
  1252. PRINT_G(KERN_INFO, "Removed " VIDEO1394_DRIVER_NAME " module");
  1253. }
  1254. static int __init video1394_init_module (void)
  1255. {
  1256. int ret;
  1257. hpsb_init_highlevel(&video1394_highlevel);
  1258. cdev_init(&video1394_cdev, &video1394_fops);
  1259. video1394_cdev.owner = THIS_MODULE;
  1260. ret = cdev_add(&video1394_cdev, IEEE1394_VIDEO1394_DEV, 16);
  1261. if (ret) {
  1262. PRINT_G(KERN_ERR, "video1394: unable to get minor device block");
  1263. return ret;
  1264. }
  1265. hpsb_register_highlevel(&video1394_highlevel);
  1266. ret = hpsb_register_protocol(&video1394_driver);
  1267. if (ret) {
  1268. PRINT_G(KERN_ERR, "video1394: failed to register protocol");
  1269. hpsb_unregister_highlevel(&video1394_highlevel);
  1270. cdev_del(&video1394_cdev);
  1271. return ret;
  1272. }
  1273. PRINT_G(KERN_INFO, "Installed " VIDEO1394_DRIVER_NAME " module");
  1274. return 0;
  1275. }
  1276. module_init(video1394_init_module);
  1277. module_exit(video1394_exit_module);